[v6] MIPS: Sync elf.h from binutils

  From: Ying Huang <ying.huang@oss.cipunited.com>

Add new definitions for the MIPS target, specifically: relocation
types, machine flags, section type names, and object attribute tags
and values.  On MIPS64, up to three relocations may be specified
within r_info, by the r_type, r_type2, and r_type3 fields, so add new
macros to get the respective reloc types for MIPS64.
---
 elf/elf.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 137 insertions(+), 3 deletions(-)
  

Hi,

On Thu, 2023-06-15 at 03:50 -0400, Ying Huang wrote:
> From: Ying Huang <ying.huang@oss.cipunited.com>
> 
> Add new definitions for the MIPS target, specifically: relocation
> types, machine flags, section type names, and object attribute tags
> and values.  On MIPS64, up to three relocations may be specified
> within r_info, by the r_type, r_type2, and r_type3 fields, so add new
> macros to get the respective reloc types for MIPS64.

This is
https://patchwork.sourceware.org/project/glibc/patch/20230615075021.1955631-1-ying.huang@oss.cipunited.com/

It does look like you resolved the issues reported against v5:
- Remove \ continuation line, reported by Maxim
- The whitespace and alignment issues, reported by Maciej

It would be nice to get this in so we can use the new defines in
elfutils.

Thanks,

Mark
  

ping

Thanks,

Ying

在 2023/6/15 15:50, Ying Huang 写道:
>
> From: Ying Huang
>
> Add new definitions for the MIPS target, specifically: relocation
> types, machine flags, section type names, and object attribute tags
> and values. On MIPS64, up to three relocations may be specified
> within r_info, by the r_type, r_type2, and r_type3 fields, so add new
> macros to get the respective reloc types for MIPS64.
> ---
> elf/elf.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 137 insertions(+), 3 deletions(-)
>
> diff --git a/elf/elf.h b/elf/elf.h
> index ac7032b7a5..ef84ea0d22 100644
> --- a/elf/elf.h
> +++ b/elf/elf.h
> @@ -678,6 +678,9 @@ typedef Elf64_Xword Elf64_Relr;
>
> #define ELF64_R_SYM(i) ((i) >> 32)
> #define ELF64_R_TYPE(i) ((i) & 0xffffffff)
> +#define ELF64_MIPS_R_TYPE(i) ((i) & 0xff)
> +#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff)
> +#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff)
> #define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type))
>
> /* Program segment header. */
> @@ -1685,11 +1688,25 @@ typedef struct
> #define EF_MIPS_PIC 2 /* Contains PIC code. */
> #define EF_MIPS_CPIC 4 /* Uses PIC calling sequence. */
> #define EF_MIPS_XGOT 8
> -#define EF_MIPS_64BIT_WHIRL 16
> +#define EF_MIPS_UCODE 16
> #define EF_MIPS_ABI2 32
> #define EF_MIPS_ABI_ON32 64
> +#define EF_MIPS_OPTIONS_FIRST 0x00000080 /* Process the .MIPS.options
> + section first by ld. */
> +#define EF_MIPS_32BITMODE 0x00000100 /* Indicates code compiled for
> + a 64-bit machine in 32-bit
> + mode (regs are 32-bits
> + wide). */
> #define EF_MIPS_FP64 512 /* Uses FP64 (12 callee-saved). */
> #define EF_MIPS_NAN2008 1024 /* Uses IEEE 754-2008 NaN encoding. */
> +#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural Extensions
> + used by this file. */
> +#define EF_MIPS_ARCH_ASE_MDMX 0x08000000 /* Use MDMX multimedia
> + extensions. */
> +#define EF_MIPS_ARCH_ASE_M16 0x04000000 /* Use MIPS-16 ISA
> + extensions. */
> +#define EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000 /* Use MICROMIPS ISA
> + extensions. */
> #define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level. */
>
> /* Legal values for MIPS architecture level. */
> @@ -1703,6 +1720,37 @@ typedef struct
> #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
> #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32r2 code. */
> #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64r2 code. */
> +#define EF_MIPS_ARCH_32R6 0x90000000 /* MIPS32r6 code. */
> +#define EF_MIPS_ARCH_64R6 0xa0000000 /* MIPS64r6 code. */
> +#define EF_MIPS_ABI 0x0000F000 /* The ABI of the file. Also
> + see EF_MIPS_ABI2 above. */
> +#define EF_MIPS_ABI_O32 0x00001000 /* The original o32 abi. */
> +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended to work on
> + 64 bit architectures. */
> +#define EF_MIPS_ABI_EABI32 0x00003000 /* EABI in 32 bit mode. */
> +#define EF_MIPS_ABI_EABI64 0x00004000 /* EABI in 64 bit mode. */
> +#define EF_MIPS_MACH 0x00FF0000
> +#define EF_MIPS_MACH_3900 0x00810000
> +#define EF_MIPS_MACH_4010 0x00820000
> +#define EF_MIPS_MACH_4100 0x00830000
> +#define EF_MIPS_MACH_4650 0x00850000
> +#define EF_MIPS_MACH_4120 0x00870000
> +#define EF_MIPS_MACH_4111 0x00880000
> +#define EF_MIPS_MACH_SB1 0x008a0000
> +#define EF_MIPS_MACH_OCTEON 0x008b0000
> +#define EF_MIPS_MACH_XLR 0x008c0000
> +#define EF_MIPS_MACH_OCTEON2 0x008d0000
> +#define EF_MIPS_MACH_OCTEON3 0x008e0000
> +#define EF_MIPS_MACH_5400 0x00910000
> +#define EF_MIPS_MACH_5900 0x00920000
> +#define EF_MIPS_MACH_IAMR2 0x00930000
> +#define EF_MIPS_MACH_5500 0x00980000
> +#define EF_MIPS_MACH_9000 0x00990000
> +#define EF_MIPS_MACH_LS2E 0x00A00000
> +#define EF_MIPS_MACH_LS2F 0x00A10000
> +#define EF_MIPS_MACH_GS464 0x00A20000
> +#define EF_MIPS_MACH_GS464E 0x00A30000
> +#define EF_MIPS_MACH_GS264E 0x00A40000
>
> /* The following are unofficial names and should not be used. */
>
> @@ -1763,6 +1811,7 @@ typedef struct
> #define SHT_MIPS_EH_REGION 0x70000027
> #define SHT_MIPS_XLATE_OLD 0x70000028
> #define SHT_MIPS_PDR_EXCEPTION 0x70000029
> +#define SHT_MIPS_ABIFLAGS 0x7000002a
> #define SHT_MIPS_XHASH 0x7000002b
>
> /* Legal values for sh_flags field of Elf32_Shdr. */
> @@ -1931,10 +1980,68 @@ typedef struct
> #define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
> #define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
> #define R_MIPS_GLOB_DAT 51
> +#define R_MIPS_PC21_S2 60
> +#define R_MIPS_PC26_S2 61
> +#define R_MIPS_PC18_S3 62
> +#define R_MIPS_PC19_S2 63
> +#define R_MIPS_PCHI16 64
> +#define R_MIPS_PCLO16 65
> +#define R_MIPS16_26 100
> +#define R_MIPS16_GPREL 101
> +#define R_MIPS16_GOT16 102
> +#define R_MIPS16_CALL16 103
> +#define R_MIPS16_HI16 104
> +#define R_MIPS16_LO16 105
> +#define R_MIPS16_TLS_GD 106
> +#define R_MIPS16_TLS_LDM 107
> +#define R_MIPS16_TLS_DTPREL_HI16 108
> +#define R_MIPS16_TLS_DTPREL_LO16 109
> +#define R_MIPS16_TLS_GOTTPREL 110
> +#define R_MIPS16_TLS_TPREL_HI16 111
> +#define R_MIPS16_TLS_TPREL_LO16 112
> +#define R_MIPS16_PC16_S1 113
> #define R_MIPS_COPY 126
> #define R_MIPS_JUMP_SLOT 127
> +#define R_MIPS_RELATIVE 128
> +#define R_MICROMIPS_26_S1 133
> +#define R_MICROMIPS_HI16 134
> +#define R_MICROMIPS_LO16 135
> +#define R_MICROMIPS_GPREL16 136
> +#define R_MICROMIPS_LITERAL 137
> +#define R_MICROMIPS_GOT16 138
> +#define R_MICROMIPS_PC7_S1 139
> +#define R_MICROMIPS_PC10_S1 140
> +#define R_MICROMIPS_PC16_S1 141
> +#define R_MICROMIPS_CALL16 142
> +#define R_MICROMIPS_GOT_DISP 145
> +#define R_MICROMIPS_GOT_PAGE 146
> +#define R_MICROMIPS_GOT_OFST 147
> +#define R_MICROMIPS_GOT_HI16 148
> +#define R_MICROMIPS_GOT_LO16 149
> +#define R_MICROMIPS_SUB 150
> +#define R_MICROMIPS_HIGHER 151
> +#define R_MICROMIPS_HIGHEST 152
> +#define R_MICROMIPS_CALL_HI16 153
> +#define R_MICROMIPS_CALL_LO16 154
> +#define R_MICROMIPS_SCN_DISP 155
> +#define R_MICROMIPS_JALR 156
> +#define R_MICROMIPS_HI0_LO16 157
> +#define R_MICROMIPS_TLS_GD 162
> +#define R_MICROMIPS_TLS_LDM 163
> +#define R_MICROMIPS_TLS_DTPREL_HI16 164
> +#define R_MICROMIPS_TLS_DTPREL_LO16 165
> +#define R_MICROMIPS_TLS_GOTTPREL 166
> +#define R_MICROMIPS_TLS_TPREL_HI16 169
> +#define R_MICROMIPS_TLS_TPREL_LO16 170
> +#define R_MICROMIPS_GPREL7_S2 172
> +#define R_MICROMIPS_PC23_S2 173
> +#define R_MIPS_PC32 248
> +#define R_MIPS_EH 249
> +#define R_MIPS_GNU_REL16_S2 250
> +#define R_MIPS_GNU_VTINHERIT 253
> +#define R_MIPS_GNU_VTENTRY 254
> /* Keep this the last entry. */
> -#define R_MIPS_NUM 128
> +#define R_MIPS_NUM 255
>
> /* Legal values for p_type field of Elf32_Phdr. */
>
> @@ -2142,6 +2249,30 @@ typedef struct
> /* Masks for the flags1 word of an ABI flags structure. */
> #define MIPS_AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */
>
> +/* Object attribute tags. */
> +enum
> +{
> + /* 0-3 are generic. */
> +
> + /* Floating-point ABI used by this object file. */
> + Tag_GNU_MIPS_ABI_FP = 4,
> +
> + /* MSA ABI used by this object file. */
> + Tag_GNU_MIPS_ABI_MSA = 8,
> +};
> +
> +/* Object attribute values. */
> +enum
> +{
> + /* Values defined for Tag_GNU_MIPS_ABI_MSA. */
> +
> + /* Not tagged or not using any ABIs affected by the differences. */
> + Val_GNU_MIPS_ABI_MSA_ANY = 0,
> +
> + /* Using 128-bit MSA. */
> + Val_GNU_MIPS_ABI_MSA_128 = 1,
> +};
> +
> /* Object attribute values. */
> enum
> {
> @@ -2161,8 +2292,11 @@ enum
> Val_GNU_MIPS_ABI_FP_64 = 6,
> /* Using -mips32r2 -mfp64 -mno-odd-spreg. */
> Val_GNU_MIPS_ABI_FP_64A = 7,
> + /* This is reserved for backward-compatibility with an earlier
> + implementation of the MIPS NaN2008 functionality. */
> + Val_GNU_MIPS_ABI_FP_NAN2008 = 8,
> /* Maximum allocated FP ABI value. */
> - Val_GNU_MIPS_ABI_FP_MAX = 7
> + Val_GNU_MIPS_ABI_FP_MAX = 8
> };
>
> /* HPPA specific definitions. */
> -- 
> 2.30.2
>
  

ping

Because I did not have commit permissions,  could you help commit?

Thanks,

Ying


在 2023/7/11 14:48, Ying Huang 写道:
>
> ping
>
> Thanks,
>
> Ying
>
> 在 2023/6/15 15:50, Ying Huang 写道:
> >
> > From: Ying Huang
> >
> > Add new definitions for the MIPS target, specifically: relocation
> > types, machine flags, section type names, and object attribute tags
> > and values. On MIPS64, up to three relocations may be specified
> > within r_info, by the r_type, r_type2, and r_type3 fields, so add new
> > macros to get the respective reloc types for MIPS64.
> > ---
> > elf/elf.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 137 insertions(+), 3 deletions(-)
> >
> > diff --git a/elf/elf.h b/elf/elf.h
> > index ac7032b7a5..ef84ea0d22 100644
> > --- a/elf/elf.h
> > +++ b/elf/elf.h
> > @@ -678,6 +678,9 @@ typedef Elf64_Xword Elf64_Relr;
> >
> > #define ELF64_R_SYM(i) ((i) >> 32)
> > #define ELF64_R_TYPE(i) ((i) & 0xffffffff)
> > +#define ELF64_MIPS_R_TYPE(i) ((i) & 0xff)
> > +#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff)
> > +#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff)
> > #define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type))
> >
> > /* Program segment header. */
> > @@ -1685,11 +1688,25 @@ typedef struct
> > #define EF_MIPS_PIC 2 /* Contains PIC code. */
> > #define EF_MIPS_CPIC 4 /* Uses PIC calling sequence. */
> > #define EF_MIPS_XGOT 8
> > -#define EF_MIPS_64BIT_WHIRL 16
> > +#define EF_MIPS_UCODE 16
> > #define EF_MIPS_ABI2 32
> > #define EF_MIPS_ABI_ON32 64
> > +#define EF_MIPS_OPTIONS_FIRST 0x00000080 /* Process the .MIPS.options
> > + section first by ld. */
> > +#define EF_MIPS_32BITMODE 0x00000100 /* Indicates code compiled for
> > + a 64-bit machine in 32-bit
> > + mode (regs are 32-bits
> > + wide). */
> > #define EF_MIPS_FP64 512 /* Uses FP64 (12 callee-saved). */
> > #define EF_MIPS_NAN2008 1024 /* Uses IEEE 754-2008 NaN encoding. */
> > +#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural Extensions
> > + used by this file. */
> > +#define EF_MIPS_ARCH_ASE_MDMX 0x08000000 /* Use MDMX multimedia
> > + extensions. */
> > +#define EF_MIPS_ARCH_ASE_M16 0x04000000 /* Use MIPS-16 ISA
> > + extensions. */
> > +#define EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000 /* Use MICROMIPS ISA
> > + extensions. */
> > #define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level. */
> >
> > /* Legal values for MIPS architecture level. */
> > @@ -1703,6 +1720,37 @@ typedef struct
> > #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
> > #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32r2 code. */
> > #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64r2 code. */
> > +#define EF_MIPS_ARCH_32R6 0x90000000 /* MIPS32r6 code. */
> > +#define EF_MIPS_ARCH_64R6 0xa0000000 /* MIPS64r6 code. */
> > +#define EF_MIPS_ABI 0x0000F000 /* The ABI of the file. Also
> > + see EF_MIPS_ABI2 above. */
> > +#define EF_MIPS_ABI_O32 0x00001000 /* The original o32 abi. */
> > +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended to work on
> > + 64 bit architectures. */
> > +#define EF_MIPS_ABI_EABI32 0x00003000 /* EABI in 32 bit mode. */
> > +#define EF_MIPS_ABI_EABI64 0x00004000 /* EABI in 64 bit mode. */
> > +#define EF_MIPS_MACH 0x00FF0000
> > +#define EF_MIPS_MACH_3900 0x00810000
> > +#define EF_MIPS_MACH_4010 0x00820000
> > +#define EF_MIPS_MACH_4100 0x00830000
> > +#define EF_MIPS_MACH_4650 0x00850000
> > +#define EF_MIPS_MACH_4120 0x00870000
> > +#define EF_MIPS_MACH_4111 0x00880000
> > +#define EF_MIPS_MACH_SB1 0x008a0000
> > +#define EF_MIPS_MACH_OCTEON 0x008b0000
> > +#define EF_MIPS_MACH_XLR 0x008c0000
> > +#define EF_MIPS_MACH_OCTEON2 0x008d0000
> > +#define EF_MIPS_MACH_OCTEON3 0x008e0000
> > +#define EF_MIPS_MACH_5400 0x00910000
> > +#define EF_MIPS_MACH_5900 0x00920000
> > +#define EF_MIPS_MACH_IAMR2 0x00930000
> > +#define EF_MIPS_MACH_5500 0x00980000
> > +#define EF_MIPS_MACH_9000 0x00990000
> > +#define EF_MIPS_MACH_LS2E 0x00A00000
> > +#define EF_MIPS_MACH_LS2F 0x00A10000
> > +#define EF_MIPS_MACH_GS464 0x00A20000
> > +#define EF_MIPS_MACH_GS464E 0x00A30000
> > +#define EF_MIPS_MACH_GS264E 0x00A40000
> >
> > /* The following are unofficial names and should not be used. */
> >
> > @@ -1763,6 +1811,7 @@ typedef struct
> > #define SHT_MIPS_EH_REGION 0x70000027
> > #define SHT_MIPS_XLATE_OLD 0x70000028
> > #define SHT_MIPS_PDR_EXCEPTION 0x70000029
> > +#define SHT_MIPS_ABIFLAGS 0x7000002a
> > #define SHT_MIPS_XHASH 0x7000002b
> >
> > /* Legal values for sh_flags field of Elf32_Shdr. */
> > @@ -1931,10 +1980,68 @@ typedef struct
> > #define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
> > #define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
> > #define R_MIPS_GLOB_DAT 51
> > +#define R_MIPS_PC21_S2 60
> > +#define R_MIPS_PC26_S2 61
> > +#define R_MIPS_PC18_S3 62
> > +#define R_MIPS_PC19_S2 63
> > +#define R_MIPS_PCHI16 64
> > +#define R_MIPS_PCLO16 65
> > +#define R_MIPS16_26 100
> > +#define R_MIPS16_GPREL 101
> > +#define R_MIPS16_GOT16 102
> > +#define R_MIPS16_CALL16 103
> > +#define R_MIPS16_HI16 104
> > +#define R_MIPS16_LO16 105
> > +#define R_MIPS16_TLS_GD 106
> > +#define R_MIPS16_TLS_LDM 107
> > +#define R_MIPS16_TLS_DTPREL_HI16 108
> > +#define R_MIPS16_TLS_DTPREL_LO16 109
> > +#define R_MIPS16_TLS_GOTTPREL 110
> > +#define R_MIPS16_TLS_TPREL_HI16 111
> > +#define R_MIPS16_TLS_TPREL_LO16 112
> > +#define R_MIPS16_PC16_S1 113
> > #define R_MIPS_COPY 126
> > #define R_MIPS_JUMP_SLOT 127
> > +#define R_MIPS_RELATIVE 128
> > +#define R_MICROMIPS_26_S1 133
> > +#define R_MICROMIPS_HI16 134
> > +#define R_MICROMIPS_LO16 135
> > +#define R_MICROMIPS_GPREL16 136
> > +#define R_MICROMIPS_LITERAL 137
> > +#define R_MICROMIPS_GOT16 138
> > +#define R_MICROMIPS_PC7_S1 139
> > +#define R_MICROMIPS_PC10_S1 140
> > +#define R_MICROMIPS_PC16_S1 141
> > +#define R_MICROMIPS_CALL16 142
> > +#define R_MICROMIPS_GOT_DISP 145
> > +#define R_MICROMIPS_GOT_PAGE 146
> > +#define R_MICROMIPS_GOT_OFST 147
> > +#define R_MICROMIPS_GOT_HI16 148
> > +#define R_MICROMIPS_GOT_LO16 149
> > +#define R_MICROMIPS_SUB 150
> > +#define R_MICROMIPS_HIGHER 151
> > +#define R_MICROMIPS_HIGHEST 152
> > +#define R_MICROMIPS_CALL_HI16 153
> > +#define R_MICROMIPS_CALL_LO16 154
> > +#define R_MICROMIPS_SCN_DISP 155
> > +#define R_MICROMIPS_JALR 156
> > +#define R_MICROMIPS_HI0_LO16 157
> > +#define R_MICROMIPS_TLS_GD 162
> > +#define R_MICROMIPS_TLS_LDM 163
> > +#define R_MICROMIPS_TLS_DTPREL_HI16 164
> > +#define R_MICROMIPS_TLS_DTPREL_LO16 165
> > +#define R_MICROMIPS_TLS_GOTTPREL 166
> > +#define R_MICROMIPS_TLS_TPREL_HI16 169
> > +#define R_MICROMIPS_TLS_TPREL_LO16 170
> > +#define R_MICROMIPS_GPREL7_S2 172
> > +#define R_MICROMIPS_PC23_S2 173
> > +#define R_MIPS_PC32 248
> > +#define R_MIPS_EH 249
> > +#define R_MIPS_GNU_REL16_S2 250
> > +#define R_MIPS_GNU_VTINHERIT 253
> > +#define R_MIPS_GNU_VTENTRY 254
> > /* Keep this the last entry. */
> > -#define R_MIPS_NUM 128
> > +#define R_MIPS_NUM 255
> >
> > /* Legal values for p_type field of Elf32_Phdr. */
> >
> > @@ -2142,6 +2249,30 @@ typedef struct
> > /* Masks for the flags1 word of an ABI flags structure. */
> > #define MIPS_AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */
> >
> > +/* Object attribute tags. */
> > +enum
> > +{
> > + /* 0-3 are generic. */
> > +
> > + /* Floating-point ABI used by this object file. */
> > + Tag_GNU_MIPS_ABI_FP = 4,
> > +
> > + /* MSA ABI used by this object file. */
> > + Tag_GNU_MIPS_ABI_MSA = 8,
> > +};
> > +
> > +/* Object attribute values. */
> > +enum
> > +{
> > + /* Values defined for Tag_GNU_MIPS_ABI_MSA. */
> > +
> > + /* Not tagged or not using any ABIs affected by the differences. */
> > + Val_GNU_MIPS_ABI_MSA_ANY = 0,
> > +
> > + /* Using 128-bit MSA. */
> > + Val_GNU_MIPS_ABI_MSA_128 = 1,
> > +};
> > +
> > /* Object attribute values. */
> > enum
> > {
> > @@ -2161,8 +2292,11 @@ enum
> > Val_GNU_MIPS_ABI_FP_64 = 6,
> > /* Using -mips32r2 -mfp64 -mno-odd-spreg. */
> > Val_GNU_MIPS_ABI_FP_64A = 7,
> > + /* This is reserved for backward-compatibility with an earlier
> > + implementation of the MIPS NaN2008 functionality. */
> > + Val_GNU_MIPS_ABI_FP_NAN2008 = 8,
> > /* Maximum allocated FP ABI value. */
> > - Val_GNU_MIPS_ABI_FP_MAX = 7
> > + Val_GNU_MIPS_ABI_FP_MAX = 8
> > };
> >
> > /* HPPA specific definitions. */
> > --
> > 2.30.2
> >
>
  

Hi,

On Tue, Jul 18, 2023 at 10:17:09AM +0800, Ying Huang wrote:
> ping
> 
> Because I did not have commit permissions,  could you help commit?

I am happy to commit this for you. But even though it is a constants
only patch at this point it should probably get an OK from Andreas,
the release manager.

Cheers,

Mark

> 在 2023/7/11 14:48, Ying Huang 写道:
> >
> > ping
> >
> > Thanks,
> >
> > Ying
> >
> > 在 2023/6/15 15:50, Ying Huang 写道:
> > >
> > > From: Ying Huang
> > >
> > > Add new definitions for the MIPS target, specifically: relocation
> > > types, machine flags, section type names, and object attribute tags
> > > and values. On MIPS64, up to three relocations may be specified
> > > within r_info, by the r_type, r_type2, and r_type3 fields, so add new
> > > macros to get the respective reloc types for MIPS64.
> > > ---
> > > elf/elf.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
> > > 1 file changed, 137 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/elf/elf.h b/elf/elf.h
> > > index ac7032b7a5..ef84ea0d22 100644
> > > --- a/elf/elf.h
> > > +++ b/elf/elf.h
> > > @@ -678,6 +678,9 @@ typedef Elf64_Xword Elf64_Relr;
> > >
> > > #define ELF64_R_SYM(i) ((i) >> 32)
> > > #define ELF64_R_TYPE(i) ((i) & 0xffffffff)
> > > +#define ELF64_MIPS_R_TYPE(i) ((i) & 0xff)
> > > +#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff)
> > > +#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff)
> > > #define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type))
> > >
> > > /* Program segment header. */
> > > @@ -1685,11 +1688,25 @@ typedef struct
> > > #define EF_MIPS_PIC 2 /* Contains PIC code. */
> > > #define EF_MIPS_CPIC 4 /* Uses PIC calling sequence. */
> > > #define EF_MIPS_XGOT 8
> > > -#define EF_MIPS_64BIT_WHIRL 16
> > > +#define EF_MIPS_UCODE 16
> > > #define EF_MIPS_ABI2 32
> > > #define EF_MIPS_ABI_ON32 64
> > > +#define EF_MIPS_OPTIONS_FIRST 0x00000080 /* Process the .MIPS.options
> > > + section first by ld. */
> > > +#define EF_MIPS_32BITMODE 0x00000100 /* Indicates code compiled for
> > > + a 64-bit machine in 32-bit
> > > + mode (regs are 32-bits
> > > + wide). */
> > > #define EF_MIPS_FP64 512 /* Uses FP64 (12 callee-saved). */
> > > #define EF_MIPS_NAN2008 1024 /* Uses IEEE 754-2008 NaN encoding. */
> > > +#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural Extensions
> > > + used by this file. */
> > > +#define EF_MIPS_ARCH_ASE_MDMX 0x08000000 /* Use MDMX multimedia
> > > + extensions. */
> > > +#define EF_MIPS_ARCH_ASE_M16 0x04000000 /* Use MIPS-16 ISA
> > > + extensions. */
> > > +#define EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000 /* Use MICROMIPS ISA
> > > + extensions. */
> > > #define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level. */
> > >
> > > /* Legal values for MIPS architecture level. */
> > > @@ -1703,6 +1720,37 @@ typedef struct
> > > #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
> > > #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32r2 code. */
> > > #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64r2 code. */
> > > +#define EF_MIPS_ARCH_32R6 0x90000000 /* MIPS32r6 code. */
> > > +#define EF_MIPS_ARCH_64R6 0xa0000000 /* MIPS64r6 code. */
> > > +#define EF_MIPS_ABI 0x0000F000 /* The ABI of the file. Also
> > > + see EF_MIPS_ABI2 above. */
> > > +#define EF_MIPS_ABI_O32 0x00001000 /* The original o32 abi. */
> > > +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended to work on
> > > + 64 bit architectures. */
> > > +#define EF_MIPS_ABI_EABI32 0x00003000 /* EABI in 32 bit mode. */
> > > +#define EF_MIPS_ABI_EABI64 0x00004000 /* EABI in 64 bit mode. */
> > > +#define EF_MIPS_MACH 0x00FF0000
> > > +#define EF_MIPS_MACH_3900 0x00810000
> > > +#define EF_MIPS_MACH_4010 0x00820000
> > > +#define EF_MIPS_MACH_4100 0x00830000
> > > +#define EF_MIPS_MACH_4650 0x00850000
> > > +#define EF_MIPS_MACH_4120 0x00870000
> > > +#define EF_MIPS_MACH_4111 0x00880000
> > > +#define EF_MIPS_MACH_SB1 0x008a0000
> > > +#define EF_MIPS_MACH_OCTEON 0x008b0000
> > > +#define EF_MIPS_MACH_XLR 0x008c0000
> > > +#define EF_MIPS_MACH_OCTEON2 0x008d0000
> > > +#define EF_MIPS_MACH_OCTEON3 0x008e0000
> > > +#define EF_MIPS_MACH_5400 0x00910000
> > > +#define EF_MIPS_MACH_5900 0x00920000
> > > +#define EF_MIPS_MACH_IAMR2 0x00930000
> > > +#define EF_MIPS_MACH_5500 0x00980000
> > > +#define EF_MIPS_MACH_9000 0x00990000
> > > +#define EF_MIPS_MACH_LS2E 0x00A00000
> > > +#define EF_MIPS_MACH_LS2F 0x00A10000
> > > +#define EF_MIPS_MACH_GS464 0x00A20000
> > > +#define EF_MIPS_MACH_GS464E 0x00A30000
> > > +#define EF_MIPS_MACH_GS264E 0x00A40000
> > >
> > > /* The following are unofficial names and should not be used. */
> > >
> > > @@ -1763,6 +1811,7 @@ typedef struct
> > > #define SHT_MIPS_EH_REGION 0x70000027
> > > #define SHT_MIPS_XLATE_OLD 0x70000028
> > > #define SHT_MIPS_PDR_EXCEPTION 0x70000029
> > > +#define SHT_MIPS_ABIFLAGS 0x7000002a
> > > #define SHT_MIPS_XHASH 0x7000002b
> > >
> > > /* Legal values for sh_flags field of Elf32_Shdr. */
> > > @@ -1931,10 +1980,68 @@ typedef struct
> > > #define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
> > > #define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
> > > #define R_MIPS_GLOB_DAT 51
> > > +#define R_MIPS_PC21_S2 60
> > > +#define R_MIPS_PC26_S2 61
> > > +#define R_MIPS_PC18_S3 62
> > > +#define R_MIPS_PC19_S2 63
> > > +#define R_MIPS_PCHI16 64
> > > +#define R_MIPS_PCLO16 65
> > > +#define R_MIPS16_26 100
> > > +#define R_MIPS16_GPREL 101
> > > +#define R_MIPS16_GOT16 102
> > > +#define R_MIPS16_CALL16 103
> > > +#define R_MIPS16_HI16 104
> > > +#define R_MIPS16_LO16 105
> > > +#define R_MIPS16_TLS_GD 106
> > > +#define R_MIPS16_TLS_LDM 107
> > > +#define R_MIPS16_TLS_DTPREL_HI16 108
> > > +#define R_MIPS16_TLS_DTPREL_LO16 109
> > > +#define R_MIPS16_TLS_GOTTPREL 110
> > > +#define R_MIPS16_TLS_TPREL_HI16 111
> > > +#define R_MIPS16_TLS_TPREL_LO16 112
> > > +#define R_MIPS16_PC16_S1 113
> > > #define R_MIPS_COPY 126
> > > #define R_MIPS_JUMP_SLOT 127
> > > +#define R_MIPS_RELATIVE 128
> > > +#define R_MICROMIPS_26_S1 133
> > > +#define R_MICROMIPS_HI16 134
> > > +#define R_MICROMIPS_LO16 135
> > > +#define R_MICROMIPS_GPREL16 136
> > > +#define R_MICROMIPS_LITERAL 137
> > > +#define R_MICROMIPS_GOT16 138
> > > +#define R_MICROMIPS_PC7_S1 139
> > > +#define R_MICROMIPS_PC10_S1 140
> > > +#define R_MICROMIPS_PC16_S1 141
> > > +#define R_MICROMIPS_CALL16 142
> > > +#define R_MICROMIPS_GOT_DISP 145
> > > +#define R_MICROMIPS_GOT_PAGE 146
> > > +#define R_MICROMIPS_GOT_OFST 147
> > > +#define R_MICROMIPS_GOT_HI16 148
> > > +#define R_MICROMIPS_GOT_LO16 149
> > > +#define R_MICROMIPS_SUB 150
> > > +#define R_MICROMIPS_HIGHER 151
> > > +#define R_MICROMIPS_HIGHEST 152
> > > +#define R_MICROMIPS_CALL_HI16 153
> > > +#define R_MICROMIPS_CALL_LO16 154
> > > +#define R_MICROMIPS_SCN_DISP 155
> > > +#define R_MICROMIPS_JALR 156
> > > +#define R_MICROMIPS_HI0_LO16 157
> > > +#define R_MICROMIPS_TLS_GD 162
> > > +#define R_MICROMIPS_TLS_LDM 163
> > > +#define R_MICROMIPS_TLS_DTPREL_HI16 164
> > > +#define R_MICROMIPS_TLS_DTPREL_LO16 165
> > > +#define R_MICROMIPS_TLS_GOTTPREL 166
> > > +#define R_MICROMIPS_TLS_TPREL_HI16 169
> > > +#define R_MICROMIPS_TLS_TPREL_LO16 170
> > > +#define R_MICROMIPS_GPREL7_S2 172
> > > +#define R_MICROMIPS_PC23_S2 173
> > > +#define R_MIPS_PC32 248
> > > +#define R_MIPS_EH 249
> > > +#define R_MIPS_GNU_REL16_S2 250
> > > +#define R_MIPS_GNU_VTINHERIT 253
> > > +#define R_MIPS_GNU_VTENTRY 254
> > > /* Keep this the last entry. */
> > > -#define R_MIPS_NUM 128
> > > +#define R_MIPS_NUM 255
> > >
> > > /* Legal values for p_type field of Elf32_Phdr. */
> > >
> > > @@ -2142,6 +2249,30 @@ typedef struct
> > > /* Masks for the flags1 word of an ABI flags structure. */
> > > #define MIPS_AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */
> > >
> > > +/* Object attribute tags. */
> > > +enum
> > > +{
> > > + /* 0-3 are generic. */
> > > +
> > > + /* Floating-point ABI used by this object file. */
> > > + Tag_GNU_MIPS_ABI_FP = 4,
> > > +
> > > + /* MSA ABI used by this object file. */
> > > + Tag_GNU_MIPS_ABI_MSA = 8,
> > > +};
> > > +
> > > +/* Object attribute values. */
> > > +enum
> > > +{
> > > + /* Values defined for Tag_GNU_MIPS_ABI_MSA. */
> > > +
> > > + /* Not tagged or not using any ABIs affected by the differences. */
> > > + Val_GNU_MIPS_ABI_MSA_ANY = 0,
> > > +
> > > + /* Using 128-bit MSA. */
> > > + Val_GNU_MIPS_ABI_MSA_128 = 1,
> > > +};
> > > +
> > > /* Object attribute values. */
> > > enum
> > > {
> > > @@ -2161,8 +2292,11 @@ enum
> > > Val_GNU_MIPS_ABI_FP_64 = 6,
> > > /* Using -mips32r2 -mfp64 -mno-odd-spreg. */
> > > Val_GNU_MIPS_ABI_FP_64A = 7,
> > > + /* This is reserved for backward-compatibility with an earlier
> > > + implementation of the MIPS NaN2008 functionality. */
> > > + Val_GNU_MIPS_ABI_FP_NAN2008 = 8,
> > > /* Maximum allocated FP ABI value. */
> > > - Val_GNU_MIPS_ABI_FP_MAX = 7
> > > + Val_GNU_MIPS_ABI_FP_MAX = 8
> > > };
> > >
> > > /* HPPA specific definitions. */
> > > --
> > > 2.30.2
> > >
> >
  

Am Samstag, 22. Juli 2023, 11:37:41 CEST schrieb Mark Wielaard:
> Hi,
> 
> On Tue, Jul 18, 2023 at 10:17:09AM +0800, Ying Huang wrote:
> > ping
> > 
> > Because I did not have commit permissions,  could you help commit?
> 
> I am happy to commit this for you. But even though it is a constants
> only patch at this point it should probably get an OK from Andreas,
> the release manager.

OK from me, looks well-separated enough.
Last feature add-on of the month. :o)

Oh and some MIPS machine testing would be great, see 
https://sourceware.org/glibc/wiki/Release/2.38#MIPS
(unfortunately all I have access to myself is qemu there).
  

Thanks very much!
> From: "Mark Wielaard"<mark@klomp.org>
> Date:  Sat, Jul 22, 17:38
> Subject:  Re: [PATCH v6] MIPS: Sync elf.h from binutils
> To: "Ying Huang"<ying.huang@oss.cipunited.com>
> Cc: "Maxim Kuvyrkov"<maxim.kuvyrkov@linaro.org>, "Libc-alpha"<libc-alpha@sourceware.org>, <yunqiang.su@oss.cipunited.com>, "Andreas K. Huettel"<dilfridge@gentoo.org>
> Hi,
> 
> On Tue, Jul 18, 2023 at 10:17:09AM +0800, Ying Huang wrote:
> > ping
> > 
> > Because I did not have commit permissions,  could you help commit?
> 
> I am happy to commit this for you. But even though it is a constants
> only patch at this point it should probably get an OK from Andreas,
> the release manager.
> 
> Cheers,
> 
> Mark
> 
> > 在 2023/7/11 14:48, Ying Huang 写道:
> > >
> > > ping
> > >
> > > Thanks,
> > >
> > > Ying
> > >
> > > 在 2023/6/15 15:50, Ying Huang 写道:
> > > >
> > > > From: Ying Huang
> > > >
> > > > Add new definitions for the MIPS target, specifically: relocation
> > > > types, machine flags, section type names, and object attribute tags
> > > > and values. On MIPS64, up to three relocations may be specified
> > > > within r_info, by the r_type, r_type2, and r_type3 fields, so add new
> > > > macros to get the respective reloc types for MIPS64.
> > > > ---
> > > > elf/elf.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
> > > > 1 file changed, 137 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/elf/elf.h b/elf/elf.h
> > > > index ac7032b7a5..ef84ea0d22 100644
> > > > --- a/elf/elf.h
> > > > +++ b/elf/elf.h
> > > > @@ -678,6 +678,9 @@ typedef Elf64_Xword Elf64_Relr;
> > > >
> > > > #define ELF64_R_SYM(i) ((i) >> 32)
> > > > #define ELF64_R_TYPE(i) ((i) & 0xffffffff)
> > > > +#define ELF64_MIPS_R_TYPE(i) ((i) & 0xff)
> > > > +#define ELF64_MIPS_R_TYPE2(i) (((i) >> 8) & 0xff)
> > > > +#define ELF64_MIPS_R_TYPE3(i) (((i) >> 16) & 0xff)
> > > > #define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type))
> > > >
> > > > /* Program segment header. */
> > > > @@ -1685,11 +1688,25 @@ typedef struct
> > > > #define EF_MIPS_PIC 2 /* Contains PIC code. */
> > > > #define EF_MIPS_CPIC 4 /* Uses PIC calling sequence. */
> > > > #define EF_MIPS_XGOT 8
> > > > -#define EF_MIPS_64BIT_WHIRL 16
> > > > +#define EF_MIPS_UCODE 16
> > > > #define EF_MIPS_ABI2 32
> > > > #define EF_MIPS_ABI_ON32 64
> > > > +#define EF_MIPS_OPTIONS_FIRST 0x00000080 /* Process the .MIPS.options
> > > > + section first by ld. */
> > > > +#define EF_MIPS_32BITMODE 0x00000100 /* Indicates code compiled for
> > > > + a 64-bit machine in 32-bit
> > > > + mode (regs are 32-bits
> > > > + wide). */
> > > > #define EF_MIPS_FP64 512 /* Uses FP64 (12 callee-saved). */
> > > > #define EF_MIPS_NAN2008 1024 /* Uses IEEE 754-2008 NaN encoding. */
> > > > +#define EF_MIPS_ARCH_ASE 0x0f000000 /* Architectural Extensions
> > > > + used by this file. */
> > > > +#define EF_MIPS_ARCH_ASE_MDMX 0x08000000 /* Use MDMX multimedia
> > > > + extensions. */
> > > > +#define EF_MIPS_ARCH_ASE_M16 0x04000000 /* Use MIPS-16 ISA
> > > > + extensions. */
> > > > +#define EF_MIPS_ARCH_ASE_MICROMIPS 0x02000000 /* Use MICROMIPS ISA
> > > > + extensions. */
> > > > #define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level. */
> > > >
> > > > /* Legal values for MIPS architecture level. */
> > > > @@ -1703,6 +1720,37 @@ typedef struct
> > > > #define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
> > > > #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32r2 code. */
> > > > #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64r2 code. */
> > > > +#define EF_MIPS_ARCH_32R6 0x90000000 /* MIPS32r6 code. */
> > > > +#define EF_MIPS_ARCH_64R6 0xa0000000 /* MIPS64r6 code. */
> > > > +#define EF_MIPS_ABI 0x0000F000 /* The ABI of the file. Also
> > > > + see EF_MIPS_ABI2 above. */
> > > > +#define EF_MIPS_ABI_O32 0x00001000 /* The original o32 abi. */
> > > > +#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended to work on
> > > > + 64 bit architectures. */
> > > > +#define EF_MIPS_ABI_EABI32 0x00003000 /* EABI in 32 bit mode. */
> > > > +#define EF_MIPS_ABI_EABI64 0x00004000 /* EABI in 64 bit mode. */
> > > > +#define EF_MIPS_MACH 0x00FF0000
> > > > +#define EF_MIPS_MACH_3900 0x00810000
> > > > +#define EF_MIPS_MACH_4010 0x00820000
> > > > +#define EF_MIPS_MACH_4100 0x00830000
> > > > +#define EF_MIPS_MACH_4650 0x00850000
> > > > +#define EF_MIPS_MACH_4120 0x00870000
> > > > +#define EF_MIPS_MACH_4111 0x00880000
> > > > +#define EF_MIPS_MACH_SB1 0x008a0000
> > > > +#define EF_MIPS_MACH_OCTEON 0x008b0000
> > > > +#define EF_MIPS_MACH_XLR 0x008c0000
> > > > +#define EF_MIPS_MACH_OCTEON2 0x008d0000
> > > > +#define EF_MIPS_MACH_OCTEON3 0x008e0000
> > > > +#define EF_MIPS_MACH_5400 0x00910000
> > > > +#define EF_MIPS_MACH_5900 0x00920000
> > > > +#define EF_MIPS_MACH_IAMR2 0x00930000
> > > > +#define EF_MIPS_MACH_5500 0x00980000
> > > > +#define EF_MIPS_MACH_9000 0x00990000
> > > > +#define EF_MIPS_MACH_LS2E 0x00A00000
> > > > +#define EF_MIPS_MACH_LS2F 0x00A10000
> > > > +#define EF_MIPS_MACH_GS464 0x00A20000
> > > > +#define EF_MIPS_MACH_GS464E 0x00A30000
> > > > +#define EF_MIPS_MACH_GS264E 0x00A40000
> > > >
> > > > /* The following are unofficial names and should not be used. */
> > > >
> > > > @@ -1763,6 +1811,7 @@ typedef struct
> > > > #define SHT_MIPS_EH_REGION 0x70000027
> > > > #define SHT_MIPS_XLATE_OLD 0x70000028
> > > > #define SHT_MIPS_PDR_EXCEPTION 0x70000029
> > > > +#define SHT_MIPS_ABIFLAGS 0x7000002a
> > > > #define SHT_MIPS_XHASH 0x7000002b
> > > >
> > > > /* Legal values for sh_flags field of Elf32_Shdr. */
> > > > @@ -1931,10 +1980,68 @@ typedef struct
> > > > #define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */
> > > > #define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */
> > > > #define R_MIPS_GLOB_DAT 51
> > > > +#define R_MIPS_PC21_S2 60
> > > > +#define R_MIPS_PC26_S2 61
> > > > +#define R_MIPS_PC18_S3 62
> > > > +#define R_MIPS_PC19_S2 63
> > > > +#define R_MIPS_PCHI16 64
> > > > +#define R_MIPS_PCLO16 65
> > > > +#define R_MIPS16_26 100
> > > > +#define R_MIPS16_GPREL 101
> > > > +#define R_MIPS16_GOT16 102
> > > > +#define R_MIPS16_CALL16 103
> > > > +#define R_MIPS16_HI16 104
> > > > +#define R_MIPS16_LO16 105
> > > > +#define R_MIPS16_TLS_GD 106
> > > > +#define R_MIPS16_TLS_LDM 107
> > > > +#define R_MIPS16_TLS_DTPREL_HI16 108
> > > > +#define R_MIPS16_TLS_DTPREL_LO16 109
> > > > +#define R_MIPS16_TLS_GOTTPREL 110
> > > > +#define R_MIPS16_TLS_TPREL_HI16 111
> > > > +#define R_MIPS16_TLS_TPREL_LO16 112
> > > > +#define R_MIPS16_PC16_S1 113
> > > > #define R_MIPS_COPY 126
> > > > #define R_MIPS_JUMP_SLOT 127
> > > > +#define R_MIPS_RELATIVE 128
> > > > +#define R_MICROMIPS_26_S1 133
> > > > +#define R_MICROMIPS_HI16 134
> > > > +#define R_MICROMIPS_LO16 135
> > > > +#define R_MICROMIPS_GPREL16 136
> > > > +#define R_MICROMIPS_LITERAL 137
> > > > +#define R_MICROMIPS_GOT16 138
> > > > +#define R_MICROMIPS_PC7_S1 139
> > > > +#define R_MICROMIPS_PC10_S1 140
> > > > +#define R_MICROMIPS_PC16_S1 141
> > > > +#define R_MICROMIPS_CALL16 142
> > > > +#define R_MICROMIPS_GOT_DISP 145
> > > > +#define R_MICROMIPS_GOT_PAGE 146
> > > > +#define R_MICROMIPS_GOT_OFST 147
> > > > +#define R_MICROMIPS_GOT_HI16 148
> > > > +#define R_MICROMIPS_GOT_LO16 149
> > > > +#define R_MICROMIPS_SUB 150
> > > > +#define R_MICROMIPS_HIGHER 151
> > > > +#define R_MICROMIPS_HIGHEST 152
> > > > +#define R_MICROMIPS_CALL_HI16 153
> > > > +#define R_MICROMIPS_CALL_LO16 154
> > > > +#define R_MICROMIPS_SCN_DISP 155
> > > > +#define R_MICROMIPS_JALR 156
> > > > +#define R_MICROMIPS_HI0_LO16 157
> > > > +#define R_MICROMIPS_TLS_GD 162
> > > > +#define R_MICROMIPS_TLS_LDM 163
> > > > +#define R_MICROMIPS_TLS_DTPREL_HI16 164
> > > > +#define R_MICROMIPS_TLS_DTPREL_LO16 165
> > > > +#define R_MICROMIPS_TLS_GOTTPREL 166
> > > > +#define R_MICROMIPS_TLS_TPREL_HI16 169
> > > > +#define R_MICROMIPS_TLS_TPREL_LO16 170
> > > > +#define R_MICROMIPS_GPREL7_S2 172
> > > > +#define R_MICROMIPS_PC23_S2 173
> > > > +#define R_MIPS_PC32 248
> > > > +#define R_MIPS_EH 249
> > > > +#define R_MIPS_GNU_REL16_S2 250
> > > > +#define R_MIPS_GNU_VTINHERIT 253
> > > > +#define R_MIPS_GNU_VTENTRY 254
> > > > /* Keep this the last entry. */
> > > > -#define R_MIPS_NUM 128
> > > > +#define R_MIPS_NUM 255
> > > >
> > > > /* Legal values for p_type field of Elf32_Phdr. */
> > > >
> > > > @@ -2142,6 +2249,30 @@ typedef struct
> > > > /* Masks for the flags1 word of an ABI flags structure. */
> > > > #define MIPS_AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */
> > > >
> > > > +/* Object attribute tags. */
> > > > +enum
> > > > +{
> > > > + /* 0-3 are generic. */
> > > > +
> > > > + /* Floating-point ABI used by this object file. */
> > > > + Tag_GNU_MIPS_ABI_FP = 4,
> > > > +
> > > > + /* MSA ABI used by this object file. */
> > > > + Tag_GNU_MIPS_ABI_MSA = 8,
> > > > +};
> > > > +
> > > > +/* Object attribute values. */
> > > > +enum
> > > > +{
> > > > + /* Values defined for Tag_GNU_MIPS_ABI_MSA. */
> > > > +
> > > > + /* Not tagged or not using any ABIs affected by the differences. */
> > > > + Val_GNU_MIPS_ABI_MSA_ANY = 0,
> > > > +
> > > > + /* Using 128-bit MSA. */
> > > > + Val_GNU_MIPS_ABI_MSA_128 = 1,
> > > > +};
> > > > +
> > > > /* Object attribute values. */
> > > > enum
> > > > {
> > > > @@ -2161,8 +2292,11 @@ enum
> > > > Val_GNU_MIPS_ABI_FP_64 = 6,
> > > > /* Using -mips32r2 -mfp64 -mno-odd-spreg. */
> > > > Val_GNU_MIPS_ABI_FP_64A = 7,
> > > > + /* This is reserved for backward-compatibility with an earlier
> > > > + implementation of the MIPS NaN2008 functionality. */
> > > > + Val_GNU_MIPS_ABI_FP_NAN2008 = 8,
> > > > /* Maximum allocated FP ABI value. */
> > > > - Val_GNU_MIPS_ABI_FP_MAX = 7
> > > > + Val_GNU_MIPS_ABI_FP_MAX = 8
> > > > };
> > > >
> > > > /* HPPA specific definitions. */
> > > > --
> > > > 2.30.2
> > > >
> > >
  

Hi,
We can support MIPS machine, mail or provide remote access?
Thanks,
Ying
> From: "Andreas K. Huettel"<dilfridge@gentoo.org>
> Date:  Sat, Jul 22, 19:03
> Subject:  Re: [PATCH v6] MIPS: Sync elf.h from binutils
> To: "Ying Huang"<ying.huang@oss.cipunited.com>, "Mark Wielaard"<mark@klomp.org>
> Cc: "Maxim Kuvyrkov"<maxim.kuvyrkov@linaro.org>, "Libc-alpha"<libc-alpha@sourceware.org>, <yunqiang.su@oss.cipunited.com>
> Am Samstag, 22. Juli 2023, 11:37:41 CEST schrieb Mark Wielaard:
> > Hi,
> > 
> > On Tue, Jul 18, 2023 at 10:17:09AM +0800, Ying Huang wrote:
> > > ping
> > > 
> > > Because I did not have commit permissions,  could you help commit?
> > 
> > I am happy to commit this for you. But even though it is a constants
> > only patch at this point it should probably get an OK from Andreas,
> > the release manager.
> 
> OK from me, looks well-separated enough.
> Last feature add-on of the month. :o)
> 
> Oh and some MIPS machine testing would be great, see 
> https://sourceware.org/glibc/wiki/Release/2.38#MIPS
> (unfortunately all I have access to myself is qemu there).
> 
> -- 
> Andreas K. Hüttel
> dilfridge@gentoo.org
> Gentoo Linux developer
> (council, toolchain, base-system, perl, libreoffice)
  

On Sat, Jul 22, 2023 at 07:29:05PM +0800, 黄莺 wrote:
> We can support MIPS machine, mail or provide remote access?

There are also some MIPS machines in the GCC Compile Farm
https://cfarm.tetaneutral.net/machines/list/

But easiest is if you can look at one of the examples on the page:
https://sourceware.org/glibc/wiki/Release/2.38#Build_and_test_results
and reproduce that for your setup (mention git checkout commit, gcc,
binutils and kernel versions)

Then mail the trimmed testresults to this list and someone can add it
to the wiki (or give you wiki EditorGroup access).

Thanks,

Mark
  

Hi,

On 2023-07-22 13:02, Andreas K. Huettel via Libc-alpha wrote:
> Am Samstag, 22. Juli 2023, 11:37:41 CEST schrieb Mark Wielaard:
> > Hi,
> > 
> > On Tue, Jul 18, 2023 at 10:17:09AM +0800, Ying Huang wrote:
> > > ping
> > > 
> > > Because I did not have commit permissions,  could you help commit?
> > 
> > I am happy to commit this for you. But even though it is a constants
> > only patch at this point it should probably get an OK from Andreas,
> > the release manager.
> 
> OK from me, looks well-separated enough.
> Last feature add-on of the month. :o)
> 

Unfortunately this commit breaks building glibc on at list
mips64el-linux-gnuabi64, unless --disable-werror is used, due to
preprocessor redefinitions:

mips64el-linux-gnuabi64-gcc-13 -mabi=64 init-first.c -c -std=gnu11 -fgnu89-inline  -pipe -O2 -g -fdebug-prefix-map=/home/aurel32/glibc-2.38=. -Wall -Wwrite-strings -Wundef -Werror -fmerge-all-constants -frounding-math -fstack-protector-strong -fno-common -Wp,-U_FORTIFY_SOURCE -Wstrict-prototypes -Wold-style-definition -fmath-errno    -fPIE    -fno-stack-protector -DSTACK_PROTECTOR_LEVEL=0 -Wa,-execstack   -ftls-model=initial-exec   -isystem /home/aurel32/glibc-2.38/debian/include  -I../include -I/home/aurel32/glibc-2.38/build-tree/mips64el-libc/csu  -I/home/aurel32/glibc-2.38/build-tree/mips64el-libc  -I../sysdeps/unix/sysv/linux/mips/mips64/n64  -I../sysdeps/unix/sysv/linux/mips/mips64  -I../sysdeps/unix/sysv/linux/mips  -I../sysdeps/mips/nptl  -I../sysdeps/unix/sysv/linux/include -I../sysdeps/unix/sysv/linux  -I../sysdeps/nptl  -I../sysdeps/pthread  -I../sysdeps/gnu  -I../sysdeps/unix/inet  -I../sysdeps/unix/sysv  -I../sysdeps/unix/mips/mips64  -I../sysdeps/unix/mips  -I../sysdeps/unix  -I../sysdeps/posix  -I../sysdeps/mips/mips64/n64/fpu  -I../sysdeps/mips/mips64/n64  -I../sysdeps/mips/ieee754  -I../sysdeps/ieee754/ldbl-128  -I../sysdeps/mips/mips64  -I../sysdeps/ieee754/flt-32  -I../sysdeps/ieee754/dbl-64  -I../sysdeps/mips/include -I../sysdeps/mips  -I../sysdeps/wordsize-64  -I../sysdeps/mips/fpu  -I../sysdeps/ieee754  -I../sysdeps/generic  -I.. -I../libio -I. -nostdinc -isystem /usr/lib/gcc/mips64el-linux-gnuabi64/13/include -isystem /home/aurel32/glibc-2.38/debian/include -D_LIBC_REENTRANT -include /home/aurel32/glibc-2.38/build-tree/mips64el-libc/libc-modules.h -DMODULE_NAME=libc -include ../include/libc-symbols.h  -DPIC     -DTOP_NAMESPACE=glibc -o /home/aurel32/glibc-2.38/build-tree/mips64el-libc/csu/init-first.o -MD -MP -MF /home/aurel32/glibc-2.38/build-tree/mips64el-libc/csu/init-first.o.dt -MT /home/aurel32/glibc-2.38/build-tree/mips64el-libc/csu/init-first.o
In file included from ../sysdeps/gnu/ldsodefs.h:46,
                 from ../sysdeps/unix/sysv/linux/ldsodefs.h:25,
                 from ../sysdeps/unix/sysv/linux/mips/ldsodefs.h:22,
                 from init-first.c:29:
../sysdeps/mips/ldsodefs.h:128: error: "ELF64_MIPS_R_TYPE" redefined [-Werror]
  128 | #define ELF64_MIPS_R_TYPE(i) \
      | 
In file included from ../include/elf.h:2,
                 from ../sysdeps/mips/stackinfo.h:24,
                 from ../include/stackinfo.h:24,
                 from ../include/alloca.h:7,
                 from ../stdlib/stdlib.h:706,
                 from ../include/stdlib.h:16,
                 from init-first.c:20:
../elf/elf.h:681: note: this is the location of the previous definition
  681 | #define ELF64_MIPS_R_TYPE(i)            ((i) & 0xff)
      | 
cc1: all warnings being treated as errors
make[3]: *** [../o-iterator.mk:9: /home/aurel32/glibc-2.38/build-tree/mips64el-libc/csu/init-first.o] Error 1
make[3]: Leaving directory '/home/aurel32/glibc-2.38/csu'
make[2]: *** [Makefile:501: csu/subdir_lib] Error 2
make[2]: Leaving directory '/home/aurel32/glibc-2.38'
make[1]: *** [Makefile:9: all] Error 2
make[1]: Leaving directory '/home/aurel32/glibc-2.38/build-tree/mips64el-libc'


Regards
Aurelien
  

Am Samstag, 22. Juli 2023, 16:36:24 CEST schrieb Aurelien Jarno:
>
> > > I am happy to commit this for you. But even though it is a constants
> > > only patch at this point it should probably get an OK from Andreas,
> > > the release manager.
> > 
> > OK from me, looks well-separated enough.
> > Last feature add-on of the month. :o)
> > 
> 
> Unfortunately this commit breaks building glibc on at list
> mips64el-linux-gnuabi64, unless --disable-werror is used, due to
> preprocessor redefinitions:
> 

Ouch. Since we have only a few days left, I would like to avoid any
hotfixing here. 

Let's revert it for the moment and address the issues after the release.
  

Hi Andreas,

On Sat, Jul 22, 2023 at 04:42:17PM +0200, Andreas K. Huettel via Libc-alpha wrote:
> Am Samstag, 22. Juli 2023, 16:36:24 CEST schrieb Aurelien Jarno:
> >
> > > > I am happy to commit this for you. But even though it is a constants
> > > > only patch at this point it should probably get an OK from Andreas,
> > > > the release manager.
> > > 
> > > OK from me, looks well-separated enough.
> > > Last feature add-on of the month. :o)
> > > 
> > 
> > Unfortunately this commit breaks building glibc on at list
> > mips64el-linux-gnuabi64, unless --disable-werror is used, due to
> > preprocessor redefinitions:
> > 
> 
> Ouch. Since we have only a few days left, I would like to avoid any
> hotfixing here. 
> 
> Let's revert it for the moment and address the issues after the release.

Yeah, the fix is probably a simple well place #ifndef ELF64_MIPS_R_TYPE.
But given I don't have a mips64el-linux-gnuabi64 at hand so let
revert the commit for now and retry after 2.38 has been branched.

Cheers,

Mark
  

Mark Wielaard <mark@klomp.org> 于2023年7月22日周六 23:00写道：
>
> Hi Andreas,
>
> On Sat, Jul 22, 2023 at 04:42:17PM +0200, Andreas K. Huettel via Libc-alpha wrote:
> > Am Samstag, 22. Juli 2023, 16:36:24 CEST schrieb Aurelien Jarno:
> > >
> > > > > I am happy to commit this for you. But even though it is a constants
> > > > > only patch at this point it should probably get an OK from Andreas,
> > > > > the release manager.
> > > >
> > > > OK from me, looks well-separated enough.
> > > > Last feature add-on of the month. :o)
> > > >
> > >
> > > Unfortunately this commit breaks building glibc on at list
> > > mips64el-linux-gnuabi64, unless --disable-werror is used, due to
> > > preprocessor redefinitions:
> > >
> >
> > Ouch. Since we have only a few days left, I would like to avoid any
> > hotfixing here.
> >
> > Let's revert it for the moment and address the issues after the release.
>
> Yeah, the fix is probably a simple well place #ifndef ELF64_MIPS_R_TYPE.
> But given I don't have a mips64el-linux-gnuabi64 at hand so let
> revert the commit for now and retry after 2.38 has been branched.
>

Ohh, the definition of ELF64_MIPS_R_TYPE in ldsodefs.h, and ELF64_MIPS_R_TYPE is
different.

I think that we should sync the name between of them.

Proposal:
1. Define ELF64_MIPS_R_TYPE1, ELF64_MIPS_R_TYPE2,ELF64_MIPS_R_TYPE3 in elf/elf.h
    And let's sync it back to binutils.
2. Rename ELF64_MIPS_R_TYPE in ldsodefs.h to ELF64_MIPS_R_TYPE_ALL.
3. Left ELF64_MIPS_R_TYPE undefined, since it is ambiguous.

> Cheers,
>
> Mark
  

* Aurelien Jarno:

> Hi,
>
> On 2023-07-22 13:02, Andreas K. Huettel via Libc-alpha wrote:
>> Am Samstag, 22. Juli 2023, 11:37:41 CEST schrieb Mark Wielaard:
>> > Hi,
>> > 
>> > On Tue, Jul 18, 2023 at 10:17:09AM +0800, Ying Huang wrote:
>> > > ping
>> > > 
>> > > Because I did not have commit permissions,  could you help commit?
>> > 
>> > I am happy to commit this for you. But even though it is a constants
>> > only patch at this point it should probably get an OK from Andreas,
>> > the release manager.
>> 
>> OK from me, looks well-separated enough.
>> Last feature add-on of the month. :o)
>> 
>
> Unfortunately this commit breaks building glibc on at list
> mips64el-linux-gnuabi64, unless --disable-werror is used, due to
> preprocessor redefinitions:

I was wondering if this is caught by build-many-glibcs.py, and it
actually is, on all MIPS targets.

We do not have a requirement to run build-many-glibcs.py (our
cross-building script); I merely wanted to check if there is a gap in
the tool that needs to be addressed.

Thanks,
Florian
  

On 24/07/23 08:39, Florian Weimer via Libc-alpha wrote:
> * Aurelien Jarno:
> 
>> Hi,
>>
>> On 2023-07-22 13:02, Andreas K. Huettel via Libc-alpha wrote:
>>> Am Samstag, 22. Juli 2023, 11:37:41 CEST schrieb Mark Wielaard:
>>>> Hi,
>>>>
>>>> On Tue, Jul 18, 2023 at 10:17:09AM +0800, Ying Huang wrote:
>>>>> ping
>>>>>
>>>>> Because I did not have commit permissions,  could you help commit?
>>>>
>>>> I am happy to commit this for you. But even though it is a constants
>>>> only patch at this point it should probably get an OK from Andreas,
>>>> the release manager.
>>>
>>> OK from me, looks well-separated enough.
>>> Last feature add-on of the month. :o)
>>>
>>
>> Unfortunately this commit breaks building glibc on at list
>> mips64el-linux-gnuabi64, unless --disable-werror is used, due to
>> preprocessor redefinitions:
> 
> I was wondering if this is caught by build-many-glibcs.py, and it
> actually is, on all MIPS targets.

It was triggered with a simple mips build for any triple, most likely
submitter used --disable-werror and did not check the warnings.

Maybe we need to enforce --disable-werror for now on, I have checked
the build with different gcc version and besides a couple of failure
it does seems fine for most architectures.

> 
> We do not have a requirement to run build-many-glibcs.py (our
> cross-building script); I merely wanted to check if there is a gap in
> the tool that needs to be addressed.
> 
> Thanks,
> Florian
>
  

On Sat, 22 Jul 2023, Mark Wielaard wrote:

> > Let's revert it for the moment and address the issues after the release.
> 
> Yeah, the fix is probably a simple well place #ifndef ELF64_MIPS_R_TYPE.

 Just #undef any conflicting macros just as with ELF64_R_SYM, etc. right 
below and then remove local duplicates, as this is all internal stuff.  I 
think it helps when submissions are verified before sending, it saves many 
people hassle.

  Maciej