diff mbox series

[v7,1/2] x86: Add comment explaining no Slow_SSE4_2 check in ifunc-sse4_2

Message ID 20220704042807.3863553-1-goldstein.w.n@gmail.com
State Committed
Commit baeae86fb8ccd85b6bf9b5091884fa9b66d84a99
Headers
Series [v7,1/2] x86: Add comment explaining no Slow_SSE4_2 check in ifunc-sse4_2 |

Checks

Context Check Description
dj/TryBot-apply_patch success Patch applied to master at the time it was sent

Commit Message

Noah Goldstein July 4, 2022, 4:28 a.m. UTC 
  Just for clarities sake and so that if a future implementation is
added we remember to add the check.
---
 sysdeps/x86_64/multiarch/ifunc-sse4_2.h | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

H.J. Lu July 5, 2022, 3:41 p.m. UTC | #1 
On Sun, Jul 3, 2022 at 9:28 PM Noah Goldstein <goldstein.w.n@gmail.com> wrote:
>
> Just for clarities sake and so that if a future implementation is
> added we remember to add the check.
> ---
>  sysdeps/x86_64/multiarch/ifunc-sse4_2.h | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> index ee36525bcf..f8b56936ec 100644
> --- a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> +++ b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
> @@ -27,6 +27,12 @@ IFUNC_SELECTOR (void)
>  {
>    const struct cpu_features* cpu_features = __get_cpu_features ();
>
> +  /* This function uses the `pcmpstri` sse4.2 instruction which can be
> +     slow on some CPUs.  This normally would be guarded by a
> +     Slow_SSE4_2 check, but since there is no other optimized
> +     implementation its best to keep it regardless.  If an optimized
> +     fallback is added add a X86_ISA_CPU_FEATURE_ARCH_P (cpu_features,
> +     Slow_SSE4_2) check.  */
>    if (CPU_FEATURE_USABLE_P (cpu_features, SSE4_2))
>      return OPTIMIZE (sse42);
>
> --
> 2.34.1
>

LGTM.

Thanks.
diff mbox series

Patch

diff --git a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
index ee36525bcf..f8b56936ec 100644
--- a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
+++ b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h
@@ -27,6 +27,12 @@  IFUNC_SELECTOR (void)
 {
   const struct cpu_features* cpu_features = __get_cpu_features ();
 
+  /* This function uses the `pcmpstri` sse4.2 instruction which can be
+     slow on some CPUs.  This normally would be guarded by a
+     Slow_SSE4_2 check, but since there is no other optimized
+     implementation its best to keep it regardless.  If an optimized
+     fallback is added add a X86_ISA_CPU_FEATURE_ARCH_P (cpu_features,
+     Slow_SSE4_2) check.  */
   if (CPU_FEATURE_USABLE_P (cpu_features, SSE4_2))
     return OPTIMIZE (sse42);