Check the HTT bit before counting logical threads
Commit Message
Skip counting logical threads for Intel processors if the HTT bit is 0
which indicates there is only a single logical processor.
Tested on x86. Any comments, feedbacks?
H.J.
---
* sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting
logical threads if the HTT bit is 0.
* sysdeps/x86/cpu-features.h (bit_cpu_HTT): New.
(index_cpu_HTT): Likewise.
(reg_HTT): Likewise.
---
sysdeps/x86/cacheinfo.c | 6 ++++++
sysdeps/x86/cpu-features.h | 3 +++
2 files changed, 9 insertions(+)
Comments
"H.J. Lu" <hongjiu.lu@intel.com> writes:
> diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
> index 8408624..09113ba 100644
> --- a/sysdeps/x86/cacheinfo.c
> +++ b/sysdeps/x86/cacheinfo.c
> @@ -506,6 +506,11 @@ init_cacheinfo (void)
> shared = core;
> }
>
> + /* A value of 0 for the HTT bit indicates there is only a single
> + logical processor. */
> + if (!HAS_CPU_FEATURE (HTT))
> + goto intel_no_threads;
Why goto?
Andreas.
On Tue, May 17, 2016 at 11:35 AM, Andreas Schwab <schwab@linux-m68k.org> wrote:
> "H.J. Lu" <hongjiu.lu@intel.com> writes:
>
>> diff --git a/sysdeps/x86/cacheinfo.c b/sysdeps/x86/cacheinfo.c
>> index 8408624..09113ba 100644
>> --- a/sysdeps/x86/cacheinfo.c
>> +++ b/sysdeps/x86/cacheinfo.c
>> @@ -506,6 +506,11 @@ init_cacheinfo (void)
>> shared = core;
>> }
>>
>> + /* A value of 0 for the HTT bit indicates there is only a single
>> + logical processor. */
>> + if (!HAS_CPU_FEATURE (HTT))
>> + goto intel_no_threads;
>
> Why goto?
>
I want to keep the change as small as possible. I can convert goto
now, later or never. I don't have a preference on it.
@@ -506,6 +506,11 @@ init_cacheinfo (void)
shared = core;
}
+ /* A value of 0 for the HTT bit indicates there is only a single
+ logical processor. */
+ if (!HAS_CPU_FEATURE (HTT))
+ goto intel_no_threads;
+
/* Figure out the number of logical threads that share the
highest cache level. */
if (max_cpuid >= 4)
@@ -594,6 +599,7 @@ init_cacheinfo (void)
>> 16) & 0xff);
}
+intel_no_threads:
/* Cap usage of highest cache level to the number of supported
threads. */
if (shared > 0 && threads > 0)
@@ -51,6 +51,7 @@
#define bit_cpu_POPCOUNT (1 << 23)
#define bit_cpu_FMA (1 << 12)
#define bit_cpu_FMA4 (1 << 16)
+#define bit_cpu_HTT (1 << 28)
/* COMMON_CPUID_INDEX_7. */
#define bit_cpu_ERMS (1 << 9)
@@ -235,6 +236,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define index_cpu_FMA4 COMMON_CPUID_INDEX_80000001
# define index_cpu_POPCOUNT COMMON_CPUID_INDEX_1
# define index_cpu_OSXSAVE COMMON_CPUID_INDEX_1
+# define index_cpu_HTT COMMON_CPUID_INDEX_1
# define reg_CX8 edx
# define reg_CMOV edx
@@ -252,6 +254,7 @@ extern const struct cpu_features *__get_cpu_features (void)
# define reg_FMA4 ecx
# define reg_POPCOUNT ecx
# define reg_OSXSAVE ecx
+# define reg_HTT edx
# define index_arch_Fast_Rep_String FEATURE_INDEX_1
# define index_arch_Fast_Copy_Backward FEATURE_INDEX_1