[v3] sim: riscv: Fix some compatibility issues with gcc
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Commit Message
This makes the riscv simulator able to execute a simple
"hello world" program when gcc is configured
with:
.../gcc-trunk/configure --target=riscv-unknown-elf
The first problem is that gcc generates rv32
code by default in this configuration, while
riscv64-unknown-elf generates rv64 code by default.
Note that using the command line argument
--architecture riscv:rv32 is not really working,
because compile-time constants like
WITH_TARGET_WORD_BITSIZE and architecture dependent
types like unsigned_word are used everywhere.
So change the riscv/acinclude.m4 to use the same
logic here, and disable selecting non-working
architectures per command line argument.
The second issue is that gcc does by default
generate instructions in INSN_CLASS_C, so move
the M(GC) to top of list, in riscv/model_list.def.
This changes the default cpu-model to include the
class c instructions when no --model command line
argument is used.
With these changes a simple C-program can be executed,
however there is still work to do, since when the
program does floating point operations, gcc starts to
generate hardware floating point instructions, with no
obvious opt-out option.
Note the gcc test suite can be used to test the
simulator in this way:
make check-gcc RUNTESTFLAGS="--target_board=multi-sim SIM=riscv-unknown-elf-run"
Now many tests are passed, except those which use
floating point instructions.
To work around the not supported float instructions the
following gcc configuration can be used, which makes
most of the gcc test cases successfully executed:
.../gcc-trunk/configure --prefix=... --target=riscv-unknown-elf
--disable-multilib --with-arch=rv32imac --with-abi=ilp32
Note: binutils are installed at prefix path and newlib/libgloss in-tree.
---
sim/configure | 6 +++---
sim/riscv/acinclude.m4 | 4 ++--
sim/riscv/machs.c | 2 +-
sim/riscv/model_list.def | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
v2: updated the commit message, with some hints
how to compile a compatible gcc toolchain.
v3: addressed review commments, disable non-working
--architecture command line options, split out the fix
for class-c instructions.
@@ -17479,10 +17479,10 @@ $as_echo "$sim_ppc_xor_endian" >&6; }
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking riscv bitsize" >&5
$as_echo_n "checking riscv bitsize... " >&6; }
-SIM_RISCV_BITSIZE=64
+SIM_RISCV_BITSIZE=32
case $target in #(
- riscv32*) :
- SIM_RISCV_BITSIZE=32 ;; #(
+ riscv64*) :
+ SIM_RISCV_BITSIZE=64 ;; #(
*) :
;;
esac
@@ -15,8 +15,8 @@ dnl along with this program. If not, see <http://www.gnu.org/licenses/>.
dnl
dnl NB: This file is included in sim/configure, so keep settings namespaced.
AC_MSG_CHECKING([riscv bitsize])
-SIM_RISCV_BITSIZE=64
+SIM_RISCV_BITSIZE=32
AS_CASE([$target],
- [riscv32*], [SIM_RISCV_BITSIZE=32])
+ [riscv64*], [SIM_RISCV_BITSIZE=64])
AC_MSG_RESULT([$SIM_RISCV_BITSIZE])
AC_SUBST(SIM_RISCV_BITSIZE)
@@ -120,7 +120,7 @@ const SIM_MACH * const riscv_sim_machs[] =
#if WITH_TARGET_WORD_BITSIZE >= 64
&rv64i_mach,
#endif
-#if WITH_TARGET_WORD_BITSIZE >= 32
+#if WITH_TARGET_WORD_BITSIZE == 32
&rv32i_mach,
#endif
NULL
@@ -1,9 +1,9 @@
+M(GC)
M(G)
M(I)
M(IM)
M(IMA)
M(IA)
-M(GC)
M(IC)
M(IMC)
M(IMAC)