diff mbox series

sim: riscv: Fix newlib issue with brk syscall

Message ID AS8P193MB12855E12BC95017B57DEA868E4062@AS8P193MB1285.EURP193.PROD.OUTLOOK.COM
State New
Headers
Series sim: riscv: Fix newlib issue with brk syscall |

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Commit Message

Bernd Edlinger April 10, 2024, 7:17 a.m. UTC 
  There is an issue with riscv newlib which uses
a brk syscall when malloc is used, and when
this syscall is not implemented, the malloc fails.
This adds a simple handling for this syscall
in order to make newlib happy.
---
 sim/riscv/sim-main.c | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Andrew Burgess April 12, 2024, 10:55 a.m. UTC | #1 
Bernd Edlinger <bernd.edlinger@hotmail.de> writes:

> There is an issue with riscv newlib which uses
> a brk syscall when malloc is used, and when
> this syscall is not implemented, the malloc fails.
> This adds a simple handling for this syscall
> in order to make newlib happy.
> ---
>  sim/riscv/sim-main.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
> index 9c0d070aa60..4e3672505c6 100644
> --- a/sim/riscv/sim-main.c
> +++ b/sim/riscv/sim-main.c
> @@ -30,6 +30,7 @@
>  #include "sim-main.h"
>  #include "sim-signal.h"
>  #include "sim-syscall.h"
> +#include "target-newlib-syscall.h"
>  
>  #include "opcode/riscv.h"
>  
> @@ -629,6 +630,14 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>        break;
>      case MATCH_ECALL:
>        TRACE_INSN (cpu, "ecall;");
> +      if (riscv_cpu->a7 == TARGET_NEWLIB_RISCV_SYS_brk)
> +	{
> +	  TRACE_SYSCALL (cpu, "brk[%i](%#lx)", TARGET_NEWLIB_RISCV_SYS_brk,
> +			 (long)riscv_cpu->a0);
> +	  if (riscv_cpu->a0 == 0)
> +	    riscv_cpu->a0 = DEFAULT_MEM_SIZE / 2;
> +	  break;
> +	}

This doesn't seem like the right solution.  I would have expected some
changes in sim/common/syscall.c in the function cb_syscall.  This would
mean that the syscall would be handled via the sim_syscall call below.

Thanks,
Andrew

>        riscv_cpu->a0 = sim_syscall (cpu, riscv_cpu->a7, riscv_cpu->a0,
>  				   riscv_cpu->a1, riscv_cpu->a2, riscv_cpu->a3);
>        break;
> -- 
> 2.25.1
Bernd Edlinger April 12, 2024, 11:41 a.m. UTC | #2 
On 4/12/24 12:55, Andrew Burgess wrote:
> Bernd Edlinger <bernd.edlinger@hotmail.de> writes:
> 
>> There is an issue with riscv newlib which uses
>> a brk syscall when malloc is used, and when
>> this syscall is not implemented, the malloc fails.
>> This adds a simple handling for this syscall
>> in order to make newlib happy.
>> ---
>>  sim/riscv/sim-main.c | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
>> index 9c0d070aa60..4e3672505c6 100644
>> --- a/sim/riscv/sim-main.c
>> +++ b/sim/riscv/sim-main.c
>> @@ -30,6 +30,7 @@
>>  #include "sim-main.h"
>>  #include "sim-signal.h"
>>  #include "sim-syscall.h"
>> +#include "target-newlib-syscall.h"
>>  
>>  #include "opcode/riscv.h"
>>  
>> @@ -629,6 +630,14 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
>>        break;
>>      case MATCH_ECALL:
>>        TRACE_INSN (cpu, "ecall;");
>> +      if (riscv_cpu->a7 == TARGET_NEWLIB_RISCV_SYS_brk)
>> +	{
>> +	  TRACE_SYSCALL (cpu, "brk[%i](%#lx)", TARGET_NEWLIB_RISCV_SYS_brk,
>> +			 (long)riscv_cpu->a0);
>> +	  if (riscv_cpu->a0 == 0)
>> +	    riscv_cpu->a0 = DEFAULT_MEM_SIZE / 2;
>> +	  break;
>> +	}
> 
> This doesn't seem like the right solution.  I would have expected some
> changes in sim/common/syscall.c in the function cb_syscall.  This would
> mean that the syscall would be handled via the sim_syscall call below.
> 

This is the only target that would need such a quirk, in the newlib
this was introduced for compatibility with qemu, (but funny thing the
fopen syscall from newlib does not work with qemu :) but I have not seen a
way to configure a callback from inside sim_syscall for such target-
specific thing.  I just saw similar things in sim/bfin/interp.c
where a CB_SYS_mmap2 had to be implemented and apparently the complete
sim_syscall was cloned into bfin_syscall which looked more ugly than this.
From there I took the idea to start the dynamic memory area at
DEFAULT_MEM_SIZE / 2, which I also just did because I have not seen
an easy way to find the end of the data segment.


Thanks
Bernd.

> Thanks,
> Andrew
> 
>>        riscv_cpu->a0 = sim_syscall (cpu, riscv_cpu->a7, riscv_cpu->a0,
>>  				   riscv_cpu->a1, riscv_cpu->a2, riscv_cpu->a3);
>>        break;
>> -- 
>> 2.25.1
>
diff mbox series

Patch

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 9c0d070aa60..4e3672505c6 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -30,6 +30,7 @@ 
 #include "sim-main.h"
 #include "sim-signal.h"
 #include "sim-syscall.h"
+#include "target-newlib-syscall.h"
 
 #include "opcode/riscv.h"
 
@@ -629,6 +630,14 @@  execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_ECALL:
       TRACE_INSN (cpu, "ecall;");
+      if (riscv_cpu->a7 == TARGET_NEWLIB_RISCV_SYS_brk)
+	{
+	  TRACE_SYSCALL (cpu, "brk[%i](%#lx)", TARGET_NEWLIB_RISCV_SYS_brk,
+			 (long)riscv_cpu->a0);
+	  if (riscv_cpu->a0 == 0)
+	    riscv_cpu->a0 = DEFAULT_MEM_SIZE / 2;
+	  break;
+	}
       riscv_cpu->a0 = sim_syscall (cpu, riscv_cpu->a7, riscv_cpu->a0,
 				   riscv_cpu->a1, riscv_cpu->a2, riscv_cpu->a3);
       break;