diff mbox

sim: move sim-engine.o/sim-hrw.o to the common list

Message ID 86d23cuzex.fsf@gmail.com
State Rejected
Headers

Commit Message

Yao Qi April 10, 2015, 9:04 a.m. UTC 
  Mike Frysinger <vapier@gentoo.org> writes:

> This makes these two objects available to all sims by default.

Hi Mike,
How about the patch below which unbreaks the sim build for
arm-none-eabi and mips-elf target?

Comments

Mike Frysinger April 12, 2015, 9:55 a.m. UTC | #1 
On 10 Apr 2015 10:04, Yao Qi wrote:
> This patch breaks the sim build for some targets, such as arm-none-eabi
> and mips-elf.
> 
>   [PATCH] sim: move sim-engine.o/sim-hrw.o to the common list
>   https://sourceware.org/ml/gdb-patches/2015-04/msg00178.html
> 
> Looks sim-engine.o is common to all targets, but sim-hrw.o isn't.  This
> patch is to move sim-hrw.o out of SIM_NEW_COMMON_OBJS, and put it back
> to each target which needs it.

the intention is to build all of common/ all the time and discourage targets
from writing their own sim_xxx funcs.  even if that means the object doesn't
get used.  i've landed a different change in the tree now which should fix
arm & mips.
-mike
diff mbox

Patch

diff --git a/sim/avr/Makefile.in b/sim/avr/Makefile.in
index d7b77d0..1fcce22 100644
--- a/sim/avr/Makefile.in
+++ b/sim/avr/Makefile.in
@@ -21,6 +21,7 @@  SIM_OBJS = \
 	interp.o \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-reason.o \
 	sim-resume.o \
 	sim-stop.o
diff --git a/sim/bfin/Makefile.in b/sim/bfin/Makefile.in
index 38531a9..8dfb731 100644
--- a/sim/bfin/Makefile.in
+++ b/sim/bfin/Makefile.in
@@ -29,6 +29,7 @@  SIM_OBJS = \
 	machs.o \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-model.o \
 	sim-reason.o \
 	sim-reg.o \
diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in
index 50db255..f2bff38 100644
--- a/sim/common/Make-common.in
+++ b/sim/common/Make-common.in
@@ -180,7 +180,6 @@  SIM_NEW_COMMON_OBJS = \
 	sim-engine.o \
 	sim-events.o \
 	sim-fpu.o \
-	sim-hrw.o \
 	sim-io.o \
 	sim-info.o \
 	sim-load.o \
diff --git a/sim/cris/Makefile.in b/sim/cris/Makefile.in
index 5459c0e..fe0191a 100644
--- a/sim/cris/Makefile.in
+++ b/sim/cris/Makefile.in
@@ -25,6 +25,7 @@  CRISV32F_OBJS = crisv32f.o cpuv32.o decodev32.o modelv32.o mloopv32f.o
 SIM_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
 	sim-cpu.o \
+	sim-hrw.o \
 	sim-model.o \
 	sim-reg.o \
 	cgen-utils.o cgen-trace.o cgen-scache.o \
diff --git a/sim/frv/Makefile.in b/sim/frv/Makefile.in
index 415d2ab..b5b3512 100644
--- a/sim/frv/Makefile.in
+++ b/sim/frv/Makefile.in
@@ -23,6 +23,7 @@  SIM_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-model.o \
 	sim-reg.o \
 	cgen-utils.o cgen-trace.o cgen-scache.o cgen-fpu.o cgen-accfp.o \
diff --git a/sim/iq2000/Makefile.in b/sim/iq2000/Makefile.in
index 3e07c53..8ed0e6c 100644
--- a/sim/iq2000/Makefile.in
+++ b/sim/iq2000/Makefile.in
@@ -23,6 +23,7 @@  SIM_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-model.o \
 	sim-reg.o \
 	cgen-utils.o cgen-trace.o cgen-scache.o \
diff --git a/sim/lm32/Makefile.in b/sim/lm32/Makefile.in
index ea2dd2d..ef87bea 100644
--- a/sim/lm32/Makefile.in
+++ b/sim/lm32/Makefile.in
@@ -8,6 +8,7 @@  SIM_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-model.o \
 	sim-reg.o \
 	sim-signal.o \
diff --git a/sim/m32r/Makefile.in b/sim/m32r/Makefile.in
index 8f134f3..e1c2d88 100644
--- a/sim/m32r/Makefile.in
+++ b/sim/m32r/Makefile.in
@@ -28,6 +28,7 @@  SIM_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-model.o \
 	sim-reg.o \
 	cgen-utils.o cgen-trace.o cgen-scache.o \
diff --git a/sim/m68hc11/Makefile.in b/sim/m68hc11/Makefile.in
index 9b931a1..ea52d9b 100644
--- a/sim/m68hc11/Makefile.in
+++ b/sim/m68hc11/Makefile.in
@@ -25,6 +25,7 @@  SIM_OBJS = $(M68HC11_OBJS) \
 	sim-load.o \
 	sim-hload.o \
 	sim-stop.o \
+	sim-hrw.o \
 	sim-reason.o
 
 SIM_PROFILE= -DPROFILE=1 -DWITH_PROFILE=-1
diff --git a/sim/mn10300/Makefile.in b/sim/mn10300/Makefile.in
index a85d932..275d378 100644
--- a/sim/mn10300/Makefile.in
+++ b/sim/mn10300/Makefile.in
@@ -22,6 +22,7 @@  MN10300_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
 	op_utils.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-resume.o \
 	sim-reason.o \
 	sim-stop.o
diff --git a/sim/moxie/Makefile.in b/sim/moxie/Makefile.in
index ff6bed9..ec83601 100644
--- a/sim/moxie/Makefile.in
+++ b/sim/moxie/Makefile.in
@@ -24,6 +24,7 @@  SIM_OBJS = \
 	interp.o \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-reason.o \
 	sim-resume.o \
 	sim-stop.o
diff --git a/sim/msp430/Makefile.in b/sim/msp430/Makefile.in
index 3ab384f..3076312 100644
--- a/sim/msp430/Makefile.in
+++ b/sim/msp430/Makefile.in
@@ -30,6 +30,7 @@  SIM_OBJS = \
 	trace.o \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-reason.o \
 	sim-reg.o \
 	sim-resume.o \
diff --git a/sim/sh64/Makefile.in b/sim/sh64/Makefile.in
index 19c9957..5747343 100644
--- a/sim/sh64/Makefile.in
+++ b/sim/sh64/Makefile.in
@@ -25,6 +25,7 @@  SIM_OBJS = \
 	$(SIM_NEW_COMMON_OBJS) \
 	sim-cpu.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-model.o \
 	sim-reg.o \
 	cgen-utils.o cgen-trace.o cgen-scache.o \
diff --git a/sim/v850/Makefile.in b/sim/v850/Makefile.in
index 726ed5e..af9cf47 100644
--- a/sim/v850/Makefile.in
+++ b/sim/v850/Makefile.in
@@ -24,6 +24,7 @@  SIM_OBJS = \
 	simops.o interp.o \
 	itable.o semantics.o idecode.o icache.o engine.o irun.o support.o \
 	sim-hload.o \
+	sim-hrw.o \
 	sim-resume.o \
 	sim-reason.o \
 	sim-stop.o