diff mbox series

[1/2] RISC-V: Add reference to Zve32*

Message ID 4dfb6749640b5ffc2280468cddd4f378415f0118.1691745446.git.research_trasio@irq.a4lg.com
State New
Headers
Series [1/2] RISC-V: Add reference to Zve32* |

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Commit Message

Tsukasa OI Aug. 11, 2023, 9:17 a.m. UTC 
  From: Tsukasa OI <research_trasio@irq.a4lg.com>

Before actual xlen handling, this commit fixes its description to allow xlen
less than 16 (but 4 or greater), to support vector subset extensions for
embedded environment ('Zve32*').
---
 gdb/arch/riscv.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)


base-commit: cca56b22a33bc279db358adca68f704329e5f0a3

Comments

Andrew Burgess Aug. 11, 2023, 12:40 p.m. UTC | #1 
Tsukasa OI <research_trasio@irq.a4lg.com> writes:

> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> Before actual xlen handling, this commit fixes its description to allow xlen
> less than 16 (but 4 or greater), to support vector subset extensions for
> embedded environment ('Zve32*').

I think you mean vlen instead of xlen in this commit message.

With that fixed this commit (1/2) is:

Approved-By: Andrew Burgess <aburgess@redhat.com>

Thanks,
Andrew


> ---
>  gdb/arch/riscv.h | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
> index 54610ed6c16b..d5ea1a55b214 100644
> --- a/gdb/arch/riscv.h
> +++ b/gdb/arch/riscv.h
> @@ -47,9 +47,10 @@ struct riscv_gdbarch_features
>    int flen = 0;
>  
>    /* The size of the v-registers in bytes.  The value 0 indicates a target
> -     with no vector registers.  The minimum value for a standard compliant
> -     target should be 16, but GDB doesn't currently mind, and will accept
> -     any vector size.  */
> +     with no vector registers.  The minimum value for a 'V'-extension compliant
> +     target should be 16 and 4 for an embedded subset compliant target (with
> +     'Zve32*' extension), but GDB doesn't currently mind, and will accept any
> +     vector size.  */
>    int vlen = 0;
>  
>    /* When true this target is RV32E.  */
>
> base-commit: cca56b22a33bc279db358adca68f704329e5f0a3
> -- 
> 2.41.0
diff mbox series

Patch

diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index 54610ed6c16b..d5ea1a55b214 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -47,9 +47,10 @@  struct riscv_gdbarch_features
   int flen = 0;
 
   /* The size of the v-registers in bytes.  The value 0 indicates a target
-     with no vector registers.  The minimum value for a standard compliant
-     target should be 16, but GDB doesn't currently mind, and will accept
-     any vector size.  */
+     with no vector registers.  The minimum value for a 'V'-extension compliant
+     target should be 16 and 4 for an embedded subset compliant target (with
+     'Zve32*' extension), but GDB doesn't currently mind, and will accept any
+     vector size.  */
   int vlen = 0;
 
   /* When true this target is RV32E.  */