diff mbox series

[v2] gdb: Add XMM16-XMM31 and K0-K1 DWARF register number mapping

Message ID 20240214154012.32319-1-hjl.tools@gmail.com
State New
Headers
Series [v2] gdb: Add XMM16-XMM31 and K0-K1 DWARF register number mapping |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gdb_build--master-aarch64 success Testing passed
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Commit Message

H.J. Lu Feb. 14, 2024, 3:40 p.m. UTC 
  Changes in v2:

1. Remove UTF-8 encoding.

---
Add XMM16-XMM31 and K0-K1 DWARF register number mapping to
amd64_dwarf_regmap.
---
 gdb/amd64-tdep.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

Comments

Willgerodt, Felix Feb. 21, 2024, 8:33 a.m. UTC | #1 
> -----Original Message-----
> From: H.J. Lu <hjl.tools@gmail.com>
> Sent: Mittwoch, 14. Februar 2024 16:40
> To: gdb-patches@sourceware.org
> Cc: Willgerodt, Felix <felix.willgerodt@intel.com>
> Subject: [PATCH v2] gdb: Add XMM16-XMM31 and K0-K1 DWARF register number
> mapping
> 
> Changes in v2:
> 
> 1. Remove UTF-8 encoding.
> 
> ---
> Add XMM16-XMM31 and K0-K1 DWARF register number mapping to
> amd64_dwarf_regmap.
> ---
>  gdb/amd64-tdep.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
> index a8ff9246b8a..b6ff1c67a86 100644
> --- a/gdb/amd64-tdep.c
> +++ b/gdb/amd64-tdep.c
> @@ -235,7 +235,28 @@ static int amd64_dwarf_regmap[] =
>    /* Floating Point Control Registers.  */
>    AMD64_MXCSR_REGNUM,
>    AMD64_FCTRL_REGNUM,
> -  AMD64_FSTAT_REGNUM
> +  AMD64_FSTAT_REGNUM,
> +
> +  /* XMM16-XMM31.  */
> +  AMD64_XMM16_REGNUM + 0, AMD64_XMM16_REGNUM + 1,
> +  AMD64_XMM16_REGNUM + 2, AMD64_XMM16_REGNUM + 3,
> +  AMD64_XMM16_REGNUM + 4, AMD64_XMM16_REGNUM + 5,
> +  AMD64_XMM16_REGNUM + 6, AMD64_XMM16_REGNUM + 7,
> +  AMD64_XMM16_REGNUM + 8, AMD64_XMM16_REGNUM + 9,
> +  AMD64_XMM16_REGNUM + 10, AMD64_XMM16_REGNUM + 11,
> +  AMD64_XMM16_REGNUM + 12, AMD64_XMM16_REGNUM + 13,
> +  AMD64_XMM16_REGNUM + 14, AMD64_XMM16_REGNUM + 15,
> +
> +  /* Reserved.  */
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> +
> +  /* Mask Registers.  */
> +  AMD64_K0_REGNUM + 0, AMD64_K0_REGNUM + 1,
> +  AMD64_K0_REGNUM + 2, AMD64_K0_REGNUM + 3,
> +  AMD64_K0_REGNUM + 4, AMD64_K0_REGNUM + 5,
> +  AMD64_K0_REGNUM + 6, AMD64_K0_REGNUM + 7
>  };
> 
>  static const int amd64_dwarf_regmap_len =
> --
> 2.43.0


While I can't approve, this looks good to me.

Reviewed-By: Felix Willgerodt <felix.willgerodt@intel.com>

Thanks,
Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de <http://www.intel.de>
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
H.J. Lu Feb. 21, 2024, 9:21 p.m. UTC | #2 
On Wed, Feb 21, 2024 at 12:33 AM Willgerodt, Felix
<felix.willgerodt@intel.com> wrote:
>
> > -----Original Message-----
> > From: H.J. Lu <hjl.tools@gmail.com>
> > Sent: Mittwoch, 14. Februar 2024 16:40
> > To: gdb-patches@sourceware.org
> > Cc: Willgerodt, Felix <felix.willgerodt@intel.com>
> > Subject: [PATCH v2] gdb: Add XMM16-XMM31 and K0-K1 DWARF register number
> > mapping
> >
> > Changes in v2:
> >
> > 1. Remove UTF-8 encoding.
> >
> > ---
> > Add XMM16-XMM31 and K0-K1 DWARF register number mapping to
> > amd64_dwarf_regmap.
> > ---
> >  gdb/amd64-tdep.c | 23 ++++++++++++++++++++++-
> >  1 file changed, 22 insertions(+), 1 deletion(-)
> >
> > diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
> > index a8ff9246b8a..b6ff1c67a86 100644
> > --- a/gdb/amd64-tdep.c
> > +++ b/gdb/amd64-tdep.c
> > @@ -235,7 +235,28 @@ static int amd64_dwarf_regmap[] =
> >    /* Floating Point Control Registers.  */
> >    AMD64_MXCSR_REGNUM,
> >    AMD64_FCTRL_REGNUM,
> > -  AMD64_FSTAT_REGNUM
> > +  AMD64_FSTAT_REGNUM,
> > +
> > +  /* XMM16-XMM31.  */
> > +  AMD64_XMM16_REGNUM + 0, AMD64_XMM16_REGNUM + 1,
> > +  AMD64_XMM16_REGNUM + 2, AMD64_XMM16_REGNUM + 3,
> > +  AMD64_XMM16_REGNUM + 4, AMD64_XMM16_REGNUM + 5,
> > +  AMD64_XMM16_REGNUM + 6, AMD64_XMM16_REGNUM + 7,
> > +  AMD64_XMM16_REGNUM + 8, AMD64_XMM16_REGNUM + 9,
> > +  AMD64_XMM16_REGNUM + 10, AMD64_XMM16_REGNUM + 11,
> > +  AMD64_XMM16_REGNUM + 12, AMD64_XMM16_REGNUM + 13,
> > +  AMD64_XMM16_REGNUM + 14, AMD64_XMM16_REGNUM + 15,
> > +
> > +  /* Reserved.  */
> > +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> > +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> > +  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
> > +
> > +  /* Mask Registers.  */
> > +  AMD64_K0_REGNUM + 0, AMD64_K0_REGNUM + 1,
> > +  AMD64_K0_REGNUM + 2, AMD64_K0_REGNUM + 3,
> > +  AMD64_K0_REGNUM + 4, AMD64_K0_REGNUM + 5,
> > +  AMD64_K0_REGNUM + 6, AMD64_K0_REGNUM + 7
> >  };
> >
> >  static const int amd64_dwarf_regmap_len =
> > --
> > 2.43.0
>
>
> While I can't approve, this looks good to me.
>
> Reviewed-By: Felix Willgerodt <felix.willgerodt@intel.com>
>

Who can approve this patch?

Thanks.
Willgerodt, Felix Feb. 22, 2024, 10:53 a.m. UTC | #3 
> > While I can't approve, this looks good to me.
> >
> > Reviewed-By: Felix Willgerodt <felix.willgerodt@intel.com>
> >
> 
> Who can approve this patch?

There is no x86 maintainer afaik. So you will need a global maintainers approval. See gdb/MAINTAINERS.

Felix
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de <http://www.intel.de>
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928
H.J. Lu Feb. 22, 2024, 2:45 p.m. UTC | #4 
On Thu, Feb 22, 2024 at 2:53 AM Willgerodt, Felix
<felix.willgerodt@intel.com> wrote:
>
> > > While I can't approve, this looks good to me.
> > >
> > > Reviewed-By: Felix Willgerodt <felix.willgerodt@intel.com>
> > >
> >
> > Who can approve this patch?
>
> There is no x86 maintainer afaik. So you will need a global maintainers approval. See gdb/MAINTAINERS.
>

Let me ping some global maintainers here.

PING:

https://patchwork.sourceware.org/project/gdb/list/?series=30935
John Baldwin Feb. 23, 2024, 12:36 a.m. UTC | #5 
On 2/22/24 2:53 AM, Willgerodt, Felix wrote:
>>> While I can't approve, this looks good to me.
>>>
>>> Reviewed-By: Felix Willgerodt <felix.willgerodt@intel.com>
>>>
>>
>> Who can approve this patch?
> 
> There is no x86 maintainer afaik. So you will need a global maintainers approval. See gdb/MAINTAINERS.

Approved-By: John Baldwin <jhb@FreeBSD.org>

Thanks
diff mbox series

Patch

diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c
index a8ff9246b8a..b6ff1c67a86 100644
--- a/gdb/amd64-tdep.c
+++ b/gdb/amd64-tdep.c
@@ -235,7 +235,28 @@  static int amd64_dwarf_regmap[] =
   /* Floating Point Control Registers.  */
   AMD64_MXCSR_REGNUM,
   AMD64_FCTRL_REGNUM,
-  AMD64_FSTAT_REGNUM
+  AMD64_FSTAT_REGNUM,
+
+  /* XMM16-XMM31.  */
+  AMD64_XMM16_REGNUM + 0, AMD64_XMM16_REGNUM + 1,
+  AMD64_XMM16_REGNUM + 2, AMD64_XMM16_REGNUM + 3,
+  AMD64_XMM16_REGNUM + 4, AMD64_XMM16_REGNUM + 5,
+  AMD64_XMM16_REGNUM + 6, AMD64_XMM16_REGNUM + 7,
+  AMD64_XMM16_REGNUM + 8, AMD64_XMM16_REGNUM + 9,
+  AMD64_XMM16_REGNUM + 10, AMD64_XMM16_REGNUM + 11,
+  AMD64_XMM16_REGNUM + 12, AMD64_XMM16_REGNUM + 13,
+  AMD64_XMM16_REGNUM + 14, AMD64_XMM16_REGNUM + 15,
+
+  /* Reserved.  */
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+  -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
+
+  /* Mask Registers.  */
+  AMD64_K0_REGNUM + 0, AMD64_K0_REGNUM + 1,
+  AMD64_K0_REGNUM + 2, AMD64_K0_REGNUM + 3,
+  AMD64_K0_REGNUM + 4, AMD64_K0_REGNUM + 5,
+  AMD64_K0_REGNUM + 6, AMD64_K0_REGNUM + 7
 };
 
 static const int amd64_dwarf_regmap_len =