diff mbox series

[13/15] sim: riscv: fix -Wshadow=local warnings

Message ID 20231222012355.7504-13-vapier@gentoo.org
State New
Headers
Series [01/15] sim: aarch64: fix -Wshadow=local warnings |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gdb_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_gdb_build--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gdb_check--master-arm success Testing passed
linaro-tcwg-bot/tcwg_gdb_check--master-aarch64 success Testing passed

Commit Message

Mike Frysinger Dec. 22, 2023, 1:23 a.m. UTC 
  Inline the one usage of sd in these macros to avoid possible shadowing.
---
 sim/riscv/sim-main.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)
diff mbox series

Patch

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 4d2053453950..b04d12c0de1c 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -48,10 +48,9 @@  static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
   do { \
     if (RISCV_XLEN (cpu) != 32) \
       { \
-	SIM_DESC sd = CPU_STATE (cpu); \
 	TRACE_INSN (cpu, "RV32I-only " fmt, ## args); \
-	sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \
-			 SIM_SIGILL); \
+	sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \
+			 sim_signalled, SIM_SIGILL); \
       } \
   } while (0)
 
@@ -59,10 +58,9 @@  static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
   do { \
     if (RISCV_XLEN (cpu) != 64) \
       { \
-	SIM_DESC sd = CPU_STATE (cpu); \
 	TRACE_INSN (cpu, "RV64I-only " fmt, ## args); \
-	sim_engine_halt (sd, cpu, NULL, sim_pc_get (cpu), sim_signalled, \
-			 SIM_SIGILL); \
+	sim_engine_halt (CPU_STATE (cpu), cpu, NULL, sim_pc_get (cpu), \
+			 sim_signalled, SIM_SIGILL); \
       } \
   } while (0)