diff mbox series

[1/3,committed] sim: m32r: add more cgen prototypes for traps

Message ID 20231208044203.25315-1-vapier@gentoo.org
State New
Headers
Series [1/3,committed] sim: m32r: add more cgen prototypes for traps |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gdb_build--master-aarch64 warning Patch is already merged
linaro-tcwg-bot/tcwg_gdb_build--master-arm warning Patch is already merged

Commit Message

Mike Frysinger Dec. 8, 2023, 4:42 a.m. UTC 
  The traps file uses a bunch of functions directly without prototypes,
and we can't safely include the relevant cpu*.h files for them.
---
 sim/m32r/m32r-sim.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h
index c72be52e18ae..875fc23bf3ef 100644
--- a/sim/m32r/m32r-sim.h
+++ b/sim/m32r/m32r-sim.h
@@ -47,6 +47,18 @@  extern void m32rbf_model_insn_before (SIM_CPU *, int);
 extern void m32rbf_model_insn_after (SIM_CPU *, int, int);
 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 extern CPUREG_STORE_FN m32rbf_store_register;
+extern UQI  m32rbf_h_psw_get (SIM_CPU *);
+extern void m32rbf_h_psw_set (SIM_CPU *, UQI);
+extern UQI  m32r2f_h_psw_get (SIM_CPU *);
+extern void m32r2f_h_psw_set (SIM_CPU *, UQI);
+extern UQI  m32rxf_h_psw_get (SIM_CPU *);
+extern void m32rxf_h_psw_set (SIM_CPU *, UQI);
+extern void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
+extern void m32r2f_h_bpsw_set (SIM_CPU *, UQI);
+extern void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
+extern SI   m32rbf_h_gr_get (SIM_CPU *, UINT);
+extern void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
+extern USI  m32rbf_h_cr_get (SIM_CPU *, UINT);
 extern void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
 
 /* Cover macros for hardware accesses.