gdb/arm: fix IPSR field test in arm_m_exception_cache ()

  Arm v8-M Architecture Reference Manual,
D1.2.141 IPSR, Interrupt Program Status Register reads
"Exception, bits [8:0]"

9 bits, not 8! It is uncommon but true!

Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
---
 gdb/arm-tdep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Hi Tomas,

On 10/22/22 09:25, Tomas Vanek wrote:
> Arm v8-M Architecture Reference Manual,
> D1.2.141 IPSR, Interrupt Program Status Register reads
> "Exception, bits [8:0]"
> 
> 9 bits, not 8! It is uncommon but true!
> 
> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
> ---
>   gdb/arm-tdep.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
> index b397ca3..923447a 100644
> --- a/gdb/arm-tdep.c
> +++ b/gdb/arm-tdep.c
> @@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
>   	}
>   
>         ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
> -      if ((xpsr & 0xff) != 0)
> +      if ((xpsr & 0x1ff) != 0)
>   	/* Handler mode: This is the mode that exceptions are handled in.  */
>   	arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
>         else

Good catch. This LGTM.

I suppose you need us to push this patch on your behalf?

One thing that would be nice to do is to have a flags/fields type for XPSR, which
would then display things in a nicer way to the user. Something like CPSR for a-profile.
  

Hi Luis,

On 25/10/2022 15:22, Luis Machado wrote:
> Hi Tomas,
>
> On 10/22/22 09:25, Tomas Vanek wrote:
>> Arm v8-M Architecture Reference Manual,
>> D1.2.141 IPSR, Interrupt Program Status Register reads
>> "Exception, bits [8:0]"
>>
>> 9 bits, not 8! It is uncommon but true!
>>
>> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
>> ---
>>   gdb/arm-tdep.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>> index b397ca3..923447a 100644
>> --- a/gdb/arm-tdep.c
>> +++ b/gdb/arm-tdep.c
>> @@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
>>       }
>>           ULONGEST xpsr = get_frame_register_unsigned (this_frame, 
>> ARM_PS_REGNUM);
>> -      if ((xpsr & 0xff) != 0)
>> +      if ((xpsr & 0x1ff) != 0)
>>       /* Handler mode: This is the mode that exceptions are handled 
>> in.  */
>>       arm_cache_switch_prev_sp (cache, tdep, 
>> tdep->m_profile_msp_s_regnum);
>>         else
>
> Good catch. This LGTM.
>
> I suppose you need us to push this patch on your behalf?
>
Yes, please push all my patches as they are ready.

Thanks
     Tomas
  

On 10/25/22 14:22, Luis Machado via Gdb-patches wrote:
> Hi Tomas,
> 
> On 10/22/22 09:25, Tomas Vanek wrote:
>> Arm v8-M Architecture Reference Manual,
>> D1.2.141 IPSR, Interrupt Program Status Register reads
>> "Exception, bits [8:0]"
>>
>> 9 bits, not 8! It is uncommon but true!
>>
>> Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
>> ---
>>   gdb/arm-tdep.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
>> index b397ca3..923447a 100644
>> --- a/gdb/arm-tdep.c
>> +++ b/gdb/arm-tdep.c
>> @@ -3441,7 +3441,7 @@ struct frame_unwind arm_stub_unwind = {
>>       }
>>         ULONGEST xpsr = get_frame_register_unsigned (this_frame, ARM_PS_REGNUM);
>> -      if ((xpsr & 0xff) != 0)
>> +      if ((xpsr & 0x1ff) != 0)
>>       /* Handler mode: This is the mode that exceptions are handled in.  */
>>       arm_cache_switch_prev_sp (cache, tdep, tdep->m_profile_msp_s_regnum);
>>         else
> 
> Good catch. This LGTM.
> 
> I suppose you need us to push this patch on your behalf?
> 
> One thing that would be nice to do is to have a flags/fields type for XPSR, which
> would then display things in a nicer way to the user. Something like CPSR for a-profile.

Pushed.