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[v8,0/1] sim: riscv: Compressed instruction simulation

Message ID 20240201044227.432079-1-jaydeep.patil@imgtec.com
Headers
Series sim: riscv: Compressed instruction simulation |

Message

Jaydeep Patil Feb. 1, 2024, 4:42 a.m. UTC 
  From: Jaydeep Patil <jaydeep.patil@imgtec.com>

Hi Mike, Andrew,

Addressed review comments.
 - Used RISCV_XLEN instead of opcode name to distinguish c.jal and c.addiw

Jaydeep Patil (1):
  sim: riscv: Add support for compressed integer instructions

 sim/riscv/model_list.def        |   9 +
 sim/riscv/sim-main.c            | 333 +++++++++++++++++++++++++++++++-
 sim/testsuite/riscv/allinsn.exp |   2 +-
 sim/testsuite/riscv/c-ext.s     |  95 +++++++++
 sim/testsuite/riscv/jalr.s      |   2 +-
 sim/testsuite/riscv/m-ext.s     |   2 +-
 sim/testsuite/riscv/pass.s      |   2 +-
 7 files changed, 437 insertions(+), 8 deletions(-)
 create mode 100644 sim/testsuite/riscv/c-ext.s