From patchwork Tue Jun 7 00:55:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 54859 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 83BCC386F0D6 for ; Tue, 7 Jun 2022 00:55:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 83BCC386F0D6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1654563336; bh=Oqlk9pBp15OZgHGhMazP9Jjzn9zQt8jItwAnyxLhIys=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=SCA+ynkLddFWBBfyqnXhbbmJFOeeWTtU+fhfznfVNj7JnU8OmHMSPUYSndSYClKjk xTQLss1Nvjz799DjnOGPxQjMnvu7SedfodZd3/owtSQLfd/t1l4MkFSDff6YoWF+u7 8m/8qBdfpCGDZPR7+CacCf1s/c4TjXOmoKdsSg08= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 21272386F0C4 for ; Tue, 7 Jun 2022 00:55:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 21272386F0C4 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 256N1ukx022296; Tue, 7 Jun 2022 00:55:04 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghtw8hcby-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jun 2022 00:55:04 +0000 Received: from m0098421.ppops.net (m0098421.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2570cDp8016968; Tue, 7 Jun 2022 00:55:04 GMT Received: from ppma03wdc.us.ibm.com (ba.79.3fa9.ip4.static.sl-reverse.com [169.63.121.186]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghtw8hcbu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jun 2022 00:55:04 +0000 Received: from pps.filterd (ppma03wdc.us.ibm.com [127.0.0.1]) by ppma03wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 2570oEA7013255; Tue, 7 Jun 2022 00:55:03 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma03wdc.us.ibm.com with ESMTP id 3gfy19gygx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jun 2022 00:55:03 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2570t2Z713894016 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 7 Jun 2022 00:55:02 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 38101136053; Tue, 7 Jun 2022 00:55:02 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9FEFA136051; Tue, 7 Jun 2022 00:55:01 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.160.87.14]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 7 Jun 2022 00:55:01 +0000 (GMT) Date: Mon, 6 Jun 2022 20:55:00 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 1/3] Disable generating store vector pair. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: fUYEZqu-k-OVUNdT6xTIoY-0AWalpaaW X-Proofpoint-GUID: RihfDlTI_YIXYWPtbrWia_EgqW2YNLTy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206070000 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH 1/3] Disable generating store vector pair. Testing has revealed that the power10 has some slowdowns if the store vector pair instruction is generated in some cases. This patch disables generating the store vector pair instructions (stxvp, pstxvp, and stxvpx) unless an undocumented switch is used. It is anticipated that perhaps with future machines we can generate the store vector pair instruction. This patch does a split after reload to convert a store vector pair instruction into a pair of store vector instructions. We do continue to generate the load vector pair instructions (lxvp, plxvp, and lxvpx), since we have found that in code that heavily uses MMA, it is still a win to generate the load vector pair instructions. There are two future patches planed: 1) Disable block moves from generating load/store vector pair instructions unless the the store vector pair instructions are being generted. 2) Make the built-in functions for generating store vector pair always generate those instructions even if store vector pair instructions are disabled. I have built bootstrap compilers and run the regression tests on three different systems: 1) Little endian power10 using the --with-cpu=power10 option. 2) Little endian power9 using the --with-cpu=power9 option. 3) Big endian power8 using the --with-cpu=power8 option. On this system, both 64-bit and 32-bit code generation was tested. There were no regressions in the runs except for the tests that are modified in patch #3 in these series of patches. Can I check this patch into the trunk? If there are no changes needed for the backports, can I check this code into the active branches after a burn-in period? 2022-06-06 Michael Meissner gcc/ * config/rs6000/mma.md (movoo): Disable generating store vector pair instructions unless these are enabled by the user. (movxo): Likewise. * config/rs6000/rs6000.cc (rs6000_setup_reg_addr_masks): If store vector pair instructions are disabled, do not allow vector pair addresses to be indexed. (rs6000_split_multireg_move): Do not split XOmode stores into two store vector pair instructions unless store vector pair instructions are enabled. * config/rs6000/rs6000.md (isa attribute): Add stxvp attribute. (enabled attribute): Disable alternative using store vector pair instructions unless they are enabled. * config/rs6000/rs6000.opt (-mstore-vector-pair): New option. gcc/testsuite/ * gcc.target/powerpc/p10-store-vector-pair-1.c: New test. * gcc.target/powerpc/p10-store-vector-pair-2.c: New test. --- gcc/config/rs6000/mma.md | 41 ++++++---- gcc/config/rs6000/rs6000.cc | 9 +- gcc/config/rs6000/rs6000.md | 8 +- gcc/config/rs6000/rs6000.opt | 4 + .../powerpc/p10-store-vector-pair-1.c | 82 +++++++++++++++++++ .../powerpc/p10-store-vector-pair-2.c | 81 ++++++++++++++++++ 6 files changed, 206 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-2.c diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index a183b6a168a..9b5f243b88d 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -274,26 +274,35 @@ (define_expand "movoo" DONE; }) +;; By default for power10, do not generate the stxvp/pstxvp/stxvpx +;; instructions. Instead, split these instructions into two separate store +;; vector instructions. We do always generate a lxvp/plxvp/lxvpx instruction. +;; We leave in the support for generating stxvp/pstxvp/stxvpx in future +;; machines. (define_insn_and_split "*movoo" - [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,m,wa") - (match_operand:OO 1 "input_operand" "m,wa,wa"))] + [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,m, o, wa") + (match_operand:OO 1 "input_operand" "m, wa,wa,wa"))] "TARGET_MMA && (gpc_reg_operand (operands[0], OOmode) || gpc_reg_operand (operands[1], OOmode))" "@ lxvp%X1 %x0,%1 stxvp%X0 %x1,%0 + # #" "&& reload_completed - && (!MEM_P (operands[0]) && !MEM_P (operands[1]))" + && ((MEM_P (operands[0]) && !TARGET_STORE_VECTOR_PAIR) + || (!MEM_P (operands[0]) && !MEM_P (operands[1])))" [(const_int 0)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "type" "vecload,vecstore,veclogical") - (set_attr "size" "256") - (set_attr "length" "*,*,8")]) + [(set_attr "type" "vecload,vecstore,vecstore,veclogical") + (set_attr "max_prefixed_insns" "*, *, 2, *") + (set_attr "length" "*, *, *, 8") + (set_attr "isa" "*, stxvp, *, *")]) + (set_attr "size" "256") ;; Vector quad support. XOmode can only live in FPRs. @@ -306,25 +315,27 @@ (define_expand "movxo" DONE; }) +;; By default for power10, do not generate two stxvp/pstxvp instructions. +;; Instead, split these instructions into four separate store vector +;; instructions. We do always generate two lxvp/plxvp instructions. We leave +;; in the support for generating stxvp/pstxvp in future machines. (define_insn_and_split "*movxo" - [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,d") - (match_operand:XO 1 "input_operand" "m,d,d"))] + [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,o,d") + (match_operand:XO 1 "input_operand" "m,d,d,d"))] "TARGET_MMA && (gpc_reg_operand (operands[0], XOmode) || gpc_reg_operand (operands[1], XOmode))" - "@ - # - # - #" + "#" "&& reload_completed" [(const_int 0)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "type" "vecload,vecstore,veclogical") - (set_attr "length" "*,*,16") - (set_attr "max_prefixed_insns" "2,2,*")]) + [(set_attr "type" "vecload,vecstore,vecstore,veclogical") + (set_attr "length" "*, *, *, 16") + (set_attr "max_prefixed_insns" "2, 2, 4, *") + (set_attr "isa" "*, stxvp, *, *")]) (define_expand "vsx_assemble_pair" [(match_operand:OO 0 "vsx_register_operand") diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 0af2085adc0..30ed24fff30 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -2714,7 +2714,8 @@ rs6000_setup_reg_addr_masks (void) /* Vector pairs can do both indexed and offset loads if the instructions are enabled, otherwise they can only do offset loads since it will be broken into two vector moves. Vector quads can - only do offset loads. */ + only do offset loads. If stxvp is disabled, we can't do indexed + arithmetic. */ else if ((addr_mask != 0) && TARGET_MMA && (m2 == OOmode || m2 == XOmode)) { @@ -2722,7 +2723,8 @@ rs6000_setup_reg_addr_masks (void) if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX) { addr_mask |= RELOAD_REG_QUAD_OFFSET; - if (m2 == OOmode) + if (m2 == OOmode + && TARGET_STORE_VECTOR_PAIR) addr_mask |= RELOAD_REG_INDEXED; } } @@ -26992,7 +26994,8 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we have a vector quad register for MMA, and this is a load or store, see if we can use vector paired load/stores. */ if (mode == XOmode && TARGET_MMA - && (MEM_P (dst) || MEM_P (src))) + && ((MEM_P (dst) && TARGET_STORE_VECTOR_PAIR) + || MEM_P (src))) { reg_mode = OOmode; nregs /= 2; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3eca448a262..7eb107148ca 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -354,7 +354,7 @@ (define_attr "cpu" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10" +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,stxvp" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -402,6 +402,12 @@ (define_attr "enabled" "" (and (eq_attr "isa" "p10") (match_test "TARGET_POWER10")) (const_int 1) + + (and (eq_attr "isa" "stxvp") + (match_test "TARGET_POWER10") + (match_test "TARGET_STORE_VECTOR_PAIR")) + (const_int 1) + ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 4931d781c4e..79ceec6e6a5 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -624,6 +624,10 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. +; Generate (do not generate) code that uses the store vector pair instruction. +mstore-vector-pair +Target Undocumented Var(TARGET_STORE_VECTOR_PAIR) Init(0) Save + -param=rs6000-density-pct-threshold= Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param When costing for loop vectorization, we probably need to penalize the loop body diff --git a/gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-1.c b/gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-1.c new file mode 100644 index 00000000000..c1a36bf5fff --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-1.c @@ -0,0 +1,82 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mstore-vector-pair -mmma" } */ + +/* Test if we generate store vector pair instructions if the user uses the + -mstore-vector-pair option. */ +static __vector_quad sq; +static __vector_pair sp; + +void +load_store_pair (__vector_pair *p, __vector_pair *q) +{ + *p = *q; /* lxvp, stxvp. */ +} + +void +load_store_pair_1 (__vector_pair *p, __vector_pair *q) +{ + p[1] = q[1]; /* lxvp, stxvp. */ +} + +void +load_store_pair_0x10000 (__vector_pair *p, __vector_pair *q) +{ + p[0x10000] = q[0x10000]; /* plxvp, pstxvp. */ +} + +void +load_store_pair_n (__vector_pair *p, __vector_pair *q, unsigned long n) +{ + p[n] = q[n]; /* lxvpx, 2x stxvp. */ +} + +void +load_pair_static (__vector_pair *p) +{ + *p = sp; /* plxvp, stxvp. */ +} + +void +store_pair_static (__vector_pair *p) +{ + sp = *p; /* lxvp, pstxvp. */ +} + +void +load_store_quad (__vector_quad *p, __vector_quad *q) +{ + *p = *q; /* 2x lxvp, 2x stxvp. */ +} + +void +load_store_quad_1 (__vector_quad *p, __vector_quad *q) +{ + p[1] = q[1]; /* 2x lxvp, 2x stxvp. */ +} + +void +load_store_quad_0x10000 (__vector_quad *p, __vector_quad *q) +{ + p[0x10000] = q[0x10000]; /* 2x plxvp, 2x pstxvp. */ +} + +void +load_store_quad_n (__vector_quad *p, __vector_quad *q, unsigned long n) +{ + p[n] = q[n]; /* 2x lxvp, 2x stxv. */ +} + +void +load_quad_static (__vector_quad *p) +{ + *p = sq; /* 2x plxvp, 2x stxvp. */ +} + +void +store_quad_static (__vector_quad *p) +{ + sq = *p; /* 2x lxvp, 2x stxvp. */ +} + +/* { dg-final { scan-assembler {\mp?stxvpx?\M} } } */ + diff --git a/gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-2.c b/gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-2.c new file mode 100644 index 00000000000..b8c3bdbfd89 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p10-store-vector-pair-2.c @@ -0,0 +1,81 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mno-store-vector-pair -mmma" } */ + +/* Test if we do not generate store vector pair instructions if the user uses + the -mno-store-vector-pair option. */ +static __vector_quad sq; +static __vector_pair sp; + +void +load_store_pair (__vector_pair *p, __vector_pair *q) +{ + *p = *q; /* lxvp, 2x stxv. */ +} + +void +load_store_pair_1 (__vector_pair *p, __vector_pair *q) +{ + p[1] = q[1]; /* lxvp, 2x stxv. */ +} + +void +load_store_pair_0x10000 (__vector_pair *p, __vector_pair *q) +{ + p[0x10000] = q[0x10000]; /* plxvp, 2x pstxv. */ +} + +void +load_store_pair_n (__vector_pair *p, __vector_pair *q, unsigned long n) +{ + p[n] = q[n]; /* lxvpx, 2x stxv. */ +} + +void +load_pair_static (__vector_pair *p) +{ + *p = sp; /* plxvp, 2x stxv. */ +} + +void +store_pair_static (__vector_pair *p) +{ + sp = *p; /* lxvp, 2x pstxv. */ +} + +void +load_store_quad (__vector_quad *p, __vector_quad *q) +{ + *p = *q; /* 2x lxvp, 4x stxv. */ +} + +void +load_store_quad_1 (__vector_quad *p, __vector_quad *q) +{ + p[1] = q[1]; /* 2x lxvp, 4x stxv. */ +} + +void +load_store_quad_0x10000 (__vector_quad *p, __vector_quad *q) +{ + p[0x10000] = q[0x10000]; /* 2x plxvp, 4x pstxv. */ +} + +void +load_store_quad_n (__vector_quad *p, __vector_quad *q, unsigned long n) +{ + p[n] = q[n]; /* 2x lxvp, 4x stxv. */ +} + +void +load_quad_static (__vector_quad *p) +{ + *p = sq; /* 2x plxvp, 4x stxv. */ +} + +void +store_quad_static (__vector_quad *p) +{ + sq = *p; /* 2x lxvp, 4x pstxv. */ +} + +/* { dg-final { scan-assembler-not {\mp?vstxvpx?\M} } } */ From patchwork Tue Jun 7 00:55:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 54860 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 60630386F0D2 for ; Tue, 7 Jun 2022 00:56:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 60630386F0D2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1654563394; bh=B6Et3oKUgvNJNp+XpqIVwAuzCzTluy4VSk/BxaFW1Kk=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=cXKBwb3/MPBoW4ig3p5Gjm0a1791UTcpd+izj/DxZ/p2DBnxjPeNC8O4WfJiztOre HCBGGusMX0A8Fvk6T//wkSQ5/rniBN2XRtc+3Ppaxhux1b/RK1FiAqBmSoMYpz+26t swjDcw+j0hAQ98Uk4dIY+uFAgw9tL6CFFliV3siw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 7B1C5386F0D8 for ; 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Tue, 7 Jun 2022 00:55:57 GMT Received: from b01cxnp22035.gho.pok.ibm.com (b01cxnp22035.gho.pok.ibm.com [9.57.198.25]) by ppma02wdc.us.ibm.com with ESMTP id 3gfy19gwgd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jun 2022 00:55:57 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2570tuhc38994240 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 7 Jun 2022 00:55:56 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ADAF1124055; Tue, 7 Jun 2022 00:55:56 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 68066124054; Tue, 7 Jun 2022 00:55:56 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.160.87.14]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTPS; Tue, 7 Jun 2022 00:55:56 +0000 (GMT) Date: Mon, 6 Jun 2022 20:55:55 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 2/3] Disable generating load/store vector pairs for block copies. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: raO8QG7INj4v0MQOq2GRnTL8GvBcRknx X-Proofpoint-GUID: oP66CVWoLZe1aVu-FONaKqsrZovq3E3Y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 mlxlogscore=999 spamscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 mlxscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206070000 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH 2/3] Disable generating load/store vector pairs for block copies. If the store vector pair instruction is disabled, do not generate block copies that use load and store vector pair instructions. I have built bootstrap compilers and run the regression tests on three different systems: 1) Little endian power10 using the --with-cpu=power10 option. 2) Little endian power9 using the --with-cpu=power9 option. 3) Big endian power8 using the --with-cpu=power8 option. On this system, both 64-bit and 32-bit code generation was tested. There were no regressions in the runs. Can I check this patch into the trunk? If there are no changes needed for the backports, can I check this code into the active branches after a burn-in period? 2022-06-06 Michael Meissner gcc/ * config/rs6000/rs6000-string.cc (expand_block_move): If the store vector pair instructions are disabled, do not generate block copies using load and store vector pairs. --- gcc/config/rs6000/rs6000-string.cc | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index 59d901ac68d..1b18e043269 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -2787,14 +2787,16 @@ expand_block_move (rtx operands[], bool might_overlap) rtx src, dest; bool move_with_length = false; - /* Use OOmode for paired vsx load/store. Use V2DI for single - unaligned vsx load/store, for consistency with what other - expansions (compare) already do, and so we can use lxvd2x on - p8. Order is VSX pair unaligned, VSX unaligned, Altivec, VSX - with length < 16 (if allowed), then gpr load/store. */ + /* Use OOmode for paired vsx load/store unless the store vector pair + instructions are disabled. Use V2DI for single unaligned vsx + load/store, for consistency with what other expansions (compare) + already do, and so we can use lxvd2x on p8. Order is VSX pair + unaligned, VSX unaligned, Altivec, VSX with length < 16 (if allowed), + then gpr load/store. */ if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX && TARGET_BLOCK_OPS_VECTOR_PAIR + && TARGET_STORE_VECTOR_PAIR && bytes >= 32 && (align >= 256 || !STRICT_ALIGNMENT)) { From patchwork Tue Jun 7 00:56:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 54861 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 94EC1386F0C9 for ; Tue, 7 Jun 2022 00:57:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 94EC1386F0C9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1654563453; bh=HhQRbyRI5OTUaRPtaso9XQ4d1yzjsqgAOGLNt3jLR/0=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=KDiN9lTrNwlN7rhZf8kCSsu5pd8yWroWAjgK34aFQkiCbPqFFOo+KbWb4itN/6Kl5 A99GJfNg3A88aJBxFBRBF8j0Z6Byz5+NNGa963885bVEcD/3aMuv3HIso0vClCi3nJ Ow5bBe2+q9K/HTT5ZeCouFyz66BYiEU4RSnrltOg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 224C1386F0C8 for ; Tue, 7 Jun 2022 00:56:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 224C1386F0C8 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 256L0ZTh019358; Tue, 7 Jun 2022 00:56:52 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghs4ck38j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jun 2022 00:56:52 +0000 Received: from m0098414.ppops.net (m0098414.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2570fwwi014179; Tue, 7 Jun 2022 00:56:51 GMT Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3ghs4ck38c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jun 2022 00:56:51 +0000 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 2570oxDm016862; Tue, 7 Jun 2022 00:56:51 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma04dal.us.ibm.com with ESMTP id 3gfy19w643-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 07 Jun 2022 00:56:51 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2570unnq15663464 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 7 Jun 2022 00:56:49 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A40266E052; Tue, 7 Jun 2022 00:56:49 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1950A6E04E; Tue, 7 Jun 2022 00:56:49 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.160.87.14]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 7 Jun 2022 00:56:49 +0000 (GMT) Date: Mon, 6 Jun 2022 20:56:47 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 3/3] Adjust MMA tests to account for no store vector pair. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: NcHYd5e0adEOw6qvzpQidpnF6Xh7QcoE X-Proofpoint-ORIG-GUID: mvKphj2gR0eiKHLSLNmABGJEp0d3x_hE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-06_07,2022-06-03_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 clxscore=1015 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2206070000 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" [PATCH 3/3] Adjust MMA tests to account for no store vector pair. In changing the default for generating the store vector pair instructions, I had to adjust several of the MMA tests to remove checking for these instructions. Mostly I just deleted the scan-assembler lines checking for stxvp. In two of the tests, I added the -mstore-vector-pair option since the point of the test was to check for specific cases with store vector pair instructions. I have built bootstrap compilers and run the regression tests on three different systems: 1) Little endian power10 using the --with-cpu=power10 option. 2) Little endian power9 using the --with-cpu=power9 option. 3) Big endian power8 using the --with-cpu=power8 option. On this system, both 64-bit and 32-bit code generation was tested. There were no regressions in the runs. Can I check this patch into the trunk? If there are no changes needed for the backports, can I check this code into the active branches after a burn-in period? 2022-06-06 Michael Meissner gcc/testsuite/ * gcc.target/powerpc/mma-builtin-1.c: Eliminate checking for store vector pair instructions. * gcc.target/powerpc/mma-builtin-10-pair.c: Likewise. * gcc.target/powerpc/mma-builtin-10-quit.c: Likewise. * gcc.target/powerpc/mma-builtin-2.c: Likewise. * gcc.target/powerpc/mma-builtin-3.c: Likewise. * gcc.target/powerpc/mma-builtin-4.c: Likewise. * gcc.target/powerpc/mma-builtin-5.c: Likewise. * gcc.target/powerpc/mma-builtin-6.c: Likewise. * gcc.target/powerpc/mma-builtin-7.c: Likewise. * gcc.target/powerpc/mma-builtin-9.c: Likewise. * gcc.target/powerpc/mma-builtin-8.c: Add -mstore-vector-pair. * gcc.target/powerpc/pr102976.c: Likewise. --- gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c | 1 - gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c | 2 -- gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c | 2 +- gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c | 2 -- gcc/testsuite/gcc.target/powerpc/pr102976.c | 6 +++++- 12 files changed, 6 insertions(+), 18 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c index 69ee826e1be..47b45b00403 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-1.c @@ -260,7 +260,6 @@ foo13b (__vector_quad *dst, __vector_quad *src, vec_t *vec) /* { dg-final { scan-assembler-times {\mlxv\M} 40 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 12 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 40 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 20 } } */ /* { dg-final { scan-assembler-times {\mxxmtacc\M} 6 } } */ /* { dg-final { scan-assembler-times {\mxvbf16ger2\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c index d8748d8e7d0..9522673d83e 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-pair.c @@ -16,6 +16,4 @@ foo (__vector_pair *dst, vec_t *src) } /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c index 02342c76f5f..3cbdffc15ba 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-10-quad.c @@ -16,8 +16,6 @@ foo (__vector_quad *dst, vec_t *src) } /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 4 } } */ /* { dg-final { scan-assembler-times {\mxxmtacc\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c index 0230d727657..5943702d8f3 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-2.c @@ -59,7 +59,6 @@ foo3 (__vector_quad *dst, __vector_quad *src, vec_t *vec, __vector_pair *pvecp) /* { dg-final { scan-assembler-times {\mxxmtacc\M} 2 } } */ /* { dg-final { scan-assembler-times {\mlxv\M} 4 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 8 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 8 } } */ /* { dg-final { scan-assembler-times {\mxvf64ger\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvf64gerpp\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvf64gerpn\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c index 9bec78d333f..ee65ef9d96f 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-3.c @@ -26,6 +26,5 @@ foo1 (vec_t *vec) /* { dg-final { scan-assembler-times {\mlxv\M} 2 } } */ /* { dg-final { scan-assembler-times {\mstxv\M} 2 } } */ /* { dg-final { scan-assembler-not {\mlxvp\M} } } */ -/* { dg-final { scan-assembler-not {\mstxvp\M} } } */ /* { dg-final { scan-assembler-times {\mxvcvspbf16\M} 1 } } */ /* { dg-final { scan-assembler-times {\mxvcvbf16spn\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c index a9fb0107d12..aa6e6136f4f 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-4.c @@ -68,6 +68,4 @@ bar2 (vec_t *dst, __vector_pair *src) /* { dg-final { scan-assembler-times {\mlxv\M} 6 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c index 00503b7343d..0d332acee93 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-5.c @@ -41,7 +41,5 @@ bar (vec_t *dst, __vector_quad *src) /* { dg-final { scan-assembler-times {\mlxv\M} 8 } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxv\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 3 } } */ /* { dg-final { scan-assembler-times {\mxxmtacc\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c index 715b28138e9..2f5747da070 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-6.c @@ -17,4 +17,3 @@ foo (__vector_quad *dst) /* { dg-final { scan-assembler-not {\mxxmtacc\M} } } */ /* { dg-final { scan-assembler-times {\mxxsetaccz\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxmfacc\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c index c661a4b84bc..6eba0a34e8a 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-7.c @@ -19,8 +19,6 @@ foo (__vector_pair *dst, __vector_pair *src, long idx) #endif /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 3 } } */ /* { dg-final { scan-assembler-times {\mlxvpx\M} 1 } } */ /* { dg-final { scan-assembler-times {\mplxvp\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c index af29e479f83..cbd2e6dbae1 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -mstore-vector-pair" } */ void foo (__vector_pair *dst, __vector_pair *src, long idx) diff --git a/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c b/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c index 397d0f1db35..7232e840204 100644 --- a/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c +++ b/gcc/testsuite/gcc.target/powerpc/mma-builtin-9.c @@ -23,6 +23,4 @@ bar (__vector_quad *dst, vec_t *src) } /* { dg-final { scan-assembler-not {\mlxv\M} } } */ -/* { dg-final { scan-assembler-not {\mstxv\M} } } */ /* { dg-final { scan-assembler-times {\mlxvp\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mstxvp\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr102976.c b/gcc/testsuite/gcc.target/powerpc/pr102976.c index 5a4320f8e0a..c975eba86da 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr102976.c +++ b/gcc/testsuite/gcc.target/powerpc/pr102976.c @@ -1,7 +1,11 @@ /* { dg-require-effective-target power10_ok } */ -/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power10 -mstore-vector-pair" } */ #include + +/* The test relies on store vector pair being generated. Otherwise, it + will generate 2 stxv instructions. */ + void bug (__vector_pair *dst) {