From patchwork Wed Jun 1 05:06:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 54641 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65EF0385702C for ; Wed, 1 Jun 2022 05:06:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 65EF0385702C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1654060001; bh=pAilYFRtQ5LTzZazaV639kD97YlaPwFWOZactULdlBs=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=pfvEmoAm4ZChsHx/J8zH07aAIAS7GocKyC1jolaE+6QXFcVLyEtjFhcKMpGXljYms djz6B3qqg4JW4Hz4Jo1QSEhrk+VWKoAduDwHBcx5bIAyzzPXgKf8YqyqJM5exzbqZB ZbfKnd0GgpQod/OTSyWfgEFiKd6uxmw9kFljEQnc= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 351D93857402 for ; Wed, 1 Jun 2022 05:06:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 351D93857402 X-IronPort-AV: E=McAfee;i="6400,9594,10364"; a="257545161" X-IronPort-AV: E=Sophos;i="5.91,266,1647327600"; d="scan'208";a="257545161" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2022 22:06:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,266,1647327600"; d="scan'208";a="576756813" Received: from scymds02.sc.intel.com ([10.82.73.244]) by orsmga007.jf.intel.com with ESMTP; 31 May 2022 22:06:08 -0700 Received: from shgcc10.sh.intel.com (shgcc10.sh.intel.com [10.239.154.125]) by scymds02.sc.intel.com with ESMTP id 251566nc019927; Tue, 31 May 2022 22:06:07 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Update {skylake, icelake, alderlake}_cost to add a bit preference to vector store. Date: Wed, 1 Jun 2022 13:06:06 +0800 Message-Id: <20220601050606.3508-1-lili.cui@intel.com> X-Mailer: git-send-email 2.17.1 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui,Lili via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: "Cui,Lili" Cc: hongtao.liu@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch is to update {skylake,icelake,alderlake}_cost to add a bit preference to vector store. Since the interger vector construction cost has changed, we need to adjust the load and store costs for intel processers. With the patch applied 538.imagic_r:gets ~6% improvement on ADL for multicopy. 525.x264_r :gets ~2% improvement on ADL and ICX for multicopy. with no measurable changes for other benchmarks. Bootstrapped and regtested on x86_64-linux-gnu{-m32,}. Ok for trunk? Thanks, Lili. gcc/ChangeLog PR target/105493 * config/i386/x86-tune-costs.h (skylake_cost): Raise the gpr load cost from 4 to 6 and gpr store cost from 6 to 8. Change SSE loads and unaligned loads cost from {6, 6, 6, 10, 20} to {8, 8, 8, 8, 16}. (icelake_cost): Ditto. (alderlake_cost): Raise the gpr store cost from 6 to 8 and SSE loads, stores and unaligned stores cost from {6, 6, 6, 10, 15} to {8, 8, 8, 10, 15}. gcc/testsuite/ PR target/105493 * gcc.target/i386/pr91446.c: Adjust to expect vectorization * gcc.target/i386/pr99881.c: XFAIL. --- gcc/config/i386/x86-tune-costs.h | 26 ++++++++++++------------- gcc/testsuite/gcc.target/i386/pr91446.c | 2 +- gcc/testsuite/gcc.target/i386/pr99881.c | 2 +- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index ea34a939c68..6c9066c84cc 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1897,15 +1897,15 @@ struct processor_costs skylake_cost = { 8, /* "large" insn */ 17, /* MOVE_RATIO */ 17, /* CLEAR_RATIO */ - {4, 4, 4}, /* cost of loading integer registers + {6, 6, 6}, /* cost of loading integer registers in QImode, HImode and SImode. Relative to reg-reg move (2). */ - {6, 6, 6}, /* cost of storing integer registers */ - {6, 6, 6, 10, 20}, /* cost of loading SSE register + {8, 8, 8}, /* cost of storing integer registers */ + {8, 8, 8, 8, 16}, /* cost of loading SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ {8, 8, 8, 8, 16}, /* cost of storing SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ - {6, 6, 6, 10, 20}, /* cost of unaligned loads. */ + {8, 8, 8, 8, 16}, /* cost of unaligned loads. */ {8, 8, 8, 8, 16}, /* cost of unaligned stores. */ 2, 2, 4, /* cost of moving XMM,YMM,ZMM register */ 6, /* cost of moving SSE register to integer. */ @@ -2023,15 +2023,15 @@ struct processor_costs icelake_cost = { 8, /* "large" insn */ 17, /* MOVE_RATIO */ 17, /* CLEAR_RATIO */ - {4, 4, 4}, /* cost of loading integer registers + {6, 6, 6}, /* cost of loading integer registers in QImode, HImode and SImode. Relative to reg-reg move (2). */ - {6, 6, 6}, /* cost of storing integer registers */ - {6, 6, 6, 10, 20}, /* cost of loading SSE register + {8, 8, 8}, /* cost of storing integer registers */ + {8, 8, 8, 8, 16}, /* cost of loading SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ {8, 8, 8, 8, 16}, /* cost of storing SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ - {6, 6, 6, 10, 20}, /* cost of unaligned loads. */ + {8, 8, 8, 8, 16}, /* cost of unaligned loads. */ {8, 8, 8, 8, 16}, /* cost of unaligned stores. */ 2, 2, 4, /* cost of moving XMM,YMM,ZMM register */ 6, /* cost of moving SSE register to integer. */ @@ -2146,13 +2146,13 @@ struct processor_costs alderlake_cost = { {6, 6, 6}, /* cost of loading integer registers in QImode, HImode and SImode. Relative to reg-reg move (2). */ - {6, 6, 6}, /* cost of storing integer registers */ - {6, 6, 6, 10, 15}, /* cost of loading SSE register + {8, 8, 8}, /* cost of storing integer registers */ + {8, 8, 8, 10, 15}, /* cost of loading SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ - {6, 6, 6, 10, 15}, /* cost of storing SSE register + {8, 8, 8, 10, 15}, /* cost of storing SSE register in 32bit, 64bit, 128bit, 256bit and 512bit */ - {6, 6, 6, 10, 15}, /* cost of unaligned loads. */ - {6, 6, 6, 10, 15}, /* cost of unaligned storess. */ + {8, 8, 8, 10, 15}, /* cost of unaligned loads. */ + {8, 8, 8, 10, 15}, /* cost of unaligned storess. */ 2, 3, 4, /* cost of moving XMM,YMM,ZMM register */ 6, /* cost of moving SSE register to integer. */ 18, 6, /* Gather load static, per_elt. */ diff --git a/gcc/testsuite/gcc.target/i386/pr91446.c b/gcc/testsuite/gcc.target/i386/pr91446.c index 067bf43f698..0243ca3ea68 100644 --- a/gcc/testsuite/gcc.target/i386/pr91446.c +++ b/gcc/testsuite/gcc.target/i386/pr91446.c @@ -21,4 +21,4 @@ foo (unsigned long long width, unsigned long long height, bar (&t); } -/* { dg-final { scan-assembler-times "xmm\[0-9\]" 0 } } */ +/* { dg-final { scan-assembler-times "vmovdqa\[^\n\r\]*xmm\[0-9\]" 2 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr99881.c b/gcc/testsuite/gcc.target/i386/pr99881.c index a1ec1d1ba8a..3e087eb2ed7 100644 --- a/gcc/testsuite/gcc.target/i386/pr99881.c +++ b/gcc/testsuite/gcc.target/i386/pr99881.c @@ -1,7 +1,7 @@ /* PR target/99881. */ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-Ofast -march=skylake" } */ -/* { dg-final { scan-assembler-not "xmm\[0-9\]" } } */ +/* { dg-final { scan-assembler-not "xmm\[0-9\]" { xfail *-*-* } } } */ void foo (int* __restrict a, int n, int c)