From patchwork Thu May 26 07:17:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Ju Wu X-Patchwork-Id: 54396 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BCB743834E43 for ; Thu, 26 May 2022 07:17:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BCB743834E43 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653549454; bh=fpvEy6d1ILodPk3ZPRIiJRGXsyRucS5IdQAGYnFrQ40=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=H3cFN3GVEn5uK5FcYagbyA3v03db0DTSVSJoWmzh7ic9Ur7vnDwGFz+gc5OWoRjYt bJWI6Ze5a8u72vGqNdktCKXh6YvdPnZNzArowckbCNLAQ8aY+UrWkJUFGww2tKXqSf J4Gg/q/OwPdOrV+2j68mKOYLlLDFNYHQA3IFkdLY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id 8743D3858C2C for ; Thu, 26 May 2022 07:17:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8743D3858C2C Received: by mail-pg1-x52e.google.com with SMTP id e66so653261pgc.8 for ; Thu, 26 May 2022 00:17:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent :content-language:from:subject:to:cc; bh=fpvEy6d1ILodPk3ZPRIiJRGXsyRucS5IdQAGYnFrQ40=; b=J/BjoQtfvjbCU4RD26ZoMZ/QxWVwHb4b+J3Uow4npFDtxzdnE/5ZnfO2U4Rr/elVEE 0x8ZW1U+J8FlObojDHU4dYuAbVApwHLFeHw/BMkYXq4Jb6NtU9DDqg3JvvFvNNTK4Lr5 w11K62sg0i51iM11AmZl0AML++miY34+IOxCI2MZaWCIxwJixSC8EouNlJUhxR5yiJKj w/GeQOBHR1TLRqSCBK21W1HO/SEfo4aM5Zr16GXzg/bp8Wect0v08MGaPApdnZg0uyQu BbEOTWF3GtJjeHY97xznw6XkoR/orfdFMxn+2vj5w7U4HrS9wbSsiZ/V8mOiz24jDVXS bEgg== X-Gm-Message-State: AOAM531RU9WrfjXB199Sd0t4iKnCZmWPea48LeOjX3PYxZJZvJ8HShLz SgZfW2SmIkG5oX3BzHmw3Js= X-Google-Smtp-Source: ABdhPJxTZ/awFY0DtJsdjirPlTowGNY7JBCKqIcXFnDV6w5vDziSl4Z5asTyhcwv6MC0gKfnxSBOfg== X-Received: by 2002:a05:6a00:1893:b0:518:9945:b288 with SMTP id x19-20020a056a00189300b005189945b288mr20513034pfh.75.1653549423098; Thu, 26 May 2022 00:17:03 -0700 (PDT) Received: from [10.223.1.10] (114-43-72-38.dynamic-ip.hinet.net. [114.43.72.38]) by smtp.gmail.com with ESMTPSA id g12-20020a63110c000000b003c66480613esm739352pgl.80.2022.05.26.00.17.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 May 2022 00:17:02 -0700 (PDT) Message-ID: <70e4f5ae-e59a-d0ba-68b9-72d27de09c44@gmail.com> Date: Thu, 26 May 2022 15:17:32 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Content-Language: en-US Subject: [PATCH 1/3][ARM] STAR-MC1 CPU Support - arm: Add star-mc1 core To: Richard.Earnshaw@arm.com, gcc-patches X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Chung-Ju Wu via Gcc-patches From: Chung-Ju Wu Reply-To: Chung-Ju Wu Cc: Jason.Wu@anshingtek.com.tw Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, STAR-MC1 is an embedded processor with armv8m architecture. Majorly it is designed to meet the requirements of AIoT application performance, power consumption and security. Early this month, star-mc1 is supported by the latest releases of MDK and CMSIS. For the completeness of Arm ecosystem, it would be great if we can have star-mc1 support in official GCC as well. Attached is the patch to support star-mc1 cpu in GCC: * Fundamental of -mcpu=star-mc1 option - Based on latest upstream commit: https://gcc.gnu.org/g:3dff965cae6709a5fd1b7b05c51c3c8aba786961 - Add star-mc1 cpu in arm-cpus.in and regenerate necessary implementation * Include VLLDM bugfix - CVE-2021-35465 also affects star-mc1 configuration [1] - We apply quirk_vlldm strategy for star-mc1 cpu Successfully bootstrapped and tested on arm-none-eabi. Is it OK for trunk? [1] https://www.cve.org/CVERecord?id=CVE-2021-35465 Regards, jasonwucj From 3405d35f4a6a6abd7808e2c62ce2d1dbd2e2cb14 Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 26 May 2022 02:58:16 +0000 Subject: [PATCH 1/3] arm: Add star-mc1 core Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * config/arm/arm-cpus.in: Add star-mc1 core. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Regenerate. --- gcc/config/arm/arm-cpus.in | 10 ++++++++++ gcc/config/arm/arm-tables.opt | 3 +++ gcc/config/arm/arm-tune.md | 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0d3082b569f..5a63bc548e5 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1638,6 +1638,16 @@ begin cpu cortex-m55 vendor 41 end cpu cortex-m55 +begin cpu star-mc1 + cname starmc1 + tune flags LDSCHED + architecture armv8-m.main+dsp+fp + option nofp remove ALL_FP + option nodsp remove armv7em + isa quirk_no_asmcpu quirk_vlldm + costs v7m +end cpu star-mc1 + # V8 R-profile implementations. begin cpu cortex-r52 cname cortexr52 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ef0cc5ef0c8..e6461abcc57 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) EnumValue Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) +EnumValue +Enum(processor_type) String(star-mc1) Value( TARGET_CPU_starmc1) + EnumValue Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 34225536042..abc290edd09 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,6 +49,6 @@ cortexa710,cortexx1,neoversen1, cortexa75cortexa55,cortexa76cortexa55,neoversev1, neoversen2,cortexm23,cortexm33, - cortexm35p,cortexm55,cortexr52, - cortexr52plus" + cortexm35p,cortexm55,starmc1, + cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)"))) From patchwork Thu May 26 07:18:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Ju Wu X-Patchwork-Id: 54397 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5308538356BB for ; Thu, 26 May 2022 07:18:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5308538356BB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653549519; bh=e/gBdhRpVuOUEtC5aW1SUFubT82whG+qv31HJ7OEFkk=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=RAvDXMUCORnNI9oZPzYQvT6qZjvUv/9/VluNAB1V6CpIF4Aazmi8l4mFxDV7FRWqn yWgmMnPF7XLmb4de7WLIuUJYB2rDOBW9lk6zBxc1IoLYGD5BIibKvQG1OH4cgJT9Kj v0YzEnx/vnDKhQZACb42khP15np1F+2/1nXo+CT4= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id 514BA3834E42 for ; Thu, 26 May 2022 07:17:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 514BA3834E42 Received: by mail-pg1-x52e.google.com with SMTP id d129so651777pgc.9 for ; Thu, 26 May 2022 00:17:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent :content-language:from:subject:to:cc; bh=e/gBdhRpVuOUEtC5aW1SUFubT82whG+qv31HJ7OEFkk=; b=joZCU0Up5Ro43jxBAFBe3074aVzZbG8H7qfX9yS4R6Kcst8dTkJ5Utrj8bbNTjh3qM 2qrytQ1iw5VN6q9HmhPLgM2GNAoaRiII5a9p2DyEhYTx48QAUNySD2WFVsX4PQS7zhcP 04mKS46rc2q6SUWAvekHSD0BxdyvpH4r0HCOclIraRGY5HQCn6YOLFmEgCIuW5jAqmIR 4C09eWphiVgCs0Li5R0kCEVDQ/yzRXMM2JvDpjFbl/O13NnP4DQDDYvJU9+lHyO9g1+S /CjPuWFtHcLd8n11EoAAM/1czZ1mI2ssOXY1iVWDC0mVc+US6KlQUjT5YJJm8nYVIMxo wdqQ== X-Gm-Message-State: AOAM532ylt+H+Om81uW1ZzDyIBODQ0QBdA0/sMG/jD/F5sgF8lygDEzT k26maIqVVBHRD8XH8wPnVzk= X-Google-Smtp-Source: ABdhPJzGH5pPxW7B75UXArJ0LhIycFGFIFqVItskUESd/oN0lr6kKroAlt0VDEq+EdTZtp2+2alyJw== X-Received: by 2002:aa7:8b57:0:b0:518:7003:e28e with SMTP id i23-20020aa78b57000000b005187003e28emr29961583pfd.28.1653549475265; Thu, 26 May 2022 00:17:55 -0700 (PDT) Received: from [10.223.1.10] (114-43-72-38.dynamic-ip.hinet.net. [114.43.72.38]) by smtp.gmail.com with ESMTPSA id br19-20020a17090b0f1300b001d954837197sm2840712pjb.22.2022.05.26.00.17.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 May 2022 00:17:54 -0700 (PDT) Message-ID: Date: Thu, 26 May 2022 15:18:25 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Content-Language: en-US Subject: [PATCH 2/3][ARM] STAR-MC1 CPU Support - arm: Add individual star-mc1 cost tables and cost functions To: Richard.Earnshaw@arm.com, gcc-patches X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Chung-Ju Wu via Gcc-patches From: Chung-Ju Wu Reply-To: Chung-Ju Wu Cc: Jason.Wu@anshingtek.com.tw Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, Attached is the patch to provide star-mc1 specific cost functions and tables. Given these individual implementation, developers are able to make their own adjustment to fine-tune star-mc1 performance without affecting other cpu configurations. Bootstrapped and tested on arm-none-eabi. Is it OK for trunk? Regards, jasonwucj From e9081bb6d7fc1521036dbceec59ba2eae532c04c Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 26 May 2022 03:47:23 +0000 Subject: [PATCH 2/3] arm: Add individual star-mc1 cost tables and cost functions Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * config/arm/arm-cpus.in (star-mc1): Use star_mc1 costs. * config/arm/arm.cc (arm_star_mc1_branch_cost): New function. (star_mc1_extra_costs): New struct. (arm_star_mc1_tune): New struct. --- gcc/config/arm/arm-cpus.in | 2 +- gcc/config/arm/arm.cc | 139 +++++++++++++++++++++++++++++++++++++ 2 files changed, 140 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 5a63bc548e5..6a346e4a93d 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1645,7 +1645,7 @@ begin cpu star-mc1 option nofp remove ALL_FP option nodsp remove armv7em isa quirk_no_asmcpu quirk_vlldm - costs v7m + costs star_mc1 end cpu star-mc1 # V8 R-profile implementations. diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 70c2d50f0cc..c8f96f92a59 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -295,6 +295,7 @@ static int arm_default_branch_cost (bool, bool); static int arm_cortex_a5_branch_cost (bool, bool); static int arm_cortex_m_branch_cost (bool, bool); static int arm_cortex_m7_branch_cost (bool, bool); +static int arm_star_mc1_branch_cost (bool, bool); static bool arm_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, const vec_perm_indices &); @@ -1847,6 +1848,113 @@ const struct cpu_cost_table v7m_extra_costs = } }; +const struct cpu_cost_table star_mc1_extra_costs = +{ + /* ALU */ + { + 0, /* arith. */ + 0, /* logical. */ + 0, /* shift. */ + 0, /* shift_reg. */ + 0, /* arith_shift. */ + COSTS_N_INSNS (1), /* arith_shift_reg. */ + 0, /* log_shift. */ + COSTS_N_INSNS (1), /* log_shift_reg. */ + 0, /* extend. */ + COSTS_N_INSNS (1), /* extend_arith. */ + 0, /* bfi. */ + 0, /* bfx. */ + 0, /* clz. */ + 0, /* rev. */ + COSTS_N_INSNS (1), /* non_exec. */ + false /* non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (1), /* simple. */ + COSTS_N_INSNS (1), /* flag_setting. */ + COSTS_N_INSNS (2), /* extend. */ + COSTS_N_INSNS (1), /* add. */ + COSTS_N_INSNS (3), /* extend_add. */ + COSTS_N_INSNS (8) /* idiv. */ + }, + /* MULT DImode */ + { + 0, /* simple (N/A). */ + 0, /* flag_setting (N/A). */ + COSTS_N_INSNS (2), /* extend. */ + 0, /* add (N/A). */ + COSTS_N_INSNS (3), /* extend_add. */ + 0 /* idiv (N/A). */ + } + }, + /* LD/ST */ + { + COSTS_N_INSNS (2), /* load. */ + 0, /* load_sign_extend. */ + COSTS_N_INSNS (3), /* ldrd. */ + COSTS_N_INSNS (2), /* ldm_1st. */ + 1, /* ldm_regs_per_insn_1st. */ + 1, /* ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (2), /* loadf. */ + COSTS_N_INSNS (3), /* loadd. */ + COSTS_N_INSNS (1), /* load_unaligned. */ + COSTS_N_INSNS (2), /* store. */ + COSTS_N_INSNS (3), /* strd. */ + COSTS_N_INSNS (2), /* stm_1st. */ + 1, /* stm_regs_per_insn_1st. */ + 1, /* stm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (2), /* storef. */ + COSTS_N_INSNS (3), /* stored. */ + COSTS_N_INSNS (1), /* store_unaligned. */ + COSTS_N_INSNS (1), /* loadv. */ + COSTS_N_INSNS (1) /* storev. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (7), /* div. */ + COSTS_N_INSNS (2), /* mult. */ + COSTS_N_INSNS (5), /* mult_addsub. */ + COSTS_N_INSNS (3), /* fma. */ + COSTS_N_INSNS (1), /* addsub. */ + 0, /* fpconst. */ + 0, /* neg. */ + 0, /* compare. */ + 0, /* widen. */ + 0, /* narrow. */ + 0, /* toint. */ + 0, /* fromint. */ + 0 /* roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (15), /* div. */ + COSTS_N_INSNS (5), /* mult. */ + COSTS_N_INSNS (7), /* mult_addsub. */ + COSTS_N_INSNS (7), /* fma. */ + COSTS_N_INSNS (3), /* addsub. */ + 0, /* fpconst. */ + 0, /* neg. */ + 0, /* compare. */ + 0, /* widen. */ + 0, /* narrow. */ + 0, /* toint. */ + 0, /* fromint. */ + 0 /* roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1), /* alu. */ + COSTS_N_INSNS (4), /* mult. */ + COSTS_N_INSNS (1), /* movi. */ + COSTS_N_INSNS (2), /* dup. */ + COSTS_N_INSNS (2) /* extract. */ + } +}; + const struct addr_mode_cost_table generic_addr_mode_costs = { /* int. */ @@ -2370,6 +2478,30 @@ const struct tune_params arm_cortex_m7_tune = tune_params::SCHED_AUTOPREF_OFF }; +/* star-mc1 tuning. */ + +const struct tune_params arm_star_mc1_tune = +{ + &star_mc1_extra_costs, + &generic_addr_mode_costs, /* Addressing mode costs. */ + NULL, /* Sched adj cost. */ + arm_star_mc1_branch_cost, + &arm_default_vec_cost, + 1, /* Constant limit. */ + 2, /* Max cond insns. */ + 8, /* Memset max inline. */ + 1, /* Issue rate. */ + ARM_PREFETCH_NOT_BENEFICIAL, + tune_params::PREF_CONST_POOL_TRUE, + tune_params::PREF_LDRD_FALSE, + tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE, /* Thumb. */ + tune_params::LOG_OP_NON_SHORT_CIRCUIT_FALSE, /* ARM. */ + tune_params::DISPARAGE_FLAGS_NEITHER, + tune_params::PREF_NEON_STRINGOPS_FALSE, + tune_params::FUSE_NOTHING, + tune_params::SCHED_AUTOPREF_OFF +}; + /* The arm_v6m_tune is duplicated from arm_cortex_tune, rather than arm_v6t2_tune. It is used for cortex-m0, cortex-m1, cortex-m0plus and cortex-m23. */ @@ -12622,6 +12754,13 @@ arm_cortex_m7_branch_cost (bool speed_p, bool predictable_p) return speed_p ? 0 : arm_default_branch_cost (speed_p, predictable_p); } +static int +arm_star_mc1_branch_cost (bool speed_p, bool predictable_p) +{ + return (TARGET_32BIT && speed_p) ? 1 + : arm_default_branch_cost (speed_p, predictable_p); +} + static bool fp_consts_inited = false; static REAL_VALUE_TYPE value_fp0; From patchwork Thu May 26 07:19:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chung-Ju Wu X-Patchwork-Id: 54398 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9E4E938356B7 for ; Thu, 26 May 2022 07:19:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9E4E938356B7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653549576; bh=Md/7lDg4lesFd+5qq6rXHwkA6y7h5IsbiWyZ+7UZ9IQ=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=okbazDfliYrrehpU5peLf1iPNRVxvHGY1ma0O1f9tyvhkH6lPDv6ktP0j+V/G7rHT Px4uFupw7CSDFttqsNmSsxDdr89sGZUxflgSH9LDuI/o1HgmQka5bhUzrMjHHiEjkt /2OUJd77OkCbf1CGnmT7k3fTY48nOyJhKV3HEKgY= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by sourceware.org (Postfix) with ESMTPS id F3B1838356BA for ; Thu, 26 May 2022 07:18:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F3B1838356BA Received: by mail-pj1-x102d.google.com with SMTP id cs3-20020a17090af50300b001e0808b5838so1030883pjb.1 for ; Thu, 26 May 2022 00:18:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent :content-language:from:subject:to:cc; bh=Md/7lDg4lesFd+5qq6rXHwkA6y7h5IsbiWyZ+7UZ9IQ=; b=J7YP9yx9zENKG9yr28yq4VInNNtR1I31gC+EeTuNgNPXl8XIQ1v1ZmlxzSUco1XySd wBQ1Ly6J4bJyiuziInXupIkfVHacqb4ezNyFLdqsgsK+Lx2zZ+IFY2yfdVbhlCKvnr/b T839eqSrZgm3W/BCzAqujVSfXiwotbT4JbLRKaell/j8/1oW80XeUW7UR/rls/d3MtTC xQf6B+8Aklq3/YzkU8JsStsQpQsmIx5r9YDwZDisG8m/PDCPYfZrHZTnTFkVd/SJ9JOM v5kzkzPyfW5DRgzgdZ41vJ9HVo8SsNYbfYfhcfQx0EaFU4m6jGOwnJUQdlzsJOFQwQ4T HSMw== X-Gm-Message-State: AOAM532lnxhwWXFcBIwaWUOj7/kBwDJqFJM8B3+FcoAGMAOu4O7CJm6w TIAR/Kly18xSzV0rzIQiI5k= X-Google-Smtp-Source: ABdhPJzqCZ4wWOOYvmnGp5WNx1QjgnN4rj6ecVwOEgNj6Fl1klVW0H9j+7ib+/eENIwliMCGQXzVTQ== X-Received: by 2002:a17:90a:4413:b0:1cd:2d00:9d0b with SMTP id s19-20020a17090a441300b001cd2d009d0bmr1180361pjg.81.1653549522722; Thu, 26 May 2022 00:18:42 -0700 (PDT) Received: from [10.223.1.10] (114-43-72-38.dynamic-ip.hinet.net. [114.43.72.38]) by smtp.gmail.com with ESMTPSA id 76-20020a62184f000000b0050dc7628131sm704765pfy.11.2022.05.26.00.18.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 May 2022 00:18:42 -0700 (PDT) Message-ID: <32d83c13-a219-2320-f6b0-550489b6983f@gmail.com> Date: Thu, 26 May 2022 15:19:12 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Content-Language: en-US Subject: [PATCH 3/3][ARM] STAR-MC1 CPU Support - docs: Add star-mc1 core To: Richard.Earnshaw@arm.com, gcc-patches X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Chung-Ju Wu via Gcc-patches From: Chung-Ju Wu Reply-To: Chung-Ju Wu Cc: Jason.Wu@anshingtek.com.tw Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This is the patch to add star-mc1 in the Arm -mtune and -mfix-cmse-cve-2021-35465 sections of gcc invoke.texi documentation. Is it OK for trunk? Regards, jasonwucj From b3bd24d842b6284f2b893caa658975d9d746be73 Mon Sep 17 00:00:00 2001 From: Chung-Ju Wu Date: Thu, 26 May 2022 05:15:13 +0000 Subject: [PATCH 3/3] docs: Add star-mc1 core Signed-off-by: Chung-Ju Wu gcc/ChangeLog: * doc/invoke.text: Add star-mc1 core. --- gcc/doc/invoke.texi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 71098d86313..ac889e6e2b4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21181,7 +21181,8 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}, @samp{fa526}, @samp{fa626}, -@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{xgene1}. +@samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}, @samp{star-mc1}, +@samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible names are: @@ -21587,8 +21588,9 @@ Development Tools Engineering Specification", which can be found on Mitigate against a potential security issue with the @code{VLLDM} instruction in some M-profile devices when using CMSE (CVE-2021-365465). This option is enabled by default when the option @option{-mcpu=} is used with -@code{cortex-m33}, @code{cortex-m35p} or @code{cortex-m55}. The option -@option{-mno-fix-cmse-cve-2021-35465} can be used to disable the mitigation. +@code{cortex-m33}, @code{cortex-m35p}, @code{cortex-m55} or @code{star-mc1}. +The option @option{-mno-fix-cmse-cve-2021-35465} can be used to disable +the mitigation. @item -mstack-protector-guard=@var{guard} @itemx -mstack-protector-guard-offset=@var{offset}