From patchwork Wed May 25 03:39:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liu, Hongtao" X-Patchwork-Id: 54365 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 477E03856091 for ; Wed, 25 May 2022 03:39:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 477E03856091 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653449994; bh=GNeIibhCRI8LRXEFCRXOFwdcQ5fVveB9Wv/qAFv566Y=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=MwffykjsXmxvm2cmOkoP9ehbsp0++7KwSn4mD4zwZfEVh9x13zl0JynpnbE+jCMhI KBx7j2v5xHg3PLB6ZL+FdLX5/+8+YssQVJUejtYSsbK/PQNnxGB8vT0YQLVmU8CSsU sPcd9c760anRqQVld2qV6B5xXPcpuzHpf9up/CcA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 9F861385608A for ; Wed, 25 May 2022 03:39:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9F861385608A X-IronPort-AV: E=McAfee;i="6400,9594,10357"; a="273703254" X-IronPort-AV: E=Sophos;i="5.91,250,1647327600"; d="scan'208";a="273703254" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2022 20:39:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,250,1647327600"; d="scan'208";a="608943802" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga001.jf.intel.com with ESMTP; 24 May 2022 20:39:22 -0700 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds01.sc.intel.com with ESMTP id 24P3dLii021178; Tue, 24 May 2022 20:39:21 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Add a bit dislike for separate mem alternative when op is REG_P. Date: Wed, 25 May 2022 11:39:20 +0800 Message-Id: <20220525033920.77449-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: "Liu, Hongtao" Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Rigt now, mem_cost for separate mem alternative is 1 * frequency which is pretty small and caused the unnecessary SSE spill in the PR, I've tried to rework backend cost model, but RA still not happy with that(regress somewhere else). I think the root cause of this is cost for separate 'm' alternative cost is too small, especially considering that the mov cost of gpr are 2(default for REGISTER_MOVE_COST). So this patch increase mem_cost to 2*frequency, also increase 1 for reg_class cost when m alternative. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/105513 * ira-costs.cc (record_reg_classes): Increase both mem_cost and reg class cost by 1 for separate mem alternative when REG_P (op). gcc/testsuite/ChangeLog: * gcc.target/i386/pr105513-1.c: New test. --- gcc/ira-costs.cc | 26 +++++++++++++--------- gcc/testsuite/gcc.target/i386/pr105513-1.c | 16 +++++++++++++ 2 files changed, 31 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr105513-1.c diff --git a/gcc/ira-costs.cc b/gcc/ira-costs.cc index 964c94a06ef..f7b8325e195 100644 --- a/gcc/ira-costs.cc +++ b/gcc/ira-costs.cc @@ -625,7 +625,8 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, for (k = cost_classes_ptr->num - 1; k >= 0; k--) { rclass = cost_classes[k]; - pp_costs[k] = mem_cost[rclass][0] * frequency; + pp_costs[k] = (mem_cost[rclass][0] + + 1) * frequency; } } else @@ -648,7 +649,8 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, for (k = cost_classes_ptr->num - 1; k >= 0; k--) { rclass = cost_classes[k]; - pp_costs[k] = mem_cost[rclass][1] * frequency; + pp_costs[k] = (mem_cost[rclass][1] + + 1) * frequency; } } else @@ -670,9 +672,9 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, for (k = cost_classes_ptr->num - 1; k >= 0; k--) { rclass = cost_classes[k]; - pp_costs[k] = ((mem_cost[rclass][0] - + mem_cost[rclass][1]) - * frequency); + pp_costs[k] = (mem_cost[rclass][0] + + mem_cost[rclass][1] + + 2) * frequency; } } else @@ -861,7 +863,8 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, for (k = cost_classes_ptr->num - 1; k >= 0; k--) { rclass = cost_classes[k]; - pp_costs[k] = mem_cost[rclass][0] * frequency; + pp_costs[k] = (mem_cost[rclass][0] + + 1) * frequency; } } else @@ -884,7 +887,8 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, for (k = cost_classes_ptr->num - 1; k >= 0; k--) { rclass = cost_classes[k]; - pp_costs[k] = mem_cost[rclass][1] * frequency; + pp_costs[k] = (mem_cost[rclass][1] + + 1) * frequency; } } else @@ -906,9 +910,9 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, for (k = cost_classes_ptr->num - 1; k >= 0; k--) { rclass = cost_classes[k]; - pp_costs[k] = ((mem_cost[rclass][0] - + mem_cost[rclass][1]) - * frequency); + pp_costs[k] = (mem_cost[rclass][0] + + mem_cost[rclass][1] + + 2) * frequency; } } else @@ -929,7 +933,7 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops, /* Although we don't need insn to reload from memory, still accessing memory is usually more expensive than a register. */ - pp->mem_cost = frequency; + pp->mem_cost = 2 * frequency; else /* If the alternative actually allows memory, make things a bit cheaper since we won't need an diff --git a/gcc/testsuite/gcc.target/i386/pr105513-1.c b/gcc/testsuite/gcc.target/i386/pr105513-1.c new file mode 100644 index 00000000000..530f5292252 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105513-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -msse2 -mtune=skylake -mfpmath=sse" } */ +/* { dg-final { scan-assembler-not "\\(%rsp\\)" } } */ + +static int as_int(float x) +{ + return (union{float x; int i;}){x}.i; +} + +float f(double y, float x) +{ + int i = as_int(x); + if (__builtin_expect(i > 99, 0)) return 0; + if (i*2u < 77) if (i==2) return 0; + return y*x; +}