From patchwork Tue May 24 21:47:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 54357 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2AF59384402D for ; Tue, 24 May 2022 21:47:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by sourceware.org (Postfix) with ESMTPS id 30A1D3857BAC for ; Tue, 24 May 2022 21:47:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 30A1D3857BAC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x236.google.com with SMTP id u7so21717989ljd.11 for ; Tue, 24 May 2022 14:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HpryVCj3GWxFgJnjpm5GAK3+bcuviAoOAFvkJwQfiTc=; b=EmKsgcrSqZ1k/Bvh7sS9twHLWhOdVW+QrrRBt+0grreJfTS3UHPBOlAhrwoHXhGZbs xDfBP0bo1H9PwgWj/Niddb8+1cuFpPW0Qndun4y3X5NXb0z75nWB87Y8nx9meOcSQWGQ Pjp2h9klF+VoxfWzUnemFFrh60xAByazes2kvfD88N+/H1DqmCU2SuKIUOGVsFVRXjFF 5VN93xYCND++Kknzc/eLVIQwasKzW3MACtHEcBRVyfH2fsae/dOzhSuXHkIuI1YQ08Ko 6cX3BqCIbZt1PbL+QFAYBUE9yA5AQgNbkvuWwJ0GqkFUvTfef5pi0XH/F+wu/R19xAe7 rTPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HpryVCj3GWxFgJnjpm5GAK3+bcuviAoOAFvkJwQfiTc=; b=hch8L98//geQKJfYbJ39Q9OMlDjUbg6JeySrhq6uIZu8J5VjHKR3o1tfAXscEaH7/P g4oP4m6naUy/lhqEHaBI3KWL/4/A2JjiTtUVE/ySDTiygrZpbgPoWvPu/LI2hE/kQNKg tgEOsB7zrypw1O5b6XXGO7kv7JWh/IfugF1iKTDco1E4tUhkK+DPAqpmQPmuuPN10mfP VEXwkrQhLQbW4ue8yeG8YTNsOVQcFVIUB5Gv9LF8it3GkL94/KDhOtM8GbhDsXQR3M6A 6WnzmDXHjAbXQHmjGzbWp5mSIREggrbXUDiqiNd4/XPfLC95Bkq5qmqHJgNZ2lwq6mUj idxA== X-Gm-Message-State: AOAM530dXtfdhgIpKjvzhfvBb88pRPMhv9uv+5PlyH5/dCQYhSswbz8d Mp/naGOzc7kLIrtAY0RB2exBHdm4AEP+WYgs X-Google-Smtp-Source: ABdhPJxnX6XlLsSvvKdM9XAB+taxpct6eUpRPbTqzkpMgmaTL/8X2xgnmiMKYspx+FGozdvCb47Z1g== X-Received: by 2002:a2e:9d93:0:b0:253:c9bd:288 with SMTP id c19-20020a2e9d93000000b00253c9bd0288mr17118420ljj.223.1653428831455; Tue, 24 May 2022 14:47:11 -0700 (PDT) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c17-20020a2e9d91000000b0024f3d1dae98sm2724165ljj.32.2022.05.24.14.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 14:47:10 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 1/3] RISC-V: add consecutive_bits_operand predicate Date: Tue, 24 May 2022 23:47:01 +0200 Message-Id: <20220524214703.4022737-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> References: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Provide an easy way to constrain for constants that are a a single, consecutive run of ones. gcc/ChangeLog: * config/riscv/predicates.md (consecutive_bits_operand): Implement new predicate. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/predicates.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index c37caa2502b..90db5dfcdd5 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -243,3 +243,14 @@ (define_predicate "const63_operand" (define_predicate "imm5_operand" (and (match_code "const_int") (match_test "INTVAL (op) < 5"))) + +;; A CONST_INT operand that consists of a single run of consecutive set bits. +(define_predicate "consecutive_bits_operand" + (match_code "const_int") +{ + unsigned HOST_WIDE_INT val = UINTVAL (op); + if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0) + return false; + + return true; +}) From patchwork Tue May 24 21:47:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 54358 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B0805384B0C3 for ; Tue, 24 May 2022 21:48:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by sourceware.org (Postfix) with ESMTPS id 7CBE138425B2 for ; Tue, 24 May 2022 21:47:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7CBE138425B2 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x133.google.com with SMTP id l13so26370223lfp.11 for ; Tue, 24 May 2022 14:47:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mKNQ195eorr9ntjXz+K+EWBXU7mx76ff3hCq5bbpymA=; b=KWI6HWyt+uXMq/ZdWIqpT1JbZ1Jdj+4cSgVWfBYDCypAQRARCgVciTb+norPaZ4Rdl vOPsscQFQD0q6xxSvwsPQwfaIMdXGvQy8UIME85K1TZIHgIInmcMkqTuT3iGk2WiuUqr n42cRunPb9GVVa7mj1C2l11rNhlx2Zwk2B8H6gT4hpvPrR0vaTF56QXl2Bq7umCDj2U1 +UndnpXNZl7WD98fuuSCkxn3eSMMCO/P8dzRCvvJjejSyK9SAxbQLDD376xZZMR4YIOz qCYDXXqGGfgo31e8CIsnhLxeEiaHHrvS7EfzaZIWwftCeQrO4dSqucA0vhlrv3qrpQ0x vv6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mKNQ195eorr9ntjXz+K+EWBXU7mx76ff3hCq5bbpymA=; b=J1mV+VGLDZ7JO31caq2/E9UjsHBo/jZbhlO3SQSyVwj5jD5OyCKAYwzyekkS09HntT oYqsCWaRaYELYMj/h05QyKghOKghASI/OvydkQrnWJA01K3+N+00RRSQEUqIXQn4Svgy 2lO5SWGo3uHml2Vr6Lr7ZVVAnjaUda8I7FbL4X5ZqwhyeIDB07IOWKHgFBzoiPySmmQz dhD654zDSuugY7mANKqXmIE9iR0c5jSmsncYfXYPoYvj5vHZsUuRlaGo9fO4Fb8Djhn8 WhnOk613un17lE7IGGoYL3jK/c6Dg+V59PR31mhyrUtrh8NuYZBPC2LWTXVLnWfIFEJC q6Kw== X-Gm-Message-State: AOAM5337IwOWcAVYJRCkDAazp7+cu1+04bfyXqjd7CbS+37AXqYMp8mm eN5rSBuTCIR5V+nUPgnc2TdlYKJpqxx7Q1x9 X-Google-Smtp-Source: ABdhPJyccfwmHlh6gVwI6SRCFT+qIgkBOYNu0w+MqXADID2seNxZExGGXVwhByjvJCA1YoVpcGZUSA== X-Received: by 2002:ac2:5bdc:0:b0:478:6d6d:9bf2 with SMTP id u28-20020ac25bdc000000b004786d6d9bf2mr9399156lfn.633.1653428833751; Tue, 24 May 2022 14:47:13 -0700 (PDT) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c17-20020a2e9d91000000b0024f3d1dae98sm2724165ljj.32.2022.05.24.14.47.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 14:47:13 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 2/3] RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w Date: Tue, 24 May 2022 23:47:02 +0200 Message-Id: <20220524214703.4022737-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> References: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When encountering a prescaled (biased) value as a candidate for sh[123]add.uw, the combine pass will present this as shifted by the aggregate amount (prescale + shift-amount) with an appropriately adjusted mask constant that has fewer than 32 bits set. E.g., here's the failing expression seen in combine for a prescale of 1 and a shift of 2 (note how 0x3fffffff8 >> 3 is 0x7fffffff). Trying 7, 8 -> 10: 7: r78:SI=r81:DI#0<<0x1 REG_DEAD r81:DI 8: r79:DI=zero_extend(r78:SI) REG_DEAD r78:SI 10: r80:DI=r79:DI<<0x2+r82:DI REG_DEAD r79:DI REG_DEAD r82:DI Failed to match this instruction: (set (reg:DI 80 [ cD.1491 ]) (plus:DI (and:DI (ashift:DI (reg:DI 81) (const_int 3 [0x3])) (const_int 17179869176 [0x3fffffff8])) (reg:DI 82))) To address this, we introduce a splitter handling these cases. gcc/ChangeLog: * config/riscv/bitmanip.md: Add split to handle opportunities for slli + sh[123]add.uw gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shadd.c: New test. Signed-off-by: Philipp Tomsich Co-developed-by: Manolis Tsamis --- gcc/config/riscv/bitmanip.md | 44 ++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zba-shadd.c | 13 +++++++ 2 files changed, 57 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shadd.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 0ab9ffe3c0b..6c1ccc6f8c5 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -79,6 +79,50 @@ (define_insn "*shNadduw" [(set_attr "type" "bitmanip") (set_attr "mode" "DI")]) +;; During combine, we may encounter an attempt to combine +;; slli rtmp, rs, #imm +;; zext.w rtmp, rtmp +;; sh[123]add rd, rtmp, rs2 +;; which will lead to the immediate not satisfying the above constraints. +;; By splitting the compound expression, we can simplify to a slli and a +;; sh[123]add.uw. +(define_split + [(set (match_operand:DI 0 "register_operand") + (plus:DI (and:DI (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand:QI 2 "immediate_operand")) + (match_operand:DI 3 "consecutive_bits_operand")) + (match_operand:DI 4 "register_operand"))) + (clobber (match_operand:DI 5 "register_operand"))] + "TARGET_64BIT && TARGET_ZBA" + [(set (match_dup 5) (ashift:DI (match_dup 1) (match_dup 6))) + (set (match_dup 0) (plus:DI (and:DI (ashift:DI (match_dup 5) + (match_dup 7)) + (match_dup 8)) + (match_dup 4)))] +{ + unsigned HOST_WIDE_INT mask = UINTVAL (operands[3]); + /* scale: shift within the sh[123]add.uw */ + int scale = 32 - clz_hwi (mask); + /* bias: pre-scale amount (i.e. the prior shift amount) */ + int bias = ctz_hwi (mask) - scale; + + /* If the bias + scale don't add up to operand[2], reject. */ + if ((scale + bias) != UINTVAL (operands[2])) + FAIL; + + /* If the shift-amount is out-of-range for sh[123]add.uw, reject. */ + if ((scale < 1) || (scale > 3)) + FAIL; + + /* If there's no bias, the '*shNadduw' pattern should have matched. */ + if (bias == 0) + FAIL; + + operands[6] = GEN_INT (bias); + operands[7] = GEN_INT (scale); + operands[8] = GEN_INT (0xffffffffULL << scale); +}) + (define_insn "*add.uw" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (zero_extend:DI diff --git a/gcc/testsuite/gcc.target/riscv/zba-shadd.c b/gcc/testsuite/gcc.target/riscv/zba-shadd.c new file mode 100644 index 00000000000..33da2530f3f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shadd.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_zba -mabi=lp64" } */ + +unsigned long foo(unsigned int a, unsigned long b) +{ + a = a << 1; + unsigned long c = (unsigned long) a; + unsigned long d = b + (c<<2); + return d; +} + +/* { dg-final { scan-assembler "sh2add.uw" } } */ +/* { dg-final { scan-assembler-not "zext" } } */ \ No newline at end of file From patchwork Tue May 24 21:47:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 54359 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 33E353857BBE for ; Tue, 24 May 2022 21:48:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by sourceware.org (Postfix) with ESMTPS id 7123338485AD for ; Tue, 24 May 2022 21:47:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7123338485AD Authentication-Results: sourceware.org; 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c17-20020a2e9d91000000b0024f3d1dae98sm2724165ljj.32.2022.05.24.14.47.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 14:47:15 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 3/3] RISC-V: Replace zero_extendsidi2_shifted with generalized split Date: Tue, 24 May 2022 23:47:03 +0200 Message-Id: <20220524214703.4022737-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> References: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The current method of treating shifts of extended values on RISC-V frequently causes sequences of 3 shifts, despite the presence of the 'zero_extendsidi2_shifted' pattern. Consider: unsigned long f(unsigned int a, unsigned long b) { a = a << 1; unsigned long c = (unsigned long) a; c = b + (c<<4); return c; } which will present at combine-time as: Trying 7, 8 -> 9: 7: r78:SI=r81:DI#0<<0x1 REG_DEAD r81:DI 8: r79:DI=zero_extend(r78:SI) REG_DEAD r78:SI 9: r72:DI=r79:DI<<0x4 REG_DEAD r79:DI Failed to match this instruction: (set (reg:DI 72 [ _1 ]) (and:DI (ashift:DI (reg:DI 81) (const_int 5 [0x5])) (const_int 68719476704 [0xfffffffe0]))) and produce the following (optimized) assembly: f: slliw a5,a0,1 slli a5,a5,32 srli a5,a5,28 add a0,a5,a1 ret The current way of handling this (in 'zero_extendsidi2_shifted') doesn't apply for two reasons: - this is seen before reload, and - (more importantly) the constant mask is not 0xfffffffful. To address this, we introduce a generalized version of shifting zero-extended values that supports any mask of consecutive ones as long as the number of training zeros is the inner shift-amount. With this new split, we generate the following assembly for the aforementioned function: f: slli a0,a0,33 srli a0,a0,28 add a0,a0,a1 ret gcc/ChangeLog: * config/riscv/riscv.md (zero_extendsidi2_shifted): Replace with a generalized split that requires no clobber, runs before reload and works for smaller masks. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.md | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index b8ab0cf169a..cc10cd90a74 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2119,23 +2119,26 @@ (define_split ;; occur when unsigned int is used for array indexing. Split this into two ;; shifts. Otherwise we can get 3 shifts. -(define_insn_and_split "zero_extendsidi2_shifted" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "I")) - (match_operand 3 "immediate_operand" ""))) - (clobber (match_scratch:DI 4 "=&r"))] - "TARGET_64BIT && !TARGET_ZBA - && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)" - "#" - "&& reload_completed" - [(set (match_dup 4) - (ashift:DI (match_dup 1) (const_int 32))) - (set (match_dup 0) - (lshiftrt:DI (match_dup 4) (match_dup 5)))] - "operands[5] = GEN_INT (32 - (INTVAL (operands [2])));" - [(set_attr "type" "shift") - (set_attr "mode" "DI")]) +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand:QI 2 "immediate_operand")) + (match_operand:DI 3 "consecutive_bits_operand")))] + "TARGET_64BIT" + [(set (match_dup 0) (ashift:DI (match_dup 1) (match_dup 4))) + (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 5)))] +{ + unsigned HOST_WIDE_INT mask = UINTVAL (operands[3]); + int leading = clz_hwi (mask); + int trailing = ctz_hwi (mask); + + /* The shift-amount must match the number of trailing bits */ + if (trailing != UINTVAL (operands[2])) + FAIL; + + operands[4] = GEN_INT (leading + trailing); + operands[5] = GEN_INT (leading); +}) ;; ;; ....................