From patchwork Fri May 13 14:52:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 53954 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A1C09396E43A for ; Fri, 13 May 2022 14:52:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A1C09396E43A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1652453569; bh=7Q/ilZXr10OdSFn5acJjP66LanyA/yNB4zi7XHtAM3A=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=NyLeomYGAbQbJ8oVd5Yw+cx3LFKjKO2xqqIHKEbpuuRHN/dP32VwpO4jehXpySyM1 sFn5VnTepKKOEE319xMzSG5F85aRt/89WAuPrZBdhCQ7dKRybt7gisPfpA+3Ljj8qM y2W2GsusxNugv7SwzdmkTYQ1nuVV+XW7r/WjaoAE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 64A393959CAE for ; Fri, 13 May 2022 14:52:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 64A393959CAE Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24DEg9a0030715; Fri, 13 May 2022 14:52:19 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3g1ra81vxt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 May 2022 14:52:18 +0000 Received: from m0098417.ppops.net (m0098417.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 24DEhUue003683; Fri, 13 May 2022 14:52:18 GMT Received: from ppma01dal.us.ibm.com (83.d6.3fa9.ip4.static.sl-reverse.com [169.63.214.131]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3g1ra81vxj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 May 2022 14:52:18 +0000 Received: from pps.filterd (ppma01dal.us.ibm.com [127.0.0.1]) by ppma01dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 24DEhIe3028591; Fri, 13 May 2022 14:52:17 GMT Received: from b03cxnp08025.gho.boulder.ibm.com (b03cxnp08025.gho.boulder.ibm.com [9.17.130.17]) by ppma01dal.us.ibm.com with ESMTP id 3fwgdbdmk7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 13 May 2022 14:52:17 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 24DEqGmO36438354 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 May 2022 14:52:16 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1CFCF6E059; Fri, 13 May 2022 14:52:16 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8B5356E053; Fri, 13 May 2022 14:52:15 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.65.255.130]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTPS; Fri, 13 May 2022 14:52:15 +0000 (GMT) Date: Fri, 13 May 2022 10:52:14 -0400 To: gcc-patches@gcc.gnu.org, Michael Meissner , Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH] Replace UNSPEC with RTL code for extendditi2. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt MIME-Version: 1.0 Content-Disposition: inline X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: bfdgApWzdXAb5F5CjZOYXeFbk_LP0Ner X-Proofpoint-GUID: A0-UejA-VLEU-gQlTEJ3PWjTxFMMgVqO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-13_04,2022-05-13_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2205130064 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Replace UNSPEC with RTL code for extendditi2. When I submitted my patch on March 12th for extendditi2, Segher wished I had removed the use of the UNSPEC for the vextsd2q instruction. This patch rewrites extendditi2_vector to use VEC_SELECT rather than UNSPEC. 2022-05-13 Michael Meissner gcc/ * config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete. (extendditi2_vector): Rewrite to use VEC_SELECT as a define_expand. (extendditi2_vector2): New insn. --- gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index a1a1ce95195..c091e5e2f47 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -358,7 +358,6 @@ (define_c_enum "unspec" UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX UNSPEC_XXGENPCV UNSPEC_MTVSBM - UNSPEC_EXTENDDITI2 UNSPEC_VCNTMB UNSPEC_VEXPAND UNSPEC_VEXTRACT @@ -5083,10 +5082,25 @@ (define_insn_and_split "extendditi2" (set_attr "type" "shift,load,vecmove,vecperm,load")]) ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg -(define_insn "extendditi2_vector" +(define_expand "extendditi2_vector" + [(use (match_operand:TI 0 "gpc_reg_operand")) + (use (match_operand:TI 1 "gpc_reg_operand"))] + "TARGET_POWER10" +{ + rtx dest = operands[0]; + rtx src_v2di = gen_lowpart (V2DImode, operands[1]); + rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT); + + emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element)); + DONE; +}) + +(define_insn "extendditi2_vector2" [(set (match_operand:TI 0 "gpc_reg_operand" "=v") - (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")] - UNSPEC_EXTENDDITI2))] + (sign_extend:TI + (vec_select:DI + (match_operand:V2DI 1 "gpc_reg_operand" "v") + (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))] "TARGET_POWER10" "vextsd2q %0,%1" [(set_attr "type" "vecexts")])