From patchwork Tue May 10 03:25:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong X-Patchwork-Id: 53691 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5335C3838038 for ; Tue, 10 May 2022 03:26:40 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 9BD4F38485AD for ; Tue, 10 May 2022 03:25:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9BD4F38485AD Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.88.16.30]) by APP-01 (Coremail) with SMTP id qwCowAAHnhU323lioBtBBQ--.37585S3; Tue, 10 May 2022 11:25:49 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH V4 1/3] RISC-V: Add mininal support for Zicbo[mzp] Date: Tue, 10 May 2022 11:25:24 +0800 Message-Id: <20220510032526.11560-2-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220510032526.11560-1-shiyulong@iscas.ac.cn> References: <20220510032526.11560-1-shiyulong@iscas.ac.cn> X-CM-TRANSID: qwCowAAHnhU323lioBtBBQ--.37585S3 X-Coremail-Antispam: 1UD129KBjvJXoWxAFW7uF47tF45Wr4DJFW7twb_yoW5ur1xpF 4kW39Ivw1FqrsxWw4xtw1rW345A3ZYgr1rCr4ru34UA3yDXrWkAF1q9w13Zr4kXFZ8Zr92 v3WY93909a1UCa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBq14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWl e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lw4CEc2x0rVAKj4xxMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2 80aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUjKL9UUUUUU== X-Originating-IP: [47.88.16.30] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@sifive.com, yulong , kito.cheng@gmail.com, jiawei@iscas.ac.cn, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. (MASK_ZICBOM): New. (MASK_ZICBOP): New. (TARGET_ZICBOZ): New. (TARGET_ZICBOM): New. (TARGET_ZICBOP): New. * config/riscv/riscv.opt: New. --- gcc/common/config/riscv/riscv-common.cc | 8 ++++++++ gcc/config/riscv/riscv-opts.h | 8 ++++++++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 19 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 1501242e296..bf7a7caabef 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -165,6 +165,10 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zk", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkn", ISA_SPEC_CLASS_NONE, 1, 0}, {"zks", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1110,6 +1114,10 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, + {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, + {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, + {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve64x", &gcc_options::x_target_flags, MASK_VECTOR}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 15bb5e76854..1e153b3a6e7 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -145,6 +145,14 @@ enum stack_protector_guard { #define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0) #define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0) +#define MASK_ZICBOZ (1 << 0) +#define MASK_ZICBOM (1 << 1) +#define MASK_ZICBOP (1 << 2) + +#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0) +#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) +#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) + /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to caclulate the minimal VLEN. */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 492aad12324..d1b3c1840a6 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -209,6 +209,9 @@ int riscv_vector_elen_flags TargetVariable int riscv_zvl_flags +TargetVariable +int riscv_zicmo_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): From patchwork Tue May 10 03:25:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong X-Patchwork-Id: 53692 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CD6E83839439 for ; Tue, 10 May 2022 03:27:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 33932385735F for ; Tue, 10 May 2022 03:25:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 33932385735F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.88.16.30]) by APP-01 (Coremail) with SMTP id qwCowAAHnhU323lioBtBBQ--.37585S4; Tue, 10 May 2022 11:25:52 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH V4 2/3] RISC-V:Cache Management Operation instructions Date: Tue, 10 May 2022 11:25:25 +0800 Message-Id: <20220510032526.11560-3-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220510032526.11560-1-shiyulong@iscas.ac.cn> References: <20220510032526.11560-1-shiyulong@iscas.ac.cn> X-CM-TRANSID: qwCowAAHnhU323lioBtBBQ--.37585S4 X-Coremail-Antispam: 1UD129KBjvJXoWxKryUCF1rGr1kKw15Jry3XFb_yoWxKryUpa 9rGw45C3s8ZwnI93yftFWUJ34rAwnagw4Yk3sxZrWqyayUZ3yDAF1qkayIqrWDZF1rJw1a 9FyakFyF9w4jk3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVWxJr0_GcWl e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lw4CEc2x0rVAKj4xxMxAIw2 8IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4l x2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrw CI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI 42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z2 80aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUU_-PUUUUUU== X-Originating-IP: [47.88.16.30] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@sifive.com, yulong , kito.cheng@gmail.com, jiawei@iscas.ac.cn, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions. diff with the previous version: We use unspec_volatile instead of unspec for those cache operations. We use UNSPECV instead of UNSPEC and move them to unspecv. gcc/ChangeLog: * config/riscv/predicates.md (imm5_operand): Add a new operand type for prefetch instructions. * config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA Extensions. (RISCV_ATYPE_SI): New. (RISCV_ATYPE_DI): New. * config/riscv/riscv-ftypes.def (0): New. (1): New. * config/riscv/riscv.md (riscv_clean_): New. (riscv_flush_): New. (riscv_inval_): New. (riscv_zero_): New. (prefetch): New. (riscv_prefetchi_): New. * config/riscv/riscv-cmo.def: New file. --- gcc/config/riscv/predicates.md | 4 +++ gcc/config/riscv/riscv-builtins.cc | 16 ++++++++++ gcc/config/riscv/riscv-cmo.def | 17 ++++++++++ gcc/config/riscv/riscv-ftypes.def | 4 +++ gcc/config/riscv/riscv.md | 51 ++++++++++++++++++++++++++++++ 5 files changed, 92 insertions(+) create mode 100644 gcc/config/riscv/riscv-cmo.def diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 97cdbdf053b..3fb4d95ab08 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -239,3 +239,7 @@ (define_predicate "const63_operand" (and (match_code "const_int") (match_test "INTVAL (op) == 63"))) + +(define_predicate "imm5_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) < 5"))) \ No newline at end of file diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 0658f8d3047..795132a0c16 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -87,6 +87,18 @@ struct riscv_builtin_description { AVAIL (hard_float, TARGET_HARD_FLOAT) + +AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) +AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) +AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) +AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) + /* Construct a riscv_builtin_description from the given arguments. INSN is the name of the associated instruction pattern, without the @@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) /* Argument types. */ #define RISCV_ATYPE_VOID void_type_node #define RISCV_ATYPE_USI unsigned_intSI_type_node +#define RISCV_ATYPE_SI intSI_type_node +#define RISCV_ATYPE_DI intDI_type_node /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists their associated RISCV_ATYPEs. */ @@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) RISCV_ATYPE_##A, RISCV_ATYPE_##B static const struct riscv_builtin_description riscv_builtins[] = { + #include "riscv-cmo.def" + DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float) }; diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def new file mode 100644 index 00000000000..01cbf6ad64f --- /dev/null +++ b/gcc/config/riscv/riscv-cmo.def @@ -0,0 +1,17 @@ +// zicbom +RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32), +RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64), + +RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32), +RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64), + +RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32), +RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64), + +// zicboz +RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32), +RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64), + +// zicbop +RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32), +RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64), \ No newline at end of file diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 2214c496f9b..62421292ce7 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -28,3 +28,7 @@ along with GCC; see the file COPYING3. If not see DEF_RISCV_FTYPE (0, (USI)) DEF_RISCV_FTYPE (1, (VOID, USI)) +DEF_RISCV_FTYPE (0, (SI)) +DEF_RISCV_FTYPE (0, (DI)) +DEF_RISCV_FTYPE (1, (SI, SI)) +DEF_RISCV_FTYPE (1, (DI, DI)) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index b3c5bce842a..b96d0c30e59 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -69,6 +69,11 @@ ;; Stack Smash Protector UNSPEC_SSP_SET UNSPEC_SSP_TEST + UNSPECV_CLEAN + UNSPECV_FLUSH + UNSPECV_INVAL + UNSPECV_ZERO + UNSPECV_PREI ]) (define_constants @@ -2863,6 +2868,52 @@ "\t%3, %1\;\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" [(set_attr "length" "12")]) +(define_insn "riscv_clean_" +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_CLEAN)] +"TARGET_ZICBOM" +"cbo.clean\t%a0" +) + +(define_insn "riscv_flush_" +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_FLUSH)] +"TARGET_ZICBOM" +"cbo.flush\t%a0" +) + +(define_insn "riscv_inval_" +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_INVAL)] +"TARGET_ZICBOM" +"cbo.inval\t%a0" +) + +(define_insn "riscv_zero_" +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_ZERO)] +"TARGET_ZICBOZ" +"cbo.zero\t%a0" +) + +(define_insn "prefetch" +[(prefetch (match_operand 0 "address_operand" "p") + (match_operand 1 "imm5_operand" "i") + (match_operand 2 "const_int_operand" "n"))] +"TARGET_ZICBOP" +{ + switch (INTVAL (operands[1])) + { + case 0: return "prefetch.r\t%a0"; + case 1: return "prefetch.w\t%a0"; + default: gcc_unreachable (); + } +}) + +(define_insn "riscv_prefetchi_" +[(unspec_volatile:X [(match_operand:X 0 "address_operand" "p") + (match_operand:X 1 "imm5_operand" "i")] + UNSPECV_PREI)] +"TARGET_ZICBOP" +"prefetch.i\t%a0" +) + (include "bitmanip.md") (include "sync.md") (include "peephole.md") From patchwork Tue May 10 03:25:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong X-Patchwork-Id: 53693 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0864638346B3 for ; Tue, 10 May 2022 03:27:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 8FF5F3870871 for ; Tue, 10 May 2022 03:25:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8FF5F3870871 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.88.16.30]) by APP-01 (Coremail) with SMTP id qwCowAAHnhU323lioBtBBQ--.37585S5; Tue, 10 May 2022 11:25:54 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH V4 3/3] RISC-V:Cache Management Operation instructions testcases Date: Tue, 10 May 2022 11:25:26 +0800 Message-Id: <20220510032526.11560-4-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220510032526.11560-1-shiyulong@iscas.ac.cn> References: <20220510032526.11560-1-shiyulong@iscas.ac.cn> X-CM-TRANSID: qwCowAAHnhU323lioBtBBQ--.37585S5 X-Coremail-Antispam: 1UD129KBjvJXoWxKF4rGw4fAF47WFyrXw4fXwb_yoW7ZFy3p3 97Gw4IvrWrZF97Grs3GF1UJwsIvrs2gry5u3s7CryUXrs7trW2q3Z7trW7Jr45JF1UJryf ua129a1ru3Wjqw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxd M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4kE6xkIj40Ew7xC0wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUPHUDUUUUU= X-Originating-IP: [47.88.16.30] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@sifive.com, yulong , kito.cheng@gmail.com, jiawei@iscas.ac.cn, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong This commit adds testcases about CMO instructions. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbom-1.c: New test. * gcc.target/riscv/cmo-zicbom-2.c: New test. * gcc.target/riscv/cmo-zicbop-1.c: New test. * gcc.target/riscv/cmo-zicbop-2.c: New test. * gcc.target/riscv/cmo-zicboz-1.c: New test. * gcc.target/riscv/cmo-zicboz-2.c: New test. --- gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 ++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 ++++++++ 6 files changed, 106 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c new file mode 100644 index 00000000000..e2ba2183511 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */ + +int foo1() +{ + return __builtin_riscv_zicbom_cbo_clean(); +} + +int foo2() +{ + return __builtin_riscv_zicbom_cbo_flush(); +} + +int foo3() +{ + return __builtin_riscv_zicbom_cbo_inval(); +} + +/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c new file mode 100644 index 00000000000..a605e8b1bdc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zicbom -mabi=ilp32" } */ + +int foo1() +{ + return __builtin_riscv_zicbom_cbo_clean(); +} + +int foo2() +{ + return __builtin_riscv_zicbom_cbo_flush(); +} + +int foo3() +{ + return __builtin_riscv_zicbom_cbo_inval(); +} + +/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c new file mode 100644 index 00000000000..c5d78c1763d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile target { { rv64-*-*}}} */ +/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ + +void foo (char *p) +{ + __builtin_prefetch (p, 0, 0); + __builtin_prefetch (p, 0, 1); + __builtin_prefetch (p, 0, 2); + __builtin_prefetch (p, 0, 3); + __builtin_prefetch (p, 1, 0); + __builtin_prefetch (p, 1, 1); + __builtin_prefetch (p, 1, 2); + __builtin_prefetch (p, 1, 3); +} + +int foo1() +{ + return __builtin_riscv_zicbop_cbo_prefetchi(1); +} + +/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c new file mode 100644 index 00000000000..6576365b39c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile target { { rv32-*-*}}} */ +/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */ + +void foo (char *p) +{ + __builtin_prefetch (p, 0, 0); + __builtin_prefetch (p, 0, 1); + __builtin_prefetch (p, 0, 2); + __builtin_prefetch (p, 0, 3); + __builtin_prefetch (p, 1, 0); + __builtin_prefetch (p, 1, 1); + __builtin_prefetch (p, 1, 2); + __builtin_prefetch (p, 1, 3); +} + +int foo1() +{ + return __builtin_riscv_zicbop_cbo_prefetchi(1); +} + +/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c new file mode 100644 index 00000000000..96c1674ef2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicboz -mabi=lp64" } */ + +int foo1() +{ + return __builtin_riscv_zicboz_cbo_zero(); +} + +/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c new file mode 100644 index 00000000000..9d99839b1e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zicboz -mabi=ilp32" } */ + +int foo1() +{ + return __builtin_riscv_zicboz_cbo_zero(); +} + +/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */