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Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; Received: from nebula.arm.com (40.67.248.234) by VE1EUR03FT022.mail.protection.outlook.com (10.152.18.64) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5206.12 via Frontend Transport; Thu, 28 Apr 2022 09:08:19 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Thu, 28 Apr 2022 09:08:20 +0000 Received: from e124257 (10.34.101.64) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Thu, 28 Apr 2022 09:08:20 +0000 To: Andrea Corallo via Gcc-patches Subject: [PATCH 1/12] arm: Make mbranch-protection opts parsing common to AArch32/64 References: Date: Thu, 28 Apr 2022 11:08:17 +0200 In-Reply-To: (Andrea Corallo via Gcc-patches's message of "Thu, 28 Apr 2022 10:39:31 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/29.0.50 (gnu/linux) MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: bb9a6427-f565-464e-ff30-08da28f6a97f X-MS-TrafficTypeDiagnostic: AM7PR08MB5365:EE_|DB5EUR03FT020:EE_|DBBPR08MB6249:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(508600001)(36860700001)(82310400005)(36756003)(316002)(235185007)(8936002)(40460700003)(8676002)(54906003)(6916009)(336012)(426003)(70586007)(70206006)(47076005)(186003)(86362001)(81166007)(33964004)(4326008)(2616005)(2906002)(83380400001)(44832011)(26005)(6666004)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 09:08:29.6994 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb9a6427-f565-464e-ff30-08da28f6a97f X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6249 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, KAM_STOCKGEN, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, This change refactors all the mbranch-protection option parsing code and types to make it common to both AArch32 and AArch64 backends. This change also pulls in some supporting types from AArch64 to make it common (aarch_parse_opt_result). The significant changes in this patch are the movement of all branch protection parsing routines from aarch64.c to aarch-common.c and supporting data types and static data structures. This patch also pre-declares variables and types required in the aarch32 back-end for moved variables for function sign scope and key to prepare for the impending series of patches that support parsing the feature mbranch-protection in the aarch32 back-end. This patch implements the changes requested and was pre-approved here . gcc/ChangeLog: * common/config/aarch64/aarch64-common.cc: Include aarch-common.h. (all_architectures): Fix comment. (aarch64_parse_extension): Rename return type, enum value names. * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Rename factored out aarch_ra_sign_scope and aarch_ra_sign_key variables. Also rename corresponding enum values. * config/aarch64/aarch64-opts.h (aarch64_function_type): Factor out aarch64_function_type and move it to common code as aarch_function_type in aarch-common.h. * config/aarch64/aarch64-protos.h: Include common types header, move out types aarch64_parse_opt_result and aarch64_key_type to aarch-common.h * config/aarch64/aarch64.cc: Move mbranch-protection parsing types and functions out into aarch-common.h and aarch-common.cc. Fix up all the name changes resulting from the move. * config/aarch64/aarch64.md: Fix up aarch64_ra_sign_key type name change and enum value. * config/aarch64/aarch64.opt: Include aarch-common.h to import type move. Fix up name changes from factoring out common code and data. * config/arm/aarch-common-protos.h: Export factored out routines to both backends. * config/arm/aarch-common.cc: Include newly factored out types. Move all mbranch-protection code and data structures from aarch64.cc. * config/arm/aarch-common.h: New header that declares types shared between aarch32 and aarch64 backends. * config/arm/arm-protos.h: Declare types and variables that are made common to aarch64 and aarch32 backends - aarch_ra_sign_key, aarch_ra_sign_scope and aarch_enable_bti. Co-Authored-By: Tejas Belagod diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc index dfda5b8372a..70a5cf98b75 100644 --- a/gcc/common/config/aarch64/aarch64-common.cc +++ b/gcc/common/config/aarch64/aarch64-common.cc @@ -30,6 +30,7 @@ #include "opts.h" #include "flags.h" #include "diagnostic.h" +#include "config/arm/aarch-common.h" #ifdef TARGET_BIG_ENDIAN_DEFAULT #undef TARGET_DEFAULT_TARGET_FLAGS @@ -192,11 +193,11 @@ static const struct arch_to_arch_name all_architectures[] = /* Parse the architecture extension string STR and update ISA_FLAGS with the architecture features turned on or off. Return a - aarch64_parse_opt_result describing the result. + aarch_parse_opt_result describing the result. When the STR string contains an invalid extension, a copy of the string is created and stored to INVALID_EXTENSION. */ -enum aarch64_parse_opt_result +enum aarch_parse_opt_result aarch64_parse_extension (const char *str, uint64_t *isa_flags, std::string *invalid_extension) { @@ -229,7 +230,7 @@ aarch64_parse_extension (const char *str, uint64_t *isa_flags, adding_ext = 1; if (len == 0) - return AARCH64_PARSE_MISSING_ARG; + return AARCH_PARSE_MISSING_ARG; /* Scan over the extensions table trying to find an exact match. */ @@ -251,13 +252,13 @@ aarch64_parse_extension (const char *str, uint64_t *isa_flags, /* Extension not found in list. */ if (invalid_extension) *invalid_extension = std::string (str, len); - return AARCH64_PARSE_INVALID_FEATURE; + return AARCH_PARSE_INVALID_FEATURE; } str = ext; }; - return AARCH64_PARSE_OK; + return AARCH_PARSE_OK; } /* Append all architecture extension candidates to the CANDIDATES vector. */ diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index caf8e332ea0..b0c5a4fd6b6 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -183,14 +183,14 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) "__ARM_FEATURE_BTI_DEFAULT", pfile); cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT"); - if (aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE) + if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE) { int v = 0; - if (aarch64_ra_sign_key == AARCH64_KEY_A) + if (aarch_ra_sign_key == AARCH_KEY_A) v |= 1; - if (aarch64_ra_sign_key == AARCH64_KEY_B) + if (aarch_ra_sign_key == AARCH_KEY_B) v |= 2; - if (aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL) + if (aarch_ra_sign_scope == AARCH_FUNCTION_ALL) v |= 4; builtin_define_with_int_value ("__ARM_FEATURE_PAC_DEFAULT", v); } diff --git a/gcc/config/aarch64/aarch64-opts.h b/gcc/config/aarch64/aarch64-opts.h index 93572fe8330..694d1738374 100644 --- a/gcc/config/aarch64/aarch64-opts.h +++ b/gcc/config/aarch64/aarch64-opts.h @@ -71,16 +71,6 @@ enum aarch64_code_model { AARCH64_CMODEL_LARGE }; -/* Function types -msign-return-address should sign. */ -enum aarch64_function_type { - /* Don't sign any function. */ - AARCH64_FUNCTION_NONE, - /* Non-leaf functions. */ - AARCH64_FUNCTION_NON_LEAF, - /* All functions. */ - AARCH64_FUNCTION_ALL -}; - /* SVE vector register sizes. */ enum aarch64_sve_vector_bits_enum { SVE_SCALABLE, diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 46bade28ed6..fe2180e95ea 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -23,6 +23,7 @@ #define GCC_AARCH64_PROTOS_H #include "input.h" +#include "config/arm/aarch-common.h" /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through high and lo relocs that calculate the base address using a PC @@ -650,18 +651,6 @@ enum aarch64_extra_tuning_flags AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1 }; -/* Enum describing the various ways that the - aarch64_parse_{arch,tune,cpu,extension} functions can fail. - This way their callers can choose what kind of error to give. */ - -enum aarch64_parse_opt_result -{ - AARCH64_PARSE_OK, /* Parsing was successful. */ - AARCH64_PARSE_MISSING_ARG, /* Missing argument. */ - AARCH64_PARSE_INVALID_FEATURE, /* Invalid feature modifier. */ - AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */ -}; - /* Enum to distinguish which type of check is to be done in aarch64_simd_valid_immediate. This is used as a bitmask where AARCH64_CHECK_MOV has both bits set. Thus AARCH64_CHECK_MOV will @@ -672,13 +661,7 @@ enum simd_immediate_check { AARCH64_CHECK_MOV = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC }; -/* The key type that -msign-return-address should use. */ -enum aarch64_key_type { - AARCH64_KEY_A, - AARCH64_KEY_B -}; - -extern enum aarch64_key_type aarch64_ra_sign_key; +extern enum aarch_key_type aarch_ra_sign_key; extern struct tune_params aarch64_tune_params; @@ -1029,9 +1012,9 @@ extern bool aarch64_classify_address (struct aarch64_address_info *, rtx, bool aarch64_handle_option (struct gcc_options *, struct gcc_options *, const struct cl_decoded_option *, location_t); const char *aarch64_rewrite_selected_cpu (const char *name); -enum aarch64_parse_opt_result aarch64_parse_extension (const char *, - uint64_t *, - std::string *); +enum aarch_parse_opt_result aarch64_parse_extension (const char *, + uint64_t *, + std::string *); void aarch64_get_all_extension_candidates (auto_vec *candidates); std::string aarch64_get_extension_string_for_isa_flags (uint64_t, uint64_t); diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 18f80499079..eec743024c1 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -81,6 +81,8 @@ #include "rtlanal.h" #include "tree-dfa.h" #include "asan.h" +#include "config/arm/aarch-common.h" +#include "config/arm/aarch-common-protos.h" /* This file should be included last. */ #include "target-def.h" @@ -321,12 +323,8 @@ bool aarch64_pcrelative_literal_loads; /* Global flag for whether frame pointer is enabled. */ bool aarch64_use_frame_pointer; -#define BRANCH_PROTECT_STR_MAX 255 char *accepted_branch_protection_string = NULL; -static enum aarch64_parse_opt_result -aarch64_parse_branch_protection (const char*, char**); - /* Support for command line parsing of boolean flags in the tuning structures. */ struct aarch64_flag_desc @@ -2711,7 +2709,7 @@ static const struct processor *selected_arch; static const struct processor *selected_cpu; static const struct processor *selected_tune; -enum aarch64_key_type aarch64_ra_sign_key = AARCH64_KEY_A; +enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A; /* The current tuning set. */ struct tune_params aarch64_tune_params = generic_tunings; @@ -2780,100 +2778,6 @@ aarch64_cc; #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1)) -struct aarch64_branch_protect_type -{ - /* The type's name that the user passes to the branch-protection option - string. */ - const char* name; - /* Function to handle the protection type and set global variables. - First argument is the string token corresponding with this type and the - second argument is the next token in the option string. - Return values: - * AARCH64_PARSE_OK: Handling was sucessful. - * AARCH64_INVALID_ARG: The type is invalid in this context and the caller - should print an error. - * AARCH64_INVALID_FEATURE: The type is invalid and the handler prints its - own error. */ - enum aarch64_parse_opt_result (*handler)(char*, char*); - /* A list of types that can follow this type in the option string. */ - const aarch64_branch_protect_type* subtypes; - unsigned int num_subtypes; -}; - -static enum aarch64_parse_opt_result -aarch64_handle_no_branch_protection (char* str, char* rest) -{ - aarch64_ra_sign_scope = AARCH64_FUNCTION_NONE; - aarch64_enable_bti = 0; - if (rest) - { - error ("unexpected %<%s%> after %<%s%>", rest, str); - return AARCH64_PARSE_INVALID_FEATURE; - } - return AARCH64_PARSE_OK; -} - -static enum aarch64_parse_opt_result -aarch64_handle_standard_branch_protection (char* str, char* rest) -{ - aarch64_ra_sign_scope = AARCH64_FUNCTION_NON_LEAF; - aarch64_ra_sign_key = AARCH64_KEY_A; - aarch64_enable_bti = 1; - if (rest) - { - error ("unexpected %<%s%> after %<%s%>", rest, str); - return AARCH64_PARSE_INVALID_FEATURE; - } - return AARCH64_PARSE_OK; -} - -static enum aarch64_parse_opt_result -aarch64_handle_pac_ret_protection (char* str ATTRIBUTE_UNUSED, - char* rest ATTRIBUTE_UNUSED) -{ - aarch64_ra_sign_scope = AARCH64_FUNCTION_NON_LEAF; - aarch64_ra_sign_key = AARCH64_KEY_A; - return AARCH64_PARSE_OK; -} - -static enum aarch64_parse_opt_result -aarch64_handle_pac_ret_leaf (char* str ATTRIBUTE_UNUSED, - char* rest ATTRIBUTE_UNUSED) -{ - aarch64_ra_sign_scope = AARCH64_FUNCTION_ALL; - return AARCH64_PARSE_OK; -} - -static enum aarch64_parse_opt_result -aarch64_handle_pac_ret_b_key (char* str ATTRIBUTE_UNUSED, - char* rest ATTRIBUTE_UNUSED) -{ - aarch64_ra_sign_key = AARCH64_KEY_B; - return AARCH64_PARSE_OK; -} - -static enum aarch64_parse_opt_result -aarch64_handle_bti_protection (char* str ATTRIBUTE_UNUSED, - char* rest ATTRIBUTE_UNUSED) -{ - aarch64_enable_bti = 1; - return AARCH64_PARSE_OK; -} - -static const struct aarch64_branch_protect_type aarch64_pac_ret_subtypes[] = { - { "leaf", aarch64_handle_pac_ret_leaf, NULL, 0 }, - { "b-key", aarch64_handle_pac_ret_b_key, NULL, 0 }, - { NULL, NULL, NULL, 0 } -}; - -static const struct aarch64_branch_protect_type aarch64_branch_protect_types[] = { - { "none", aarch64_handle_no_branch_protection, NULL, 0 }, - { "standard", aarch64_handle_standard_branch_protection, NULL, 0 }, - { "pac-ret", aarch64_handle_pac_ret_protection, aarch64_pac_ret_subtypes, - ARRAY_SIZE (aarch64_pac_ret_subtypes) }, - { "bti", aarch64_handle_bti_protection, NULL, 0 }, - { NULL, NULL, NULL, 0 } -}; /* The condition codes of the processor, and the inverse function. */ static const char * const aarch64_condition_codes[] = @@ -8621,10 +8525,10 @@ aarch64_return_address_signing_enabled (void) if (crtl->calls_eh_return) return false; - /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function + /* If signing scope is AARCH_FUNCTION_NON_LEAF, we only sign a leaf function if its LR is pushed onto stack. */ - return (aarch64_ra_sign_scope == AARCH64_FUNCTION_ALL - || (aarch64_ra_sign_scope == AARCH64_FUNCTION_NON_LEAF + return (aarch_ra_sign_scope == AARCH_FUNCTION_ALL + || (aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF && known_ge (cfun->machine->frame.reg_offset[LR_REGNUM], 0))); } @@ -8632,7 +8536,7 @@ aarch64_return_address_signing_enabled (void) bool aarch64_bti_enabled (void) { - return (aarch64_enable_bti == 1); + return (aarch_enable_bti == 1); } /* The caller is going to use ST1D or LD1D to save or restore an SVE @@ -9624,12 +9528,12 @@ aarch64_expand_prologue (void) /* Sign return address for functions. */ if (aarch64_return_address_signing_enabled ()) { - switch (aarch64_ra_sign_key) + switch (aarch_ra_sign_key) { - case AARCH64_KEY_A: + case AARCH_KEY_A: insn = emit_insn (gen_paciasp ()); break; - case AARCH64_KEY_B: + case AARCH_KEY_B: insn = emit_insn (gen_pacibsp ()); break; default: @@ -9930,12 +9834,12 @@ aarch64_expand_epilogue (bool for_sibcall) if (aarch64_return_address_signing_enabled () && (for_sibcall || !TARGET_ARMV8_3)) { - switch (aarch64_ra_sign_key) + switch (aarch_ra_sign_key) { - case AARCH64_KEY_A: + case AARCH_KEY_A: insn = emit_insn (gen_autiasp ()); break; - case AARCH64_KEY_B: + case AARCH_KEY_B: insn = emit_insn (gen_autibsp ()); break; default: @@ -17077,12 +16981,12 @@ static void initialize_aarch64_code_model (struct gcc_options *); /* Parse the TO_PARSE string and put the architecture struct that it selects into RES and the architectural features into ISA_FLAGS. - Return an aarch64_parse_opt_result describing the parse result. + Return an aarch_parse_opt_result describing the parse result. If there is an error parsing, RES and ISA_FLAGS are left unchanged. When the TO_PARSE string contains an invalid extension, a copy of the string is created and stored to INVALID_EXTENSION. */ -static enum aarch64_parse_opt_result +static enum aarch_parse_opt_result aarch64_parse_arch (const char *to_parse, const struct processor **res, uint64_t *isa_flags, std::string *invalid_extension) { @@ -17098,7 +17002,7 @@ aarch64_parse_arch (const char *to_parse, const struct processor **res, len = strlen (to_parse); if (len == 0) - return AARCH64_PARSE_MISSING_ARG; + return AARCH_PARSE_MISSING_ARG; /* Loop through the list of supported ARCHes to find a match. */ @@ -17112,32 +17016,32 @@ aarch64_parse_arch (const char *to_parse, const struct processor **res, if (ext != NULL) { /* TO_PARSE string contains at least one extension. */ - enum aarch64_parse_opt_result ext_res + enum aarch_parse_opt_result ext_res = aarch64_parse_extension (ext, &isa_temp, invalid_extension); - if (ext_res != AARCH64_PARSE_OK) + if (ext_res != AARCH_PARSE_OK) return ext_res; } /* Extension parsing was successful. Confirm the result arch and ISA flags. */ *res = arch; *isa_flags = isa_temp; - return AARCH64_PARSE_OK; + return AARCH_PARSE_OK; } } /* ARCH name not found in list. */ - return AARCH64_PARSE_INVALID_ARG; + return AARCH_PARSE_INVALID_ARG; } /* Parse the TO_PARSE string and put the result tuning in RES and the - architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result + architecture flags in ISA_FLAGS. Return an aarch_parse_opt_result describing the parse result. If there is an error parsing, RES and ISA_FLAGS are left unchanged. When the TO_PARSE string contains an invalid extension, a copy of the string is created and stored to INVALID_EXTENSION. */ -static enum aarch64_parse_opt_result +static enum aarch_parse_opt_result aarch64_parse_cpu (const char *to_parse, const struct processor **res, uint64_t *isa_flags, std::string *invalid_extension) { @@ -17153,7 +17057,7 @@ aarch64_parse_cpu (const char *to_parse, const struct processor **res, len = strlen (to_parse); if (len == 0) - return AARCH64_PARSE_MISSING_ARG; + return AARCH_PARSE_MISSING_ARG; /* Loop through the list of supported CPUs to find a match. */ @@ -17167,29 +17071,29 @@ aarch64_parse_cpu (const char *to_parse, const struct processor **res, if (ext != NULL) { /* TO_PARSE string contains at least one extension. */ - enum aarch64_parse_opt_result ext_res + enum aarch_parse_opt_result ext_res = aarch64_parse_extension (ext, &isa_temp, invalid_extension); - if (ext_res != AARCH64_PARSE_OK) + if (ext_res != AARCH_PARSE_OK) return ext_res; } /* Extension parsing was successfull. Confirm the result cpu and ISA flags. */ *res = cpu; *isa_flags = isa_temp; - return AARCH64_PARSE_OK; + return AARCH_PARSE_OK; } } /* CPU name not found in list. */ - return AARCH64_PARSE_INVALID_ARG; + return AARCH_PARSE_INVALID_ARG; } /* Parse the TO_PARSE string and put the cpu it selects into RES. - Return an aarch64_parse_opt_result describing the parse result. + Return an aarch_parse_opt_result describing the parse result. If the parsing fails the RES does not change. */ -static enum aarch64_parse_opt_result +static enum aarch_parse_opt_result aarch64_parse_tune (const char *to_parse, const struct processor **res) { const struct processor *cpu; @@ -17200,12 +17104,12 @@ aarch64_parse_tune (const char *to_parse, const struct processor **res) if (strcmp (cpu->name, to_parse) == 0) { *res = cpu; - return AARCH64_PARSE_OK; + return AARCH_PARSE_OK; } } /* CPU name not found in list. */ - return AARCH64_PARSE_INVALID_ARG; + return AARCH_PARSE_INVALID_ARG; } /* Parse TOKEN, which has length LENGTH to see if it is an option @@ -17783,22 +17687,22 @@ aarch64_validate_mcpu (const char *str, const struct processor **res, uint64_t *isa_flags) { std::string invalid_extension; - enum aarch64_parse_opt_result parse_res + enum aarch_parse_opt_result parse_res = aarch64_parse_cpu (str, res, isa_flags, &invalid_extension); - if (parse_res == AARCH64_PARSE_OK) + if (parse_res == AARCH_PARSE_OK) return true; switch (parse_res) { - case AARCH64_PARSE_MISSING_ARG: + case AARCH_PARSE_MISSING_ARG: error ("missing cpu name in %<-mcpu=%s%>", str); break; - case AARCH64_PARSE_INVALID_ARG: + case AARCH_PARSE_INVALID_ARG: error ("unknown value %qs for %<-mcpu%>", str); aarch64_print_hint_for_core (str); break; - case AARCH64_PARSE_INVALID_FEATURE: + case AARCH_PARSE_INVALID_FEATURE: error ("invalid feature modifier %qs in %<-mcpu=%s%>", invalid_extension.c_str (), str); aarch64_print_hint_for_extensions (invalid_extension); @@ -17883,110 +17787,6 @@ aarch64_validate_sls_mitigation (const char *const_str) free (str_root); } -/* Parses CONST_STR for branch protection features specified in - aarch64_branch_protect_types, and set any global variables required. Returns - the parsing result and assigns LAST_STR to the last processed token from - CONST_STR so that it can be used for error reporting. */ - -static enum -aarch64_parse_opt_result aarch64_parse_branch_protection (const char *const_str, - char** last_str) -{ - char *str_root = xstrdup (const_str); - char* token_save = NULL; - char *str = strtok_r (str_root, "+", &token_save); - enum aarch64_parse_opt_result res = AARCH64_PARSE_OK; - if (!str) - res = AARCH64_PARSE_MISSING_ARG; - else - { - char *next_str = strtok_r (NULL, "+", &token_save); - /* Reset the branch protection features to their defaults. */ - aarch64_handle_no_branch_protection (NULL, NULL); - - while (str && res == AARCH64_PARSE_OK) - { - const aarch64_branch_protect_type* type = aarch64_branch_protect_types; - bool found = false; - /* Search for this type. */ - while (type && type->name && !found && res == AARCH64_PARSE_OK) - { - if (strcmp (str, type->name) == 0) - { - found = true; - res = type->handler (str, next_str); - str = next_str; - next_str = strtok_r (NULL, "+", &token_save); - } - else - type++; - } - if (found && res == AARCH64_PARSE_OK) - { - bool found_subtype = true; - /* Loop through each token until we find one that isn't a - subtype. */ - while (found_subtype) - { - found_subtype = false; - const aarch64_branch_protect_type *subtype = type->subtypes; - /* Search for the subtype. */ - while (str && subtype && subtype->name && !found_subtype - && res == AARCH64_PARSE_OK) - { - if (strcmp (str, subtype->name) == 0) - { - found_subtype = true; - res = subtype->handler (str, next_str); - str = next_str; - next_str = strtok_r (NULL, "+", &token_save); - } - else - subtype++; - } - } - } - else if (!found) - res = AARCH64_PARSE_INVALID_ARG; - } - } - /* Copy the last processed token into the argument to pass it back. - Used by option and attribute validation to print the offending token. */ - if (last_str) - { - if (str) strcpy (*last_str, str); - else *last_str = NULL; - } - if (res == AARCH64_PARSE_OK) - { - /* If needed, alloc the accepted string then copy in const_str. - Used by override_option_after_change_1. */ - if (!accepted_branch_protection_string) - accepted_branch_protection_string = (char *) xmalloc ( - BRANCH_PROTECT_STR_MAX - + 1); - strncpy (accepted_branch_protection_string, const_str, - BRANCH_PROTECT_STR_MAX + 1); - /* Forcibly null-terminate. */ - accepted_branch_protection_string[BRANCH_PROTECT_STR_MAX] = '\0'; - } - return res; -} - -static bool -aarch64_validate_mbranch_protection (const char *const_str) -{ - char *str = (char *) xmalloc (strlen (const_str)); - enum aarch64_parse_opt_result res = - aarch64_parse_branch_protection (const_str, &str); - if (res == AARCH64_PARSE_INVALID_ARG) - error ("invalid argument %<%s%> for %<-mbranch-protection=%>", str); - else if (res == AARCH64_PARSE_MISSING_ARG) - error ("missing argument for %<-mbranch-protection=%>"); - free (str); - return res == AARCH64_PARSE_OK; -} - /* Validate a command-line -march option. Parse the arch and extensions (if any) specified in STR and throw errors if appropriate. Put the results, if they are valid, in RES and ISA_FLAGS. Return whether the @@ -17997,22 +17797,22 @@ aarch64_validate_march (const char *str, const struct processor **res, uint64_t *isa_flags) { std::string invalid_extension; - enum aarch64_parse_opt_result parse_res + enum aarch_parse_opt_result parse_res = aarch64_parse_arch (str, res, isa_flags, &invalid_extension); - if (parse_res == AARCH64_PARSE_OK) + if (parse_res == AARCH_PARSE_OK) return true; switch (parse_res) { - case AARCH64_PARSE_MISSING_ARG: + case AARCH_PARSE_MISSING_ARG: error ("missing arch name in %<-march=%s%>", str); break; - case AARCH64_PARSE_INVALID_ARG: + case AARCH_PARSE_INVALID_ARG: error ("unknown value %qs for %<-march%>", str); aarch64_print_hint_for_arch (str); break; - case AARCH64_PARSE_INVALID_FEATURE: + case AARCH_PARSE_INVALID_FEATURE: error ("invalid feature modifier %qs in %<-march=%s%>", invalid_extension.c_str (), str); aarch64_print_hint_for_extensions (invalid_extension); @@ -18032,18 +17832,18 @@ aarch64_validate_march (const char *str, const struct processor **res, static bool aarch64_validate_mtune (const char *str, const struct processor **res) { - enum aarch64_parse_opt_result parse_res + enum aarch_parse_opt_result parse_res = aarch64_parse_tune (str, res); - if (parse_res == AARCH64_PARSE_OK) + if (parse_res == AARCH_PARSE_OK) return true; switch (parse_res) { - case AARCH64_PARSE_MISSING_ARG: + case AARCH_PARSE_MISSING_ARG: error ("missing cpu name in %<-mtune=%s%>", str); break; - case AARCH64_PARSE_INVALID_ARG: + case AARCH_PARSE_INVALID_ARG: error ("unknown value %qs for %<-mtune%>", str); aarch64_print_hint_for_core (str); break; @@ -18131,7 +17931,7 @@ aarch64_override_options (void) aarch64_validate_sls_mitigation (aarch64_harden_sls_string); if (aarch64_branch_protection_string) - aarch64_validate_mbranch_protection (aarch64_branch_protection_string); + aarch_validate_mbranch_protection (aarch64_branch_protection_string); /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU. If either of -march or -mtune is given, they override their @@ -18209,12 +18009,12 @@ aarch64_override_options (void) if (!selected_tune) selected_tune = selected_cpu; - if (aarch64_enable_bti == 2) + if (aarch_enable_bti == 2) { #ifdef TARGET_ENABLE_BTI - aarch64_enable_bti = 1; + aarch_enable_bti = 1; #else - aarch64_enable_bti = 0; + aarch_enable_bti = 0; #endif } @@ -18224,9 +18024,9 @@ aarch64_override_options (void) if (!TARGET_ILP32 && accepted_branch_protection_string == NULL) { #ifdef TARGET_ENABLE_PAC_RET - aarch64_ra_sign_scope = AARCH64_FUNCTION_NON_LEAF; + aarch_ra_sign_scope = AARCH_FUNCTION_NON_LEAF; #else - aarch64_ra_sign_scope = AARCH64_FUNCTION_NONE; + aarch_ra_sign_scope = AARCH_FUNCTION_NONE; #endif } @@ -18240,7 +18040,7 @@ aarch64_override_options (void) /* Convert -msve-vector-bits to a VG count. */ aarch64_sve_vg = aarch64_convert_sve_vector_bits (aarch64_sve_vector_bits); - if (aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE && TARGET_ILP32) + if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE && TARGET_ILP32) sorry ("return address signing is only supported for %<-mabi=lp64%>"); /* Make sure we properly set up the explicit options. */ @@ -18367,7 +18167,7 @@ aarch64_option_restore (struct gcc_options *opts, = ptr->x_aarch64_branch_protection_string; if (opts->x_aarch64_branch_protection_string) { - aarch64_parse_branch_protection (opts->x_aarch64_branch_protection_string, + aarch_parse_branch_protection (opts->x_aarch64_branch_protection_string, NULL); } @@ -18491,10 +18291,10 @@ aarch64_handle_attr_arch (const char *str) { const struct processor *tmp_arch = NULL; std::string invalid_extension; - enum aarch64_parse_opt_result parse_res + enum aarch_parse_opt_result parse_res = aarch64_parse_arch (str, &tmp_arch, &aarch64_isa_flags, &invalid_extension); - if (parse_res == AARCH64_PARSE_OK) + if (parse_res == AARCH_PARSE_OK) { gcc_assert (tmp_arch); selected_arch = tmp_arch; @@ -18504,14 +18304,14 @@ aarch64_handle_attr_arch (const char *str) switch (parse_res) { - case AARCH64_PARSE_MISSING_ARG: + case AARCH_PARSE_MISSING_ARG: error ("missing name in % pragma or attribute"); break; - case AARCH64_PARSE_INVALID_ARG: + case AARCH_PARSE_INVALID_ARG: error ("invalid name %qs in % pragma or attribute", str); aarch64_print_hint_for_arch (str); break; - case AARCH64_PARSE_INVALID_FEATURE: + case AARCH_PARSE_INVALID_FEATURE: error ("invalid feature modifier %s of value %qs in " "% pragma or attribute", invalid_extension.c_str (), str); aarch64_print_hint_for_extensions (invalid_extension); @@ -18530,10 +18330,10 @@ aarch64_handle_attr_cpu (const char *str) { const struct processor *tmp_cpu = NULL; std::string invalid_extension; - enum aarch64_parse_opt_result parse_res + enum aarch_parse_opt_result parse_res = aarch64_parse_cpu (str, &tmp_cpu, &aarch64_isa_flags, &invalid_extension); - if (parse_res == AARCH64_PARSE_OK) + if (parse_res == AARCH_PARSE_OK) { gcc_assert (tmp_cpu); selected_tune = tmp_cpu; @@ -18546,14 +18346,14 @@ aarch64_handle_attr_cpu (const char *str) switch (parse_res) { - case AARCH64_PARSE_MISSING_ARG: + case AARCH_PARSE_MISSING_ARG: error ("missing name in % pragma or attribute"); break; - case AARCH64_PARSE_INVALID_ARG: + case AARCH_PARSE_INVALID_ARG: error ("invalid name %qs in % pragma or attribute", str); aarch64_print_hint_for_core (str); break; - case AARCH64_PARSE_INVALID_FEATURE: + case AARCH_PARSE_INVALID_FEATURE: error ("invalid feature modifier %qs of value %qs in " "% pragma or attribute", invalid_extension.c_str (), str); aarch64_print_hint_for_extensions (invalid_extension); @@ -18571,23 +18371,23 @@ aarch64_handle_attr_cpu (const char *str) aarch64_handle_attr_branch_protection (const char* str) { char *err_str = (char *) xmalloc (strlen (str) + 1); - enum aarch64_parse_opt_result res = aarch64_parse_branch_protection (str, - &err_str); + enum aarch_parse_opt_result res = aarch_parse_branch_protection (str, + &err_str); bool success = false; switch (res) { - case AARCH64_PARSE_MISSING_ARG: + case AARCH_PARSE_MISSING_ARG: error ("missing argument to % pragma or" " attribute"); break; - case AARCH64_PARSE_INVALID_ARG: + case AARCH_PARSE_INVALID_ARG: error ("invalid protection type %qs in % pragma or attribute", err_str); break; - case AARCH64_PARSE_OK: + case AARCH_PARSE_OK: success = true; /* Fall through. */ - case AARCH64_PARSE_INVALID_FEATURE: + case AARCH_PARSE_INVALID_FEATURE: break; default: gcc_unreachable (); @@ -18602,10 +18402,10 @@ static bool aarch64_handle_attr_tune (const char *str) { const struct processor *tmp_tune = NULL; - enum aarch64_parse_opt_result parse_res + enum aarch_parse_opt_result parse_res = aarch64_parse_tune (str, &tmp_tune); - if (parse_res == AARCH64_PARSE_OK) + if (parse_res == AARCH_PARSE_OK) { gcc_assert (tmp_tune); selected_tune = tmp_tune; @@ -18615,7 +18415,7 @@ aarch64_handle_attr_tune (const char *str) switch (parse_res) { - case AARCH64_PARSE_INVALID_ARG: + case AARCH_PARSE_INVALID_ARG: error ("invalid name %qs in % pragma or attribute", str); aarch64_print_hint_for_core (str); break; @@ -18634,7 +18434,7 @@ aarch64_handle_attr_tune (const char *str) static bool aarch64_handle_attr_isa_flags (char *str) { - enum aarch64_parse_opt_result parse_res; + enum aarch_parse_opt_result parse_res; uint64_t isa_flags = aarch64_isa_flags; /* We allow "+nothing" in the beginning to clear out all architectural @@ -18648,7 +18448,7 @@ aarch64_handle_attr_isa_flags (char *str) std::string invalid_extension; parse_res = aarch64_parse_extension (str, &isa_flags, &invalid_extension); - if (parse_res == AARCH64_PARSE_OK) + if (parse_res == AARCH_PARSE_OK) { aarch64_isa_flags = isa_flags; return true; @@ -18656,11 +18456,11 @@ aarch64_handle_attr_isa_flags (char *str) switch (parse_res) { - case AARCH64_PARSE_MISSING_ARG: + case AARCH_PARSE_MISSING_ARG: error ("missing value in % pragma or attribute"); break; - case AARCH64_PARSE_INVALID_FEATURE: + case AARCH_PARSE_INVALID_FEATURE: error ("invalid feature modifier %qs of value %qs in " "% pragma or attribute", invalid_extension.c_str (), str); break; @@ -18909,10 +18709,10 @@ aarch64_process_target_attr (tree args) leading '+'. */ uint64_t isa_temp = 0; auto with_plus = std::string ("+") + token; - enum aarch64_parse_opt_result ext_res + enum aarch_parse_opt_result ext_res = aarch64_parse_extension (with_plus.c_str (), &isa_temp, nullptr); - if (ext_res == AARCH64_PARSE_OK) + if (ext_res == AARCH_PARSE_OK) error ("arch extension %<%s%> should be prefixed by %<+%>", token); else @@ -22606,7 +22406,7 @@ void aarch64_post_cfi_startproc (FILE *f, tree ignored ATTRIBUTE_UNUSED) { if (cfun->machine->frame.laid_out && aarch64_return_address_signing_enabled () - && aarch64_ra_sign_key == AARCH64_KEY_B) + && aarch_ra_sign_key == AARCH_KEY_B) asm_fprintf (f, "\t.cfi_b_key_frame\n"); } @@ -26892,7 +26692,7 @@ aarch64_file_end_indicate_exec_stack () if (aarch64_bti_enabled ()) feature_1_and |= GNU_PROPERTY_AARCH64_FEATURE_1_BTI; - if (aarch64_ra_sign_scope != AARCH64_FUNCTION_NONE) + if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE) feature_1_and |= GNU_PROPERTY_AARCH64_FEATURE_1_PAC; if (feature_1_and) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c98525075a0..072264b89d8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -890,7 +890,7 @@ if (aarch64_return_address_signing_enabled () && (TARGET_PAUTH)) { - if (aarch64_ra_sign_key == AARCH64_KEY_B) + if (aarch_ra_sign_key == AARCH_KEY_B) ret = "retab"; else ret = "retaa"; diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index 92220b26ee2..61937fb92cf 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -21,6 +21,9 @@ HeaderInclude config/aarch64/aarch64-opts.h +HeaderInclude +config/arm/aarch-common.h + TargetVariable enum aarch64_processor explicit_tune_core = aarch64_none @@ -34,7 +37,7 @@ TargetVariable uint64_t aarch64_isa_flags = 0 TargetVariable -unsigned aarch64_enable_bti = 2 +unsigned aarch_enable_bti = 2 ; The TLS dialect names to use with -mtls-dialect. @@ -161,21 +164,21 @@ Target RejectNegative Joined Var(aarch64_branch_protection_string) Save Use branch-protection features. msign-return-address= -Target WarnRemoved RejectNegative Joined Enum(aarch64_ra_sign_scope_t) Var(aarch64_ra_sign_scope) Init(AARCH64_FUNCTION_NONE) Save +Target WarnRemoved RejectNegative Joined Enum(aarch_ra_sign_scope_t) Var(aarch_ra_sign_scope) Init(AARCH_FUNCTION_NONE) Save Select return address signing scope. Enum -Name(aarch64_ra_sign_scope_t) Type(enum aarch64_function_type) +Name(aarch_ra_sign_scope_t) Type(enum aarch_function_type) Supported AArch64 return address signing scope (for use with -msign-return-address= option): EnumValue -Enum(aarch64_ra_sign_scope_t) String(none) Value(AARCH64_FUNCTION_NONE) +Enum(aarch_ra_sign_scope_t) String(none) Value(AARCH_FUNCTION_NONE) EnumValue -Enum(aarch64_ra_sign_scope_t) String(non-leaf) Value(AARCH64_FUNCTION_NON_LEAF) +Enum(aarch_ra_sign_scope_t) String(non-leaf) Value(AARCH_FUNCTION_NON_LEAF) EnumValue -Enum(aarch64_ra_sign_scope_t) String(all) Value(AARCH64_FUNCTION_ALL) +Enum(aarch_ra_sign_scope_t) String(all) Value(AARCH_FUNCTION_ALL) mlow-precision-recip-sqrt Target Var(flag_mrecip_low_precision_sqrt) Optimization diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index ae0465159f7..17a369f7e99 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -153,4 +153,10 @@ rtx_insn *arm_md_asm_adjust (vec &outputs, vec & /*inputs*/, vec &clobbers, HARD_REG_SET &clobbered_regs, location_t loc); +/* Parsing routine for branch-protection common to AArch64 and Arm. */ +enum aarch_parse_opt_result aarch_parse_branch_protection (const char*, char**); + +/* Validation routine for branch-protection common to AArch64 and Arm. */ +bool aarch_validate_mbranch_protection (const char *); + #endif /* GCC_AARCH_COMMON_PROTOS_H */ diff --git a/gcc/config/arm/aarch-common.cc b/gcc/config/arm/aarch-common.cc index 04a53d75093..6d254101f6a 100644 --- a/gcc/config/arm/aarch-common.cc +++ b/gcc/config/arm/aarch-common.cc @@ -36,6 +36,7 @@ #include "expr.h" #include "function.h" #include "emit-rtl.h" +#include "aarch-common.h" /* Return TRUE if X is either an arithmetic shift left, or is a multiplication by a power of two. */ @@ -657,3 +658,187 @@ arm_md_asm_adjust (vec &outputs, vec & /*inputs*/, return saw_asm_flag ? seq : NULL; } + +#define BRANCH_PROTECT_STR_MAX 255 +extern char *accepted_branch_protection_string; +extern enum aarch_key_type aarch_ra_sign_key; + +static enum aarch_parse_opt_result +aarch_handle_no_branch_protection (char* str, char* rest) +{ + aarch_ra_sign_scope = AARCH_FUNCTION_NONE; + aarch_enable_bti = 0; + if (rest) + { + error ("unexpected %<%s%> after %<%s%>", rest, str); + return AARCH_PARSE_INVALID_FEATURE; + } + return AARCH_PARSE_OK; +} + +static enum aarch_parse_opt_result +aarch_handle_standard_branch_protection (char* str, char* rest) +{ + aarch_ra_sign_scope = AARCH_FUNCTION_NON_LEAF; + aarch_ra_sign_key = AARCH_KEY_A; + aarch_enable_bti = 1; + if (rest) + { + error ("unexpected %<%s%> after %<%s%>", rest, str); + return AARCH_PARSE_INVALID_FEATURE; + } + return AARCH_PARSE_OK; +} + +static enum aarch_parse_opt_result +aarch_handle_pac_ret_protection (char* str ATTRIBUTE_UNUSED, + char* rest ATTRIBUTE_UNUSED) +{ + aarch_ra_sign_scope = AARCH_FUNCTION_NON_LEAF; + aarch_ra_sign_key = AARCH_KEY_A; + return AARCH_PARSE_OK; +} + +static enum aarch_parse_opt_result +aarch_handle_pac_ret_leaf (char* str ATTRIBUTE_UNUSED, + char* rest ATTRIBUTE_UNUSED) +{ + aarch_ra_sign_scope = AARCH_FUNCTION_ALL; + return AARCH_PARSE_OK; +} + +static enum aarch_parse_opt_result +aarch_handle_pac_ret_b_key (char* str ATTRIBUTE_UNUSED, + char* rest ATTRIBUTE_UNUSED) +{ + aarch_ra_sign_key = AARCH_KEY_B; + return AARCH_PARSE_OK; +} + +static enum aarch_parse_opt_result +aarch_handle_bti_protection (char* str ATTRIBUTE_UNUSED, + char* rest ATTRIBUTE_UNUSED) +{ + aarch_enable_bti = 1; + return AARCH_PARSE_OK; +} + +static const struct aarch_branch_protect_type aarch_pac_ret_subtypes[] = { + { "leaf", aarch_handle_pac_ret_leaf, NULL, 0 }, + { "b-key", aarch_handle_pac_ret_b_key, NULL, 0 }, + { NULL, NULL, NULL, 0 } +}; + +static const struct aarch_branch_protect_type aarch_branch_protect_types[] = { + { "none", aarch_handle_no_branch_protection, NULL, 0 }, + { "standard", aarch_handle_standard_branch_protection, NULL, 0 }, + { "pac-ret", aarch_handle_pac_ret_protection, aarch_pac_ret_subtypes, + ARRAY_SIZE (aarch_pac_ret_subtypes) }, + { "bti", aarch_handle_bti_protection, NULL, 0 }, + { NULL, NULL, NULL, 0 } +}; + +/* Parses CONST_STR for branch protection features specified in + aarch64_branch_protect_types, and set any global variables required. Returns + the parsing result and assigns LAST_STR to the last processed token from + CONST_STR so that it can be used for error reporting. */ + +enum aarch_parse_opt_result +aarch_parse_branch_protection (const char *const_str, char** last_str) +{ + char *str_root = xstrdup (const_str); + char* token_save = NULL; + char *str = strtok_r (str_root, "+", &token_save); + enum aarch_parse_opt_result res = AARCH_PARSE_OK; + if (!str) + res = AARCH_PARSE_MISSING_ARG; + else + { + char *next_str = strtok_r (NULL, "+", &token_save); + /* Reset the branch protection features to their defaults. */ + aarch_handle_no_branch_protection (NULL, NULL); + + while (str && res == AARCH_PARSE_OK) + { + const aarch_branch_protect_type* type = aarch_branch_protect_types; + bool found = false; + /* Search for this type. */ + while (type && type->name && !found && res == AARCH_PARSE_OK) + { + if (strcmp (str, type->name) == 0) + { + found = true; + res = type->handler (str, next_str); + str = next_str; + next_str = strtok_r (NULL, "+", &token_save); + } + else + type++; + } + if (found && res == AARCH_PARSE_OK) + { + bool found_subtype = true; + /* Loop through each token until we find one that isn't a + subtype. */ + while (found_subtype) + { + found_subtype = false; + const aarch_branch_protect_type *subtype = type->subtypes; + /* Search for the subtype. */ + while (str && subtype && subtype->name && !found_subtype + && res == AARCH_PARSE_OK) + { + if (strcmp (str, subtype->name) == 0) + { + found_subtype = true; + res = subtype->handler (str, next_str); + str = next_str; + next_str = strtok_r (NULL, "+", &token_save); + } + else + subtype++; + } + } + } + else if (!found) + res = AARCH_PARSE_INVALID_ARG; + } + } + /* Copy the last processed token into the argument to pass it back. + Used by option and attribute validation to print the offending token. */ + if (last_str) + { + if (str) + strcpy (*last_str, str); + else + *last_str = NULL; + } + + if (res == AARCH_PARSE_OK) + { + /* If needed, alloc the accepted string then copy in const_str. + Used by override_option_after_change_1. */ + if (!accepted_branch_protection_string) + accepted_branch_protection_string + = (char *) xmalloc (BRANCH_PROTECT_STR_MAX + 1); + strncpy (accepted_branch_protection_string, const_str, + BRANCH_PROTECT_STR_MAX + 1); + /* Forcibly null-terminate. */ + accepted_branch_protection_string[BRANCH_PROTECT_STR_MAX] = '\0'; + } + return res; +} + +bool +aarch_validate_mbranch_protection (const char *const_str) +{ + char *str = (char *) xmalloc (strlen (const_str)); + enum aarch_parse_opt_result res = + aarch_parse_branch_protection (const_str, &str); + if (res == AARCH_PARSE_INVALID_ARG) + error ("invalid argument %<%s%> for %<-mbranch-protection=%>", str); + else if (res == AARCH_PARSE_MISSING_ARG) + error ("missing argument for %<-mbranch-protection=%>"); + free (str); + return res == AARCH_PARSE_OK; +} diff --git a/gcc/config/arm/aarch-common.h b/gcc/config/arm/aarch-common.h new file mode 100644 index 00000000000..b5591d60c5a --- /dev/null +++ b/gcc/config/arm/aarch-common.h @@ -0,0 +1,73 @@ +/* Types shared between arm and aarch64. + + Copyright (C) 2009-2021 Free Software Foundation, Inc. + Contributed by Arm Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_AARCH_COMMON_H +#define GCC_AARCH_COMMON_H + +/* Enum describing the various ways that the + aarch*_parse_{arch,tune,cpu,extension} functions can fail. + This way their callers can choose what kind of error to give. */ + +enum aarch_parse_opt_result +{ + AARCH_PARSE_OK, /* Parsing was successful. */ + AARCH_PARSE_MISSING_ARG, /* Missing argument. */ + AARCH_PARSE_INVALID_FEATURE, /* Invalid feature modifier. */ + AARCH_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */ +}; + +/* Function types -msign-return-address should sign. */ +enum aarch_function_type { + /* Don't sign any function. */ + AARCH_FUNCTION_NONE, + /* Non-leaf functions. */ + AARCH_FUNCTION_NON_LEAF, + /* All functions. */ + AARCH_FUNCTION_ALL +}; + +/* The key type that -msign-return-address should use. */ +enum aarch_key_type { + AARCH_KEY_A, + AARCH_KEY_B +}; + +struct aarch_branch_protect_type +{ + /* The type's name that the user passes to the branch-protection option + string. */ + const char* name; + /* Function to handle the protection type and set global variables. + First argument is the string token corresponding with this type and the + second argument is the next token in the option string. + Return values: + * AARCH_PARSE_OK: Handling was sucessful. + * AARCH_INVALID_ARG: The type is invalid in this context and the caller + should print an error. + * AARCH_INVALID_FEATURE: The type is invalid and the handler prints its + own error. */ + enum aarch_parse_opt_result (*handler)(char*, char*); + /* A list of types that can follow this type in the option string. */ + const struct aarch_branch_protect_type* subtypes; + unsigned int num_subtypes; +}; + +#endif /* GCC_AARCH_COMMON_H */ diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 9d142096cb6..cff7ff1da2a 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -586,6 +586,8 @@ struct cpu_option extern const arch_option all_architectures[]; extern const cpu_option all_cores[]; +extern enum aarch_key_type aarch_ra_sign_key; + const cpu_option *arm_parse_cpu_option_name (const cpu_option *, const char *, const char *, bool = true); const arch_option *arm_parse_arch_option_name (const arch_option *, diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 14e2fdfeafa..60f3eae82a4 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -72,6 +72,8 @@ #include "selftest.h" #include "tree-vectorizer.h" #include "opts.h" +#include "aarch-common.h" +#include "aarch-common-protos.h" /* This file should be included last. */ #include "target-def.h" @@ -2417,6 +2419,11 @@ const struct tune_params arm_fa726te_tune = tune_params::SCHED_AUTOPREF_OFF }; +/* Key type for Pointer Authentication extension. */ +enum aarch_key_type aarch_ra_sign_key = AARCH_KEY_A; + +char *accepted_branch_protection_string = NULL; + /* Auto-generated CPU, FPU and architecture tables. */ #include "arm-cpu-data.h" diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 3209b6c623b..f54ec8356c3 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -21,6 +21,15 @@ HeaderInclude config/arm/arm-opts.h +HeaderInclude +config/arm/aarch-common.h + +TargetVariable +enum aarch_function_type aarch_ra_sign_scope = AARCH_FUNCTION_NONE + +TargetVariable +unsigned aarch_enable_bti = 2 + Enum Name(tls_type) Type(enum arm_tls_type) TLS dialect to use: From patchwork Thu Apr 28 09:37:32 2022 Content-Type: text/plain; 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Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; Received: from nebula.arm.com (40.67.248.234) by AM5EUR03FT032.mail.protection.outlook.com (10.152.16.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5206.12 via Frontend Transport; Thu, 28 Apr 2022 09:37:35 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Thu, 28 Apr 2022 09:37:35 +0000 Received: from e124257 (10.34.101.64) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Thu, 28 Apr 2022 09:37:35 +0000 To: Andrea Corallo via Gcc-patches Subject: [PATCH 2/12] arm: Add Armv8.1-M Mainline target feature +pacbti References: Date: Thu, 28 Apr 2022 11:37:32 +0200 In-Reply-To: (Andrea Corallo via Gcc-patches's message of "Thu, 28 Apr 2022 10:39:31 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/29.0.50 (gnu/linux) MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 8eceace7-9a79-41de-ac4b-08da28fabf89 X-MS-TrafficTypeDiagnostic: AM0PR08MB5490:EE_|VE1EUR03FT047:EE_|GV2PR08MB8049:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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This feature enables pointer signing and authentication instructions on M-class architectures. Pre-approved here . gcc/Changelog: * config/arm/arm.h (TARGET_HAVE_PACBTI): New macro. * config/arm/arm-cpus.in (pacbti): New feature. * doc/invoke.texi (Arm Options): Document it. Co-Authored-By: Tejas Belagod diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0d3082b569f..6c1dffe56e3 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -229,6 +229,10 @@ define feature cdecp5 define feature cdecp6 define feature cdecp7 +# M-profile control flow integrity extensions (PAC/AUT/BTI). +# Optional from Armv8.1-M Mainline. +define feature pacbti + # Feature groups. Conventionally all (or mostly) upper case. # ALL_FPU lists all the feature bits associated with the floating-point # unit; these will all be removed if the floating-point unit is disabled @@ -748,6 +752,7 @@ begin arch armv8.1-m.main option nofp remove ALL_FP option mve add MVE option mve.fp add MVE_FP + option pacbti add pacbti option cdecp0 add cdecp0 option cdecp1 add cdecp1 option cdecp2 add cdecp2 diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index f479540812a..3495ab857ea 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -335,6 +335,12 @@ emission of floating point pcs attributes. */ isa_bit_mve_float) \ && !TARGET_GENERAL_REGS_ONLY) +/* Non-zero if this target supports Armv8.1-M Mainline pointer-signing + extension. */ +#define TARGET_HAVE_PACBTI (arm_arch8_1m_main \ + && bitmap_bit_p (arm_active_target.isa, \ + isa_bit_pacbti)) + /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3936aef69d0..079e34ed98c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21002,6 +21002,9 @@ Disable the floating-point extension. @item +cdecp0, +cdecp1, ... , +cdecp7 Enable the Custom Datapath Extension (CDE) on selected coprocessors according to the numbers given in the options in the range 0 to 7. + +@item +pacbti +Enable the Pointer Authentication and Branch Target Identification Extension. @end table @item armv8-m.main From patchwork Thu Apr 28 09:38:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 53296 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8AA6E3857357 for ; Thu, 28 Apr 2022 09:40:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8AA6E3857357 DKIM-Signature: v=1; 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This option enables the code-generation of pointer signing and authentication instructions in function prologues and epilogues. gcc/ChangeLog: * config/arm/arm.c (arm_configure_build_target): Parse and validate -mbranch-protection option and initialize appropriate data structures. * config/arm/arm.opt (-mbranch-protection): New option. * doc/invoke.texi (Arm Options): Document it. Co-Authored-By: Tejas Belagod Co-Authored-By: Richard Earnshaw diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 60f3eae82a4..0068817b0f2 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -3263,6 +3263,17 @@ arm_configure_build_target (struct arm_build_target *target, tune_opts = strchr (opts->x_arm_tune_string, '+'); } + if (opts->x_arm_branch_protection_string) + { + aarch_validate_mbranch_protection (opts->x_arm_branch_protection_string); + + if (aarch_ra_sign_key != AARCH_KEY_A) + { + warning (0, "invalid key type for %<-mbranch-protection=%>"); + aarch_ra_sign_key = AARCH_KEY_A; + } + } + if (arm_selected_arch) { arm_initialize_isa (target->isa, arm_selected_arch->common.isa_bits); diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index f54ec8356c3..d292e23ea11 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -323,6 +323,10 @@ mbranch-cost= Target RejectNegative Joined UInteger Var(arm_branch_cost) Init(-1) Cost to assume for a branch insn. +mbranch-protection= +Target RejectNegative Joined Var(arm_branch_protection_string) Save +Use branch-protection features. + mgeneral-regs-only Target RejectNegative Mask(GENERAL_REGS_ONLY) Save Generate code which uses the core registers only (r0-r14). diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 079e34ed98c..f6f724af26e 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -825,7 +825,9 @@ Objective-C and Objective-C++ Dialects}. -mcmse @gol -mfix-cmse-cve-2021-35465 @gol -mstack-protector-guard=@var{guard} -mstack-protector-guard-offset=@var{offset} @gol --mfdpic} +-mfdpic @gol +-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}] +[+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]]} @emph{AVR Options} @gccoptlist{-mmcu=@var{mcu} -mabsdata -maccumulate-args @gol @@ -21521,6 +21523,37 @@ The opposite @option{-mno-fdpic} option is useful (and required) to build the Linux kernel using the same (@code{arm-*-uclinuxfdpiceabi}) toolchain as the one used to build the userland programs. +@item +-mbranch-protection=@var{none}|@var{standard}|@var{pac-ret}[+@var{leaf}][+@var{bti}]|@var{bti}[+@var{pac-ret}[+@var{leaf}]] +@opindex mbranch-protection +Enable branch protection features (armv8.1-m.main only). +@samp{none} generate code without branch protection or return address +signing. +@samp{standard[+@var{leaf}]} generate code with all branch protection +features enabled at their standard level. +@samp{pac-ret[+@var{leaf}]} generate code with return address signing +set to its standard level, which is to sign all functions that save +the return address to memory. +@samp{leaf} When return address signing is enabled, also sign leaf +functions even if they do not write the return address to memory. ++@samp{bti} Add landing-pad instructions at the permitted targets of +indirect branch instructions. + +If the @samp{+pacbti} architecture extension is not enabled, then all +branch protection and return address signing operations are +constrained to use only the instructions defined in the +architectural-NOP space. The generated code will remain +backwards-compatible with earlier versions of the architecture, but +the additional security can be enabled at run time on processors that +support the @samp{PACBTI} extension. + +Branch target enforcement using BTI can only be enabled at runtime if +all code in the application has been compiled with at least +@samp{-mbranch-protection=bti}. + +The default is to generate code without branch protection or return +address signing. + @end table @node AVR Options From patchwork Thu Apr 28 09:40:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 53297 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D5AD53857434 for ; Thu, 28 Apr 2022 09:41:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D5AD53857434 DKIM-Signature: v=1; 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Pre-approved with the requested changes here . gcc/testsuite/ChangeLog: * testsuite/lib/target-supports.exp: (check_effective_target_arm_pacbti_hw): New. * doc/sourcebuild.texi: Document arm_pacbti_hw. Co-Authored-By: Tejas Belagod diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 613ac29967b..e8cbd8e4aef 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2167,6 +2167,10 @@ ARM target supports options to generate instructions from ARMv8.1-M with the Custom Datapath Extension (CDE) and M-Profile Vector Extension (MVE). Some multilibs may be incompatible with these options. +@item arm_pacbti_hw +Test system supports executing Pointer Authentication and Branch Target +Identification instructions. + @item arm_prefer_ldrd_strd ARM target prefers @code{LDRD} and @code{STRD} instructions over @code{LDM} and @code{STM} instructions. diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index ff8edbd3e17..df8ab037fb3 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -5090,6 +5090,22 @@ proc check_effective_target_arm_cmse_clear_ok {} { } "-mcmse"]; } +# Return 1 if the target supports executing PACBTI instructions, 0 +# otherwise. + +proc check_effective_target_arm_pacbti_hw {} { + return [check_runtime arm_pacbti_hw_available { + __attribute__ ((naked)) int + main (void) + { + asm ("pac r12, lr, sp"); + asm ("mov r0, #0"); + asm ("autg r12, lr, sp"); + asm ("bx lr"); + } + } ""] +} + # Return 1 if this compilation turns on string_ops_prefer_neon on. proc check_effective_target_arm_tune_string_ops_prefer_neon { } { From patchwork Thu Apr 28 09:42:48 2022 Content-Type: text/plain; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(46966006)(36840700001)(5660300002)(235185007)(4326008)(84970400001)(8676002)(316002)(508600001)(81166007)(8936002)(82310400005)(36860700001)(6916009)(2906002)(70586007)(47076005)(44832011)(26005)(2616005)(70206006)(186003)(54906003)(426003)(36756003)(336012)(40460700003)(33964004)(83380400001)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 09:42:59.1708 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3dd60340-03c7-4576-e4e6-08da28fb7afd X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT041.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2529 X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch implements target feature macros when PACBTI is enabled through the -march option or -mbranch-protection. The target feature macros __ARM_FEATURE_PAC_DEFAULT and __ARM_FEATURE_BTI_DEFAULT are specified in ARM ACLE __ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI are specified in the pull-request . Approved here . gcc/ChangeLog: * config/arm/arm-c.c (arm_cpu_builtins): Define __ARM_FEATURE_BTI_DEFAULT, __ARM_FEATURE_PAC_DEFAULT, __ARM_FEATURE_PAUTH and __ARM_FEATURE_BTI. gcc/testsuite/ChangeLog: * gcc.target/arm/acle/pacbti-m-predef-2.c: New test. * gcc.target/arm/acle/pacbti-m-predef-4.c: New test. * gcc.target/arm/acle/pacbti-m-predef-5.c: New test. Co-Authored-By: Tejas Belagod diff --git a/gcc/config/arm/arm-c.cc b/gcc/config/arm/arm-c.cc index a8697b8c62f..190099b2c37 100644 --- a/gcc/config/arm/arm-c.cc +++ b/gcc/config/arm/arm-c.cc @@ -212,6 +212,24 @@ arm_cpu_builtins (struct cpp_reader* pfile) def_or_undef_macro (pfile, "__ARM_FEATURE_COMPLEX", TARGET_COMPLEX); def_or_undef_macro (pfile, "__ARM_32BIT_STATE", TARGET_32BIT); + def_or_undef_macro (pfile, "__ARM_FEATURE_PAUTH", TARGET_HAVE_PACBTI); + def_or_undef_macro (pfile, "__ARM_FEATURE_BTI", TARGET_HAVE_PACBTI); + def_or_undef_macro (pfile, "__ARM_FEATURE_BTI_DEFAULT", + aarch_enable_bti == 1); + + cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT"); + if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE) + { + unsigned int pac = 1; + + gcc_assert (aarch_ra_sign_key == AARCH_KEY_A); + + if (aarch_ra_sign_scope == AARCH_FUNCTION_ALL) + pac |= 0x4; + + builtin_define_with_int_value ("__ARM_FEATURE_PAC_DEFAULT", pac); + } + cpp_undef (pfile, "__ARM_FEATURE_MVE"); if (TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT) { diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c new file mode 100644 index 00000000000..4394fd147d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-2.c @@ -0,0 +1,24 @@ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-additional-options " -mbranch-protection=bti+pac-ret+leaf" } */ + +#if !defined (__ARM_FEATURE_BTI_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined." +#endif + +#if !defined (__ARM_FEATURE_PAC_DEFAULT) +#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined." +#endif + +int +main() +{ + if (__ARM_FEATURE_BTI_DEFAULT != 1) + __builtin_abort (); + + if (__ARM_FEATURE_PAC_DEFAULT != 5) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c new file mode 100644 index 00000000000..90f0c724b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-4.c @@ -0,0 +1,21 @@ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-additional-options " -mbranch-protection=pac-ret" } */ + +#if !defined (__ARM_FEATURE_PAC_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined." +#endif + +#if defined (__ARM_FEATURE_BTI_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined." +#endif + +int +main() +{ + if (__ARM_FEATURE_PAC_DEFAULT != 1) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c new file mode 100644 index 00000000000..c865809b8b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-5.c @@ -0,0 +1,24 @@ + +/* { dg-do run } */ +/* { dg-require-effective-target arm_pacbti_hw } */ +/* { dg-additional-options " -mbranch-protection=bti+pac-ret" } */ + +#if !defined (__ARM_FEATURE_BTI_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined." +#endif + +#if !defined (__ARM_FEATURE_PAC_DEFAULT) +#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined." +#endif + +int +main() +{ + if (__ARM_FEATURE_BTI_DEFAULT != 1) + __builtin_abort (); + + if (__ARM_FEATURE_PAC_DEFAULT != 1) + __builtin_abort (); + + return 0; +} From patchwork Thu Apr 28 09:44:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 53299 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 45C803857350 for ; Thu, 28 Apr 2022 09:44:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 45C803857350 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1651139090; bh=AIiZcAM8kx1tOW2z+W0mziUxDe2C/98PvhcV+q3fGeU=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=cUwt348a8HljsaRgfNSDC/bNw3wXTPHeXIvNz0Mzk8DMTNbLTX6DKAuHKWLiq5rwL dTyi4muf9wCk17hdXwSsKQ0fSSSShA6ekEMOn+tesbSo2JbQyPuKSEJOLYhp0WoX3T 3vmgfU+dDLeEScDl2/4QL5160e2A0VZ/1/qPm5OU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR03-AM5-obe.outbound.protection.outlook.com (mail-eopbgr30086.outbound.protection.outlook.com [40.107.3.86]) by sourceware.org (Postfix) with ESMTPS id EB8F63858C2C for ; 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All the changes here are done to the runtime code in libgcc's unwinder code for Arm target. All the changes are guarded under defined (__ARM_FEATURE_PAC_DEFAULT) and activated only if the +pacbti feature is switched on for the architecture. This means that switching on the target feature via -march or -mcpu is sufficient and -mbranch-protection need not be enabled. This ensures that the unwinder is authenticated only if the PACBTI instructions are available in the non-NOP space as it uses AUTG. Just generating PAC/AUT instructions using -mbranch-protection will not enable authentication on the unwinder. Pre-approved with the requested changes here . gcc/ChangeLog: * ginclude/unwind-arm-common.h (_Unwind_VRS_RegClass): Introduce new pseudo register class _UVRSC_PAC. * libgcc/config/arm/pr-support.c (__gnu_unwind_execute): Decode exception opcode (0xb4) for saving RA_AUTH_CODE and authenticate with AUTG if found. * libgcc/config/arm/unwind-arm.c (struct pseudo_regs): New. (phase1_vrs): Introduce new field to store pseudo-reg state. (phase2_vrs): Likewise. (_Unwind_VRS_Get): Load pseudo register state from virtual reg set. (_Unwind_VRS_Set): Store pseudo register state to virtual reg set. (_Unwind_VRS_Pop): Load pseudo register value from stack into VRS. Co-Authored-By: Tejas Belagod diff --git a/gcc/ginclude/unwind-arm-common.h b/gcc/ginclude/unwind-arm-common.h index d3831f6c60a..f26702e8c6c 100644 --- a/gcc/ginclude/unwind-arm-common.h +++ b/gcc/ginclude/unwind-arm-common.h @@ -127,7 +127,8 @@ extern "C" { _UVRSC_VFP = 1, /* vfp */ _UVRSC_FPA = 2, /* fpa */ _UVRSC_WMMXD = 3, /* Intel WMMX data register */ - _UVRSC_WMMXC = 4 /* Intel WMMX control register */ + _UVRSC_WMMXC = 4, /* Intel WMMX control register */ + _UVRSC_PAC = 5 /* Armv8.1-M Mainline PAC/AUTH pseudo-register */ } _Unwind_VRS_RegClass; diff --git a/libgcc/config/arm/pr-support.c b/libgcc/config/arm/pr-support.c index 2de96c2a447..e48854587c6 100644 --- a/libgcc/config/arm/pr-support.c +++ b/libgcc/config/arm/pr-support.c @@ -106,6 +106,7 @@ __gnu_unwind_execute (_Unwind_Context * context, __gnu_unwind_state * uws) { _uw op; int set_pc; + int set_pac = 0; _uw reg; set_pc = 0; @@ -114,6 +115,27 @@ __gnu_unwind_execute (_Unwind_Context * context, __gnu_unwind_state * uws) op = next_unwind_byte (uws); if (op == CODE_FINISH) { + /* When we reach end, we have to authenticate R12 we just popped + earlier. + + Note: while the check provides additional security against a + corrupted unwind chain, it isn't essential for correct unwinding + of an uncorrupted chain. */ +#if defined(TARGET_HAVE_PACBTI) + if (set_pac) + { + _uw sp; + _uw lr; + _uw pac; + _Unwind_VRS_Get (context, _UVRSC_CORE, R_SP, _UVRSD_UINT32, &sp); + _Unwind_VRS_Get (context, _UVRSC_CORE, R_LR, _UVRSD_UINT32, &lr); + _Unwind_VRS_Get (context, _UVRSC_PAC, R_IP, + _UVRSD_UINT32, &pac); + __asm__ __volatile__ + ("autg %0, %1, %2" : : "r"(pac), "r"(lr), "r"(sp) :); + } +#endif + /* If we haven't already set pc then copy it from lr. */ if (!set_pc) { @@ -227,6 +249,16 @@ __gnu_unwind_execute (_Unwind_Context * context, __gnu_unwind_state * uws) return _URC_FAILURE; continue; } + /* Pop PAC off the stack into VRS pseudo.pac. */ + if (op == 0xb4) + { + if (_Unwind_VRS_Pop (context, _UVRSC_PAC, 0, _UVRSD_UINT32) + != _UVRSR_OK) + return _URC_FAILURE; + set_pac = 1; + continue; + } + if ((op & 0xfc) == 0xb4) /* Obsolete FPA. */ return _URC_FAILURE; diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c index 386406564af..89f945d047e 100644 --- a/libgcc/config/arm/unwind-arm.c +++ b/libgcc/config/arm/unwind-arm.c @@ -64,6 +64,12 @@ struct wmmxc_regs _uw wc[4]; }; +/* Holds value of pseudo registers eg. PAC. */ +struct pseudo_regs +{ + _uw pac; +}; + /* The ABI specifies that the unwind routines may only use core registers, except when actually manipulating coprocessor state. This allows us to write one implementation that works on all platforms by @@ -78,6 +84,9 @@ typedef struct /* The first fields must be the same as a phase2_vrs. */ _uw demand_save_flags; struct core_regs core; + /* Armv8.1-M Mainline PAC/AUTH values. This field should be in the same field + order as phase2_vrs. */ + struct pseudo_regs pseudo; _uw prev_sp; /* Only valid during forced unwinding. */ struct vfp_regs vfp; struct vfpv3_regs vfp_regs_16_to_31; @@ -99,6 +108,7 @@ typedef struct { _uw demand_save_flags; struct core_regs core; + struct pseudo_regs pac; } phase2_vrs; /* Coprocessor register state manipulation functions. */ @@ -175,6 +185,10 @@ _Unwind_VRS_Result _Unwind_VRS_Get (_Unwind_Context *context, case _UVRSC_WMMXC: return _UVRSR_NOT_IMPLEMENTED; + case _UVRSC_PAC: + *(_uw *) valuep = vrs->pseudo.pac; + return _UVRSR_OK; + default: return _UVRSR_FAILED; } @@ -206,6 +220,10 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context, case _UVRSC_WMMXC: return _UVRSR_NOT_IMPLEMENTED; + case _UVRSC_PAC: + vrs->pseudo.pac = *(_uw *) valuep; + return _UVRSR_OK; + default: return _UVRSR_FAILED; } @@ -246,6 +264,14 @@ _Unwind_VRS_Result _Unwind_VRS_Pop (_Unwind_Context *context, } return _UVRSR_OK; + case _UVRSC_PAC: + { + if (discriminator != 0) + return _UVRSR_FAILED; + vrs->pseudo.pac = *(_uw *) vrs->core.r[R_SP]; + return _UVRSR_OK; + } + case _UVRSC_VFP: { _uw start = discriminator >> 16; From patchwork Thu Apr 28 09:45:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 53300 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D62ED385735D for ; Thu, 28 Apr 2022 09:45:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D62ED385735D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1651139149; bh=XBS5Ujt7a48UlddQKedRFdjJlfuKLApPZwSp4vOzvlI=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=G3nWNR5ehSC8hRwfeuuGbdPXKiU0740Au+hFerkoWzJo/d56byyyB62qcozKbBzhG i5dtDatg4DiVjJkMgAta+STW29L1KJPDSIaUkLOlczFKZapcEBvXpCvJGyov1Nw4iA E73bXM5qoxAZWIIKTvOiG7JuC83FBrlxu4ZxW8RA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR01-HE1-obe.outbound.protection.outlook.com (mail-eopbgr130075.outbound.protection.outlook.com [40.107.13.75]) by sourceware.org (Postfix) with ESMTPS id 711A13857346 for ; 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Thu, 28 Apr 2022 09:45:05 +0000 To: Andrea Corallo via Gcc-patches Subject: [PATCH 7/12] arm: Emit build attributes for PACBTI target feature References: Date: Thu, 28 Apr 2022 11:45:02 +0200 In-Reply-To: (Andrea Corallo via Gcc-patches's message of "Thu, 28 Apr 2022 10:39:31 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/29.0.50 (gnu/linux) MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: f9d8a684-be79-4938-fd6f-08da28fbcba8 X-MS-TrafficTypeDiagnostic: DB9PR08MB6395:EE_|DB5EUR03FT031:EE_|VE1PR08MB5646:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: bWSrXitHwa2KkyqGP7lKIBRROFn0ak74LwJLY7Faf9Cgxj2eNDjbhNOfeKhoaqFTgQLmKe4ICMkMk3jDt09JawjkGllnuOqbYEz/DGldMqWN6SXksRxdQEmIjun7nnUvbS4f9vSEWUKtZ+uTQPdyF/9A6qZ4YAWXpCLdpb5u2EZo1dobFeOPPzZ7tp5AbAT7yuy7kcy7bKeFR8Z8vwXc0TdT9rr9u5OjzgyZGubumm2dJhC7FO6k5JzplAnFuoF2sUr314rNgAeYhsz5VtRiTR0bREApnsGnfYvCea6UmdiDzqlsdnJligCvYh3KO37KyjKMMDfYr3jUytkNW7Dz5SSFKm7WogNkrOCUWZKXYmGDhPTlV12VflO4OqxhgCGLLeQKUlQNZnBK9kdaovzI9q8n80Skp+vcV1499oUrW52z1HyOB/nsBR03LZcr40+JToDYQn7shVHzXAINTwnUYjVjHoy2uAkz8ZE4aWCYZFXqUx/Pmwr6q3/vnlchtkCWPa4yPSOpSxj0kvkDMFXDA9aeg4CO6F0cnQXwkx3E8tH3PnZAfQDeBHRxZlA27hQ04a3zHI4PggJHIo0rOHEDI1VTcpVIUnGRffh3XGjgnfcU8SyFMHPlETPprFKBpye1jvphOOxkeC91XOG21BEHeiBLDNjRLOAuiZXeGHvpmGVGn7BBmOR3GrBXRGGBz5w8oatAPXoKvCTvkdmb6lAZ2ZlKegbu0HJe6Ah+Oz6urfMl9vzh8OvrkTipk9Gphu4Q7LPPGiZ5XAyezgThfoWkCAPqtZX13QO1qBiyrYpMQRa0sl865hRrh5JRdDhbGIjBcLw2IJR2H5Sn2Dmn4zZfEw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(316002)(186003)(47076005)(44832011)(36860700001)(6666004)(508600001)(235185007)(426003)(36756003)(8936002)(86362001)(54906003)(6916009)(336012)(40460700003)(2616005)(82310400005)(84970400001)(83380400001)(81166007)(5660300002)(70586007)(2906002)(70206006)(4326008)(33964004)(8676002)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 09:45:14.4942 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9d8a684-be79-4938-fd6f-08da28fbcba8 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT031.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5646 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch emits assembler directives for PACBTI build attributes as defined by the ABI. gcc/ChangeLog: * config/arm/arm.c (arm_file_start): Emit EABI attributes for Tag_PAC_extension, Tag_BTI_extension, TAG_BTI_use, TAG_PACRET_use. gcc/testsuite/ChangeLog: * gcc.target/arm/acle/pacbti-m-predef-1.c: New test. * gcc.target/arm/acle/pacbti-m-predef-3: Likewise. * gcc.target/arm/acle/pacbti-m-predef-6.c: Likewise. * gcc.target/arm/acle/pacbti-m-predef-7.c: Likewise. Co-Authored-By: Tejas Belagod diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 0068817b0f2..ceec14f84b6 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -28349,6 +28349,8 @@ static void arm_file_start (void) { int val; + bool pac = (aarch_ra_sign_scope != AARCH_FUNCTION_NONE); + bool bti = (aarch_enable_bti == 1); arm_print_asm_arch_directives (asm_out_file, TREE_TARGET_OPTION (target_option_default_node)); @@ -28419,6 +28421,22 @@ arm_file_start (void) arm_emit_eabi_attribute ("Tag_ABI_FP_16bit_format", 38, (int) arm_fp16_format); + if (TARGET_HAVE_PACBTI) + { + arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 2); + arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 2); + } + else if (pac || bti) + { + arm_emit_eabi_attribute ("Tag_PAC_extension", 50, 1); + arm_emit_eabi_attribute ("Tag_BTI_extension", 52, 1); + } + + if (bti) + arm_emit_eabi_attribute ("TAG_BTI_use", 74, 1); + if (pac) + arm_emit_eabi_attribute ("TAG_PACRET_use", 76, 1); + if (arm_lang_output_object_attributes_hook) arm_lang_output_object_attributes_hook(); } diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c new file mode 100644 index 00000000000..75d3e00ef64 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-additional-options " -mbranch-protection=pac-ret+bti --save-temps" } */ + +#if !defined (__ARM_FEATURE_BTI_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined." +#endif + +#if !defined (__ARM_FEATURE_PAC_DEFAULT) +#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined." +#endif + +/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 74, 1" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 76, 1" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c new file mode 100644 index 00000000000..bf6c3ba90c9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-3.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-additional-options " -mbranch-protection=pac-ret+leaf --save-temps" } */ + +#if defined (__ARM_FEATURE_BTI_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined." +#endif + +#if !defined (__ARM_FEATURE_PAC_DEFAULT) +#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be defined." +#endif + +/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */ +/* { dg-final { scan-assembler-not "\.eabi_attribute 74" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 76, 1" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c new file mode 100644 index 00000000000..82af11ee407 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-6.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-additional-options " -mbranch-protection=bti --save-temps" } */ + +#if !defined (__ARM_FEATURE_BTI_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be defined." +#endif + +#if defined (__ARM_FEATURE_PAC_DEFAULT) +#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be undefined." +#endif +/* { dg-final { scan-assembler-not "\.arch_extension pacbti" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 50, 1" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 52, 1" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 74, 1" } } */ +/* { dg-final { scan-assembler-not "\.eabi_attribute 76" } } */ diff --git a/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c new file mode 100644 index 00000000000..48a40e64c11 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/acle/pacbti-m-predef-7.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.1-m.main+pacbti --save-temps" } */ + +#if defined (__ARM_FEATURE_BTI_DEFAULT) +#error "Feature test macro __ARM_FEATURE_BTI_DEFAULT should be undefined." +#endif + +#if defined (__ARM_FEATURE_PAC_DEFAULT) +#error "Feature test macro __ARM_FEATURE_PAC_DEFAULT should be undefined." +#endif + +/* { dg-final { scan-assembler "\.arch_extension pacbti" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 50, 2" } } */ +/* { dg-final { scan-assembler "\.eabi_attribute 52, 2" } } */ +/* { dg-final { scan-assembler-not "\.eabi_attribute 74" } } */ +/* { dg-final { scan-assembler-not "\.eabi_attribute 76" } } */ From patchwork Thu Apr 28 09:46:26 2022 Content-Type: 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4299 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch add the following new multilibs. thumb/v8.1-m.main+pacbti/mbranch-protection/nofp thumb/v8.1-m.main+pacbti+dp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard thumb/v8.1-m.main+pacbti+fp/mbranch-protection/soft thumb/v8.1-m.main+pacbti+fp/mbranch-protection/hard thumb/v8.1-m.main+pacbti+mve/mbranch-protection/hard Triggering the following compiler flags: -mthumb -march=armv8.1-m.main+pacbti -mbranch-protection=standard -mfloat-abi=soft -mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mfloat-abi=softfp -mthumb -march=armv8.1-m.main+pacbti+fp -mbranch-protection=standard -mfloat-abi=hard -mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard -mfloat-abi=softfp -mthumb -march=armv8.1-m.main+pacbti+fp.dp -mbranch-protection=standard -mfloat-abi=hard -mthumb -march=armv8.1-m.main+pacbti+mve -mbranch-protection=standard -mfloat-abi=hard gcc/ChangeLog: * config/arm/t-rmprofile: Add multilib rules for +pacbti. diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile index eb321e832f1..542ff874b2e 100644 --- a/gcc/config/arm/t-rmprofile +++ b/gcc/config/arm/t-rmprofile @@ -27,8 +27,11 @@ # Arch and FPU variants to build libraries with -MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve -MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp v8.1-m.main+mve +MULTI_ARCH_OPTS_RM = march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp/march=armv8.1-m.main+mve/march=armv8.1-m.main+pacbti/march=armv8.1-m.main+pacbti+fp/march=armv8.1-m.main+pacbti+fp.dp/march=armv8.1-m.main+pacbti+mve +MULTI_ARCH_DIRS_RM = v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp v8.1-m.main+mve v8.1-m.main+pacbti v8.1-m.main+pacbti+fp v8.1-m.main+pacbti+dp 8.1-m.main+pacbti+mve + +MULTI_ARCH_OPTS_RM += mbranch-protection=pac-ret+bti +MULTI_ARCH_DIRS_RM += mbranch-protection # Base M-profile (no fp) MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft @@ -50,6 +53,14 @@ MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=softfp MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+mve/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+pacbti/mbranch-protection=standard/mfloat-abi=soft +MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+pacbti+fp/mbranch-protection=standard/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=softfp +MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+pacbti+fp.dp/mbranch-protection=standard/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv8.1-m.main+pacbti+mve/mbranch-protection=standard/mfloat-abi=hard + + # Arch Matches MULTILIB_MATCHES += march?armv6s-m=march?armv6-m @@ -93,3 +104,4 @@ MULTILIB_MATCHES += march?armv8-m.main=mlibarch?armv8-m.main MULTILIB_MATCHES += march?armv8-m.main+fp=mlibarch?armv8-m.main+fp MULTILIB_MATCHES += march?armv8-m.main+fp.dp=mlibarch?armv8-m.main+fp.dp MULTILIB_MATCHES += march?armv8.1-m.main+mve=mlibarch?armv8.1-m.main+mve +MULTILIB_MATCHES += march?armv8.1-m.main+pacbti=mlibarch?armv8.1-m.main+pacbti From patchwork Thu Apr 28 09:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 53303 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C73F33857432 for ; Thu, 28 Apr 2022 09:50:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C73F33857432 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; 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X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR08MB8198 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This change add bti instructions at the beginning of arm specific libgcc hand written assembly routines. 2022-03-31 Andrea Corallo * libgcc/config/arm/crti.S (FUNC_START): Add bti instruction if necessary. * libgcc/config/arm/lib1funcs.S (THUMB_FUNC_START, FUNC_START): Likewise. diff --git a/libgcc/config/arm/crti.S b/libgcc/config/arm/crti.S index 0192972a7e6..bac2d87fbb9 100644 --- a/libgcc/config/arm/crti.S +++ b/libgcc/config/arm/crti.S @@ -51,7 +51,9 @@ .macro FUNC_START #ifdef __thumb__ .thumb - +#if defined(__ARM_FEATURE_BTI) + bti +#endif push {r3, r4, r5, r6, r7, lr} #else .arm diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 8c39c9f20a2..45dfb5da9ee 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -345,6 +345,9 @@ LSYM(Ldiv0): TYPE (\name) .thumb_func SYM (\name): +#if defined(__ARM_FEATURE_BTI) + bti +#endif .endm /* Function start macros. Variants for ARM and Thumb. */ @@ -372,6 +375,9 @@ SYM (\name): THUMB_FUNC THUMB_SYNTAX SYM (__\name): +#if defined(__ARM_FEATURE_BTI) + bti +#endif .endm .macro ARM_SYM_START name From patchwork Thu Apr 28 09:50:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 53304 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3835B385742B for ; Thu, 28 Apr 2022 09:51:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3835B385742B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1651139494; bh=1Cv0WBoDKvrN5DduT4nyRW2DoUvYLUoFThzc5pU1zBM=; h=To:Subject:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=NWSC7o9JaAGS5AOMbvzOGH7adEnQp/6GoW8uKoE9IBLjvl0QLz6Oc8XLirxELzckX lBPd0Xno4IOCI315YCx1vb1LHD1xd6J1mHYrMTkfDiNPHAWzEmlVon0B7sDii6Muku y9RTXICYlhLJFnxiUr9u37WD3OyN65WoS6lnxoLo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-eopbgr70072.outbound.protection.outlook.com [40.107.7.72]) by sourceware.org (Postfix) with ESMTPS id D20E33857357 for ; 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Thu, 28 Apr 2022 09:50:07 +0000 To: Andrea Corallo via Gcc-patches Subject: [PATCH 10/12] arm: Implement cortex-M return signing address codegen References: Date: Thu, 28 Apr 2022 11:50:04 +0200 In-Reply-To: (Andrea Corallo via Gcc-patches's message of "Thu, 28 Apr 2022 10:39:31 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/29.0.50 (gnu/linux) MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: b2ff5741-1aef-457e-c8c6-08da28fc8181 X-MS-TrafficTypeDiagnostic: PAXPR08MB7202:EE_|AM5EUR03FT023:EE_|DB7PR08MB3227:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: x+uB3BzkCkk1ZHEy0P/v5dmK6FmFiy60S1Evxjzs/wouV2Wo1Z5Fvh0D5qwJpz3QLgy8dlnfQ1Yjl6HA6c/OwejDmFYVMaF4RCyhUCaBSlIVhlEbUDD6qPaTvc+ZJ0e69lzZCnjheozEs6fTRyYk7pWchoilag3nc6DKYL+QWmOQL9PmT+l+gXAEzVobS1lK3MjFFQQpJCqp3JKKEiBP1IL+3Nq/FH3jxAAdAa+I1LXZbbruCf9GV2PuvRqAjU/mVr9hIA207gke8usodxIY9kmcYARPIyvavu7R3dF69tsvGwAH9U+KDPHy1n7651+24EYypk92rn2J6ItchgmOsn/4rSA64jxxxDwog6IIjMQBGI7jaS4COnM7BRp1hXM67v31FmzIM+LwdBLOjBzSByc0z0kjgylwN/Gc+7ewkwaYDZNz1zPDeAA9Dl+v4+ZDxkZXKMK0wIJCyeVfDF8MMDvP14FKxvFBOc3z0ObvCcusSZWnr8Fa2fW/zmdJnXJjTGVoIIuHV74u6ylspRdBefSYhNJxX0NNNPQvBfzclBLBPsMigT8Zxx3F+LOCRs8M/855iZswasxP1jfAyJcJLi3QwUCBnAdBGSqsoxjMnQNi+xe4gM4SL4PWmYkMBu80OylaZ8XmSJ2/s3B5Vsuoc3qpyY9RU5IBMal2BY7AS1JbMYt+cEp+hEoGpTMUsgYQtwl9h9iCXhsQc6JrbH0qaZJw7fihmfGox1ZSwCGIyoPgOXGcuz+ceucmezv5wAL2XLbu2gvFw+qYhpnckSW492yz71Drg1EszPePSI2p3czmbhQg56ihOlfWPH8/W07GfITlcOYqF5GDoFacDnzitA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(40470700004)(36840700001)(46966006)(235185007)(47076005)(84970400001)(86362001)(316002)(508600001)(2616005)(6916009)(54906003)(33964004)(70206006)(81166007)(70586007)(82310400005)(6666004)(40460700003)(26005)(426003)(336012)(5660300002)(4326008)(8936002)(36756003)(83380400001)(2906002)(44832011)(186003)(36860700001)(8676002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 09:50:19.5045 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2ff5741-1aef-457e-c8c6-08da28fc8181 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT023.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR08MB3227 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, this patch enables address return signature and verification based on Armv8.1-M Pointer Authentication [1]. To sign the return address, we use the PAC R12, LR, SP instruction upon function entry. This is signing LR using SP and storing the result in R12. R12 will be pushed into the stack. During function epilogue R12 will be popped and AUT R12, LR, SP will be used to verify that the content of LR is still valid before return. Here an example of PAC instrumented function prologue and epilogue: void foo (void); int main() { foo (); return 0; } Compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret -mthumb' translates into: main: pac ip, lr, sp push {r3, r7, ip, lr} add r7, sp, #0 bl foo movs r3, #0 mov r0, r3 pop {r3, r7, ip, lr} aut ip, lr, sp bx lr The patch also takes care of generating a PACBTI instruction in place of the sequence BTI+PAC when Branch Target Identification is enabled contextually. Ex. the previous example compiled with '-march=armv8.1-m.main -mbranch-protection=pac-ret+bti -mthumb' translates into: main: pacbti ip, lr, sp push {r3, r7, ip, lr} add r7, sp, #0 bl foo movs r3, #0 mov r0, r3 pop {r3, r7, ip, lr} aut ip, lr, sp bx lr As part of previous upstream suggestions a test for varargs has been added and '-mtpcs-frame' is deemed being incompatible with this return signing address feature being introduced. [1] gcc/Changelog * config/arm/arm.c: (arm_compute_frame_layout) (arm_expand_prologue, thumb2_expand_return, arm_expand_epilogue) (arm_conditional_register_usage): Update for pac codegen. (arm_current_function_pac_enabled_p): New function. * config/arm/arm.md (pac_ip_lr_sp, pacbti_ip_lr_sp, aut_ip_lr_sp): Add new patterns. * config/arm/unspecs.md (UNSPEC_PAC_IP_LR_SP) (UNSPEC_PACBTI_IP_LR_SP, UNSPEC_AUT_IP_LR_SP): Add unspecs. gcc/testsuite/Changelog * gcc.target/arm/pac.h : New file. * gcc.target/arm/pac-1.c : New test case. * gcc.target/arm/pac-2.c : Likewise. * gcc.target/arm/pac-3.c : Likewise. * gcc.target/arm/pac-4.c : Likewise. * gcc.target/arm/pac-5.c : Likewise. * gcc.target/arm/pac-6.c : Likewise. * gcc.target/arm/pac-7.c : Likewise. * gcc.target/arm/pac-8.c : Likewise. diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index ceec14f84b6..c91dae292c8 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -302,6 +302,7 @@ static bool arm_vectorize_vec_perm_const (machine_mode, rtx, rtx, rtx, const vec_perm_indices &); static bool aarch_macro_fusion_pair_p (rtx_insn*, rtx_insn*); +static bool arm_current_function_pac_enabled_p (void); static int arm_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, tree vectype, @@ -21139,6 +21140,14 @@ arm_compute_save_core_reg_mask (void) save_reg_mask |= arm_compute_save_reg0_reg12_mask (); + if (arm_current_function_pac_enabled_p ()) + { + if (TARGET_TPCS_FRAME + || (TARGET_TPCS_LEAF_FRAME && crtl->is_leaf)) + error ("TPCS incompatible with return address signing."); + save_reg_mask |= 1 << IP_REGNUM; + } + /* Decide if we need to save the link register. Interrupt routines have their own banked link register, so they never need to save it. @@ -22302,7 +22311,7 @@ arm_emit_multi_reg_pop (unsigned long saved_regs_mask) par = emit_insn (par); REG_NOTES (par) = dwarf; - if (!return_in_pc) + if (!return_in_pc && !frame_pointer_needed) arm_add_cfa_adjust_cfa_note (par, UNITS_PER_WORD * num_regs, stack_pointer_rtx, stack_pointer_rtx); } @@ -23352,6 +23361,11 @@ output_probe_stack_range (rtx reg1, rtx reg2) return ""; } +static bool aarch_bti_enabled () +{ + return false; +} + /* Generate the prologue instructions for entry into an ARM or Thumb-2 function. */ void @@ -23431,11 +23445,12 @@ arm_expand_prologue (void) /* The static chain register is the same as the IP register. If it is clobbered when creating the frame, we need to save and restore it. */ clobber_ip = IS_NESTED (func_type) - && ((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) - || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK - || flag_stack_clash_protection) - && !df_regs_ever_live_p (LR_REGNUM) - && arm_r3_live_at_start_p ())); + && (((TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) + || ((flag_stack_check == STATIC_BUILTIN_STACK_CHECK + || flag_stack_clash_protection) + && !df_regs_ever_live_p (LR_REGNUM) + && arm_r3_live_at_start_p ())) + || (arm_current_function_pac_enabled_p ())); /* Find somewhere to store IP whilst the frame is being created. We try the following places in order: @@ -23511,6 +23526,14 @@ arm_expand_prologue (void) } } + if (arm_current_function_pac_enabled_p ()) + { + if (aarch_bti_enabled ()) + emit_insn (gen_pacbti_nop ()); + else + emit_insn (gen_pac_nop ()); + } + if (TARGET_APCS_FRAME && frame_pointer_needed && TARGET_ARM) { if (IS_INTERRUPT (func_type)) @@ -27299,7 +27322,8 @@ thumb2_expand_return (bool simple_return) to assert it for now to ensure that future code changes do not silently change this behavior. */ gcc_assert (!IS_CMSE_ENTRY (arm_current_func_type ())); - if (num_regs == 1) + if (num_regs == 1 + && !(arm_current_function_pac_enabled_p ())) { rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2)); rtx reg = gen_rtx_REG (SImode, PC_REGNUM); @@ -27314,10 +27338,20 @@ thumb2_expand_return (bool simple_return) } else { - saved_regs_mask &= ~ (1 << LR_REGNUM); - saved_regs_mask |= (1 << PC_REGNUM); - arm_emit_multi_reg_pop (saved_regs_mask); - } + if (arm_current_function_pac_enabled_p ()) + { + saved_regs_mask &= ~ (1 << PC_REGNUM); + arm_emit_multi_reg_pop (saved_regs_mask); + emit_insn (gen_aut_nop ()); + emit_jump_insn (simple_return_rtx); + } + else + { + saved_regs_mask &= ~ (1 << LR_REGNUM); + saved_regs_mask |= (1 << PC_REGNUM); + arm_emit_multi_reg_pop (saved_regs_mask); + } + } } else { @@ -27723,7 +27757,8 @@ arm_expand_epilogue (bool really_return) && really_return && crtl->args.pretend_args_size == 0 && saved_regs_mask & (1 << LR_REGNUM) - && !crtl->calls_eh_return) + && !crtl->calls_eh_return + && !arm_current_function_pac_enabled_p ()) { saved_regs_mask &= ~(1 << LR_REGNUM); saved_regs_mask |= (1 << PC_REGNUM); @@ -27837,6 +27872,9 @@ arm_expand_epilogue (bool really_return) } } + if (arm_current_function_pac_enabled_p ()) + emit_insn (gen_aut_nop ()); + if (!really_return) return; @@ -30541,6 +30579,9 @@ arm_conditional_register_usage (void) global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; } + if (TARGET_HAVE_PACBTI) + call_used_regs[IP_REGNUM] = 1; + /* The Q and GE bits are only accessed via special ACLE patterns. */ CLEAR_HARD_REG_BIT (operand_reg_set, APSRQ_REGNUM); CLEAR_HARD_REG_BIT (operand_reg_set, APSRGE_REGNUM); @@ -32931,6 +32972,15 @@ arm_fusion_enabled_p (tune_params::fuse_ops op) return current_tune->fusible_ops & op; } +/* Return TRUE if return address signing mechanism is enabled. */ +static bool +arm_current_function_pac_enabled_p (void) +{ + return aarch_ra_sign_scope == AARCH_FUNCTION_ALL + || (aarch_ra_sign_scope == AARCH_FUNCTION_NON_LEAF + && !crtl->is_leaf); +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 60468f6182c..b480f76a876 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12890,6 +12890,29 @@ (set_attr "length" "8")] ) +(define_insn "pac_nop" + [(set (reg:SI IP_REGNUM) + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + UNSPEC_PAC_NOP))] + "TARGET_THUMB2" + "pac\t%|ip, %|lr, %|sp" + [(set_attr "length" "2")]) + +(define_insn "pacbti_nop" + [(set (reg:SI IP_REGNUM) + (unspec:SI [(reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + UNSPEC_PACBTI_NOP))] + "TARGET_THUMB2" + "pacbti\t%|ip, %|lr, %|sp" + [(set_attr "length" "2")]) + +(define_insn "aut_nop" + [(unspec:SI [(reg:SI IP_REGNUM) (reg:SI SP_REGNUM) (reg:SI LR_REGNUM)] + UNSPEC_AUT_NOP)] + "TARGET_THUMB2" + "aut\t%|ip, %|lr, %|sp" + [(set_attr "length" "2")]) + ;; Vector bits common to IWMMXT, Neon and MVE (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 7748e784379..dbe243a03f6 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -159,6 +159,9 @@ UNSPEC_VCDE ; Custom Datapath Extension instruction. UNSPEC_VCDEA ; Custom Datapath Extension instruction. UNSPEC_DLS ; Used for DLS (Do Loop Start), Armv8.1-M Mainline instruction + UNSPEC_PAC_NOP ; Represents PAC signing LR + UNSPEC_PACBTI_NOP ; Represents PAC signing LR + valid landing pad + UNSPEC_AUT_NOP ; Represents PAC verifying LR ]) diff --git a/gcc/testsuite/gcc.target/arm/pac-1.c b/gcc/testsuite/gcc.target/arm/pac-1.c new file mode 100644 index 00000000000..627a93f8a56 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-1.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-2.c b/gcc/testsuite/gcc.target/arm/pac-2.c new file mode 100644 index 00000000000..a89eb73f012 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-2.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret -mthumb --save-temps -O0" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler "pac\tip, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tip, lr, sp" } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-3.c b/gcc/testsuite/gcc.target/arm/pac-3.c new file mode 100644 index 00000000000..a241fd0f172 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-3.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=bti+pac-ret+leaf -mthumb --save-temps -O2" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-times "pacbti\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "\tbti\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-4.c b/gcc/testsuite/gcc.target/arm/pac-4.c new file mode 100644 index 00000000000..63dc9a9e08e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-4.c @@ -0,0 +1,9 @@ +/* Testing return address signing. */ +/* { dg-do compile } */ +/* { dg-options "-march=armv8.1-m.main+pacbti -mthumb --save-temps -O2" } */ + +#include "pac.h" + +/* { dg-final { scan-assembler-not "\tbti\t" } } */ +/* { dg-final { scan-assembler-not "\tpac\t" } } */ +/* { dg-final { scan-assembler-not "\tpacbti\t" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-5.c b/gcc/testsuite/gcc.target/arm/pac-5.c new file mode 100644 index 00000000000..97de00d8057 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-5.c @@ -0,0 +1,26 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + int square (int z) { return z * z; } + return square (a) + square (b); +} + +int +main (void) +{ + if (foo1 (1, 2) != 5) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-6.c b/gcc/testsuite/gcc.target/arm/pac-6.c new file mode 100644 index 00000000000..0d640751335 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-6.c @@ -0,0 +1,18 @@ +/* Check that GCC does .save and .cfi_offset directives with RA_AUTH_CODE pseudo hard-register. */ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0 -g" } */ + +int i; + +void foo (int); + +int bar() +{ + foo (i); + return 0; +} + +/* { dg-final { scan-assembler "pac\tip, lr, sp" } } */ +/* { dg-final { scan-assembler "aut\tip, lr, sp" } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-7.c b/gcc/testsuite/gcc.target/arm/pac-7.c new file mode 100644 index 00000000000..3882b05a9be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-7.c @@ -0,0 +1,30 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + int x = 4; + int foo2 (int a, int b) + { + return a + b + x; + } + return foo2 (a, b); +} + +int +main (void) +{ + if (foo1 (1, 2) != 7) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 3 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac-8.c b/gcc/testsuite/gcc.target/arm/pac-8.c new file mode 100644 index 00000000000..35728308c32 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac-8.c @@ -0,0 +1,32 @@ +/* Testing return address signing. */ +/* { dg-do run } */ +/* { dg-options "-march=armv8.1-m.main -mbranch-protection=pac-ret+leaf -mthumb --save-temps -O0" } */ + +#include +#include + +int acc (int n, ...) +{ + int sum = 0; + va_list ptr; + + va_start (ptr, n); + + for (int i = 0; i < n; i++) + sum += va_arg (ptr, int); + va_end (ptr); + + return sum; +} + +int main() +{ + if (acc (3, 1, 2, 3) != 6) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler-times "pac\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-times "aut\tip, lr, sp" 2 } } */ +/* { dg-final { scan-assembler-not "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/pac.h b/gcc/testsuite/gcc.target/arm/pac.h new file mode 100644 index 00000000000..7355e6b2954 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pac.h @@ -0,0 +1,17 @@ +#include + +int +__attribute__((noinline)) +foo1 (int a, int b) +{ + return a + b; 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Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; Received: from nebula.arm.com (40.67.248.234) by DB5EUR03FT003.mail.protection.outlook.com (10.152.20.157) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5206.12 via Frontend Transport; Thu, 28 Apr 2022 09:51:48 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Thu, 28 Apr 2022 09:51:45 +0000 Received: from e124257 (10.34.101.64) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27 via Frontend Transport; Thu, 28 Apr 2022 09:51:45 +0000 To: Andrea Corallo via Gcc-patches Subject: [PATCH 11/12] aarch64: Make bti pass generic so it can be used by the arm backend References: Date: Thu, 28 Apr 2022 11:51:43 +0200 In-Reply-To: (Andrea Corallo via Gcc-patches's message of "Thu, 28 Apr 2022 10:39:31 +0200") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/29.0.50 (gnu/linux) MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: c5d4471e-8446-402d-0bde-08da28fcbb8e X-MS-TrafficTypeDiagnostic: VI1PR08MB4336:EE_|AM5EUR03FT020:EE_|VI1PR0802MB2269:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(36860700001)(70206006)(70586007)(5660300002)(235185007)(186003)(81166007)(8936002)(82310400005)(36756003)(8676002)(4326008)(44832011)(316002)(83380400001)(86362001)(2906002)(54906003)(6916009)(33964004)(47076005)(2616005)(508600001)(40460700003)(426003)(336012)(26005)(41533002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2022 09:51:56.8981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c5d4471e-8446-402d-0bde-08da28fcbb8e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT020.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0802MB2269 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Cc: Richard Earnshaw , nd Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, this patch splits and restructures the aarch64 bti pass code in order to have it usable by the arm backend as well. These changes have no functional impact. Best Regards Andrea gcc/Changelog * config.gcc (aarch64*-*-*): Rename 'aarch64-bti-insert.o' into 'aarch-bti-insert.o'. * config/aarch64/aarch64-protos.h: Remove 'aarch64_bti_enabled' proto. * config/aarch64/aarch64.cc (aarch_bti_enabled): Rename. (aarch_bti_j_insn_p, aarch_pac_insn_p): New functions. (aarch64_output_mi_thunk) (aarch64_print_patchable_function_entry) (aarch64_file_end_indicate_exec_stack): Update renamed function calls to renamed functions. * config/aarch64/t-aarch64 (aarch-bti-insert.o): Update target. * config/arm/aarch-bti-insert.cc: New file including and generalizing code from aarch64-bti-insert.cc. * config/arm/aarch-common-protos.h: Update. * config/arm/arm-passes.def: New file. diff --git a/gcc/config.gcc b/gcc/config.gcc index 7b58e1314ff..2021bdf9d2f 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -329,7 +329,7 @@ aarch64*-*-*) c_target_objs="aarch64-c.o" cxx_target_objs="aarch64-c.o" d_target_objs="aarch64-d.o" - extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch64-bti-insert.o aarch64-cc-fusion.o" + extra_objs="aarch64-builtins.o aarch-common.o aarch64-sve-builtins.o aarch64-sve-builtins-shapes.o aarch64-sve-builtins-base.o aarch64-sve-builtins-sve2.o cortex-a57-fma-steering.o aarch64-speculation.o falkor-tag-collision-avoidance.o aarch-bti-insert.o aarch64-cc-fusion.o" target_gtfiles="\$(srcdir)/config/aarch64/aarch64-builtins.cc \$(srcdir)/config/aarch64/aarch64-sve-builtins.h \$(srcdir)/config/aarch64/aarch64-sve-builtins.cc" target_has_targetm_common=yes ;; diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index b0c5a4fd6b6..a9aad3abdc2 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -179,7 +179,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_RNG, "__ARM_FEATURE_RNG", pfile); aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile); - aarch64_def_or_undef (aarch64_bti_enabled (), + aarch64_def_or_undef (aarch_bti_enabled (), "__ARM_FEATURE_BTI_DEFAULT", pfile); cpp_undef (pfile, "__ARM_FEATURE_PAC_DEFAULT"); diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index fe2180e95ea..9fdf7f9cc9c 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -891,7 +891,6 @@ void aarch64_register_pragmas (void); void aarch64_relayout_simd_types (void); void aarch64_reset_previous_fndecl (void); bool aarch64_return_address_signing_enabled (void); -bool aarch64_bti_enabled (void); void aarch64_save_restore_target_globals (tree); void aarch64_addti_scratch_regs (rtx, rtx, rtx *, rtx *, rtx *, diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index eec743024c1..2f67f3872f6 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -8534,11 +8534,61 @@ aarch64_return_address_signing_enabled (void) /* Return TRUE if Branch Target Identification Mechanism is enabled. */ bool -aarch64_bti_enabled (void) +aarch_bti_enabled (void) { return (aarch_enable_bti == 1); } +/* Check if INSN is a BTI J insn. */ +bool +aarch_bti_j_insn_p (rtx_insn *insn) +{ + if (!insn || !INSN_P (insn)) + return false; + + rtx pat = PATTERN (insn); + return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J; +} + +/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */ +bool +aarch_pac_insn_p (rtx x) +{ + if (!INSN_P (x)) + return false; + + subrtx_var_iterator::array_type array; + FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL) + { + rtx sub = *iter; + if (sub && GET_CODE (sub) == UNSPEC) + { + int unspec_val = XINT (sub, 1); + switch (unspec_val) + { + case UNSPEC_PACIASP: + case UNSPEC_PACIBSP: + return true; + + default: + return false; + } + iter.skip_subrtxes (); + } + } + return false; +} + +rtx aarch_gen_bti_c (void) +{ + return gen_bti_c (); +} + +rtx aarch_gen_bti_j (void) +{ + return gen_bti_j (); +} + /* The caller is going to use ST1D or LD1D to save or restore an SVE register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by: @@ -9918,7 +9968,7 @@ aarch64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, rtx_insn *insn; const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); - if (aarch64_bti_enabled ()) + if (aarch_bti_enabled ()) emit_insn (gen_bti_c()); reload_completed = 1; @@ -22360,7 +22410,7 @@ aarch64_print_patchable_function_entry (FILE *file, bool record_p) { if (cfun->machine->label_is_assembled - && aarch64_bti_enabled () + && aarch_bti_enabled () && !cgraph_node::get (cfun->decl)->only_called_directly_p ()) { /* Remove the BTI that follows the patch area and insert a new BTI @@ -26689,7 +26739,7 @@ aarch64_file_end_indicate_exec_stack () file_end_indicate_exec_stack (); unsigned feature_1_and = 0; - if (aarch64_bti_enabled ()) + if (aarch_bti_enabled ()) feature_1_and |= GNU_PROPERTY_AARCH64_FEATURE_1_BTI; if (aarch_ra_sign_scope != AARCH_FUNCTION_NONE) diff --git a/gcc/config/aarch64/t-aarch64 b/gcc/config/aarch64/t-aarch64 index 75b463d2f03..eb6ad3db955 100644 --- a/gcc/config/aarch64/t-aarch64 +++ b/gcc/config/aarch64/t-aarch64 @@ -149,14 +149,14 @@ falkor-tag-collision-avoidance.o: \ $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ $(srcdir)/config/aarch64/falkor-tag-collision-avoidance.cc -aarch64-bti-insert.o: $(srcdir)/config/aarch64/aarch64-bti-insert.cc \ +aarch-bti-insert.o: $(srcdir)/config/arm/aarch-bti-insert.cc \ $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \ dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \ output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \ $(CONTEXT_H) $(TREE_PASS_H) regrename.h \ $(srcdir)/config/aarch64/aarch64-protos.h $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ - $(srcdir)/config/aarch64/aarch64-bti-insert.cc + $(srcdir)/config/arm/aarch-bti-insert.cc aarch64-cc-fusion.o: $(srcdir)/config/aarch64/aarch64-cc-fusion.cc \ $(CONFIG_H) $(SYSTEM_H) $(CORETYPES_H) $(BACKEND_H) $(RTL_H) $(DF_H) \ diff --git a/gcc/config/aarch64/aarch64-bti-insert.cc b/gcc/config/arm/aarch-bti-insert.cc similarity index 80% rename from gcc/config/aarch64/aarch64-bti-insert.cc rename to gcc/config/arm/aarch-bti-insert.cc index 7caed310bbc..2d1d2e334a9 100644 --- a/gcc/config/aarch64/aarch64-bti-insert.cc +++ b/gcc/config/arm/aarch-bti-insert.cc @@ -42,10 +42,11 @@ #include "tree-pass.h" #include "cgraph.h" -/* This pass enables the support for Branch Target Identification Mechanism - for AArch64. This is a new security feature introduced in ARMv8.5-A - archtitecture. A BTI instruction is used to guard against the execution - of instructions which are not the intended target of an indirect branch. +/* This pass enables the support for Branch Target Identification Mechanism for + Arm/AArch64. This is a security feature introduced in ARMv8.5-A + architecture and ARMv8.1-M. A BTI instruction is used to guard against the + execution of instructions which are not the intended target of an indirect + branch. Outside of a guarded memory region, a BTI instruction executes as a NOP. Within a guarded memory region any target of an indirect branch must be @@ -53,7 +54,8 @@ branch is triggered in a non-guarded memory region). An incompatibility generates a Branch Target Exception. - The compatibility of the BTI instruction is as follows: + The compatibility of the BTI instruction is as follows (AArch64 + examples): BTI j : Can be a target of any indirect jump (BR Xn). BTI c : Can be a target of any indirect call (BLR Xn and BR X16/X17). BTI jc: Can be a target of any indirect call or indirect jump. @@ -90,47 +92,6 @@ const pass_data pass_data_insert_bti = 0, /* todo_flags_finish. */ }; -/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */ -static bool -aarch64_pac_insn_p (rtx x) -{ - if (!INSN_P (x)) - return false; - - subrtx_var_iterator::array_type array; - FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (x), ALL) - { - rtx sub = *iter; - if (sub && GET_CODE (sub) == UNSPEC) - { - int unspec_val = XINT (sub, 1); - switch (unspec_val) - { - case UNSPEC_PACIASP: - /* fall-through. */ - case UNSPEC_PACIBSP: - return true; - - default: - return false; - } - iter.skip_subrtxes (); - } - } - return false; -} - -/* Check if INSN is a BTI J insn. */ -static bool -aarch64_bti_j_insn_p (rtx_insn *insn) -{ - if (!insn || !INSN_P (insn)) - return false; - - rtx pat = PATTERN (insn); - return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J; -} - /* Insert the BTI instruction. */ /* This is implemented as a late RTL pass that runs before branch shortening and does the following. */ @@ -155,7 +116,7 @@ rest_of_insert_bti (void) && (LABEL_PRESERVE_P (insn) || bb->flags & BB_NON_LOCAL_GOTO_TARGET)) { - bti_insn = gen_bti_j (); + bti_insn = aarch_gen_bti_j (); emit_insn_after (bti_insn, insn); continue; } @@ -177,10 +138,10 @@ rest_of_insert_bti (void) { label = as_a (XEXP (RTVEC_ELT (vec, j), 0)); rtx_insn *next = next_nonnote_nondebug_insn (label); - if (aarch64_bti_j_insn_p (next)) + if (aarch_bti_j_insn_p (next)) continue; - bti_insn = gen_bti_j (); + bti_insn = aarch_gen_bti_j (); emit_insn_after (bti_insn, label); } } @@ -191,7 +152,7 @@ rest_of_insert_bti (void) will return. */ if (CALL_P (insn) && (find_reg_note (insn, REG_SETJMP, NULL))) { - bti_insn = gen_bti_j (); + bti_insn = aarch_gen_bti_j (); emit_insn_after (bti_insn, insn); continue; } @@ -207,9 +168,9 @@ rest_of_insert_bti (void) { bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb; insn = BB_HEAD (bb); - if (!aarch64_pac_insn_p (get_first_nonnote_insn ())) + if (!aarch_pac_insn_p (get_first_nonnote_insn ())) { - bti_insn = gen_bti_c (); + bti_insn = aarch_gen_bti_c (); emit_insn_before (bti_insn, insn); } } @@ -229,7 +190,7 @@ public: /* opt_pass methods: */ virtual bool gate (function *) { - return aarch64_bti_enabled (); + return aarch_bti_enabled (); } virtual unsigned int execute (function *) diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 17a369f7e99..374982752ad 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -42,6 +42,11 @@ extern int arm_no_early_alu_shift_value_dep (rtx, rtx); extern int arm_no_early_mul_dep (rtx, rtx); extern int arm_no_early_store_addr_dep (rtx, rtx); extern bool arm_rtx_shift_left_p (rtx); +extern bool aarch_bti_enabled (void); +extern bool aarch_bti_j_insn_p (rtx_insn *); +extern bool aarch_pac_insn_p (rtx); +extern rtx aarch_gen_bti_c (void); +extern rtx aarch_gen_bti_j (void); /* RTX cost table definitions. These are used when tuning for speed rather than for size and should reflect the _additional_ cost over the cost diff --git a/gcc/config/arm/arm-passes.def b/gcc/config/arm/arm-passes.def new file mode 100644 index 00000000000..beecd2b5455 --- /dev/null +++ b/gcc/config/arm/arm-passes.def @@ -0,0 +1,21 @@ +/* Arm-specific passes declarations. + Copyright (C) 2021 Free Software Foundation, Inc. + Contributed by Arm Ltd. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. 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This is achieved by using the bti pass made common with Aarch64. The pass iterates through the instructions and adds the necessary BTI instructions at the beginning of every function and at every landing pads targeted by indirect jumps. Best Regards Andrea [1] gcc/ChangeLog * config.gcc (arm*-*-*): Add 'aarch-bti-insert.o' object. * config/arm/arm-protos.h: Update. * config/arm/arm.cc (aarch_bti_enabled, aarch_bti_j_insn_p) (aarch_pac_insn_p, aarch_gen_bti_c, aarch_gen_bti_j): New functions. * config/arm/arm.md (bti_nop): New insn. * config/arm/t-arm (PASSES_EXTRA): Add 'arm-passes.def'. (aarch-bti-insert.o): New target. * config/arm/unspecs.md (UNSPEC_BTI_NOP): New unspec. gcc/testsuite/ChangeLog * gcc.target/arm/bti-1.c: New testcase. * gcc.target/arm/bti-2.c: Likewise. diff --git a/gcc/config.gcc b/gcc/config.gcc index 2021bdf9d2f..004e1dfa8d8 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -353,7 +353,7 @@ arc*-*-*) ;; arm*-*-*) cpu_type=arm - extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o" + extra_objs="arm-builtins.o arm-mve-builtins.o aarch-common.o aarch-bti-insert.o" extra_headers="mmintrin.h arm_neon.h arm_acle.h arm_fp16.h arm_cmse.h arm_bf16.h arm_mve_types.h arm_mve.h arm_cde.h" target_type_format_char='%' c_target_objs="arm-c.o" diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index cff7ff1da2a..da23e0a4735 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -24,6 +24,8 @@ #include "sbitmap.h" +rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt); + extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *); extern int use_return_insn (int, rtx); extern bool use_simple_return_p (void); diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index c91dae292c8..a2b720a6660 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -23361,11 +23361,6 @@ output_probe_stack_range (rtx reg1, rtx reg2) return ""; } -static bool aarch_bti_enabled () -{ - return false; -} - /* Generate the prologue instructions for entry into an ARM or Thumb-2 function. */ void @@ -32981,6 +32976,56 @@ arm_current_function_pac_enabled_p (void) && !crtl->is_leaf); } +/* Return TRUE if Branch Target Identification Mechanism is enabled. */ +bool +aarch_bti_enabled (void) +{ + return aarch_enable_bti == 1; +} + +/* Check if INSN is a BTI J insn. */ +bool +aarch_bti_j_insn_p (rtx_insn *insn) +{ + if (!insn || !INSN_P (insn)) + return false; + + rtx pat = PATTERN (insn); + return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPEC_BTI_NOP; +} + +/* Check if X (or any sub-rtx of X) is a PACIASP/PACIBSP instruction. */ +bool +aarch_pac_insn_p (rtx x) +{ + if (!x || !INSN_P (x)) + return false; + + rtx pat = PATTERN (x); + + if (GET_CODE (pat) == SET) + { + rtx tmp = XEXP (pat, 1); + if (tmp + && GET_CODE (tmp) == UNSPEC + && (XINT (tmp, 1) == UNSPEC_PAC_NOP + || XINT (tmp, 1) == UNSPEC_PACBTI_NOP)) + return true; + } + + return false; +} + +rtx aarch_gen_bti_c (void) +{ + return gen_bti_nop (); +} + +rtx aarch_gen_bti_j (void) +{ + return gen_bti_nop (); +} + /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be scheduled for speculative execution. Reject the long-running division and square-root instructions. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index b480f76a876..2221bc68f35 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12913,6 +12913,12 @@ "aut\t%|ip, %|lr, %|sp" [(set_attr "length" "2")]) +(define_insn "bti_nop" + [(unspec_volatile [(const_int 0)] UNSPEC_BTI_NOP)] + "TARGET_THUMB2" + "bti" + [(set_attr "type" "mov_reg")]) + ;; Vector bits common to IWMMXT, Neon and MVE (include "vec-common.md") ;; Load the Intel Wireless Multimedia Extension patterns diff --git a/gcc/config/arm/t-arm b/gcc/config/arm/t-arm index 041cc6ec045..683342cb528 100644 --- a/gcc/config/arm/t-arm +++ b/gcc/config/arm/t-arm @@ -175,3 +175,13 @@ arm-d.o: $(srcdir)/config/arm/arm-d.cc arm-common.o: arm-cpu-cdata.h driver-arm.o: arm-native.h + +PASSES_EXTRA += $(srcdir)/config/arm/arm-passes.def + +aarch-bti-insert.o: $(srcdir)/config/arm/aarch-bti-insert.cc \ + $(CONFIG_H) $(SYSTEM_H) $(TM_H) $(REGS_H) insn-config.h $(RTL_BASE_H) \ + dominance.h cfg.h cfganal.h $(BASIC_BLOCK_H) $(INSN_ATTR_H) $(RECOG_H) \ + output.h hash-map.h $(DF_H) $(OBSTACK_H) $(TARGET_H) $(RTL_H) \ + $(CONTEXT_H) $(TREE_PASS_H) regrename.h + $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \ + $(srcdir)/config/arm/aarch-bti-insert.cc diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index dbe243a03f6..78e723a4b3c 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -162,6 +162,7 @@ UNSPEC_PAC_NOP ; Represents PAC signing LR UNSPEC_PACBTI_NOP ; Represents PAC signing LR + valid landing pad UNSPEC_AUT_NOP ; Represents PAC verifying LR + UNSPEC_BTI_NOP ; Represent BTI ]) diff --git a/gcc/testsuite/gcc.target/arm/bti-1.c b/gcc/testsuite/gcc.target/arm/bti-1.c new file mode 100644 index 00000000000..230ebb5a1da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bti-1.c @@ -0,0 +1,12 @@ +/* Check that GCC does bti instruction. */ +/* { dg-do compile } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ +/* { dg-options "-march=armv8.1-m.main -mthumb -mbranch-protection=bti --save-temps" } */ + +int +main (void) +{ + return 0; +} + +/* { dg-final { scan-assembler "bti" } } */ diff --git a/gcc/testsuite/gcc.target/arm/bti-2.c b/gcc/testsuite/gcc.target/arm/bti-2.c new file mode 100644 index 00000000000..35aef6992e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/bti-2.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* -Os to create jump table. */ +/* { dg-options "-Os" } */ +/* { dg-skip-if "avoid conflicting multilib options" { *-*-* } { "-marm" "-mcpu=*" } } */ +/* { dg-options "-march=armv8.1-m.main -mthumb -mbranch-protection=bti --save-temps" } */ + +extern int f1 (void); +extern int f2 (void); +extern int f3 (void); +extern int f4 (void); +extern int f5 (void); +extern int f6 (void); +extern int f7 (void); +extern int f8 (void); +extern int f9 (void); +extern int f10 (void); + +int (*ptr) (void); + +int +f_jump_table (int y, int n) +{ + int i; + for (i = 0; i < n ;i ++) + { + switch (y) + { + case 0 : ptr = f1; break; + case 1 : ptr = f2; break; + case 2 : ptr = f3; break; + case 3 : ptr = f4; break; + case 4 : ptr = f5; break; + case 5 : ptr = f6; break; + case 6 : ptr = f7; break; + case 7 : ptr = f8; break; + case 8 : ptr = f9; break; + case 9 : ptr = f10; break; + default: break; + } + y += ptr (); + } + return (y == 0)? y+1:4; +} + +int +f_label_address () +{ + static void * addr = &&lab1; + goto *addr; +lab1: + addr = &&lab2; + return 1; +lab2: + addr = &&lab1; + return 2; +} + +/* { dg-final { scan-assembler-times "bti" 15 } } */