From patchwork Wed Apr 20 02:19:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: joshua X-Patchwork-Id: 53059 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3749F3857811 for ; Wed, 20 Apr 2022 02:20:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3749F3857811 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1650421235; bh=ulCSObp9D50VW/T9RzZ0M/8W7VJhGTwNIb8+yqUQDoY=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=GuyoxsZ/ThyY/mbs0SDFEu+mmXt9925WSreNDEYGLLLvaPnspUTkWf+PxjO+H3WH1 HATUthsq4kadXsWHu0ANdM079mwq3Ap3e3YDzEVxyJPI3DcbpLReOZafnB+gtRwlj5 YcpSOVmzFNMR/LuC/wbluAV/IgKFoeBcqEmdk7BU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-44.freemail.mail.aliyun.com (out30-44.freemail.mail.aliyun.com [115.124.30.44]) by sourceware.org (Postfix) with ESMTPS id 783AE3858D3C for ; Wed, 20 Apr 2022 02:20:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 783AE3858D3C X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=e01e04395; MF=cooper.joshua@linux.alibaba.com; NM=1; PH=DW; RN=3; SR=0; TI=W4_0.1.30_DEFAULT_21129326_1650421188789_o7001c110p; Received: from WS-web (cooper.joshua@linux.alibaba.com[W4_0.1.30_DEFAULT_21129326_1650421188789_o7001c110p]) by ay29a033018045209.et135 at Wed, 20 Apr 2022 10:19:48 +0800 Date: Wed, 20 Apr 2022 10:19:48 +0800 To: "Jim Wilson" , "gcc-patches" , "Kito Cheng" Message-ID: <647e1cb6-5382-43f9-b8d9-3a44977b67c0.cooper.joshua@linux.alibaba.com> Subject: =?utf-8?b?5Zue5aSN77yaW1BBVENIXSBBc2FuIGNoYW5nZXMgZm9yIFJJU0MtVi4=?= X-Mailer: [Alimail-Mailagent][W4_0.1.30][DEFAULT][Chrome] MIME-Version: 1.0 References: <20201028235817.17405-1-jimw@sifive.com> x-aliyun-mail-creator: W4_0.1.30_DEFAULT_M2ITW96aWxsYS81LjAgKFdpbmRvd3MgTlQgMTAuMDsgV2luNjQ7IHg2NCkgQXBwbGVXZWJLaXQvNTM3LjM2IChLSFRNTCwgbGlrZSBHZWNrbykgQ2hyb21lLzEwMC4wLjQ4OTYuNzUgU2FmYXJpLzUzNy4zNg==3L In-Reply-To: <20201028235817.17405-1-jimw@sifive.com> X-Spam-Status: No, score=-19.3 required=5.0 tests=BAYES_00, BODY_8BITS, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, HTML_MESSAGE, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: joshua via Gcc-patches From: joshua Reply-To: joshua Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Does Asan work for RISC-V currently? It seems that '-fsanitize=address' is still unsupported for RISC-V. If I add '--enable-libsanitizer' in Makefile.in to reconfigure, there are compiling errors. Is it because # libsanitizer not supported rv32, but it will break the rv64 multi-lib build, so we disable that temporally until rv32 supported# in Makefile.in? ------------------------------------------------------------------ 发件人：Jim Wilson 发送时间：2020年10月29日(星期四) 07:59 收件人：gcc-patches 抄　送：cooper.joshua ; Jim Wilson 主　题：[PATCH] Asan changes for RISC-V. We have only riscv64 asan support, there is no riscv32 support as yet. So I need to be able to conditionally enable asan support for the riscv target. I implemented this by returning zero from the asan_shadow_offset function. This requires a change to toplev.c and docs in target.def. The asan support works on a 5.5 kernel, but does not work on a 4.15 kernel. The problem is that the asan high memory region is a small wedge below 0x4000000000. The new kernel puts shared libraries at 0x3fffffffff and going down which works. But the old kernel puts shared libraries at 0x2000000000 and going up which does not work, as it isn't in any recognized memory region. This might be fixable with more asan work, but we don't really need support for old kernel versions. The asan port is curious in that it uses 1<<29 for the shadow offset, but all other 64-bit targets use a number larger than 1<<32. But what we have is working OK for now. I did a make check RUNTESTFLAGS="asan.exp" on Fedora rawhide image running on qemu and the results look reasonable. === gcc Summary === # of expected passes 1905 # of unexpected failures 11 # of unsupported tests 224 === g++ Summary === # of expected passes 2002 # of unexpected failures 6 # of unresolved testcases 1 # of unsupported tests 175 OK? Jim 2020-10-28 Jim Wilson gcc/ * config/riscv/riscv.c (riscv_asan_shadow_offset): New. (TARGET_ASAN_SHADOW_OFFSET): New. * doc/tm.texi: Regenerated. * target.def (asan_shadow_offset); Mention that it can return zero. * toplev.c (process_options): Check for and handle zero return from targetm.asan_shadow_offset call. Co-Authored-By: cooper.joshua --- gcc/config/riscv/riscv.c | 16 ++++++++++++++++ gcc/doc/tm.texi | 3 ++- gcc/target.def | 3 ++- gcc/toplev.c | 3 ++- 4 files changed, 22 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 989a9f15250..6909e200de1 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -5299,6 +5299,19 @@ riscv_gpr_save_operation_p (rtx op) return true; } +/* Implement TARGET_ASAN_SHADOW_OFFSET. */ + +static unsigned HOST_WIDE_INT +riscv_asan_shadow_offset (void) +{ + /* We only have libsanitizer support for RV64 at present. + + This number must match kRiscv*_ShadowOffset* in the file + libsanitizer/asan/asan_mapping.h which is currently 1<<29 for rv64, + even though 1<<36 makes more sense. */ + return TARGET_64BIT ? (HOST_WIDE_INT_1 << 29) : 0; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -5482,6 +5495,9 @@ riscv_gpr_save_operation_p (rtx op) #undef TARGET_NEW_ADDRESS_PROFITABLE_P #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p +#undef TARGET_ASAN_SHADOW_OFFSET +#define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 24c37f655c8..39c596b647a 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -12078,7 +12078,8 @@ is zero, which disables this optimization. @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_ASAN_SHADOW_OFFSET (void) Return the offset bitwise ored into shifted address to get corresponding Address Sanitizer shadow memory address. NULL if Address Sanitizer is not -supported by the target. +supported by the target. May return 0 if Address Sanitizer is not supported +by a subtarget. @end deftypefn @deftypefn {Target Hook} {unsigned HOST_WIDE_INT} TARGET_MEMMODEL_CHECK (unsigned HOST_WIDE_INT @var{val}) diff --git a/gcc/target.def b/gcc/target.def index ed2da154e30..268b56b6ebd 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -4452,7 +4452,8 @@ DEFHOOK (asan_shadow_offset, "Return the offset bitwise ored into shifted address to get corresponding\n\ Address Sanitizer shadow memory address. NULL if Address Sanitizer is not\n\ -supported by the target.", +supported by the target. May return 0 if Address Sanitizer is not supported\n\ +by a subtarget.", unsigned HOST_WIDE_INT, (void), NULL) diff --git a/gcc/toplev.c b/gcc/toplev.c index 20e231f4d2a..cf89598252c 100644 --- a/gcc/toplev.c +++ b/gcc/toplev.c @@ -1834,7 +1834,8 @@ process_options (void) } if ((flag_sanitize & SANITIZE_USER_ADDRESS) - && targetm.asan_shadow_offset == NULL) + && ((targetm.asan_shadow_offset == NULL) + || (targetm.asan_shadow_offset () == 0))) { warning_at (UNKNOWN_LOCATION, 0, "%<-fsanitize=address%> not supported for this target");