From patchwork Wed Apr 6 12:38:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 52672 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D1F06385DC31 for ; Wed, 6 Apr 2022 12:38:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D1F06385DC31 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1649248722; bh=4Mhz9Tt25xp/nd91UoUlWT4OQJGq3OaCkjEtkM0BL8w=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=hhKNplhTVWpodux2R6FeJuaGdJh+EgAZip6QOlV2QLbOZEItaumcN/a/nOe7Vob2G BsN0GjUzsfG4Mv8Y5EXrLunj2gWtk3V+w9/HL41Yru7Fjm+TH7jy/5bC1aB4f3WF7k zQBIMyzQ4VrfV1WggoyB1ontyaGVvdwQ8pT/pE4E= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mengyan1223.wang (mengyan1223.wang [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id E27B6385840C; Wed, 6 Apr 2022 12:38:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E27B6385840C Received: from [IPv6:240e:358:1198:7700:dc73:854d:832e:4] (unknown [IPv6:240e:358:1198:7700:dc73:854d:832e:4]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384)) (Client did not present a certificate) (Authenticated sender: xry111@mengyan1223.wang) by mengyan1223.wang (Postfix) with ESMTPSA id CE97D6624C; Wed, 6 Apr 2022 08:38:09 -0400 (EDT) Message-ID: Subject: mips: Use c.ngl instead of c.ueq for LTGT [PR 91323] To: gcc-patches@gcc.gnu.org Date: Wed, 06 Apr 2022 20:38:06 +0800 User-Agent: Evolution 3.44.0 MIME-Version: 1.0 X-Spam-Status: No, score=-3038.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Cc: Richard Sandiford , Jakub Jelinek , YunQiang Su Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Fixes gcc.dg/torture/pr91323.c fail for MIPS. Ok for trunk? LTGT should trap for unordered operands (see discussion in bugzilla), but c.ueq does not trap for qNaN. Use c.ngl as it handles non-NaN operands like c.ueq, but traps for qNaN as we want for LTGT. gcc/ PR target/91323 * config/mips/mips.md (sngl__using_cc): New insn pattern for c.ngl.{f,d}. * config/mips/mips.cc (mips_emit_compare): Use c.ngl.{f,d} for LTGT. --- gcc/config/mips/mips.cc | 38 +++++++++++++++++++++++++++++++++----- gcc/config/mips/mips.md | 10 ++++++++++ 2 files changed, 43 insertions(+), 5 deletions(-) diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc index 5010f99f761..77675a57a01 100644 --- a/gcc/config/mips/mips.cc +++ b/gcc/config/mips/mips.cc @@ -5625,6 +5625,7 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) } else { + bool need_ngl = false; enum rtx_code cmp_code; /* Floating-point tests use a separate C.cond.fmt or CMP.cond.fmt @@ -5643,10 +5644,20 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) } else { - /* Three FP conditions cannot be implemented by reversing the - operands for C.cond.fmt, instead a reversed condition code is - required and a test for false. */ - *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE; + /* We'll need a special case. LTGT is not an unordered compare + (PR 91323) so we can't simply use !UNEQ for it. MIPS has + "ngl" (Not Greater than or Less than) condition as a perfect + opposite of LTGT, but we don't have an rtx_code for it. */ + if (cmp_code == LTGT) + { + need_ngl = true; + *code = EQ; + } + else + /* Three FP conditions cannot be implemented by reversing the + operands for C.cond.fmt, instead a reversed condition code + is required and a test for false. */ + *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE; if (ISA_HAS_8CC) *op0 = mips_allocate_fcc (CCmode); else @@ -5654,7 +5665,24 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) } *op1 = const0_rtx; - mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1); + if (need_ngl) + { + rtx insn; + switch (GET_MODE (cmp_op0)) + { + case SFmode: + insn = gen_sngl_sf_using_cc (*op0, cmp_op0, cmp_op1); + break; + case DFmode: + insn = gen_sngl_df_using_cc (*op0, cmp_op0, cmp_op1); + break; + default: + gcc_unreachable (); + } + emit_insn(insn); + } + else + mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1); } } diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e0f0a582732..47405f03d7a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -6293,6 +6293,16 @@ (define_insn "s__using_" "..\t%Z0%2,%1" [(set_attr "type" "fcmp") (set_attr "mode" "FPSW")]) + +(define_insn "sngl__using_cc" + [(set (match_operand:CC 0 "register_operand" "=z") + (eq:CC (const_int 0) + (ltgt:CC (match_operand:SCALARF 1 "register_operand" "f") + (match_operand:SCALARF 2 "register_operand" "f"))))] + "!ISA_HAS_CCF" + "c.ngl.\t%Z0%1,%2" + [(set_attr "type" "fcmp") + (set_attr "mode" "FPSW")]) ;; ;; ....................