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(Coremail) with SMTP id zQCowACn30FlfiFiZUgYAg--.62793S3; Fri, 04 Mar 2022 10:50:31 +0800 (CST) From: yulong@nj.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/3] RISC-V: Add mininal support for Zicbo[mzp] Date: Fri, 4 Mar 2022 10:49:53 +0800 Message-Id: <20220304024955.25201-2-yulong@nj.iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> References: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> X-CM-TRANSID: zQCowACn30FlfiFiZUgYAg--.62793S3 X-Coremail-Antispam: 1UD129KBjvJXoWxJFy5ZF1UJrWrXF43tw4DCFg_yoW5CF18pF W8WwsxZ34FqFsxWw4xtr18Ga45A3ZYgr1fGF48ur1UAayDX3y8AFn09w13ZrWkXFs8Zrn2 v3Wj9w1Y9w4UCFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 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T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cmuellner@ventanamicro.com, ptomsich@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, kito.cheng@gmail.com, jiawei@iscas.ac.cn, research_trasio@irq.a4lg.com, wuwei2016@iscas.ac.cn, yulong-plct , shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong-plct This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions. 7 8 gcc/ChangeLog: 9 10 * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. 11 * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. 12 (MASK_ZICBOM): New. 13 (MASK_ZICBOP): New. 14 (TARGET_ZICBOZ): New. 15 (TARGET_ZICBOM): New. 16 (TARGET_ZICBOP): New. 17 * config/riscv/riscv.opt: New. --- gcc/common/config/riscv/riscv-common.cc | 6 ++++++ gcc/config/riscv/riscv-opts.h | 9 +++++++++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 18 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index a904893b9ed..3ba8f240977 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -164,6 +164,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zksed", ISA_SPEC_CLASS_NONE, 1, 0}, {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0}, {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1049,6 +1052,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zksed", &gcc_options::x_riscv_zk_subext, MASK_ZKSED}, {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, + {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, + {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 929e4e3a7c5..d17cf6ea18a 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,6 +83,15 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZICBOZ (1 << 0) +#define MASK_ZICBOM (1 << 1) +#define MASK_ZICBOP (1 << 2) + + +#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0) +#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) +#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) + #define MASK_ZBKB (1 << 0) #define MASK_ZBKC (1 << 1) #define MASK_ZBKX (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 9fffc08220d..2058a874d31 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -200,6 +200,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zicmo_subext + TargetVariable int riscv_zk_subext From patchwork Fri Mar 4 02:49:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong@nj.iscas.ac.cn X-Patchwork-Id: 51543 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6F6633858012 for ; Fri, 4 Mar 2022 02:51:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 24D88385803D for ; Fri, 4 Mar 2022 02:50:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 24D88385803D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nj.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=nj.iscas.ac.cn Received: from localhost.localdomain (unknown [47.88.16.30]) by APP-05 (Coremail) with SMTP id zQCowACn30FlfiFiZUgYAg--.62793S4; Fri, 04 Mar 2022 10:50:34 +0800 (CST) From: yulong@nj.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/3] RISC-V:Cache Management Operation instructions Date: Fri, 4 Mar 2022 10:49:54 +0800 Message-Id: <20220304024955.25201-3-yulong@nj.iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> References: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> X-CM-TRANSID: zQCowACn30FlfiFiZUgYAg--.62793S4 X-Coremail-Antispam: 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Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong-plct This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions. 7 8 gcc/ChangeLog: 9 10 * config/riscv/predicates.md (imm5_operand): Add a new operand type for prefetch instructions. 11 * config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA Extensions. 12 (RISCV_ATYPE_SI): New. 13 (RISCV_ATYPE_DI): New. 14 * config/riscv/riscv-ftypes.def (0): New. 15 (1): New. 16 * config/riscv/riscv.md (riscv_clean_): Add a new mode for cbo.clean instruction. 17 (riscv_flush_): Add a new mode for cbo.flush instruction. 18 (riscv_inval_): Add a new mode for cbo.inval instruction. 19 (riscv_zero_): Add a new mode for cbo.zero instruction. 20 (prefetch): Add a new mode for prefetch.r and prefetch.w instructions. 21 (riscv_prefetchi_): Add a new mode for prefetch.i instruction. 22 * config/riscv/riscv-cmo.def: New file. --- gcc/config/riscv/predicates.md | 4 +++ gcc/config/riscv/riscv-builtins.cc | 16 +++++++++ gcc/config/riscv/riscv-cmo.def | 17 ++++++++++ gcc/config/riscv/riscv-ftypes.def | 4 +++ gcc/config/riscv/riscv.md | 52 ++++++++++++++++++++++++++++++ 5 files changed, 93 insertions(+) create mode 100644 gcc/config/riscv/riscv-cmo.def diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 97cdbdf053b..3fb4d95ab08 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -239,3 +239,7 @@ (define_predicate "const63_operand" (and (match_code "const_int") (match_test "INTVAL (op) == 63"))) + +(define_predicate "imm5_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) < 5"))) \ No newline at end of file diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 0658f8d3047..795132a0c16 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -87,6 +87,18 @@ struct riscv_builtin_description { AVAIL (hard_float, TARGET_HARD_FLOAT) + +AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT) +AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT) +AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) +AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) +AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) +AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) + /* Construct a riscv_builtin_description from the given arguments. INSN is the name of the associated instruction pattern, without the @@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) /* Argument types. */ #define RISCV_ATYPE_VOID void_type_node #define RISCV_ATYPE_USI unsigned_intSI_type_node +#define RISCV_ATYPE_SI intSI_type_node +#define RISCV_ATYPE_DI intDI_type_node /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists their associated RISCV_ATYPEs. */ @@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) RISCV_ATYPE_##A, RISCV_ATYPE_##B static const struct riscv_builtin_description riscv_builtins[] = { + #include "riscv-cmo.def" + DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float) }; diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def new file mode 100644 index 00000000000..8829a1d664d --- /dev/null +++ b/gcc/config/riscv/riscv-cmo.def @@ -0,0 +1,17 @@ +// zicbom +RISCV_BUILTIN (clean_si, "clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32), +RISCV_BUILTIN (clean_di, "clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64), + +RISCV_BUILTIN (flush_si, "flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32), +RISCV_BUILTIN (flush_di, "flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64), + +RISCV_BUILTIN (inval_si, "inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32), +RISCV_BUILTIN (inval_di, "inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64), + +// zicboz +RISCV_BUILTIN (zero_si, "zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32), +RISCV_BUILTIN (zero_di, "zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64), + +// zicbop +RISCV_BUILTIN (prefetchi_si, "prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32), +RISCV_BUILTIN (prefetchi_di, "prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64), \ No newline at end of file diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def index 2214c496f9b..62421292ce7 100644 --- a/gcc/config/riscv/riscv-ftypes.def +++ b/gcc/config/riscv/riscv-ftypes.def @@ -28,3 +28,7 @@ along with GCC; see the file COPYING3. If not see DEF_RISCV_FTYPE (0, (USI)) DEF_RISCV_FTYPE (1, (VOID, USI)) +DEF_RISCV_FTYPE (0, (SI)) +DEF_RISCV_FTYPE (0, (DI)) +DEF_RISCV_FTYPE (1, (SI, SI)) +DEF_RISCV_FTYPE (1, (DI, DI)) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index b3c5bce842a..43ad6e5a481 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -45,6 +45,11 @@ ;; Stack tie UNSPEC_TIE + UNSPEC_CLEAN + UNSPEC_FLUSH + UNSPEC_INVAL + UNSPEC_ZERO + UNSPEC_PREI ]) (define_c_enum "unspecv" [ @@ -69,6 +74,7 @@ ;; Stack Smash Protector UNSPEC_SSP_SET UNSPEC_SSP_TEST + ]) (define_constants @@ -2863,6 +2869,52 @@ "\t%3, %1\;\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" [(set_attr "length" "12")]) +(define_insn "riscv_clean_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_CLEAN)] +"TARGET_ZICBOM" +"cbo.clean\t%0" +) + +(define_insn "riscv_flush_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_FLUSH)] +"TARGET_ZICBOM" +"cbo.flush\t%0" +) + +(define_insn "riscv_inval_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_INVAL)] +"TARGET_ZICBOM" +"cbo.inval\t%0" +) + +(define_insn "riscv_zero_" +[(unspec:X [(match_operand:X 0 "register_operand" "r")] UNSPEC_ZERO)] +"TARGET_ZICBOZ" +"cbo.zero\t%0" +) + +(define_insn "prefetch" +[(prefetch (match_operand 0 "address_operand" "p") + (match_operand 1 "imm5_operand" "i") + (match_operand 2 "const_int_operand" "n"))] +"TARGET_ZICBOP" +{ + switch (INTVAL (operands[1])) + { + case 0: return "prefetch.r\t%a0"; + case 1: return "prefetch.w\t%a0"; + default: gcc_unreachable (); + } +}) + +(define_insn "riscv_prefetchi_" +[(unspec:X [(match_operand:X 0 "address_operand" "p") + (match_operand:X 1 "imm5_operand" "i")] + UNSPEC_PREI)] +"TARGET_ZICBOP" +"prefetch.i\t%0" +) + (include "bitmanip.md") (include "sync.md") (include "peephole.md") From patchwork Fri Mar 4 02:49:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: yulong@nj.iscas.ac.cn X-Patchwork-Id: 51544 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 86CCA3858C20 for ; Fri, 4 Mar 2022 02:52:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id 849903857C6A for ; Fri, 4 Mar 2022 02:50:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 849903857C6A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nj.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=nj.iscas.ac.cn Received: from localhost.localdomain (unknown [47.88.16.30]) by APP-05 (Coremail) with SMTP id zQCowACn30FlfiFiZUgYAg--.62793S5; Fri, 04 Mar 2022 10:50:38 +0800 (CST) From: yulong@nj.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 3/3] RISC-V:Cache Management Operation instructions testcases Date: Fri, 4 Mar 2022 10:49:55 +0800 Message-Id: <20220304024955.25201-4-yulong@nj.iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> References: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> X-CM-TRANSID: zQCowACn30FlfiFiZUgYAg--.62793S5 X-Coremail-Antispam: 1UD129KBjvJXoW3Jw1rAr4UKry3GrW3CrykKrg_yoW7ur15pw s7Gw4FvrWrJF97GrWfKF1UJwsIvrs2gry5u397CryUZrs3trZFq3Z7tFW7Jr45JF1UJryf uanrua1ru3WYqw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQ014x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7M4kE6xkIj40Ew7xC0wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8 JwCFI7km07C267AKxVWUXVWUAwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14 v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY 67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI 8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v2 6r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUOOJ5UUUUU X-Originating-IP: [47.88.16.30] X-CM-SenderInfo: p1xo00fj6qyh5lvft2wodfhubq/ X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, KHOP_HELO_FCRDNS, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cmuellner@ventanamicro.com, ptomsich@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, kito.cheng@gmail.com, jiawei@iscas.ac.cn, research_trasio@irq.a4lg.com, wuwei2016@iscas.ac.cn, yulong-plct , shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong-plct This commit adds testcases about CMO instructions. 7 8 gcc/testsuite/ChangeLog: 9 10 * gcc.target/riscv/cmo-zicbom-1.c: New test. 11 * gcc.target/riscv/cmo-zicbom-2.c: New test. 12 * gcc.target/riscv/cmo-zicbop-1.c: New test. 13 * gcc.target/riscv/cmo-zicbop-2.c: New test. 14 * gcc.target/riscv/cmo-zicboz-1.c: New test. 15 * gcc.target/riscv/cmo-zicboz-2.c: New test. --- gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 ++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 ++++++++ 6 files changed, 106 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c new file mode 100644 index 00000000000..16935ff3d31 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */ + +int foo1() +{ + return __builtin_riscv_clean(); +} + +int foo2() +{ + return __builtin_riscv_flush(); +} + +int foo3() +{ + return __builtin_riscv_inval(); +} + +/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c new file mode 100644 index 00000000000..fc14f2b9c2b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zicbom -mabi=ilp32" } */ + +int foo1() +{ + return __builtin_riscv_clean(); +} + +int foo2() +{ + return __builtin_riscv_flush(); +} + +int foo3() +{ + return __builtin_riscv_inval(); +} + +/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c new file mode 100644 index 00000000000..b8bac2e8c51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile target { { rv64-*-*}}} */ +/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ + +void foo (char *p) +{ + __builtin_prefetch (p, 0, 0); + __builtin_prefetch (p, 0, 1); + __builtin_prefetch (p, 0, 2); + __builtin_prefetch (p, 0, 3); + __builtin_prefetch (p, 1, 0); + __builtin_prefetch (p, 1, 1); + __builtin_prefetch (p, 1, 2); + __builtin_prefetch (p, 1, 3); +} + +int foo1() +{ + return __builtin_riscv_prefetchi(1); +} + +/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c new file mode 100644 index 00000000000..5ace6e2b349 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile target { { rv32-*-*}}} */ +/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */ + +void foo (char *p) +{ + __builtin_prefetch (p, 0, 0); + __builtin_prefetch (p, 0, 1); + __builtin_prefetch (p, 0, 2); + __builtin_prefetch (p, 0, 3); + __builtin_prefetch (p, 1, 0); + __builtin_prefetch (p, 1, 1); + __builtin_prefetch (p, 1, 2); + __builtin_prefetch (p, 1, 3); +} + +int foo1() +{ + return __builtin_riscv_prefetchi(1); +} + +/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c new file mode 100644 index 00000000000..c2401fe0cf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicboz -mabi=lp64" } */ + +int foo1() +{ + return __builtin_riscv_zero(); +} + +/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c new file mode 100644 index 00000000000..98fb3bf978a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zicboz -mabi=ilp32" } */ + +int foo1() +{ + return __builtin_riscv_zero(); +} + +/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */ \ No newline at end of file