From patchwork Sun Feb 27 08:45:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 51408 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C6B5F3858022 for ; Sun, 27 Feb 2022 08:46:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 159843858D35 for ; Sun, 27 Feb 2022 08:46:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 159843858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:To:From:Sender:Reply-To:Cc:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=mVsdBXKg/GithbBYfQ/e5RilJ8IIbAYgpwhmiHSn2fg=; b=GN7aDubd6FbYAJho+Mnk8esoir YV7JZJk8chOvu/mZHBwDkXNV6LJVZS5RzJlUtZlT/rxckICxrIEnFBPOAObkbIXrTG7LLNidzEuNs JYN3Zl0ytskOBhNaKmnaJ3g7TEemDoJ2hYZMSnupX70t7iK8C44WNGd0iJX4Bi8/JYzz4ZWYoPV6r UQyaZRvDjJCvWEQOiFWfX8hUAtuGPz5sJBXByhwryDzd7cEM5nc4OGjmvXYx9Sm06G8hSecdHXOf5 4zBaaP0fwRdNFAO00s2RCNExgXt6tr0zx3SYbeyFaBULCcuOzwCKE9+xjcSGV03uY+EIR0TCS4J4D jkDuc3nA==; Received: from host86-186-213-42.range86-186.btcentralplus.com ([86.186.213.42]:58366 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nOFBo-0006qA-FK for gcc-patches@gcc.gnu.org; Sun, 27 Feb 2022 03:46:00 -0500 From: "Roger Sayle" To: Subject: [PATCH] PR middle-end/80270: ICE in extract_bit_field_1 Date: Sun, 27 Feb 2022 08:45:57 -0000 Message-ID: <012701d82bb6$71834460$5489cd20$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdgrtffJeEUg9ELqSRWA9YOleUIc3A== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_FMBLA_NEWDOM, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch fixes PR middle-end/80270, an ICE-on-valid regression, where performing a bitfield extraction on a variable explicitly stored in a hard register by the user causes a segmentation fault during RTL expansion. Nearly identical source code without the "asm" qualifier compiles fine. The point of divergence is in simplify_gen_subreg which tries to avoid creating non-trivial SUBREGs of hard registers, to avoid problems during register allocation. This suggests the simple solution proposed here, to copy hard registers to a new pseudo in extract_integral_bit_field, just before calling simplify_gen_subreg. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check with no new failures. Ok for mainline? 2022-02-27 Roger Sayle gcc/ChangeLog PR middle-end/80270 * expmed.cc (extract_integral_bit_field): If OP0 is a hard register, copy it to a pseudo before calling simplify_gen_subreg. gcc/testsuite/ChangeLog * gcc.target/i386/pr80270.c: New test case. Thanks in advance, Roger diff --git a/gcc/expmed.cc b/gcc/expmed.cc index 80a16ce..b51450d 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -1975,6 +1975,14 @@ extract_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode, unsignedp, reverse); return convert_extracted_bit_field (target, mode, tmode, unsignedp); } + /* If OP0 is a hard register, copy it to a pseudo before calling + simplify_gen_subreg. */ + if (REG_P (op0) && HARD_REGISTER_P (op0)) + { + rtx tmp = gen_reg_rtx (GET_MODE (op0)); + emit_move_insn (tmp, op0); + op0 = tmp; + } op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (), bitnum / BITS_PER_WORD * UNITS_PER_WORD); op0_mode = word_mode; diff --git a/gcc/testsuite/gcc.target/i386/pr80270.c b/gcc/testsuite/gcc.target/i386/pr80270.c new file mode 100644 index 0000000..89e9c33 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80270.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse" } */ + +typedef int v8 __attribute__((vector_size(8))); +struct S1 { + v8 s1f; +}; +struct S2 { + struct S1 s2f1; + v8 s2f2; +}; + +extern void foo(int); + +void bar() { + int tmp, i = 3; + register struct S2 b asm("xmm0"); + tmp = b.s2f1.s1f[i]; + foo(tmp); +} +