From patchwork Wed Feb 23 11:40:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tom de Vries X-Patchwork-Id: 51332 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 422063948A49 for ; Wed, 23 Feb 2022 11:41:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 422063948A49 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1645616468; bh=XCWbW31K6LYN1QUWweZoAFr2NsA3KBmUQg/pl0wGhvY=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=xkgtHj0CPtrKbgsP05erNfvAOt2cex9+MEJv06A0Wj94j6bEQO0GcStB2Y93Re2Ui OiolY1wc3S+3m1paj5SpibIFK4mA9AouOjROl1emObFrVR9bxDpBW26thzF1Z4klSK vqqeSvQ1xldevxheGNrbLX+oREZWFyFhIAeNergo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.220.29]) by sourceware.org (Postfix) with ESMTPS id 2AC4A385BF81 for ; Wed, 23 Feb 2022 11:40:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2AC4A385BF81 Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 1BA3B1F3A3 for ; Wed, 23 Feb 2022 11:40:38 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 0958A13C75 for ; Wed, 23 Feb 2022 11:40:38 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id 7Is5ATYdFmJqbQAAMHmgww (envelope-from ) for ; Wed, 23 Feb 2022 11:40:38 +0000 Date: Wed, 23 Feb 2022 12:40:36 +0100 To: gcc-patches@gcc.gnu.org Subject: [PATCH][nvptx] Add shf.{l,r}.wrap insn Message-ID: <20220223114035.GA7222@delia.home> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tom de Vries via Gcc-patches From: Tom de Vries Reply-To: Tom de Vries Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, Ptx contains funnel shift operations shf.l.wrap and shf.r.wrap that can be used to implement 32-bit left or right rotate. Add define_insns rotlsi3 and rotrsi3. Currently testing. Thanks, - Tom [nvptx] Add shf.{l,r}.wrap insn gcc/ChangeLog: 2022-02-23 Tom de Vries * config/nvptx/nvptx.md (define_insn "rotlsi3", define_insn "rotrsi3"): New define_insn. gcc/testsuite/ChangeLog: 2022-02-23 Tom de Vries * gcc.target/nvptx/rotate-run.c: New test. * gcc.target/nvptx/rotate.c: New test. --- gcc/config/nvptx/nvptx.md | 16 ++++++++++++++++ gcc/testsuite/gcc.target/nvptx/rotate-run.c | 23 +++++++++++++++++++++++ gcc/testsuite/gcc.target/nvptx/rotate.c | 20 ++++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index 216e89f230ac..4989b5642e29 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -808,6 +808,22 @@ "" "%.\\tshr.u%T0\\t%0, %1, %2;") +(define_insn "rotlsi3" + [(set (match_operand:SI 0 "nvptx_register_operand" "=R") + (rotate:SI (match_operand:SI 1 "nvptx_register_operand" "R") + (and:SI (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri") + (const_int 31))))] + "TARGET_SM35" + "%.\\tshf.l.wrap.b32\\t%0, %1, %1, %2;") + +(define_insn "rotrsi3" + [(set (match_operand:SI 0 "nvptx_register_operand" "=R") + (rotatert:SI (match_operand:SI 1 "nvptx_register_operand" "R") + (and:SI (match_operand:SI 2 "nvptx_nonmemory_operand" "Ri") + (const_int 31))))] + "TARGET_SM35" + "%.\\tshf.r.wrap.b32\\t%0, %1, %1, %2;") + ;; Logical operations (define_code_iterator any_logic [and ior xor]) diff --git a/gcc/testsuite/gcc.target/nvptx/rotate-run.c b/gcc/testsuite/gcc.target/nvptx/rotate-run.c new file mode 100644 index 000000000000..14cb6f8b0b3f --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/rotate-run.c @@ -0,0 +1,23 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include "rotate.c" + +#define ASSERT(EXPR) \ + do \ + { \ + if (!(EXPR)) \ + __builtin_abort (); \ + } while (0) + +int +main (void) +{ + ASSERT (rotl (0x12345678, 8) == 0x34567812); + ASSERT (rotl (0x12345678, 8 + 32) == 0x34567812); + + ASSERT (rotr (0x12345678, 8) == 0x78123456); + ASSERT (rotr (0x12345678, 8 + 32) == 0x78123456); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/nvptx/rotate.c b/gcc/testsuite/gcc.target/nvptx/rotate.c new file mode 100644 index 000000000000..1c9b83b4809d --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/rotate.c @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -save-temps" } */ + +#define MASK 0x1f + +unsigned int +rotl (unsigned int val, unsigned int cnt) { + cnt &= MASK; + return (val << cnt) | (val >> (-cnt & MASK)); +} + +unsigned int +rotr (unsigned int val, unsigned int cnt) { + cnt &= MASK; + return (val >> cnt) | (val << (-cnt & MASK)); +} + +/* { dg-final { scan-assembler-times "shf.l.wrap.b32" 1 } } */ +/* { dg-final { scan-assembler-times "shf.r.wrap.b32" 1 } } */ +/* { dg-final { scan-assembler-not "and.b32" } } */