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Tue, 22 Feb 2022 02:47:49 +0000 (GMT) To: GCC Patches Subject: [PATCH] rs6000: Fix some issues related to Power10 fusion [PR104024] Message-ID: <7d52f901-8d59-1948-421f-680ba8b4cfce@linux.ibm.com> Date: Tue, 22 Feb 2022 10:47:45 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4OHdzKFrAog33fSTxbpMNJ-XySGFeK_M X-Proofpoint-ORIG-GUID: fNWkb-t0f05Ddy2d1XwAP_DgrxShTMHK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-21_11,2022-02-21_02,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 impostorscore=0 adultscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2202220013 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Cc: Peter Bergner , Bill Schmidt , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, As PR104024 shows, currently the option -mpower10-fusion isn't guarded under -mcpu=power10, so compiler can optimize some patterns unexpectedly. As the option is undocumented, this patch just simply unmasks it. For some define_insns in fusion.md which have constraint v, they don't have the correct conditions there, it can cause ICEs if the modes are not supported there. Besides, it seems better to use BOOL_128 instead of VM since the patterns are vector logical operations. Bootstrapped and regtested on powerpc64-linux-gnu P8 and powerpc64le-linux-gnu P9 and P10. Is it ok for trunk? BR, Kewen ----- PR target/104024 gcc/ChangeLog: * config/rs6000/fusion.md: Regenerate. * config/rs6000/genfusion.pl: Add the check for define_insns with constraint v, use BOOL_128 instead of VM. gcc/testsuite/ChangeLog: * gcc.target/powerpc/pr104024-1.c: New test. * gcc.target/powerpc/pr104024-2.c: New test. --- gcc/config/rs6000/fusion.md | 770 +++++++++--------- gcc/config/rs6000/genfusion.pl | 14 +- gcc/config/rs6000/rs6000.cc | 11 +- gcc/testsuite/gcc.target/powerpc/pr104024-1.c | 16 + gcc/testsuite/gcc.target/powerpc/pr104024-2.c | 18 + 5 files changed, 434 insertions(+), 395 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr104024-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr104024-2.c diff --git a/gcc/config/rs6000/fusion.md b/gcc/config/rs6000/fusion.md index 15f0c16f705..11cc3cb0e8e 100644 --- a/gcc/config/rs6000/fusion.md +++ b/gcc/config/rs6000/fusion.md @@ -1870,12 +1870,12 @@ (define_insn "*fuse_or_rsubf" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vand (define_insn "*fuse_vand_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vand %3,%3,%2 vand %3,%1,%0\;vand %3,%3,%2 @@ -1888,12 +1888,12 @@ (define_insn "*fuse_vand_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vand (define_insn "*fuse_vandc_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vand %3,%3,%2 vandc %3,%1,%0\;vand %3,%3,%2 @@ -1906,12 +1906,12 @@ (define_insn "*fuse_vandc_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vand (define_insn "*fuse_veqv_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vand %3,%3,%2 veqv %3,%1,%0\;vand %3,%3,%2 @@ -1924,12 +1924,12 @@ (define_insn "*fuse_veqv_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vand (define_insn "*fuse_vnand_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vand %3,%3,%2 vnand %3,%1,%0\;vand %3,%3,%2 @@ -1942,12 +1942,12 @@ (define_insn "*fuse_vnand_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vand (define_insn "*fuse_vnor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vand %3,%3,%2 vnor %3,%1,%0\;vand %3,%3,%2 @@ -1960,12 +1960,12 @@ (define_insn "*fuse_vnor_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vand (define_insn "*fuse_vor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vand %3,%3,%2 vor %3,%1,%0\;vand %3,%3,%2 @@ -1978,12 +1978,12 @@ (define_insn "*fuse_vor_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vand (define_insn "*fuse_vorc_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vand %3,%3,%2 vorc %3,%1,%0\;vand %3,%3,%2 @@ -1996,12 +1996,12 @@ (define_insn "*fuse_vorc_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vand (define_insn "*fuse_vxor_vand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vand %3,%3,%2 vxor %3,%1,%0\;vand %3,%3,%2 @@ -2014,12 +2014,12 @@ (define_insn "*fuse_vxor_vand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vandc (define_insn "*fuse_vand_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vandc %3,%3,%2 vand %3,%1,%0\;vandc %3,%3,%2 @@ -2032,12 +2032,12 @@ (define_insn "*fuse_vand_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vandc (define_insn "*fuse_vandc_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vandc %3,%3,%2 vandc %3,%1,%0\;vandc %3,%3,%2 @@ -2050,12 +2050,12 @@ (define_insn "*fuse_vandc_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vandc (define_insn "*fuse_veqv_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vandc %3,%3,%2 veqv %3,%1,%0\;vandc %3,%3,%2 @@ -2068,12 +2068,12 @@ (define_insn "*fuse_veqv_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vandc (define_insn "*fuse_vnand_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vandc %3,%3,%2 vnand %3,%1,%0\;vandc %3,%3,%2 @@ -2086,12 +2086,12 @@ (define_insn "*fuse_vnand_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vandc (define_insn "*fuse_vnor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vandc %3,%3,%2 vnor %3,%1,%0\;vandc %3,%3,%2 @@ -2104,12 +2104,12 @@ (define_insn "*fuse_vnor_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vandc (define_insn "*fuse_vor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vandc %3,%3,%2 vor %3,%1,%0\;vandc %3,%3,%2 @@ -2122,12 +2122,12 @@ (define_insn "*fuse_vor_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vandc (define_insn "*fuse_vorc_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vandc %3,%3,%2 vorc %3,%1,%0\;vandc %3,%3,%2 @@ -2140,12 +2140,12 @@ (define_insn "*fuse_vorc_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vandc (define_insn "*fuse_vxor_vandc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vandc %3,%3,%2 vxor %3,%1,%0\;vandc %3,%3,%2 @@ -2158,12 +2158,12 @@ (define_insn "*fuse_vxor_vandc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> veqv (define_insn "*fuse_vand_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;veqv %3,%3,%2 vand %3,%1,%0\;veqv %3,%3,%2 @@ -2176,12 +2176,12 @@ (define_insn "*fuse_vand_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> veqv (define_insn "*fuse_vandc_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;veqv %3,%3,%2 vandc %3,%1,%0\;veqv %3,%3,%2 @@ -2194,12 +2194,12 @@ (define_insn "*fuse_vandc_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> veqv (define_insn "*fuse_veqv_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "%v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;veqv %3,%3,%2 veqv %3,%1,%0\;veqv %3,%3,%2 @@ -2212,12 +2212,12 @@ (define_insn "*fuse_veqv_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> veqv (define_insn "*fuse_vnand_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;veqv %3,%3,%2 vnand %3,%1,%0\;veqv %3,%3,%2 @@ -2230,12 +2230,12 @@ (define_insn "*fuse_vnand_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> veqv (define_insn "*fuse_vnor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;veqv %3,%3,%2 vnor %3,%1,%0\;veqv %3,%3,%2 @@ -2248,12 +2248,12 @@ (define_insn "*fuse_vnor_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> veqv (define_insn "*fuse_vor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;veqv %3,%3,%2 vor %3,%1,%0\;veqv %3,%3,%2 @@ -2266,12 +2266,12 @@ (define_insn "*fuse_vor_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> veqv (define_insn "*fuse_vorc_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;veqv %3,%3,%2 vorc %3,%1,%0\;veqv %3,%3,%2 @@ -2284,12 +2284,12 @@ (define_insn "*fuse_vorc_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> veqv (define_insn "*fuse_vxor_veqv" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (not:VM (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (not:BOOL_128 (xor:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;veqv %3,%3,%2 vxor %3,%1,%0\;veqv %3,%3,%2 @@ -2302,12 +2302,12 @@ (define_insn "*fuse_vxor_veqv" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnand (define_insn "*fuse_vand_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnand %3,%3,%2 vand %3,%1,%0\;vnand %3,%3,%2 @@ -2320,12 +2320,12 @@ (define_insn "*fuse_vand_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnand (define_insn "*fuse_vandc_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnand %3,%3,%2 vandc %3,%1,%0\;vnand %3,%3,%2 @@ -2338,12 +2338,12 @@ (define_insn "*fuse_vandc_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnand (define_insn "*fuse_veqv_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnand %3,%3,%2 veqv %3,%1,%0\;vnand %3,%3,%2 @@ -2356,12 +2356,12 @@ (define_insn "*fuse_veqv_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnand (define_insn "*fuse_vnand_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnand %3,%3,%2 vnand %3,%1,%0\;vnand %3,%3,%2 @@ -2374,12 +2374,12 @@ (define_insn "*fuse_vnand_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnand (define_insn "*fuse_vnor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnand %3,%3,%2 vnor %3,%1,%0\;vnand %3,%3,%2 @@ -2392,12 +2392,12 @@ (define_insn "*fuse_vnor_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnand (define_insn "*fuse_vor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnand %3,%3,%2 vor %3,%1,%0\;vnand %3,%3,%2 @@ -2410,12 +2410,12 @@ (define_insn "*fuse_vor_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnand (define_insn "*fuse_vorc_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnand %3,%3,%2 vorc %3,%1,%0\;vnand %3,%3,%2 @@ -2428,12 +2428,12 @@ (define_insn "*fuse_vorc_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnand (define_insn "*fuse_vxor_vnand" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnand %3,%3,%2 vxor %3,%1,%0\;vnand %3,%3,%2 @@ -2446,12 +2446,12 @@ (define_insn "*fuse_vxor_vnand" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vnor (define_insn "*fuse_vand_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vnor %3,%3,%2 vand %3,%1,%0\;vnor %3,%3,%2 @@ -2464,12 +2464,12 @@ (define_insn "*fuse_vand_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vnor (define_insn "*fuse_vandc_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vnor %3,%3,%2 vandc %3,%1,%0\;vnor %3,%3,%2 @@ -2482,12 +2482,12 @@ (define_insn "*fuse_vandc_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vnor (define_insn "*fuse_veqv_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vnor %3,%3,%2 veqv %3,%1,%0\;vnor %3,%3,%2 @@ -2500,12 +2500,12 @@ (define_insn "*fuse_veqv_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vnor (define_insn "*fuse_vnand_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vnor %3,%3,%2 vnand %3,%1,%0\;vnor %3,%3,%2 @@ -2518,12 +2518,12 @@ (define_insn "*fuse_vnand_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vnor (define_insn "*fuse_vnor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vnor %3,%3,%2 vnor %3,%1,%0\;vnor %3,%3,%2 @@ -2536,12 +2536,12 @@ (define_insn "*fuse_vnor_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vnor (define_insn "*fuse_vor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vnor %3,%3,%2 vor %3,%1,%0\;vnor %3,%3,%2 @@ -2554,12 +2554,12 @@ (define_insn "*fuse_vor_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vnor (define_insn "*fuse_vorc_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vnor %3,%3,%2 vorc %3,%1,%0\;vnor %3,%3,%2 @@ -2572,12 +2572,12 @@ (define_insn "*fuse_vorc_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vnor (define_insn "*fuse_vxor_vnor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (and:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (and:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vnor %3,%3,%2 vxor %3,%1,%0\;vnor %3,%3,%2 @@ -2590,12 +2590,12 @@ (define_insn "*fuse_vxor_vnor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vor (define_insn "*fuse_vand_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vor %3,%3,%2 vand %3,%1,%0\;vor %3,%3,%2 @@ -2608,12 +2608,12 @@ (define_insn "*fuse_vand_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vor (define_insn "*fuse_vandc_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vor %3,%3,%2 vandc %3,%1,%0\;vor %3,%3,%2 @@ -2626,12 +2626,12 @@ (define_insn "*fuse_vandc_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vor (define_insn "*fuse_veqv_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vor %3,%3,%2 veqv %3,%1,%0\;vor %3,%3,%2 @@ -2644,12 +2644,12 @@ (define_insn "*fuse_veqv_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vor (define_insn "*fuse_vnand_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vor %3,%3,%2 vnand %3,%1,%0\;vor %3,%3,%2 @@ -2662,12 +2662,12 @@ (define_insn "*fuse_vnand_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vor (define_insn "*fuse_vnor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vor %3,%3,%2 vnor %3,%1,%0\;vor %3,%3,%2 @@ -2680,12 +2680,12 @@ (define_insn "*fuse_vnor_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vor (define_insn "*fuse_vor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vor %3,%3,%2 vor %3,%1,%0\;vor %3,%3,%2 @@ -2698,12 +2698,12 @@ (define_insn "*fuse_vor_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vor (define_insn "*fuse_vorc_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vor %3,%3,%2 vorc %3,%1,%0\;vor %3,%3,%2 @@ -2716,12 +2716,12 @@ (define_insn "*fuse_vorc_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vor (define_insn "*fuse_vxor_vor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vor %3,%3,%2 vxor %3,%1,%0\;vor %3,%3,%2 @@ -2734,12 +2734,12 @@ (define_insn "*fuse_vxor_vor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vorc (define_insn "*fuse_vand_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vorc %3,%3,%2 vand %3,%1,%0\;vorc %3,%3,%2 @@ -2752,12 +2752,12 @@ (define_insn "*fuse_vand_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vorc (define_insn "*fuse_vandc_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vorc %3,%3,%2 vandc %3,%1,%0\;vorc %3,%3,%2 @@ -2770,12 +2770,12 @@ (define_insn "*fuse_vandc_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vorc (define_insn "*fuse_veqv_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vorc %3,%3,%2 veqv %3,%1,%0\;vorc %3,%3,%2 @@ -2788,12 +2788,12 @@ (define_insn "*fuse_veqv_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vorc (define_insn "*fuse_vnand_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vorc %3,%3,%2 vnand %3,%1,%0\;vorc %3,%3,%2 @@ -2806,12 +2806,12 @@ (define_insn "*fuse_vnand_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vorc (define_insn "*fuse_vnor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vorc %3,%3,%2 vnor %3,%1,%0\;vorc %3,%3,%2 @@ -2824,12 +2824,12 @@ (define_insn "*fuse_vnor_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vorc (define_insn "*fuse_vor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vorc %3,%3,%2 vor %3,%1,%0\;vorc %3,%3,%2 @@ -2842,12 +2842,12 @@ (define_insn "*fuse_vor_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vorc (define_insn "*fuse_vorc_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vorc %3,%3,%2 vorc %3,%1,%0\;vorc %3,%3,%2 @@ -2860,12 +2860,12 @@ (define_insn "*fuse_vorc_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vorc (define_insn "*fuse_vxor_vorc" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (ior:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 2 "altivec_register_operand" "v,v,v,v")))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (ior:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v")))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vorc %3,%3,%2 vxor %3,%1,%0\;vorc %3,%3,%2 @@ -2878,12 +2878,12 @@ (define_insn "*fuse_vxor_vorc" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vand -> vxor (define_insn "*fuse_vand_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (and:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (and:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vand %3,%1,%0\;vxor %3,%3,%2 vand %3,%1,%0\;vxor %3,%3,%2 @@ -2896,12 +2896,12 @@ (define_insn "*fuse_vand_vxor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vandc -> vxor (define_insn "*fuse_vandc_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vandc %3,%1,%0\;vxor %3,%3,%2 vandc %3,%1,%0\;vxor %3,%3,%2 @@ -2914,12 +2914,12 @@ (define_insn "*fuse_vandc_vxor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector veqv -> vxor (define_insn "*fuse_veqv_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (not:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (not:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ veqv %3,%1,%0\;vxor %3,%3,%2 veqv %3,%1,%0\;vxor %3,%3,%2 @@ -2932,12 +2932,12 @@ (define_insn "*fuse_veqv_vxor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnand -> vxor (define_insn "*fuse_vnand_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnand %3,%1,%0\;vxor %3,%3,%2 vnand %3,%1,%0\;vxor %3,%3,%2 @@ -2950,12 +2950,12 @@ (define_insn "*fuse_vnand_vxor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vnor -> vxor (define_insn "*fuse_vnor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (and:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (not:VM (match_operand:VM 1 "altivec_register_operand" "v,v,v,v"))) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (and:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (not:BOOL_128 (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v"))) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vnor %3,%1,%0\;vxor %3,%3,%2 vnor %3,%1,%0\;vxor %3,%3,%2 @@ -2968,12 +2968,12 @@ (define_insn "*fuse_vnor_vxor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vor -> vxor (define_insn "*fuse_vor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (ior:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (ior:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vor %3,%1,%0\;vxor %3,%3,%2 vor %3,%1,%0\;vxor %3,%3,%2 @@ -2986,12 +2986,12 @@ (define_insn "*fuse_vor_vxor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vorc -> vxor (define_insn "*fuse_vorc_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (ior:VM (not:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 1 "altivec_register_operand" "v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (ior:BOOL_128 (not:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 1 "altivec_register_operand" "v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vorc %3,%1,%0\;vxor %3,%3,%2 vorc %3,%1,%0\;vxor %3,%3,%2 @@ -3004,12 +3004,12 @@ (define_insn "*fuse_vorc_vxor" ;; logical-logical fusion pattern generated by gen_logical_addsubf ;; vector vxor -> vxor (define_insn "*fuse_vxor_vxor" - [(set (match_operand:VM 3 "altivec_register_operand" "=&0,&1,&v,v") - (xor:VM (xor:VM (match_operand:VM 0 "altivec_register_operand" "v,v,v,v") - (match_operand:VM 1 "altivec_register_operand" "%v,v,v,v")) - (match_operand:VM 2 "altivec_register_operand" "v,v,v,v"))) - (clobber (match_scratch:VM 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + [(set (match_operand:BOOL_128 3 "altivec_register_operand" "=&0,&1,&v,v") + (xor:BOOL_128 (xor:BOOL_128 (match_operand:BOOL_128 0 "altivec_register_operand" "v,v,v,v") + (match_operand:BOOL_128 1 "altivec_register_operand" "%v,v,v,v")) + (match_operand:BOOL_128 2 "altivec_register_operand" "v,v,v,v"))) + (clobber (match_scratch:BOOL_128 4 "=X,X,X,&v"))] + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && TARGET_P10_FUSION)" "@ vxor %3,%1,%0\;vxor %3,%3,%2 vxor %3,%1,%0\;vxor %3,%3,%2 @@ -3045,7 +3045,7 @@ (define_insn "*fuse_vaddudm_vaddudm" (match_operand:V2DI 1 "altivec_register_operand" "%v,v,v,v")) (match_operand:V2DI 2 "altivec_register_operand" "v,v,v,v"))) (clobber (match_scratch:V2DI 4 "=X,X,X,&v"))] - "(TARGET_P10_FUSION)" + "(VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DImode) && TARGET_P10_FUSION)" "@ vaddudm %3,%1,%0\;vaddudm %3,%3,%2 vaddudm %3,%1,%0\;vaddudm %3,%3,%2 diff --git a/gcc/config/rs6000/genfusion.pl b/gcc/config/rs6000/genfusion.pl index 81cc2255f53..63679714d65 100755 --- a/gcc/config/rs6000/genfusion.pl +++ b/gcc/config/rs6000/genfusion.pl @@ -167,21 +167,23 @@ sub gen_logical_addsubf $inner_comp, $inner_inv, $inner_rtl, $inner_op, $both_commute, $c4, $bc, $inner_arg0, $inner_arg1, $inner_exp, $outer_arg2, $outer_exp, $ftype, $insn, $is_subf, $is_rsubf, $outer_32, $outer_42,$outer_name, - $fuse_type); + $fuse_type, $constraint_cond); KIND: foreach $kind ('scalar','vector') { @outer_ops = @logicals; if ( $kind eq 'vector' ) { $vchr = "v"; - $mode = "VM"; + $mode = "BOOL_128"; $pred = "altivec_register_operand"; $constraint = "v"; $fuse_type = "fused_vector"; + $constraint_cond = "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) && "; } else { $vchr = ""; $mode = "GPR"; $pred = "gpc_reg_operand"; $constraint = "r"; $fuse_type = "fused_arith_logical"; + $constraint_cond = ""; push (@outer_ops, @addsub); push (@outer_ops, ( "rsubf" )); } @@ -263,7 +265,7 @@ sub gen_logical_addsubf [(set (match_operand:${mode} 3 "${pred}" "=&0,&1,&${constraint},${constraint}") ${outer_exp}) (clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint}"))] - "(TARGET_P10_FUSION)" + "(${constraint_cond}TARGET_P10_FUSION)" "@ ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} ${inner_op} %3,%1,%0\\;${outer_op} %3,${outer_32} @@ -282,7 +284,7 @@ EOF sub gen_addadd { - my ($kind, $vchr, $op, $type, $mode, $pred, $constraint); + my ($kind, $vchr, $op, $type, $mode, $pred, $constraint, $constraint_cond); foreach $kind ('scalar','vector') { if ( $kind eq 'vector' ) { $vchr = "v"; @@ -291,6 +293,7 @@ sub gen_addadd $mode = "V2DI"; $pred = "altivec_register_operand"; $constraint = "v"; + $constraint_cond = "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DImode) && "; } else { $vchr = ""; $op = "add"; @@ -298,6 +301,7 @@ sub gen_addadd $mode = "GPR"; $pred = "gpc_reg_operand"; $constraint = "r"; + $constraint_cond = ""; } my $c4 = "${constraint},${constraint},${constraint},${constraint}"; print <<"EOF"; @@ -310,7 +314,7 @@ sub gen_addadd (match_operand:${mode} 1 "${pred}" "%${c4}")) (match_operand:${mode} 2 "${pred}" "${c4}"))) (clobber (match_scratch:${mode} 4 "=X,X,X,&${constraint}"))] - "(TARGET_P10_FUSION)" + "(${constraint_cond}TARGET_P10_FUSION)" "@ ${op} %3,%1,%0\\;${op} %3,%3,%2 ${op} %3,%1,%0\\;${op} %3,%3,%2 diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d7a7cfe860f..f41b8f740ba 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4441,11 +4441,6 @@ rs6000_option_override_internal (bool global_init_p) /* Enable -mmma by default on power10 systems. */ if (TARGET_POWER10 && (rs6000_isa_flags_explicit & OPTION_MASK_MMA) == 0) rs6000_isa_flags |= OPTION_MASK_MMA; - - if (TARGET_POWER10 - && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION) == 0) - rs6000_isa_flags |= OPTION_MASK_P10_FUSION; - /* Turn off vector pair/mma options on non-power10 systems. */ else if (!TARGET_POWER10 && TARGET_MMA) { @@ -4455,6 +4450,12 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_MMA; } + if (TARGET_POWER10 + && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION) == 0) + rs6000_isa_flags |= OPTION_MASK_P10_FUSION; + else if (!TARGET_POWER10 && TARGET_P10_FUSION) + rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION; + /* MMA requires SIMD support as ISA 3.1 claims and our implementation such as "*movoo" uses vector pair access which use VSX registers. So make MMA require VSX support here. */ diff --git a/gcc/testsuite/gcc.target/powerpc/pr104024-1.c b/gcc/testsuite/gcc.target/powerpc/pr104024-1.c new file mode 100644 index 00000000000..19575627342 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr104024-1.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target int128 } */ +/* { dg-options "-O1 -mdejagnu-cpu=power6 -mpower10-fusion" } */ + +/* Verify there is no ICE. */ + +int v; + +__attribute__((noinline, noclone)) void bar(void) { v++; } + +__attribute__((noinline, noclone)) signed __int128 +t100_1add(signed __int128 x, signed __int128 y) { + signed __int128 r; + if (__builtin_add_overflow(x, y, &r)) + bar(); + return r; +} diff --git a/gcc/testsuite/gcc.target/powerpc/pr104024-2.c b/gcc/testsuite/gcc.target/powerpc/pr104024-2.c new file mode 100644 index 00000000000..11c837aa8e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr104024-2.c @@ -0,0 +1,18 @@ +/* { dg-require-effective-target int128 } */ +/* -w disable the warning that '-mno-altivec' disables vsx. */ +/* { dg-options "-O1 -mdejagnu-cpu=power10 -mpower10-fusion -mno-altivec -w" } */ + +/* Verify there is no ICE. */ + +int v; + +__attribute__((noinline, noclone)) void bar(void) { v++; } + +__attribute__((noinline, noclone)) signed __int128 +t100_1add(signed __int128 x, signed __int128 y) { + signed __int128 r; + if (__builtin_add_overflow(x, y, &r)) + bar(); + return r; +} +