From patchwork Thu Feb 10 18:22:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 51017 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1F5733858D1E for ; Thu, 10 Feb 2022 18:23:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1F5733858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1644517385; bh=DClJU9VCH+xUapYH5AEV0ZIRUSKN14ab3qd4VlJhsb8=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=DWWfifeR3eyLdRuKIRDy7G6Oq1WaGTeBYwr+mSrdMfwxUEHb35gwV2H7SbTMxJZ5Z HeixUTQSSvSP1iIqmZLPuAeQMe7uQwQHdvTTIo4VyBB0ooCipstrAnSzynyued9Y1p LefupVrXxCvlYzcy4PyCU7+mTDEu+872EcFf/QhI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id E95763858C20 for ; Thu, 10 Feb 2022 18:22:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E95763858C20 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 21AGqw4k026972; Thu, 10 Feb 2022 18:22:32 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 3e51dsjrw2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Feb 2022 18:22:32 +0000 Received: from m0187473.ppops.net (m0187473.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.43/8.16.0.43) with SMTP id 21AIC5t0007921; Thu, 10 Feb 2022 18:22:31 GMT Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 3e51dsjrvv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Feb 2022 18:22:31 +0000 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 21AIDiHJ029552; Thu, 10 Feb 2022 18:22:30 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma04wdc.us.ibm.com with ESMTP id 3e2btbtc3g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Feb 2022 18:22:30 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 21AIMTjd37683588 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Feb 2022 18:22:29 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 733EF136060; Thu, 10 Feb 2022 18:22:29 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4481713606A; Thu, 10 Feb 2022 18:22:29 +0000 (GMT) Received: from [9.211.95.26] (unknown [9.211.95.26]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP; Thu, 10 Feb 2022 18:22:29 +0000 (GMT) Message-ID: Date: Thu, 10 Feb 2022 12:22:28 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.0 To: GCC Patches Subject: [PATCH, 11 backport] rs6000: Fix LE code gen for vec_cnt[lt]z_lsbb [PR95082] X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 7LWENfYqQUhQMau4Fy4DKkZKJLYUwoSJ X-Proofpoint-GUID: h2wdeB3jPgSG_21_TO14JLIL1tju2NNf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-02-10_08,2022-02-09_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 spamscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2202100095 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Bill Schmidt via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: wschmidt@linux.ibm.com Cc: David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi! This is a backport from mainline 3f30f2d1dbb3228b8468b26239fe60c2974ce2ac. These built-ins were misimplemented as always having big-endian semantics. Because the built-in infrastructure has changed, the modifications to the source are different but achieve the same purpose. The modifications to the test suite are identical (after fixing the issue with -mbig that David pointed out with the original patch). Bootstrapped and tested on powerpc64le-linux-gnu with no regressions. Is this okay for releases/gcc-11? Thanks! Bill 2022-02-10 Bill Schmidt gcc/ PR target/95082 * config/rs6000/rs6000-builtin.def (VCLZLSBB_V16QI): Change default pattern. (VCLZLSBB_V8HI): Likewise. (VCLZLSBB_V4SI): Likewise. (VCTZLSBB_V16QI): Likewise. (VCTZLSBB_V8HI): Likewise. (VCTZLSBB_V4SI): Likewise. * config/rs6000/rs6000-call.c (rs6000_expand_builtin): Make big-endian adjustments to P9V_BUILTIN_VC[LT]ZLSBB_* built-in expansions. gcc/testsuite/ PR target/95082 * gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Restrict to big-endian. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: New. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: New. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Restrict to big-endian. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: New. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: New. --- gcc/config/rs6000/rs6000-builtin.def | 12 ++++---- gcc/config/rs6000/rs6000-call.c | 30 +++++++++++++++++++ .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c | 1 + .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c | 1 + .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c | 15 ++++++++++ .../gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c | 15 ++++++++++ .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c | 1 + .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c | 1 + .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c | 15 ++++++++++ .../gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c | 15 ++++++++++ 10 files changed, 100 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 6270444ef70..b28ee02070a 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -2678,12 +2678,12 @@ BU_P9V_64BIT_AV_X (STXVL, "stxvl", MISC) BU_P9V_64BIT_AV_X (XST_LEN_R, "xst_len_r", MISC) /* 1 argument vector functions added in ISA 3.0 (power9). */ -BU_P9V_AV_1 (VCLZLSBB_V16QI, "vclzlsbb_v16qi", CONST, vclzlsbb_v16qi) -BU_P9V_AV_1 (VCLZLSBB_V8HI, "vclzlsbb_v8hi", CONST, vclzlsbb_v8hi) -BU_P9V_AV_1 (VCLZLSBB_V4SI, "vclzlsbb_v4si", CONST, vclzlsbb_v4si) -BU_P9V_AV_1 (VCTZLSBB_V16QI, "vctzlsbb_v16qi", CONST, vctzlsbb_v16qi) -BU_P9V_AV_1 (VCTZLSBB_V8HI, "vctzlsbb_v8hi", CONST, vctzlsbb_v8hi) -BU_P9V_AV_1 (VCTZLSBB_V4SI, "vctzlsbb_v4si", CONST, vctzlsbb_v4si) +BU_P9V_AV_1 (VCLZLSBB_V16QI, "vclzlsbb_v16qi", CONST, vctzlsbb_v16qi) +BU_P9V_AV_1 (VCLZLSBB_V8HI, "vclzlsbb_v8hi", CONST, vctzlsbb_v8hi) +BU_P9V_AV_1 (VCLZLSBB_V4SI, "vclzlsbb_v4si", CONST, vctzlsbb_v4si) +BU_P9V_AV_1 (VCTZLSBB_V16QI, "vctzlsbb_v16qi", CONST, vclzlsbb_v16qi) +BU_P9V_AV_1 (VCTZLSBB_V8HI, "vctzlsbb_v8hi", CONST, vclzlsbb_v8hi) +BU_P9V_AV_1 (VCTZLSBB_V4SI, "vctzlsbb_v4si", CONST, vclzlsbb_v4si) /* Built-in support for Power9 "VSU option" string operations includes new awareness of the "vector compare not equal" (vcmpneb, vcmpneb., diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index ef20cb30388..27bb25fa4d8 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -13221,6 +13221,36 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, } break; + case P9V_BUILTIN_VCLZLSBB_V16QI: + if (BYTES_BIG_ENDIAN) + icode = CODE_FOR_vclzlsbb_v16qi; + break; + + case P9V_BUILTIN_VCLZLSBB_V8HI: + if (BYTES_BIG_ENDIAN) + icode = CODE_FOR_vclzlsbb_v8hi; + break; + + case P9V_BUILTIN_VCLZLSBB_V4SI: + if (BYTES_BIG_ENDIAN) + icode = CODE_FOR_vclzlsbb_v4si; + break; + + case P9V_BUILTIN_VCTZLSBB_V16QI: + if (BYTES_BIG_ENDIAN) + icode = CODE_FOR_vctzlsbb_v16qi; + break; + + case P9V_BUILTIN_VCTZLSBB_V8HI: + if (BYTES_BIG_ENDIAN) + icode = CODE_FOR_vctzlsbb_v8hi; + break; + + case P9V_BUILTIN_VCTZLSBB_V4SI: + if (BYTES_BIG_ENDIAN) + icode = CODE_FOR_vctzlsbb_v4si; + break; + default: break; } diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c index 0faf233425e..e2f6b08bc0f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c index 201ed17e2fd..a9647e749ae 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c new file mode 100644 index 00000000000..6ee31a11aee --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_leading_zero_byte_bits (vector signed char *arg1_p) +{ + vector signed char arg_1 = *arg1_p; + + return vec_cntlz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vctzlsbb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c new file mode 100644 index 00000000000..6105091b016 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_leading_zero_byte_bits (vector unsigned char *arg1_p) +{ + vector unsigned char arg_1 = *arg1_p; + + return vec_cntlz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vctzlsbb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c index 70a398ac401..7ee2b6e87db 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c index f6d41e3e728..d87a7903fce 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c @@ -1,6 +1,7 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ /* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-additional-options "-mbig" { target powerpc64le-*-* } } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c new file mode 100644 index 00000000000..a9245d8200c --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_trailing_zero_byte_bits (vector signed char *arg1_p) +{ + vector signed char arg_1 = *arg1_p; + + return vec_cnttz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vclzlsbb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c new file mode 100644 index 00000000000..71fea5306c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_trailing_zero_byte_bits (vector unsigned char *arg1_p) +{ + vector unsigned char arg_1 = *arg1_p; + + return vec_cnttz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vclzlsbb" } } */