From patchwork Wed Feb 9 20:12:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 50975 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 30009385843F for ; Wed, 9 Feb 2022 20:12:42 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 25BEF3858404 for ; Wed, 9 Feb 2022 20:12:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 25BEF3858404 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:To:From:Sender:Reply-To:Cc:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=O11iB9zg5jdw1bjdE/Kiratb0g7r49djswxpXrWScDY=; b=RdcEOc0myKh7ScbjL7ffUFYx4o tjU1YRjXoY0h9NIEkSYRrJ7r5ZtHthi2d5or6LhL/fdkUSP4jNF8njiakLArKH421QWnfE8HM1uEN +QhoTz1momO8IR8Nh1wiPMZWyEju79pD4uX173fd6UqgasmTYybK5exX5N8EJYK4/5d6nOKbZDm+V vPsDpwYfjxjS4iY8btHxrcmF/nZpSRMzRUCgvSiE0MIVCn6I27aMi/T5Pa28Hlk2BCauRzN1Hn/4y PzYrjtmXoQxferY6siK28fPa5STDt7zQvb63BT53LpWxSryNcvCop+qpvsGOClLX3l06vjG7leozK mHoOq4gQ==; Received: from host86-160-23-130.range86-160.btcentralplus.com ([86.160.23.130]:55936 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nHtJw-0007em-G3 for gcc-patches@gcc.gnu.org; Wed, 09 Feb 2022 15:12:08 -0500 From: "Roger Sayle" To: Subject: [PATCH] middle-end: Support ABIs that pass FP values as wider integers. Date: Wed, 9 Feb 2022 20:12:06 -0000 Message-ID: <057201d81df1$50523bc0$f0f6b340$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adgd8A6yCdjCHv8zQj2fMaVN3fYjiw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds middle-end support for target ABIs that pass/return floating point values in integer registers with precision wider than the original FP mode. An example, is the nvptx backend where 16-bit HFmode registers are passed/returned as (promoted to) SImode registers. Unfortunately, this currently falls foul of the various (recent?) sanity checks that (very sensibly) prevent creating paradoxical SUBREGs of floating point registers. The approach below is to explicitly perform the conversion/promotion in two steps, via an integer mode of same precision as the floating point value. So on nvptx, 16-bit HFmode is initially converted to 16-bit HImode (using SUBREG), then zero-extended to SImode, and likewise when going the other way, parameters truncated to HImode then converted to HFmode (using SUBREG). These changes are localized to expand_value_return and expanding DECL_RTL to support strange ABIs, rather than inside convert_modes or gen_lowpart, as mismatched precision integer/FP conversions should be explicit in the RTL, and these semantics not generally visible/implicit in user code. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check with no new failures, and on nvptx-none, where it is the middle-end portion of a pair of patches to allow the default ISA to be advanced. Ok for mainline? 2022-02-09 Roger Sayle gcc/ChangeLog * cfgexpand.cc (expand_value_return): Allow backends to promote a scalar floating point return value to a wider integer mode. * expr.cc (expand_expr_real_1) [expand_decl_rtl]: Likewise, allow backends to promote scalar FP PARM_DECLs to wider integer modes. Thanks in advance, Roger diff --git a/gcc/cfgexpand.cc b/gcc/cfgexpand.cc index d51af2e..c377f16 100644 --- a/gcc/cfgexpand.cc +++ b/gcc/cfgexpand.cc @@ -3715,7 +3715,22 @@ expand_value_return (rtx val) mode = promote_function_mode (type, old_mode, &unsignedp, funtype, 1); if (mode != old_mode) - val = convert_modes (mode, old_mode, val, unsignedp); + { + /* Some ABIs require scalar floating point modes to be returned + in a wider scalar integer mode. We need to explicitly + reinterpret to an integer mode of the correct precision + before extending to the desired result. */ + if (SCALAR_INT_MODE_P (mode) + && SCALAR_FLOAT_MODE_P (old_mode) + && known_gt (GET_MODE_SIZE (mode), GET_MODE_SIZE (old_mode))) + { + scalar_int_mode imode = int_mode_for_mode (old_mode).require (); + val = force_reg (imode, gen_lowpart (imode, val)); + val = convert_modes (mode, imode, val, 1); + } + else + val = convert_modes (mode, old_mode, val, unsignedp); + } if (GET_CODE (return_reg) == PARALLEL) emit_group_load (return_reg, val, type, int_size_in_bytes (type)); diff --git a/gcc/expr.cc b/gcc/expr.cc index 35e4029..e4efdcd 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -10674,6 +10674,19 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode, pmode = promote_ssa_mode (ssa_name, &unsignedp); gcc_assert (GET_MODE (decl_rtl) == pmode); + /* Some ABIs require scalar floating point modes to be passed + in a wider scalar integer mode. We need to explicitly + truncate to an integer mode of the correct precision before + using a SUBREG to reinterpret as a floating point value. */ + if (SCALAR_FLOAT_MODE_P (mode) + && SCALAR_INT_MODE_P (pmode) + && known_lt (GET_MODE_SIZE (mode), GET_MODE_SIZE (pmode))) + { + scalar_int_mode imode = int_mode_for_mode (mode).require (); + temp = force_reg (imode, gen_lowpart (imode, decl_rtl)); + return gen_lowpart_SUBREG (mode, temp); + } + temp = gen_lowpart_SUBREG (mode, decl_rtl); SUBREG_PROMOTED_VAR_P (temp) = 1; SUBREG_PROMOTED_SET (temp, unsignedp);