From patchwork Wed Feb 9 19:23:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 50972 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D264A385841A for ; Wed, 9 Feb 2022 19:23:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D264A385841A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1644434633; bh=7DyMJpshP2lPUHc8rUDktmRda1nY6JQLjyKdXO7e8Q4=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=RtMZGNAkzHBOWt/g192kpaFghmjRgTgq4I2GwUNCgLDlfIlpOhuDLUdTdjrsH3Mfs 4S6NFaXO1qlctU87KrRvA3GQcNOnOYwiWa03YmV+DcEUtSyDaXHIU6jfpu64Udvutv DQngNzI9nPHgVJWIB0ALxpnK0QHBv+ShozsDBh7o= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x82a.google.com (mail-qt1-x82a.google.com [IPv6:2607:f8b0:4864:20::82a]) by sourceware.org (Postfix) with ESMTPS id CB18C3858D1E for ; Wed, 9 Feb 2022 19:23:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CB18C3858D1E Received: by mail-qt1-x82a.google.com with SMTP id l14so2722658qtp.7 for ; Wed, 09 Feb 2022 11:23:23 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=7DyMJpshP2lPUHc8rUDktmRda1nY6JQLjyKdXO7e8Q4=; b=nSfSrcl3wVsmMQsdmUR0eSsSPSFs5DMyWSAG+faeRD1YEAjbJN4yZUMFJx1cVCmH46 QLcn6lthLR5C8y8qeDYaUN//HgQFNhg3K3+WchV72a0kKsY48ocyRZNQ7vDcQPivkN0Q v17ukU8KJ1k4zm0az3OO+XjX35WQ//W6ilX+Jw5bGm7AkpSEPqghc4h0lDLgT6YiUrRw b6EouMkudjIunpgl70ZN5Xl5ymExGNXXUf90YTe1cCNw0U0WthLZHATqU5xtkBF7XYrq YiZ6OASl7syCSmQ8ZYunWe5z0m2LpHQMp2op/Hvv8Ovjg7ydwQAPDyAPBhFZGWLZ++LG roog== X-Gm-Message-State: AOAM532fTsyTIdP/kzn8pJP1nMFKGQhLVV2EK356QpCtiKd9ezxg4XWz 6tV3uylqmwmxONZ7EAZJx+MviMp4mdoMMebW03IApcthqLY71w== X-Google-Smtp-Source: ABdhPJzoJb7zrDuvXD8bj9g2pqbKRqrDvUaf8v5UWCzTO3EA9WpDOfRv97QDW3fC8siq717r9RG6bEq1yHOStNxTZRc= X-Received: by 2002:ac8:5f09:: with SMTP id x9mr2511635qta.5.1644434603137; Wed, 09 Feb 2022 11:23:23 -0800 (PST) MIME-Version: 1.0 Date: Wed, 9 Feb 2022 20:23:11 +0100 Message-ID: Subject: [PATCH] i386: Force inputs to a register to avoid lowpart_subreg failure [PR104458] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Input operands can be in the form of: (subreg:DI (reg:V2SF 96) 0) which chokes lowpart_subreg. Force inputs to a register, which is preferable even when the input operand is from memory. 2022-02-09 Uroš Bizjak gcc/ChangeLog: PR target/104458 * config/i386/i386-expand.cc (ix86_split_idivmod): Force operands[2] and operands[3] into a register.. gcc/testsuite/ChangeLog: PR target/104458 * gcc.target/i386/pr104458.c: New test. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index eb1930ba375..ce9607e36de 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -1407,6 +1407,9 @@ ix86_split_idivmod (machine_mode mode, rtx operands[], rtx scratch, tmp0, tmp1, tmp2; rtx (*gen_divmod4_1) (rtx, rtx, rtx, rtx); + operands[2] = force_reg (mode, operands[2]); + operands[3] = force_reg (mode, operands[3]); + switch (mode) { case E_SImode: diff --git a/gcc/testsuite/gcc.target/i386/pr104458.c b/gcc/testsuite/gcc.target/i386/pr104458.c new file mode 100644 index 00000000000..d1d28c13118 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr104458.c @@ -0,0 +1,13 @@ +/* PR target/104458 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O1 -m8bit-idiv" } */ + +typedef float __attribute__((__vector_size__ (8))) F; + +int i; + +void +foo (F f) +{ + i += i % (long) f; +}