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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id lr7sm10386931pjb.42.2022.02.06.22.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 22:06:39 -0800 (PST) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Enable TARGET_SUPPORTS_WIDE_INT Date: Sun, 6 Feb 2022 22:06:37 -0800 Message-Id: <20220207060637.487010-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Maciej W . Rozycki" , Andrew Waterman , Vineet Gupta , kito.cheng@gmail.com, Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This is at par with other major arches such as aarch64, i386, s390 ... No testsuite regressions: same numbers w/ w/o | === gcc Summary === | |# of expected passes 113392 |# of unexpected failures 27 |# of unexpected successes 3 |# of expected failures 605 |# of unsupported tests 2523 | | === g++ Summary === | |# of expected passes 172997 |# of unexpected failures 26 |# of expected failures 706 |# of unsupported tests 9566 Signed-off-by: Vineet Gupta Reviewed-by: Palmer Dabbelt --- gcc/config/riscv/predicates.md | 2 +- gcc/config/riscv/riscv.c | 6 ++++++ gcc/config/riscv/riscv.h | 2 ++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 3da6fd4c0491..cf902229954b 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -52,7 +52,7 @@ (match_test "INTVAL (op) + 1 != 0"))) (define_predicate "const_0_operand" - (and (match_code "const_int,const_wide_int,const_double,const_vector") + (and (match_code "const_int,const_wide_int,const_vector") (match_test "op == CONST0_RTX (GET_MODE (op))"))) (define_predicate "reg_or_0_operand" diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index c830cd8f4ad1..d2f2d9e0276f 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1774,6 +1774,12 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN case SYMBOL_REF: case LABEL_REF: case CONST_DOUBLE: + /* With TARGET_SUPPORTS_WIDE_INT const int can't be in CONST_DOUBLE + rtl object. Weird recheck due to switch-case fall through above. */ + if (GET_CODE (x) == CONST_DOUBLE) + gcc_assert (GET_MODE (x) != VOIDmode); + /* Fall through. */ + case CONST: if ((cost = riscv_const_insns (x)) > 0) { diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index ff6729aedac2..91cfc82b4aa4 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -997,4 +997,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void); #define HARD_REGNO_RENAME_OK(FROM, TO) riscv_hard_regno_rename_ok (FROM, TO) +#define TARGET_SUPPORTS_WIDE_INT 1 + #endif /* ! GCC_RISCV_H */