From patchwork Thu Jan 20 10:10:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robin Dapp X-Patchwork-Id: 50266 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 260A73858D35 for ; Thu, 20 Jan 2022 10:11:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 260A73858D35 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1642673474; bh=6xnV9qzlPbnpV+JvhwYChRocD3Ko77aBLUIz4wjG8Uk=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=VM+2E1RZanyHDfIif5VfisKLbOyNLm1+qf/Vyhcv+29Hj7242blg+wkGRJbbr4Mq9 DcAlIySM9TISnOFcVZBDQyz0W2H32IVbIVkO+eEUtyuBnOW53CmNVu0xtqB+r5zhrU 9/PU/zACVrUzUf8WOrPapKqdKMALfYc2YUS6UqBo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id A767C3858D37 for ; Thu, 20 Jan 2022 10:10:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A767C3858D37 Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 20K9ueou016593 for ; Thu, 20 Jan 2022 10:10:44 GMT Received: from ppma06fra.de.ibm.com (48.49.7a9f.ip4.static.sl-reverse.com [159.122.73.72]) by mx0a-001b2d01.pphosted.com with ESMTP id 3dq5j5r9jf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 20 Jan 2022 10:10:43 +0000 Received: from pps.filterd (ppma06fra.de.ibm.com [127.0.0.1]) by ppma06fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 20KA3s9r010155 for ; Thu, 20 Jan 2022 10:10:42 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma06fra.de.ibm.com with ESMTP id 3dknhjnvey-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 20 Jan 2022 10:10:41 +0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 20KAAc7U20447614 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 20 Jan 2022 10:10:38 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A787A11C05B; Thu, 20 Jan 2022 10:10:38 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7981E11C04C; Thu, 20 Jan 2022 10:10:38 +0000 (GMT) Received: from [9.171.25.184] (unknown [9.171.25.184]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTPS; Thu, 20 Jan 2022 10:10:38 +0000 (GMT) Message-ID: <46d6cd86-2194-ca0b-7873-0ff121fa33d4@linux.ibm.com> Date: Thu, 20 Jan 2022 11:10:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Content-Language: en-US Subject: [PATCH] s390: Change costs for load on condition. To: GCC Patches , Andreas Krebbel X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: DBKI0AraSMbI6vGTLXpE1hSpOYVumhtW X-Proofpoint-GUID: DBKI0AraSMbI6vGTLXpE1hSpOYVumhtW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-20_03,2022-01-20_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 mlxlogscore=999 malwarescore=0 spamscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 phishscore=0 clxscore=1015 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201200050 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Robin Dapp via Gcc-patches From: Robin Dapp Reply-To: Robin Dapp Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, this patch is a follow-up patch to the recent ifcvt changes. It increased costs for a load on condition to 6. This ensures that we if-convert sequences of three regular instructions (of cost 4) e.g. a compare and two SETs into two loads on condition (of cost 6). With a cost of 5, four-insn sequences (three SETs) would also be if-converted. The adjustment to the mov[qi/si]cc expander makes sure we if-convert a QImode/bool. Before, combine would create a paradoxical subreg itself but need an additional insn. Bootstrapped and regtested on s390x. Is it OK? Regards Robin --- gcc/ChangeLog: * config/s390/s390.cc (s390_rtx_costs): Increase costs for load on condition. * config/s390/s390.md: Change mov[qi/si]cc expander. commit b246f96c2a2813d0e509e7916744cda07cc5131c Author: Robin Dapp Date: Fri Jun 18 10:51:22 2021 +0200 s390: Increase costs for load on condition and change movqicc expander. diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index 43c5c72554a..f2e4474df99 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -3636,7 +3636,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code, /* It is going to be a load/store on condition. Make it slightly more expensive than a normal load. */ - *total = COSTS_N_INSNS (1) + 1; + *total = COSTS_N_INSNS (1) + 2; rtx dst = SET_DEST (x); rtx then = XEXP (SET_SRC (x), 1); diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index e3ccbac58c0..5eee8e86b42 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -7003,9 +7003,9 @@ if (!CONSTANT_P (els)) els = simplify_gen_subreg (E_SImode, els, mode, 0); - rtx tmp_target = gen_reg_rtx (E_SImode); + rtx tmp_target = simplify_gen_subreg (E_SImode, operands[0], mode, 0); + emit_insn (gen_movsicc (tmp_target, operands[1], then, els)); - emit_move_insn (operands[0], gen_lowpart (mode, tmp_target)); DONE; })