From patchwork Sun Jan 16 11:49:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 50079 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CACB63858437 for ; Sun, 16 Jan 2022 11:50:08 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 71ECF3858D28 for ; Sun, 16 Jan 2022 11:49:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 71ECF3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=bBpZQ8a0sHjsC/krqPr7Obnw2Xf4KkXZuJnTkv2JRnw=; b=qMIDuglZTv9FcOKrcMKDE5j9cM t6MboEX3tGwzwVd/c4slAoJd806AsE2kB5Zkb9xeIWaguIbfcTNLddLT3/g9v1q+4h4XJpefJgxWv hSoBUK7JsELjSV+4IHijKPDAZ5NkPQ6MvsE1P2526nyC2RS3/EnQa2dy5rr0pYq7TUXE+C6XN1cq6 58zjPubuc1s4DSvNDYXh83kXCT3eYsc+Ni9ABr48q4vwX02wZE74yx7H/MZ0ArgUcdXQztsS3OoG1 s+rX6IXORXM2xZXrxLOSdQAEJjGzo13JOKtdfOkJ0WI1BaDIkfg9S+vl7fqRIkM9RrKYezA5RVw+i 4CxmewPg==; Received: from host86-160-23-130.range86-160.btcentralplus.com ([86.160.23.130]:58966 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1n942g-0001go-CD; Sun, 16 Jan 2022 06:49:50 -0500 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH] nvptx: Fix and use BI mode logic instructions (e.g. and.pred). Date: Sun, 16 Jan 2022 11:49:49 -0000 Message-ID: <026701d80acf$2be278c0$83a76a40$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdgKzOOWNeSFLxmBQc6V1ohu4iLrwg== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch adds support for nvptx's BImode and.pred, or.pred and xor.pred instructions. Technically, nvptx.md previously defined andbi3, iorbi3 and xorbi3 instructions, but the assembly language mnemonic output for these was incorrect (e.g. and.b1) and would be rejected by the ptxas assembler. The most significant part of this patch is the new define_split which teaches the compiler to actually use these instructions when appropriate (exposing the latent bug above). After https://gcc.gnu.org/pipermail/gcc-patches/2022-January/587999.html (still awaiting review/approval), the function: int foo(int x, int y) { return (x==21) && (y==69); } when compiled with -O2 produces: mov.u32 %r26, %ar0; mov.u32 %r27, %ar1; setp.eq.u32 %r31, %r26, 21; setp.eq.u32 %r34, %r27, 69; selp.u32 %r37, 1, 0, %r31; selp.u32 %r38, 1, 0, %r34; and.b32 %value, %r37, %r38; with this patch we now save an extra instruction and generate: mov.u32 %r26, %ar0; mov.u32 %r27, %ar1; setp.eq.u32 %r31, %r26, 21; setp.eq.u32 %r34, %r27, 69; and.pred %r39, %r34, %r31; selp.u32 %value, 1, 0, %r39; This patch has been tested (on top of the patch mentioned above) on nvptx-none hosted on x86_64-pc-linux-gnu (including newlib) with a make and make -k check with no new failures. Ok for mainline? 2022-01-16 Roger Sayle gcc/ChangeLog * config/nvptx/nvptx.md (any_logic): Move code iterator earlier in machine description. (logic): Move code attribute earlier in machine description. (ilogic): New code attribute, like logic but "ior" for IOR. (and3, ior3, xor3): Delete. Replace with... (3): New define_insn for HSDIM logic operations. (bi3): New define_insn for BI mode logic operations. (define_split): Lower logic operations from integer modes to BI mode predicate operations. gcc/testsuite/ChangeLog * gcc.target/nvptx/bool-2.c: New test case for and.pred. * gcc.target/nvptx/bool-3.c: New test case for or.pred. * gcc.target/nvptx/bool-4.c: New test case for xor.pred. Many thanks in advance. Roger diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index ce74672..0349c32 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -740,26 +740,38 @@ ;; Logical operations -(define_insn "and3" - [(set (match_operand:BHSDIM 0 "nvptx_register_operand" "=R") - (and:BHSDIM (match_operand:BHSDIM 1 "nvptx_register_operand" "R") - (match_operand:BHSDIM 2 "nvptx_nonmemory_operand" "Ri")))] - "" - "%.\\tand.b%T0\\t%0, %1, %2;") +(define_code_iterator any_logic [and ior xor]) +(define_code_attr logic [(and "and") (ior "or") (xor "xor")]) +(define_code_attr ilogic [(and "and") (ior "ior") (xor "xor")]) -(define_insn "ior3" - [(set (match_operand:BHSDIM 0 "nvptx_register_operand" "=R") - (ior:BHSDIM (match_operand:BHSDIM 1 "nvptx_register_operand" "R") - (match_operand:BHSDIM 2 "nvptx_nonmemory_operand" "Ri")))] +(define_insn "3" + [(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R") + (any_logic:HSDIM + (match_operand:HSDIM 1 "nvptx_register_operand" "R") + (match_operand:HSDIM 2 "nvptx_nonmemory_operand" "Ri")))] "" - "%.\\tor.b%T0\\t%0, %1, %2;") + "%.\\t.b%T0\\t%0, %1, %2;") -(define_insn "xor3" - [(set (match_operand:BHSDIM 0 "nvptx_register_operand" "=R") - (xor:BHSDIM (match_operand:BHSDIM 1 "nvptx_register_operand" "R") - (match_operand:BHSDIM 2 "nvptx_nonmemory_operand" "Ri")))] +(define_insn "bi3" + [(set (match_operand:BI 0 "nvptx_register_operand" "=R") + (any_logic:BI (match_operand:BI 1 "nvptx_register_operand" "R") + (match_operand:BI 2 "nvptx_register_operand" "R")))] "" - "%.\\txor.b%T0\\t%0, %1, %2;") + "%.\\t.pred\\t%0, %1, %2;") + +(define_split + [(set (match_operand:HSDIM 0 "nvptx_register_operand") + (any_logic:HSDIM + (ne:HSDIM (match_operand:BI 1 "nvptx_register_operand") + (const_int 0)) + (ne:HSDIM (match_operand:BI 2 "nvptx_register_operand") + (const_int 0))))] + "can_create_pseudo_p ()" + [(set (match_dup 3) (any_logic:BI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (ne:HSDIM (match_dup 3) (const_int 0)))] +{ + operands[3] = gen_reg_rtx (BImode); +}) ;; Comparisons and branches @@ -1845,9 +1857,6 @@ } [(set_attr "atomic" "true")]) -(define_code_iterator any_logic [and ior xor]) -(define_code_attr logic [(and "and") (ior "or") (xor "xor")]) - (define_insn "atomic_fetch_" [(set (match_operand:SDIM 1 "memory_operand" "+m") (unspec_volatile:SDIM diff --git a/gcc/testsuite/gcc.target/nvptx/bool-2.c b/gcc/testsuite/gcc.target/nvptx/bool-2.c new file mode 100644 index 0000000..b779248 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/bool-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x, int y) +{ + return (x==21) && (y==69); +} + +int bar(int x, int y) +{ + return (x==21) & (y==69); +} + +/* { dg-final { scan-assembler-times "and.pred" 2 } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/bool-3.c b/gcc/testsuite/gcc.target/nvptx/bool-3.c new file mode 100644 index 0000000..ab4206a --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/bool-3.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x, int y) +{ + return (x==21) || (y==69); +} + +int bar(int x, int y) +{ + return (x==21) | (y==69); +} + +/* { dg-final { scan-assembler-times "or.pred" 2 } } */ diff --git a/gcc/testsuite/gcc.target/nvptx/bool-4.c b/gcc/testsuite/gcc.target/nvptx/bool-4.c new file mode 100644 index 0000000..b588574 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/bool-4.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x, int y) +{ + return (x==21) ^ (y==69); +} + +/* { dg-final { scan-assembler "xor.pred" } } */