From patchwork Fri Jan 14 17:03:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Andre Vieira (lists)" X-Patchwork-Id: 50045 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7A90C386EC4B for ; Fri, 14 Jan 2022 17:03:46 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7A90C386EC4B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1642179826; bh=jVmstMx859mfM+rygWVH474jx3dEfeVQctNluFha+rg=; h=Date:Subject:To:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=WRnm33lmdVOIARokVuZS0GH90HE6ohqmRF8WCJiNPPBwPQa3DxtGl/9Qp6G30Rmny SyHXRdYaRyozqy4H/mH93gq8LoaM14SK4+GzwrbXzf+k72YaWeY99PeFAdJR4rq+GL qYGmWeflhXvqN4gEuxHB+0FIcwSYExGaTEyUq6WQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 7DA383858423 for ; Fri, 14 Jan 2022 17:03:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7DA383858423 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1BADB6D; Fri, 14 Jan 2022 09:03:17 -0800 (PST) Received: from [10.57.11.97] (unknown [10.57.11.97]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8596E3F766; Fri, 14 Jan 2022 09:03:16 -0800 (PST) Message-ID: <52549bc7-2784-c721-0420-67ad4d40a5ca@arm.com> Date: Fri, 14 Jan 2022 17:03:22 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.4.1 Subject: [arm] MVE: Relax addressing modes for full loads and stores Content-Language: en-US To: Christophe Lyon , gcc-patches@gcc.gnu.org References: <20220113145645.4077141-1-christophe.lyon@foss.st.com> <20220113145645.4077141-16-christophe.lyon@foss.st.com> In-Reply-To: <20220113145645.4077141-16-christophe.lyon@foss.st.com> X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, BODY_8BITS, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Andre Vieira \(lists\) via Gcc-patches" From: "Andre Vieira (lists)" Reply-To: "Andre Vieira \(lists\)" Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi Christophe, This patch relaxes the addressing modes for the mve full load and stores (by full loads and stores I mean non-widening or narrowing loads and stores resp). The code before was requiring a LO_REGNUM for these, where this is only a requirement if the load is widening or the store narrowing. So with this your patch should not be necessary. Regression tested on arm-none-eabi-gcc.  Can you please confirm this fixes the issue you were seeing too? gcc/ChangeLog:         * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.         * config/arm/arm.c (mve_vector_mem_operand): Relax constraint on         base register for non widening loads or narrowing stores. Kind Regards, Andre Vieira diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index dacce2b7f086eeffb0cd36b26f102f77130a92fa..f39786d0f9e19e81841a45f6d7e92e408272fe23 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1099,6 +1099,10 @@ extern const int arm_arch_cde_coproc_bits[]; ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ || (MODE) == V16QImode) +/* Modes used in MVE's narrowing stores or widening loads. */ +#define MVE_STN_LDW_MODE(MODE) \ + ((MODE) == V4QImode || (MODE) == V8QImode || (MODE) == V4HImode) + #define VALID_MVE_SF_MODE(MODE) \ ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index bb75921f32df6185711d5304c044ce67a2d5671e..f5e09cb00b5478546d29c05cc885aeaa89501d39 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -13438,27 +13438,28 @@ mve_vector_mem_operand (machine_mode mode, rtx op, bool strict) case E_V16QImode: case E_V8QImode: case E_V4QImode: - if (abs (val) <= 127) - return (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM) - || reg_no >= FIRST_PSEUDO_REGISTER; - return FALSE; + if (abs (val) > 127) + return FALSE; + break; case E_V8HImode: case E_V8HFmode: case E_V4HImode: case E_V4HFmode: - if (val % 2 == 0 && abs (val) <= 254) - return reg_no <= LAST_LO_REGNUM - || reg_no >= FIRST_PSEUDO_REGISTER; - return FALSE; + if (val % 2 != 0 || abs (val) > 254) + return FALSE; + break; case E_V4SImode: case E_V4SFmode: - if (val % 4 == 0 && abs (val) <= 508) - return (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM) - || reg_no >= FIRST_PSEUDO_REGISTER; - return FALSE; + if (val % 4 != 0 || abs (val) > 508) + return FALSE; + break; default: return FALSE; } + return reg_no >= FIRST_PSEUDO_REGISTER + || (MVE_STN_LDW_MODE (mode) + ? reg_no <= LAST_LO_REGNUM + : (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)); } return FALSE; }