From patchwork Wed Aug 5 08:00:43 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 140626 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CFE424BA2E23 for ; Wed, 5 Aug 2026 08:03:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CFE424BA2E23 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=HqDp/QVR X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) by sourceware.org (Postfix) with ESMTPS id 8C8A64BA2E08 for ; Wed, 5 Aug 2026 08:02:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8C8A64BA2E08 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 8C8A64BA2E08 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1785916932; cv=none; b=osw5Rl9pKsa9uCPJ4LeMEYB1l6hnrD+47RlTfWAYqOKHzb7mnIiTSI3D6WUmhCZRceopUSBKyp7UULLNJrbTtEKUcEnBBNMTcaxnkgBGFhEq0zuvM7+ED/JG2QXglAQCwpMlJMymvaLoGiMh24kekJHvSzI+R4NolvgOjSFuhaM= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1785916932; c=relaxed/simple; bh=9TNiSegsHXmaSlNxL58RPPcZfAEldUkMoQvEgapqrbw=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Uvqe4SAWbONrILr8EOHtvLnX/E3wViSGdmXl92O+MZioN4bE7uWAA89ZiBDxurUWPMiPTS2djjehTyoBiwQFmBORK5zB+xwnrFCqvJ3O99s0/pdXptio6BXPy8SytmsX1C4EDhO1m9F4lX+/kVNEsazOdPx2TvrW8SsPeYJ7lHo= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=HqDp/QVR DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C8A64BA2E08 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1785916932; x=1817452932; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9TNiSegsHXmaSlNxL58RPPcZfAEldUkMoQvEgapqrbw=; b=HqDp/QVRQKkccX2uGxO5qyz6PrgsWzECCI8Ce6moEXQqOQng1gJ2yVxD XiFQniZWit+hHdoGsHY+hJoCY63LaH1DqrqM8HerBkWcfLDDbHNPYefr6 YBDhx9YgDlyzQpkndt7bxSWaY5SN5WmrnhLa9vjD0lR5Ae2OwS0jk9q6I YpTvKm4Q7OSvIXkRlvDH3DUec8UMlwvRRFFjCUcoR1BEDTBxJNCwXVhq2 MY1NUqGrTPJm7Y/A8QkyLHsDcBs53WoKa+WQ3HxIyOkI+trfMi7XWD/vj YzgX6dR1N/fyl+cXfaKiuKYKFh7cQG5LRS0CPEnHPyw+1W1QuEwYwK9HV A==; X-CSE-ConnectionGUID: ZYwMMqRZQdW7QxHsYCtngQ== X-CSE-MsgGUID: 8OL/QgocRM+9VVpSvlimYQ== X-IronPort-AV: E=McAfee;i="6800,10657,11865"; a="90297835" X-IronPort-AV: E=Sophos;i="6.25,206,1779174000"; d="scan'208";a="90297835" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Aug 2026 01:02:07 -0700 X-CSE-ConnectionGUID: PKlmghDtRCOBZG0owDa4Gg== X-CSE-MsgGUID: EwOoEZjsRIu5IdlfIjxmhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,206,1779174000"; d="scan'208";a="258396140" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa007.fm.intel.com with ESMTP; 05 Aug 2026 01:01:49 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li , Claude Opus 5 Subject: [PATCH v1 1/3] RISC-V: Allow RVV register overlap for vwmulsu.vv Date: Wed, 5 Aug 2026 16:00:43 +0800 Message-ID: <20260805080146.2333958-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805080146.2333958-1-pan2.li@intel.com> References: <20260805080146.2333958-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Like vw{add,sub,mul}[u].vv, allow the rvv register overlap for the dual widen vv insn vwmulsu.vv. gcc/ChangeLog: * config/riscv/vector.md: Leverage Wvr constraint. Signed-off-by: Pan Li Co-Authored-By: Claude Opus 5 (1M context) --- gcc/config/riscv/vector.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index afaa3a51ece..4efee02fb3b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4303,22 +4303,22 @@ (define_insn "@pred_single_widen_sub_extended_scalar" (set_attr "mode" "")]) (define_insn "@pred_widen_mulsu" - [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr") + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VWEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 5 "vector_length_operand" " rvl, rvl") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "Wc1,Wc1, vm, vm") + (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (mult:VWEXTI (sign_extend:VWEXTI - (match_operand: 3 "register_operand" " vr, vr")) + (match_operand: 3 "register_operand" "Wvr,Wvr,Wvr,Wvr")) (zero_extend:VWEXTI - (match_operand: 4 "register_operand" " vr, vr"))) - (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 4 "register_operand" "Wvr,Wvr,Wvr,Wvr"))) + (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vwmulsu.vv\t%0,%3,%4%p1" [(set_attr "type" "viwmul") From patchwork Wed Aug 5 08:00:44 2026 Content-Type: text/plain; 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d="scan'208";a="258396142" Received: from pli28-desk.sh.intel.com ([10.238.208.139]) by fmviesa007.fm.intel.com with ESMTP; 05 Aug 2026 01:01:52 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li , Claude Opus 5 Subject: [PATCH v1 2/3] RISC-V: Add test cases for vwmulsu.vv reg overlap Date: Wed, 5 Aug 2026 16:00:44 +0800 Message-ID: <20260805080146.2333958-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805080146.2333958-1-pan2.li@intel.com> References: <20260805080146.2333958-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, PROLO_LEO1, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add test cases for register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf8.c: New test. Signed-off-by: Pan Li Co-Authored-By: Claude Opus 5 (1M context) --- .../rvv/autovec/group_overlap/group_overlap.h | 158 ++++++++++++++++++ .../autovec/group_overlap/vwmulsu_vv-i16-m1.c | 19 +++ .../autovec/group_overlap/vwmulsu_vv-i16-m2.c | 19 +++ .../autovec/group_overlap/vwmulsu_vv-i16-m4.c | 19 +++ .../group_overlap/vwmulsu_vv-i16-mf2.c | 21 +++ .../group_overlap/vwmulsu_vv-i16-mf4.c | 21 +++ .../autovec/group_overlap/vwmulsu_vv-i32-m1.c | 19 +++ .../autovec/group_overlap/vwmulsu_vv-i32-m2.c | 19 +++ .../autovec/group_overlap/vwmulsu_vv-i32-m4.c | 19 +++ .../group_overlap/vwmulsu_vv-i32-mf2.c | 21 +++ .../autovec/group_overlap/vwmulsu_vv-i8-m1.c | 19 +++ .../autovec/group_overlap/vwmulsu_vv-i8-m2.c | 19 +++ .../autovec/group_overlap/vwmulsu_vv-i8-m4.c | 19 +++ .../autovec/group_overlap/vwmulsu_vv-i8-mf2.c | 21 +++ .../autovec/group_overlap/vwmulsu_vv-i8-mf4.c | 21 +++ .../autovec/group_overlap/vwmulsu_vv-i8-mf8.c | 21 +++ 16 files changed, 455 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h index 647622cae5a..9d6e5f2b804 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/group_overlap.h @@ -391,6 +391,148 @@ ST_F ((void *)out, vd14, VL); OUT += VL; \ ST_F ((void *)out, vd15, VL); OUT += VL; \ +#define LOOP_DUAL_WIDEN_BINARY_BODY_SU_X4(NT, NUT, WT, LD_NF, \ + LD_NUF, OUT_F, ST_F, OUT, \ + START, VL) \ + NT vs0 = LD_NF ((void *)START, VL); START += VL; \ + NT vs1 = LD_NF ((void *)START, VL); START += VL; \ + NT vs2 = LD_NF ((void *)START, VL); START += VL; \ + NT vs3 = LD_NF ((void *)START, VL); START += VL; \ + NUT vt0 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt1 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt2 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt3 = LD_NUF ((void *)START, VL); START += VL; \ + \ + asm volatile("nop" ::: "memory"); \ + \ + WT vd0 = OUT_F (vs0, vt0, VL); \ + WT vd1 = OUT_F (vs1, vt1, VL); \ + WT vd2 = OUT_F (vs2, vt2, VL); \ + WT vd3 = OUT_F (vs3, vt3, VL); \ + \ + asm volatile("nop" ::: "memory"); \ + \ + ST_F ((void *)out, vd0, VL); OUT += VL; \ + ST_F ((void *)out, vd1, VL); OUT += VL; \ + ST_F ((void *)out, vd2, VL); OUT += VL; \ + ST_F ((void *)out, vd3, VL); OUT += VL; \ + +#define LOOP_DUAL_WIDEN_BINARY_BODY_SU_X8(NT, NUT, WT, LD_NF, \ + LD_NUF, OUT_F, ST_F, OUT, \ + START, VL) \ + NT vs0 = LD_NF ((void *)START, VL); START += VL; \ + NT vs1 = LD_NF ((void *)START, VL); START += VL; \ + NT vs2 = LD_NF ((void *)START, VL); START += VL; \ + NT vs3 = LD_NF ((void *)START, VL); START += VL; \ + NT vs4 = LD_NF ((void *)START, VL); START += VL; \ + NT vs5 = LD_NF ((void *)START, VL); START += VL; \ + NT vs6 = LD_NF ((void *)START, VL); START += VL; \ + NT vs7 = LD_NF ((void *)START, VL); START += VL; \ + NUT vt0 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt1 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt2 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt3 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt4 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt5 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt6 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt7 = LD_NUF ((void *)START, VL); START += VL; \ + \ + asm volatile("nop" ::: "memory"); \ + \ + WT vd0 = OUT_F (vs0, vt0, VL); \ + WT vd1 = OUT_F (vs1, vt1, VL); \ + WT vd2 = OUT_F (vs2, vt2, VL); \ + WT vd3 = OUT_F (vs3, vt3, VL); \ + WT vd4 = OUT_F (vs4, vt4, VL); \ + WT vd5 = OUT_F (vs5, vt5, VL); \ + WT vd6 = OUT_F (vs6, vt6, VL); \ + WT vd7 = OUT_F (vs7, vt7, VL); \ + \ + asm volatile("nop" ::: "memory"); \ + \ + ST_F ((void *)out, vd0, VL); OUT += VL; \ + ST_F ((void *)out, vd1, VL); OUT += VL; \ + ST_F ((void *)out, vd2, VL); OUT += VL; \ + ST_F ((void *)out, vd3, VL); OUT += VL; \ + ST_F ((void *)out, vd4, VL); OUT += VL; \ + ST_F ((void *)out, vd5, VL); OUT += VL; \ + ST_F ((void *)out, vd6, VL); OUT += VL; \ + ST_F ((void *)out, vd7, VL); OUT += VL; \ + +#define LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16(NT, NUT, WT, LD_NF, \ + LD_NUF, OUT_F, ST_F, OUT, \ + START, VL) \ + NT vs0 = LD_NF ((void *)START, VL); START += VL; \ + NT vs1 = LD_NF ((void *)START, VL); START += VL; \ + NT vs2 = LD_NF ((void *)START, VL); START += VL; \ + NT vs3 = LD_NF ((void *)START, VL); START += VL; \ + NT vs4 = LD_NF ((void *)START, VL); START += VL; \ + NT vs5 = LD_NF ((void *)START, VL); START += VL; \ + NT vs6 = LD_NF ((void *)START, VL); START += VL; \ + NT vs7 = LD_NF ((void *)START, VL); START += VL; \ + NT vs8 = LD_NF ((void *)START, VL); START += VL; \ + NT vs9 = LD_NF ((void *)START, VL); START += VL; \ + NT vs10 = LD_NF ((void *)START, VL); START += VL; \ + NT vs11 = LD_NF ((void *)START, VL); START += VL; \ + NT vs12 = LD_NF ((void *)START, VL); START += VL; \ + NT vs13 = LD_NF ((void *)START, VL); START += VL; \ + NT vs14 = LD_NF ((void *)START, VL); START += VL; \ + NT vs15 = LD_NF ((void *)START, VL); START += VL; \ + NUT vt0 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt1 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt2 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt3 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt4 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt5 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt6 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt7 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt8 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt9 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt10 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt11 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt12 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt13 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt14 = LD_NUF ((void *)START, VL); START += VL; \ + NUT vt15 = LD_NUF ((void *)START, VL); START += VL; \ + \ + asm volatile("nop" ::: "memory"); \ + \ + WT vd0 = OUT_F (vs0, vt0, VL); \ + WT vd1 = OUT_F (vs1, vt1, VL); \ + WT vd2 = OUT_F (vs2, vt2, VL); \ + WT vd3 = OUT_F (vs3, vt3, VL); \ + WT vd4 = OUT_F (vs4, vt4, VL); \ + WT vd5 = OUT_F (vs5, vt5, VL); \ + WT vd6 = OUT_F (vs6, vt6, VL); \ + WT vd7 = OUT_F (vs7, vt7, VL); \ + WT vd8 = OUT_F (vs8, vt8, VL); \ + WT vd9 = OUT_F (vs9, vt9, VL); \ + WT vd10 = OUT_F (vs10, vt10, VL); \ + WT vd11 = OUT_F (vs11, vt11, VL); \ + WT vd12 = OUT_F (vs12, vt12, VL); \ + WT vd13 = OUT_F (vs13, vt13, VL); \ + WT vd14 = OUT_F (vs14, vt14, VL); \ + WT vd15 = OUT_F (vs15, vt15, VL); \ + \ + asm volatile("nop" ::: "memory"); \ + \ + ST_F ((void *)out, vd0, VL); OUT += VL; \ + ST_F ((void *)out, vd1, VL); OUT += VL; \ + ST_F ((void *)out, vd2, VL); OUT += VL; \ + ST_F ((void *)out, vd3, VL); OUT += VL; \ + ST_F ((void *)out, vd4, VL); OUT += VL; \ + ST_F ((void *)out, vd5, VL); OUT += VL; \ + ST_F ((void *)out, vd6, VL); OUT += VL; \ + ST_F ((void *)out, vd7, VL); OUT += VL; \ + ST_F ((void *)out, vd8, VL); OUT += VL; \ + ST_F ((void *)out, vd9, VL); OUT += VL; \ + ST_F ((void *)out, vd10, VL); OUT += VL; \ + ST_F ((void *)out, vd11, VL); OUT += VL; \ + ST_F ((void *)out, vd12, VL); OUT += VL; \ + ST_F ((void *)out, vd13, VL); OUT += VL; \ + ST_F ((void *)out, vd14, VL); OUT += VL; \ + ST_F ((void *)out, vd15, VL); OUT += VL; \ + #define DEF_GROUP_OVERLAP_UNARY_0(VL_F, NT, WT, LD_F, OUT_F, ST_F, NAME, \ LOOP_BODY) \ void test_group_overlap_##NAME##_##NT##_unary_0(uint8_t *data, \ @@ -436,4 +578,20 @@ } \ } +#define DEF_GROUP_OVERLAP_BINARY_2(VL_F, NT, NUT, WT, LD_NF, LD_NUF, \ + OUT_F, ST_F, NAME, LOOP_BODY) \ + void test_group_overlap_##NAME##_##NT##_binary_2(uint8_t *data, \ + uint8_t *out, \ + size_t limit) \ + { \ + uint8_t *start = data; \ + uint8_t *end = data + limit; \ + size_t vl = VL_F (); \ + \ + while (start < end) { \ + LOOP_BODY (NT, NUT, WT, LD_NF, LD_NUF, OUT_F, ST_F, out, start, \ + vl); \ + } \ + } + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m1.c new file mode 100644 index 00000000000..81210f52f94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e16m1, + vint16m1_t, + vuint16m1_t, + vint32m2_t, + __riscv_vle16_v_i16m1, + __riscv_vle16_v_u16m1, + __riscv_vwmulsu_vv_i32m2, + __riscv_vse32_v_i32m2, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m2.c new file mode 100644 index 00000000000..3711878cb90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e16m2, + vint16m2_t, + vuint16m2_t, + vint32m4_t, + __riscv_vle16_v_i16m2, + __riscv_vle16_v_u16m2, + __riscv_vwmulsu_vv_i32m4, + __riscv_vse32_v_i32m4, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X8) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m4.c new file mode 100644 index 00000000000..69b895e2c68 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-m4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e16m4, + vint16m4_t, + vuint16m4_t, + vint32m8_t, + __riscv_vle16_v_i16m4, + __riscv_vle16_v_u16m4, + __riscv_vwmulsu_vv_i32m8, + __riscv_vse32_v_i32m8, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X4) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf2.c new file mode 100644 index 00000000000..49df7b7005f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e16m1, + vint16mf2_t, + vuint16mf2_t, + vint32m1_t, + __riscv_vle16_v_i16mf2, + __riscv_vle16_v_u16mf2, + __riscv_vwmulsu_vv_i32m1, + __riscv_vse32_v_i32m1, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf4.c new file mode 100644 index 00000000000..07d927d87cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i16-mf4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e16m1, + vint16mf4_t, + vuint16mf4_t, + vint32mf2_t, + __riscv_vle16_v_i16mf4, + __riscv_vle16_v_u16mf4, + __riscv_vwmulsu_vv_i32mf2, + __riscv_vse32_v_i32mf2, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m1.c new file mode 100644 index 00000000000..9c5a435b58e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e32m1, + vint32m1_t, + vuint32m1_t, + vint64m2_t, + __riscv_vle32_v_i32m1, + __riscv_vle32_v_u32m1, + __riscv_vwmulsu_vv_i64m2, + __riscv_vse64_v_i64m2, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m2.c new file mode 100644 index 00000000000..833b8906083 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e32m2, + vint32m2_t, + vuint32m2_t, + vint64m4_t, + __riscv_vle32_v_i32m2, + __riscv_vle32_v_u32m2, + __riscv_vwmulsu_vv_i64m4, + __riscv_vse64_v_i64m4, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X8) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m4.c new file mode 100644 index 00000000000..a769b55966e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-m4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e32m4, + vint32m4_t, + vuint32m4_t, + vint64m8_t, + __riscv_vle32_v_i32m4, + __riscv_vle32_v_u32m4, + __riscv_vwmulsu_vv_i64m8, + __riscv_vse64_v_i64m8, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X4) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-mf2.c new file mode 100644 index 00000000000..50b37333588 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i32-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e32m1, + vint32mf2_t, + vuint32mf2_t, + vint64m1_t, + __riscv_vle32_v_i32mf2, + __riscv_vle32_v_u32mf2, + __riscv_vwmulsu_vv_i64m1, + __riscv_vse64_v_i64m1, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m1.c new file mode 100644 index 00000000000..383d29f26f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e8m1, + vint8m1_t, + vuint8m1_t, + vint16m2_t, + __riscv_vle8_v_i8m1, + __riscv_vle8_v_u8m1, + __riscv_vwmulsu_vv_i16m2, + __riscv_vse16_v_i16m2, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m2.c new file mode 100644 index 00000000000..d9de8bae64a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m2.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e8m2, + vint8m2_t, + vuint8m2_t, + vint16m4_t, + __riscv_vle8_v_i8m2, + __riscv_vle8_v_u8m2, + __riscv_vwmulsu_vv_i16m4, + __riscv_vse16_v_i16m4, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X8) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m4.c new file mode 100644 index 00000000000..4360d79e313 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-m4.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e8m4, + vint8m4_t, + vuint8m4_t, + vint16m8_t, + __riscv_vle8_v_i8m4, + __riscv_vle8_v_u8m4, + __riscv_vwmulsu_vv_i16m8, + __riscv_vse16_v_i16m8, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X4) + +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vwmulsu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf2.c new file mode 100644 index 00000000000..6691f4f6b8e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e8m1, + vint8mf2_t, + vuint8mf2_t, + vint16m1_t, + __riscv_vle8_v_i8mf2, + __riscv_vle8_v_u8mf2, + __riscv_vwmulsu_vv_i16m1, + __riscv_vse16_v_i16m1, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf4.c new file mode 100644 index 00000000000..7c0a16085c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e8m1, + vint8mf4_t, + vuint8mf4_t, + vint16mf2_t, + __riscv_vle8_v_i8mf4, + __riscv_vle8_v_u8mf4, + __riscv_vwmulsu_vv_i16mf2, + __riscv_vse16_v_i16mf2, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf8.c new file mode 100644 index 00000000000..bba41cf3011 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwmulsu_vv-i8-mf8.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_BINARY_2( + __riscv_vsetvlmax_e8m1, + vint8mf8_t, + vuint8mf8_t, + vint16mf4_t, + __riscv_vle8_v_i8mf8, + __riscv_vle8_v_u8mf8, + __riscv_vwmulsu_vv_i16mf4, + __riscv_vse16_v_i16mf4, + vwmulsu_vv, + LOOP_DUAL_WIDEN_BINARY_BODY_SU_X16) + +/* The fractional LMUL source has EMUL < 1, thus the widened destination + register group must not overlap either source at all. */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),\1,} } } */ +/* { dg-final { scan-assembler-not {vwmulsu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */ From patchwork Wed Aug 5 08:00:45 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 140629 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 13CA84BAE7D2 for ; Wed, 5 Aug 2026 08:05:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 13CA84BAE7D2 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com 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kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li , Claude Opus 5 Subject: [PATCH v1 3/3] RISC-V: Add more test cases for vwmulsu.vv Date: Wed, 5 Aug 2026 16:00:45 +0800 Message-ID: <20260805080146.2333958-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260805080146.2333958-1-pan2.li@intel.com> References: <20260805080146.2333958-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li For csrr not asm check when enable overlap enabled. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-48.c: New test. Signed-off-by: Pan Li Co-Authored-By: Claude Opus 5 (1M context) --- .../gcc.target/riscv/rvv/base/pr112431-48.c | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c new file mode 100644 index 00000000000..17631c347b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-48.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (void *in, void *out, int n) +{ + for (int i = 0; i < n; i++) + { + asm volatile("nop" ::: "memory"); + vint16m4_t v0 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v0_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v0, 1)); + vuint8m2_t v0_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v0_n); + v0 = __riscv_vwmulsu_vv_i16m4_tu (v0, v0_n, v0_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v1 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v1_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v1, 1)); + vuint8m2_t v1_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v1_n); + v1 = __riscv_vwmulsu_vv_i16m4_tu (v1, v1_n, v1_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v2 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v2_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v2, 1)); + vuint8m2_t v2_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v2_n); + v2 = __riscv_vwmulsu_vv_i16m4_tu (v2, v2_n, v2_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v3 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v3_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v3, 1)); + vuint8m2_t v3_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v3_n); + v3 = __riscv_vwmulsu_vv_i16m4_tu (v3, v3_n, v3_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v4 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v4_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v4, 1)); + vuint8m2_t v4_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v4_n); + v4 = __riscv_vwmulsu_vv_i16m4_tu (v4, v4_n, v4_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v5 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v5_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v5, 1)); + vuint8m2_t v5_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v5_n); + v5 = __riscv_vwmulsu_vv_i16m4_tu (v5, v5_n, v5_nu, 4); + asm volatile("nop" ::: "memory"); + vint16m4_t v6 = __riscv_vle16_v_i16m4 (in, 4);in+=100; + vint8m2_t v6_n = __riscv_vreinterpret_v_i16m2_i8m2 (__riscv_vget_v_i16m4_i16m2 (v6, 1)); + vuint8m2_t v6_nu = __riscv_vreinterpret_v_i8m2_u8m2 (v6_n); + v6 = __riscv_vwmulsu_vv_i16m4_tu (v6, v6_n, v6_nu, 4); + asm volatile("nop" ::: "memory"); + vint8m2_t v7_n = __riscv_vle8_v_i8m2 (in, 4);in+=100; + vint16m4_t v7 = __riscv_vwcvt_x_x_v_i16m4 (v7_n, 4); + + asm volatile("nop" ::: "memory"); + __riscv_vsse16_v_i16m4 (out, 4, v0, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v1, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v2, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v3, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v4, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v5, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v6, 4);out+=100; + __riscv_vsse16_v_i16m4 (out, 4, v7, 4);out+=100; + } +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv2r} } } */ +/* { dg-final { scan-assembler-not {vmv4r} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {vmv8r} } } */ +/* { dg-final { scan-assembler-not {csrr} } } */