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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af6a14csm56383065e9.5.2026.07.24.03.14.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:14:01 -0700 (PDT) Message-ID: <626f1b57-dd4e-4d04-af71-ceaeb65b92db@suse.com> Date: Fri, 24 Jul 2026 12:14:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 1/4] x86: copy template's .operand_types[] into global insn data From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This is to reduce the churn by a subsequent change, where .operand_types[] is to no longer be directly embedded in the templates. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -306,6 +306,9 @@ struct _i386_insn /* TM holds the template for the insn were currently assembling. */ insn_template tm; + /* TM_TYPES are the operand types as referenced by TM. */ + i386_operand_type tm_types[MAX_OPERANDS]; + /* SUFFIX holds the instruction size suffix for byte, word, dword or qword, if given. */ char suffix; @@ -4236,6 +4239,9 @@ install_template (const insn_template *t i.tm = *t; + for (l = 0; l < t->operands; ++l) + i.tm_types[l] = t->operand_types[l]; + /* Dual VEX/EVEX templates need stripping one of the possible variants. */ if (t->opcode_modifier.vex && t->opcode_modifier.evex) { @@ -4645,9 +4651,9 @@ build_evex_prefix (void) /* Determine vector length from the last multi-length vector operand. */ for (op = i.operands; op--;) - if (i.tm.operand_types[op].bitfield.xmmword - + i.tm.operand_types[op].bitfield.ymmword - + i.tm.operand_types[op].bitfield.zmmword > 1) + if (i.tm_types[op].bitfield.xmmword + + i.tm_types[op].bitfield.ymmword + + i.tm_types[op].bitfield.zmmword > 1) { if (i.types[op].bitfield.zmmword) { @@ -5132,7 +5138,7 @@ optimize_encoding (void) i.op[0].disps->X_add_number &= 0xffff; } - i.tm.operand_types[0] = i.types[0]; + i.tm_types[0] = i.types[0]; i.imm_operands = 1; if (!i.op[0].imms) { @@ -5236,7 +5242,7 @@ optimize_encoding (void) with the register number being 0 (i.e. not altering the opcode). */ i.reg_operands = 1; i.op[0].regs = i.op[1].regs; - i.tm.operand_types[1].bitfield.class = ClassNone; + i.tm_types[1].bitfield.class = ClassNone; return; } @@ -5278,8 +5284,8 @@ optimize_encoding (void) i.op[0].imms = &im_expressions[0]; operand_type_set (&i.types[0], 0); i.types[0].bitfield.imm8 = 1; - i.tm.operand_types[0] = i.types[0]; - i.tm.operand_types[0].bitfield.class = ClassNone; + i.tm_types[0] = i.types[0]; + i.tm_types[0].bitfield.class = ClassNone; i.imm_operands = 1; i.suffix = 0; @@ -5296,7 +5302,7 @@ optimize_encoding (void) i.base_reg = i.op[0].regs; operand_type_set (&i.types[0], 0); i.types[0].bitfield.baseindex = 1; - i.tm.operand_types[0] = i.types[0]; + i.tm_types[0] = i.types[0]; i.op[0].disps = NULL; i.flags[0] = Operand_Mem; i.mem_operands = 1; @@ -5405,9 +5411,9 @@ optimize_encoding (void) movq $imm31, %r64 -> movl $imm31, %r32 movq $imm32, %r64 -> movl $imm32, %r32 */ - i.tm.operand_types[0].bitfield.imm32 = 1; - i.tm.operand_types[0].bitfield.imm32s = 0; - i.tm.operand_types[0].bitfield.imm64 = 0; + i.tm_types[0].bitfield.imm32 = 1; + i.tm_types[0].bitfield.imm32s = 0; + i.tm_types[0].bitfield.imm64 = 0; if ((i.tm.base_opcode | 1) == 0xc7) { /* Handle @@ -5581,7 +5587,7 @@ optimize_encoding (void) && (pp.encoding != encoding_evex || cpu_arch_isa_flags.bitfield.cpuavx512vl || is_cpu (&i.tm, CpuAVX512VL) - || (i.tm.operand_types[2].bitfield.zmmword + || (i.tm_types[2].bitfield.zmmword && i.types[2].bitfield.ymmword)))) && i.tm.opcode_space == SPACE_0F && ((i.tm.base_opcode | 2) == 0x57 @@ -5641,7 +5647,7 @@ optimize_encoding (void) else return; } - else if (i.tm.operand_types[0].bitfield.class == RegMask) + else if (i.tm_types[0].bitfield.class == RegMask) { i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; i.tm.opcode_modifier.vexw = VEXW0; @@ -5819,7 +5825,7 @@ optimize_encoding (void) i.tm.base_opcode |= 0xfc; /* {,v}padd{w,d} */ else { - gas_assert (i.tm.operand_types[1].bitfield.class != RegMMX); + gas_assert (i.tm_types[1].bitfield.class != RegMMX); i.tm.base_opcode = 0xd4; /* {,v}paddq */ } i.tm.extension_opcode = None; @@ -6101,13 +6107,13 @@ optimize_nf_encoding (void) i.tm.opcode_modifier.w = 0; i.op[0].imms->X_add_number = -i.op[0].imms->X_add_number; - i.tm.operand_types[0].bitfield.imm8 = 0; - i.tm.operand_types[0].bitfield.imm8s = 1; - i.tm.operand_types[0].bitfield.imm16 = 0; - i.tm.operand_types[0].bitfield.imm32 = 0; - i.tm.operand_types[0].bitfield.imm32s = 0; + i.tm_types[0].bitfield.imm8 = 0; + i.tm_types[0].bitfield.imm8s = 1; + i.tm_types[0].bitfield.imm16 = 0; + i.tm_types[0].bitfield.imm32 = 0; + i.tm_types[0].bitfield.imm32s = 0; - i.types[0] = i.tm.operand_types[0]; + i.types[0] = i.tm_types[0]; } else if ((i.tm.base_opcode | 3) == 0x83 && (i.tm.extension_opcode == 0 || i.tm.extension_opcode == 5) @@ -6158,7 +6164,7 @@ optimize_nf_encoding (void) gas_assert (i.tm.extension_opcode <= 1); i.tm.extension_opcode ^= 1; i.tm.base_opcode = 0xd0; - i.tm.operand_types[0].bitfield.imm1 = 1; + i.tm_types[0].bitfield.imm1 = 1; i.imm_operands = 0; } else if ((i.tm.base_opcode | 2) == 0x6b @@ -6193,17 +6199,17 @@ optimize_nf_encoding (void) { i.tm.base_opcode = 0xc0; i.op[0].imms->X_add_number = ffs (i.op[0].imms->X_add_number) - 1; - i.tm.operand_types[0].bitfield.imm8 = 1; - i.tm.operand_types[0].bitfield.imm16 = 0; - i.tm.operand_types[0].bitfield.imm32 = 0; - i.tm.operand_types[0].bitfield.imm32s = 0; + i.tm_types[0].bitfield.imm8 = 1; + i.tm_types[0].bitfield.imm16 = 0; + i.tm_types[0].bitfield.imm32 = 0; + i.tm_types[0].bitfield.imm32s = 0; } else { i.tm.base_opcode = 0xd0; - i.tm.operand_types[0].bitfield.imm1 = 1; + i.tm_types[0].bitfield.imm1 = 1; } - i.types[0] = i.tm.operand_types[0]; + i.types[0] = i.tm_types[0]; i.tm.extension_opcode = 4; i.tm.opcode_modifier.w = 1; i.tm.opcode_modifier.operandconstraint = 0; @@ -6297,7 +6303,7 @@ optimize_nf_encoding (void) operand_type_set (&i.types[0], 0); i.types[0].bitfield.baseindex = 1; - i.tm.operand_types[0] = i.types[0]; + i.tm_types[0] = i.types[0]; i.op[0].disps = NULL; i.flags[0] = Operand_Mem; @@ -6364,7 +6370,7 @@ optimize_nf_encoding (void) i.op[0].disps = i.op[0].imms; i.flags[0] = Operand_Mem; optimize_disp (&i.tm); - i.tm.operand_types[0] = i.types[0]; + i.tm_types[0] = i.types[0]; i.operands = 2; i.disp_operands = i.mem_operands = i.reg_operands = 1; @@ -6413,7 +6419,7 @@ optimize_nf_encoding (void) operand_type_set (&i.types[0], 0); i.types[0].bitfield.baseindex = 1; - i.tm.operand_types[0] = i.types[0]; + i.tm_types[0] = i.types[0]; i.op[0].disps = NULL; i.flags[0] = Operand_Mem; @@ -6438,13 +6444,13 @@ optimize_nf_encoding (void) {nf} %cl, ..., %rN -> x %{e,r}cx, ..., %rN (no eGPR used) */ gas_assert (i.tm.extension_opcode & 4); - i.tm.operand_types[0] = i.tm.operand_types[i.operands - 1]; + i.tm_types[0] = i.tm_types[i.operands - 1]; /* NB: i.op[0].regs specifying %cl is good enough. */ i.types[0] = i.types[i.operands - 1]; if (i.operands == 2) { - i.tm.operand_types[0].bitfield.baseindex = 0; - i.tm.operand_types[2] = i.tm.operand_types[0]; + i.tm_types[0].bitfield.baseindex = 0; + i.tm_types[2] = i.tm_types[0]; i.op[2].regs = i.op[1].regs; i.types[2] = i.types[1]; i.reg_operands = i.operands = 3; @@ -6479,7 +6485,7 @@ optimize_nf_encoding (void) if (i.operands == 2) { copy_operand (2, 1); - i.tm.operand_types[2].bitfield.baseindex = 0; + i.tm_types[2].bitfield.baseindex = 0; i.reg_operands = 2; i.operands = 3; } @@ -6509,9 +6515,9 @@ optimize_nf_encoding (void) {nf} mul %edx -> mulx %eax, %eax, %edx {nf} mul %rdx -> mulx %rax, %rax, %rdx */ - i.tm.operand_types[1] = i.tm.operand_types[0]; - i.tm.operand_types[1].bitfield.baseindex = 0; - i.tm.operand_types[2] = i.tm.operand_types[1]; + i.tm_types[1] = i.tm_types[0]; + i.tm_types[1].bitfield.baseindex = 0; + i.tm_types[2] = i.tm_types[1]; i.op[2].regs = i.op[0].regs; /* NB: %eax is good enough also for 64-bit operand size. */ i.op[1].regs = i.op[0].regs = reg_eax; @@ -7594,8 +7600,8 @@ i386_assemble (char *line) #endif if ((is_any_vex_encoding (&i.tm) && i.tm.opcode_space != SPACE_MAP4) - || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX - || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX + || i.tm_types[i.imm_operands].bitfield.class >= RegMMX + || i.tm_types[i.imm_operands + 1].bitfield.class >= RegMMX || is_padlock(&i.tm)) { /* Check for data size prefix on VEX/XOP/EVEX encoded, SIMD, and @@ -7696,8 +7702,8 @@ i386_assemble (char *line) { enum operand_class class = i.types[j].bitfield.class; - i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); - switch (i.tm.operand_types[j].bitfield.class) + i.types[j] = operand_type_and (i.types[j], i.tm_types[j]); + switch (i.tm_types[j].bitfield.class) { default: break; @@ -7708,16 +7714,16 @@ i386_assemble (char *line) i.xstate |= xstate_mask; break; case RegSIMD: - if (i.tm.operand_types[j].bitfield.tmmword) + if (i.tm_types[j].bitfield.tmmword) i.xstate |= xstate_tmm; - else if (i.tm.operand_types[j].bitfield.zmmword + else if (i.tm_types[j].bitfield.zmmword && !i.tm.opcode_modifier.vex && vector_size >= VSZ512) i.xstate |= xstate_zmm; - else if (i.tm.operand_types[j].bitfield.ymmword + else if (i.tm_types[j].bitfield.ymmword && vector_size >= VSZ256) i.xstate |= xstate_ymm; - else if (i.tm.operand_types[j].bitfield.xmmword) + else if (i.tm_types[j].bitfield.xmmword) i.xstate |= xstate_xmm; break; case ClassNone: @@ -8424,7 +8430,7 @@ static void copy_operand (unsigned int to, unsigned int from) { i.types[to] = i.types[from]; - i.tm.operand_types[to] = i.tm.operand_types[from]; + i.tm_types[to] = i.tm_types[from]; i.flags[to] = i.flags[from]; i.op[to] = i.op[from]; i.reloc[to] = i.reloc[from]; @@ -10073,7 +10079,7 @@ match_template (char mnem_suffix) install_template (t); if (addr_prefix_disp != -1) - i.tm.operand_types[addr_prefix_disp] + i.tm_types[addr_prefix_disp] = operand_types[addr_prefix_disp]; /* APX insns acting on byte operands are WIG, yet that can't be expressed @@ -10119,8 +10125,8 @@ match_template (char mnem_suffix) if (i.tm.opcode_space == SPACE_MAP4 && !t->opcode_modifier.commutative) i.tm.opcode_modifier.operandconstraint = EVEX_NF; - i.tm.operand_types[0] = operand_types[i.operands - 1]; - i.tm.operand_types[i.operands - 1] = operand_types[0]; + i.tm_types[0] = operand_types[i.operands - 1]; + i.tm_types[i.operands - 1] = operand_types[0]; break; case Opcode_VexW: @@ -10132,9 +10138,9 @@ match_template (char mnem_suffix) i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1; swap_first_2: - j = i.tm.operand_types[0].bitfield.imm8; - i.tm.operand_types[j] = operand_types[j + 1]; - i.tm.operand_types[j + 1] = operand_types[j]; + j = i.tm_types[0].bitfield.imm8; + i.tm_types[j] = operand_types[j + 1]; + i.tm_types[j + 1] = operand_types[j]; break; } @@ -10145,7 +10151,7 @@ static int check_string (void) { unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; - unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; + unsigned int op = i.tm_types[0].bitfield.baseindex ? es_op : 0; if (i.seg[op] != NULL && i.seg[op] != reg_es) { @@ -10198,7 +10204,7 @@ process_suffix (const insn_template *t) --i.operands; /* crc32 needs REX.W set regardless of suffix / source operand size. */ - if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword) + if (i.tm.mnem_off == MN_crc32 && i.tm_types[1].bitfield.qword) i.rex |= REX_W; /* If there's no instruction mnemonic suffix we try to invent one @@ -10212,8 +10218,8 @@ process_suffix (const insn_template *t) unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands; while (op--) - if (i.tm.operand_types[op].bitfield.instance == InstanceNone - || i.tm.operand_types[op].bitfield.instance == Accum) + if (i.tm_types[op].bitfield.instance == InstanceNone + || i.tm_types[op].bitfield.instance == Accum) { if (i.types[op].bitfield.class != Reg) continue; @@ -10386,33 +10392,33 @@ process_suffix (const insn_template *t) { if (vector_size < VSZ512) { - i.tm.operand_types[op].bitfield.zmmword = 0; + i.tm_types[op].bitfield.zmmword = 0; if (vector_size < VSZ256) { - i.tm.operand_types[op].bitfield.ymmword = 0; - if (i.tm.operand_types[op].bitfield.xmmword + i.tm_types[op].bitfield.ymmword = 0; + if (i.tm_types[op].bitfield.xmmword && i.tm.opcode_modifier.evex == EVEXDYN) i.tm.opcode_modifier.evex = EVEX128; } - else if (i.tm.operand_types[op].bitfield.ymmword - && !i.tm.operand_types[op].bitfield.xmmword + else if (i.tm_types[op].bitfield.ymmword + && !i.tm_types[op].bitfield.xmmword && i.tm.opcode_modifier.evex == EVEXDYN) i.tm.opcode_modifier.evex = EVEX256; } else if (i.tm.opcode_modifier.evex && !cpu_arch_flags.bitfield.cpuavx512vl) { - if (i.tm.operand_types[op].bitfield.ymmword) - i.tm.operand_types[op].bitfield.xmmword = 0; - if (i.tm.operand_types[op].bitfield.zmmword) - i.tm.operand_types[op].bitfield.ymmword = 0; + if (i.tm_types[op].bitfield.ymmword) + i.tm_types[op].bitfield.xmmword = 0; + if (i.tm_types[op].bitfield.zmmword) + i.tm_types[op].bitfield.ymmword = 0; if (i.tm.opcode_modifier.evex == EVEXDYN) i.tm.opcode_modifier.evex = EVEX512; } - if (i.tm.operand_types[op].bitfield.xmmword - + i.tm.operand_types[op].bitfield.ymmword - + i.tm.operand_types[op].bitfield.zmmword < 2) + if (i.tm_types[op].bitfield.xmmword + + i.tm_types[op].bitfield.ymmword + + i.tm_types[op].bitfield.zmmword < 2) continue; /* Any properly sized operand disambiguates the insn. */ @@ -10426,13 +10432,13 @@ process_suffix (const insn_template *t) } if ((i.flags[op] & Operand_Mem) - && i.tm.operand_types[op].bitfield.unspecified) + && i.tm_types[op].bitfield.unspecified) { - if (i.tm.operand_types[op].bitfield.xmmword) + if (i.tm_types[op].bitfield.xmmword) suffixes |= 1 << 6; - if (i.tm.operand_types[op].bitfield.ymmword) + if (i.tm_types[op].bitfield.ymmword) suffixes |= 1 << 7; - if (i.tm.operand_types[op].bitfield.zmmword) + if (i.tm_types[op].bitfield.zmmword) suffixes |= 1 << 8; if (i.tm.opcode_modifier.evex) evex = EVEX512; @@ -10505,8 +10511,8 @@ process_suffix (const insn_template *t) } if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) - i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) - != (i.tm.operand_types[1].bitfield.class == Reg); + i.short_form = (i.tm_types[0].bitfield.class == Reg) + != (i.tm_types[1].bitfield.class == Reg); /* Change the opcode based on the operand size given by i.suffix. */ switch (i.suffix) @@ -10587,10 +10593,10 @@ process_suffix (const insn_template *t) && (!i.reg_operands || (i.reg_operands == 1 /* ShiftCount */ - && (i.tm.operand_types[0].bitfield.instance == RegC + && (i.tm_types[0].bitfield.instance == RegC /* InOutPortReg */ - || i.tm.operand_types[0].bitfield.instance == RegD - || i.tm.operand_types[1].bitfield.instance == RegD + || i.tm_types[0].bitfield.instance == RegD + || i.tm_types[1].bitfield.instance == RegD || i.tm.mnem_off == MN_crc32)))) i.tm.base_opcode |= 1; break; @@ -10601,7 +10607,7 @@ process_suffix (const insn_template *t) gas_assert (!i.suffix); gas_assert (i.reg_operands); - if (i.tm.operand_types[0].bitfield.instance == Accum + if (i.tm_types[0].bitfield.instance == Accum || i.operands == 1) { /* The address size override prefix changes the size of the @@ -10707,8 +10713,8 @@ check_byte_reg (void) } /* I/O port address operands are OK too. */ - if (i.tm.operand_types[op].bitfield.instance == RegD - && i.tm.operand_types[op].bitfield.word) + if (i.tm_types[op].bitfield.instance == RegD + && i.tm_types[op].bitfield.word) continue; /* crc32 only wants its source operand checked here. */ @@ -10736,9 +10742,9 @@ check_long_reg (void) /* Reject eight bit registers, except where the template requires them. (eg. movzb) */ else if (i.types[op].bitfield.byte - && (i.tm.operand_types[op].bitfield.word - || i.tm.operand_types[op].bitfield.dword - || i.tm.operand_types[op].bitfield.qword)) + && (i.tm_types[op].bitfield.word + || i.tm_types[op].bitfield.dword + || i.tm_types[op].bitfield.qword)) { as_bad (_("`%s%s' not allowed with `%s%c'"), register_prefix, @@ -10751,7 +10757,7 @@ check_long_reg (void) prefix on a general reg is present. */ else if ((i.types[op].bitfield.word || i.types[op].bitfield.qword) - && i.tm.operand_types[op].bitfield.dword) + && i.tm_types[op].bitfield.dword) { as_bad (_("incorrect register `%s%s' used with `%c' suffix"), register_prefix, i.op[op].regs->reg_name, @@ -10776,9 +10782,9 @@ check_qword_reg (void) /* Reject eight bit registers, except where the template requires them. (eg. movzb) */ else if (i.types[op].bitfield.byte - && (i.tm.operand_types[op].bitfield.word - || i.tm.operand_types[op].bitfield.dword - || i.tm.operand_types[op].bitfield.qword)) + && (i.tm_types[op].bitfield.word + || i.tm_types[op].bitfield.dword + || i.tm_types[op].bitfield.qword)) { as_bad (_("`%s%s' not allowed with `%s%c'"), register_prefix, @@ -10790,7 +10796,7 @@ check_qword_reg (void) /* Error if the r prefix on a general reg is missing. */ else if ((i.types[op].bitfield.word || i.types[op].bitfield.dword) - && i.tm.operand_types[op].bitfield.qword) + && i.tm_types[op].bitfield.qword) { as_bad (_("incorrect register `%s%s' used with `%c' suffix"), register_prefix, i.op[op].regs->reg_name, i.suffix); @@ -10813,9 +10819,9 @@ check_word_reg (void) /* Reject eight bit registers, except where the template requires them. (eg. movzb) */ else if (i.types[op].bitfield.byte - && (i.tm.operand_types[op].bitfield.word - || i.tm.operand_types[op].bitfield.dword - || i.tm.operand_types[op].bitfield.qword)) + && (i.tm_types[op].bitfield.word + || i.tm_types[op].bitfield.dword + || i.tm_types[op].bitfield.qword)) { as_bad (_("`%s%s' not allowed with `%s%c'"), register_prefix, @@ -10827,7 +10833,7 @@ check_word_reg (void) /* Error if the e or r prefix on a general reg is present. */ else if ((i.types[op].bitfield.dword || i.types[op].bitfield.qword) - && i.tm.operand_types[op].bitfield.word) + && i.tm_types[op].bitfield.word) { as_bad (_("incorrect register `%s%s' used with `%c' suffix"), register_prefix, i.op[op].regs->reg_name, @@ -10845,8 +10851,8 @@ update_imm (unsigned int j) { i386_operand_type overlap = i.types[j]; - if (i.tm.operand_types[j].bitfield.imm8 - && i.tm.operand_types[j].bitfield.imm8s + if (i.tm_types[j].bitfield.imm8 + && i.tm_types[j].bitfield.imm8s && overlap.bitfield.imm8 && overlap.bitfield.imm8s) { /* This combination is used on 8-bit immediates where e.g. $~0 is @@ -11032,13 +11038,13 @@ process_operands (void) && MAX_OPERANDS > dupl && operand_type_equal (&i.types[dest], ®xmm)); - if (i.tm.operand_types[0].bitfield.instance == Accum - && i.tm.operand_types[0].bitfield.xmmword) + if (i.tm_types[0].bitfield.instance == Accum + && i.tm_types[0].bitfield.xmmword) { /* Keep xmm0 for instructions with VEX prefix and 3 sources. */ - i.tm.operand_types[0].bitfield.instance = InstanceNone; - i.tm.operand_types[0].bitfield.class = RegSIMD; + i.tm_types[0].bitfield.instance = InstanceNone; + i.tm_types[0].bitfield.class = RegSIMD; i.reg_operands++; goto duplicate; } @@ -11053,7 +11059,7 @@ process_operands (void) copy_operand (j, j - 1); i.op[0].regs = str_hash_find (reg_hash, "xmm0"); i.types[0] = regxmm; - i.tm.operand_types[0] = regxmm; + i.tm_types[0] = regxmm; i.operands += 2; i.reg_operands += 2; @@ -11075,7 +11081,7 @@ process_operands (void) if (i.tm.opcode_modifier.immext) process_immext (); } - else if (i.tm.operand_types[0].bitfield.instance == Accum + else if (i.tm_types[0].bitfield.instance == Accum && i.tm.opcode_modifier.modrm) { unsigned int j; @@ -11237,7 +11243,7 @@ process_operands (void) } else if (i.reg_operands == 1 && !i.flags[i.operands - 1] - && i.tm.operand_types[i.operands - 1].bitfield.instance + && i.tm_types[i.operands - 1].bitfield.instance == InstanceNone) { gas_assert (is_any_vex_encoding (&i.tm) @@ -11278,19 +11284,19 @@ build_modrm_byte (void) const reg_entry *default_seg = NULL; unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext /* Compensate for kludge in md_assemble(). */ - + i.tm.operand_types[0].bitfield.imm1; + + i.tm_types[0].bitfield.imm1; unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext; unsigned int v, op, reg_slot; /* Accumulator (in particular %st), shift count (%cl), and alike need to be skipped just like immediate operands do. */ - if (i.tm.operand_types[source].bitfield.instance) + if (i.tm_types[source].bitfield.instance) ++source; - while (i.tm.operand_types[dest].bitfield.instance) + while (i.tm_types[dest].bitfield.instance) --dest; for (op = source; op < i.operands; ++op) - if (i.tm.operand_types[op].bitfield.baseindex) + if (i.tm_types[op].bitfield.baseindex) break; if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) @@ -11310,7 +11316,7 @@ build_modrm_byte (void) { gas_assert (i.tm.opcode_modifier.vexvvvv && i.tm.opcode_modifier.vexw); - gas_assert (i.tm.operand_types[dest].bitfield.class == RegSIMD); + gas_assert (i.tm_types[dest].bitfield.class == RegSIMD); } /* Of the first two non-immediate operands the one with the template @@ -11322,11 +11328,11 @@ build_modrm_byte (void) if (!dot_insn ()) { - gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); + gas_assert (i.tm_types[reg_slot].bitfield.class == RegSIMD); gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex)); } else - gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone); + gas_assert (i.tm_types[reg_slot].bitfield.class != ClassNone); if (i.imm_operands == 0) { @@ -11693,8 +11699,8 @@ flip_code16 (unsigned int code16) gas_assert (i.tm.operands == 1); return !(i.prefix[REX_PREFIX] & REX_W) - && (code16 ? i.tm.operand_types[0].bitfield.disp32 - : i.tm.operand_types[0].bitfield.disp16) + && (code16 ? i.tm_types[0].bitfield.disp32 + : i.tm_types[0].bitfield.disp16) ? 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957bd9e980sm38718435e9.0.2026.07.24.03.14.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:14:29 -0700 (PDT) Message-ID: Date: Fri, 24 Jul 2026 12:14:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 2/4] x86: correct operand_types[] used in build_vex_prefix() From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org While benign at the moment, using t's ->operand_types[] isn't really correct: Closer to the top of the function we may have installed t[1] for use by the insn. Hence we should also use its .operand_types[], which now are in i.tm_types[]. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4402,8 +4402,8 @@ build_vex_prefix (const insn_template *t operand. */ vector_length = 0; for (op = t->operands; op--;) - if (t->operand_types[op].bitfield.xmmword - && t->operand_types[op].bitfield.ymmword + if (i.tm_types[op].bitfield.xmmword + && i.tm_types[op].bitfield.ymmword && i.types[op].bitfield.ymmword) { vector_length = 1; From patchwork Fri Jul 24 10:14:49 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 139886 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E43AD4BA2E3F for ; Fri, 24 Jul 2026 10:15:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E43AD4BA2E3F Authentication-Results: sourceware.org; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af89be2sm70359075e9.12.2026.07.24.03.14.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:14:50 -0700 (PDT) Message-ID: <54396697-ca30-4b9e-b1a8-b80284dec395@suse.com> Date: Fri, 24 Jul 2026 12:14:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 3/4] x86: helper function + variables for templates' ->operand_types[] accesses From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This again is to reduce the churn by a subsequent change, where .operand_types[] is to no longer be directly embedded in the templates. A few instances cannot sensibly changed following the pattern used. In match_template() one use to be replaced is covered by slightly re-ordering code there, to then use an existing local variable. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2548,6 +2548,12 @@ operand_type_check (i386_operand_type t, return 0; } +static INLINE const i386_operand_type * +get_operand_types (const insn_template *t) +{ + return t->operand_types; +} + /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit size between operand GIVEN and operand WANTED for instruction template T. */ @@ -2555,20 +2561,22 @@ static INLINE int match_operand_size (const insn_template *t, unsigned int wanted, unsigned int given) { + const i386_operand_type *t_types = get_operand_types (t); + return !((i.types[given].bitfield.byte - && !t->operand_types[wanted].bitfield.byte) + && !t_types[wanted].bitfield.byte) || (i.types[given].bitfield.word - && !t->operand_types[wanted].bitfield.word) + && !t_types[wanted].bitfield.word) || (i.types[given].bitfield.dword - && !t->operand_types[wanted].bitfield.dword) + && !t_types[wanted].bitfield.dword) || (i.types[given].bitfield.qword - && (!t->operand_types[wanted].bitfield.qword + && (!t_types[wanted].bitfield.qword /* Don't allow 64-bit (memory) operands outside of 64-bit mode, when they're used where a 64-bit GPR could also be used. Checking is needed for Intel Syntax only. */ || (intel_syntax && flag_code != CODE_64BIT - && (t->operand_types[wanted].bitfield.class == Reg + && (t_types[wanted].bitfield.class == Reg || t->opcode_modifier.isstring))))); } @@ -2576,28 +2584,28 @@ match_operand_size (const insn_template between operand GIVEN and operand WANTED for instruction template T. */ static INLINE int -match_fp_size (const insn_template *t, unsigned int wanted, +match_fp_size (const i386_operand_type *t_types, unsigned int wanted, unsigned int given) { return !i.types[given].bitfield.tbyte - || t->operand_types[wanted].bitfield.tbyte; + || t_types[wanted].bitfield.tbyte; } /* Return 1 if there is no conflict in SIMD register between operand GIVEN and operand WANTED for instruction template T. */ static INLINE int -match_simd_size (const insn_template *t, unsigned int wanted, +match_simd_size (const i386_operand_type *t_types, unsigned int wanted, unsigned int given) { return !((i.types[given].bitfield.xmmword - && !t->operand_types[wanted].bitfield.xmmword) + && !t_types[wanted].bitfield.xmmword) || (i.types[given].bitfield.ymmword - && !t->operand_types[wanted].bitfield.ymmword) + && !t_types[wanted].bitfield.ymmword) || (i.types[given].bitfield.zmmword - && !t->operand_types[wanted].bitfield.zmmword) + && !t_types[wanted].bitfield.zmmword) || (i.types[given].bitfield.tmmword - && !t->operand_types[wanted].bitfield.tmmword)); + && !t_types[wanted].bitfield.tmmword)); } /* Return 1 if there is no conflict in any size between operand GIVEN @@ -2607,29 +2615,31 @@ static INLINE int match_mem_size (const insn_template *t, unsigned int wanted, unsigned int given) { + const i386_operand_type *t_types = get_operand_types (t); + return (match_operand_size (t, wanted, given) && (!i.types[given].bitfield.tbyte - || t->operand_types[wanted].bitfield.tbyte) + || t_types[wanted].bitfield.tbyte) && !((i.types[given].bitfield.unspecified && !i.broadcast.type && !i.broadcast.bytes - && !t->operand_types[wanted].bitfield.unspecified) + && !t_types[wanted].bitfield.unspecified) || (i.types[given].bitfield.fword - && !t->operand_types[wanted].bitfield.fword) + && !t_types[wanted].bitfield.fword) /* For scalar opcode templates to allow register and memory operands at the same time, some special casing is needed here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and down-conversion vpmov*. */ - || ((t->operand_types[wanted].bitfield.class == RegSIMD - && t->operand_types[wanted].bitfield.byte - + t->operand_types[wanted].bitfield.word - + t->operand_types[wanted].bitfield.dword - + t->operand_types[wanted].bitfield.qword + || ((t_types[wanted].bitfield.class == RegSIMD + && t_types[wanted].bitfield.byte + + t_types[wanted].bitfield.word + + t_types[wanted].bitfield.dword + + t_types[wanted].bitfield.qword > !!t->opcode_modifier.broadcast) ? (i.types[given].bitfield.xmmword || i.types[given].bitfield.ymmword || i.types[given].bitfield.zmmword) - : !match_simd_size(t, wanted, given)))); + : !match_simd_size(t_types, wanted, given)))); } /* Return value has MATCH_STRAIGHT set if there is no size conflict on any @@ -2643,6 +2653,7 @@ match_mem_size (const insn_template *t, static INLINE unsigned int operand_size_match (const insn_template *t) { + const i386_operand_type *t_types = get_operand_types (t); unsigned int j, match = MATCH_STRAIGHT; /* Don't check non-absolute jump instructions. */ @@ -2657,8 +2668,8 @@ operand_size_match (const insn_template first template if sign-extended 8-bit immediate operand should be excluded. */ if (pp.no_imm8s - && !t->operand_types[j].bitfield.imm8 - && t->operand_types[j].bitfield.imm8s) + && !t_types[j].bitfield.imm8 + && t_types[j].bitfield.imm8s) { gas_assert (!t->opcode_modifier.d); return 0; @@ -2668,12 +2679,12 @@ operand_size_match (const insn_template for (; j < i.operands; j++) { if (i.types[j].bitfield.class == Reg - && (t->operand_types[j].bitfield.class == Reg - || (t->operand_types[j].bitfield.instance == Accum - && (t->operand_types[j].bitfield.byte - || t->operand_types[j].bitfield.word - || t->operand_types[j].bitfield.dword - || t->operand_types[j].bitfield.qword))) + && (t_types[j].bitfield.class == Reg + || (t_types[j].bitfield.instance == Accum + && (t_types[j].bitfield.byte + || t_types[j].bitfield.word + || t_types[j].bitfield.dword + || t_types[j].bitfield.qword))) && !match_operand_size (t, j, j)) { match = 0; @@ -2681,28 +2692,28 @@ operand_size_match (const insn_template } if (i.types[j].bitfield.class == RegFP - && (t->operand_types[j].bitfield.class == RegFP - || (t->operand_types[j].bitfield.instance == Accum - && t->operand_types[j].bitfield.tbyte)) - && !match_fp_size (t, j, j)) + && (t_types[j].bitfield.class == RegFP + || (t_types[j].bitfield.instance == Accum + && t_types[j].bitfield.tbyte)) + && !match_fp_size (t_types, j, j)) { match = 0; break; } if (i.types[j].bitfield.class == RegSIMD - && (t->operand_types[j].bitfield.class == RegSIMD - || (t->operand_types[j].bitfield.instance == Accum + && (t_types[j].bitfield.class == RegSIMD + || (t_types[j].bitfield.instance == Accum /* Note: %ymm0, %zmm0, and %tmm0 aren't marked Accum. */ - && t->operand_types[j].bitfield.xmmword)) - && !match_simd_size (t, j, j)) + && t_types[j].bitfield.xmmword)) + && !match_simd_size (t_types, j, j)) { match = 0; break; } if ((i.flags[j] & Operand_Mem) - && operand_type_check (t->operand_types[j], anymem) + && operand_type_check (t_types[j], anymem) && t->opcode_modifier.operandconstraint != ANY_SIZE && !match_mem_size (t, j, j)) { @@ -2729,32 +2740,32 @@ operand_size_match (const insn_template given = j < 2 ? 1 - j : j; if (i.types[given].bitfield.class == Reg - && (t->operand_types[j].bitfield.class == Reg - || (t->operand_types[j].bitfield.instance == Accum - && (t->operand_types[j].bitfield.byte - || t->operand_types[j].bitfield.word - || t->operand_types[j].bitfield.dword - || t->operand_types[j].bitfield.qword - || t->operand_types[j].bitfield.tbyte))) + && (t_types[j].bitfield.class == Reg + || (t_types[j].bitfield.instance == Accum + && (t_types[j].bitfield.byte + || t_types[j].bitfield.word + || t_types[j].bitfield.dword + || t_types[j].bitfield.qword + || t_types[j].bitfield.tbyte))) && !match_operand_size (t, j, given)) return match; if (i.types[given].bitfield.class == RegFP - && (t->operand_types[j].bitfield.class == RegFP - || (t->operand_types[j].bitfield.instance == Accum - && t->operand_types[j].bitfield.tbyte)) - && !match_fp_size (t, j, given)) + && (t_types[j].bitfield.class == RegFP + || (t_types[j].bitfield.instance == Accum + && t_types[j].bitfield.tbyte)) + && !match_fp_size (t_types, j, given)) return match; /* No need to check for Accum here: There are no such templates with D set. */ if (i.types[given].bitfield.class == RegSIMD - && t->operand_types[j].bitfield.class == RegSIMD - && !match_simd_size (t, j, given)) + && t_types[j].bitfield.class == RegSIMD + && !match_simd_size (t_types, j, given)) return match; if ((i.flags[given] & Operand_Mem) - && operand_type_check (t->operand_types[j], anymem) + && operand_type_check (t_types[j], anymem) && !match_mem_size (t, j, given)) return match; } @@ -3866,10 +3877,11 @@ pte (insn_template *t) if (t->opcode_modifier.w) fprintf (stdout, "W"); fprintf (stdout, "\n"); + const i386_operand_type *t_types = get_operand_types (t); for (j = 0; j < t->operands; j++) { fprintf (stdout, " #%d type ", j + 1); - pt (t->operand_types[j]); + pt (t_types[j]); fprintf (stdout, "\n"); } } @@ -4239,8 +4251,9 @@ install_template (const insn_template *t i.tm = *t; + const i386_operand_type *t_types = get_operand_types (t); for (l = 0; l < t->operands; ++l) - i.tm_types[l] = t->operand_types[l]; + i.tm_types[l] = t_types[l]; /* Dual VEX/EVEX templates need stripping one of the possible variants. */ if (t->opcode_modifier.vex && t->opcode_modifier.evex) @@ -4500,6 +4513,7 @@ static unsigned int get_broadcast_bytes (const insn_template *t, bool diag) { unsigned int op, bytes; + const i386_operand_type *t_types = get_operand_types (t); const i386_operand_type *types; if (i.broadcast.type) @@ -4508,7 +4522,7 @@ get_broadcast_bytes (const insn_template gas_assert (intel_syntax); for (op = 0; op < t->operands; ++op) - if (t->operand_types[op].bitfield.baseindex) + if (t_types[op].bitfield.baseindex) break; gas_assert (op < t->operands); @@ -4517,23 +4531,23 @@ get_broadcast_bytes (const insn_template switch (i.broadcast.bytes) { case 1: - if (t->operand_types[op].bitfield.word) + if (t_types[op].bitfield.word) return 2; /* Fall through. */ case 2: - if (t->operand_types[op].bitfield.dword) + if (t_types[op].bitfield.dword) return 4; /* Fall through. */ case 4: - if (t->operand_types[op].bitfield.qword) + if (t_types[op].bitfield.qword) return 8; /* Fall through. */ case 8: - if (t->operand_types[op].bitfield.xmmword) + if (t_types[op].bitfield.xmmword) return 16; - if (t->operand_types[op].bitfield.ymmword) + if (t_types[op].bitfield.ymmword) return 32; - if (t->operand_types[op].bitfield.zmmword) + if (t_types[op].bitfield.zmmword) return 64; /* Fall through. */ default: @@ -4542,15 +4556,15 @@ get_broadcast_bytes (const insn_template gas_assert (op + 1 < t->operands); - if (t->operand_types[op + 1].bitfield.xmmword - + t->operand_types[op + 1].bitfield.ymmword - + t->operand_types[op + 1].bitfield.zmmword > 1) + if (t_types[op + 1].bitfield.xmmword + + t_types[op + 1].bitfield.ymmword + + t_types[op + 1].bitfield.zmmword > 1) { types = &i.types[op + 1]; diag = false; } else /* Ambiguous - guess with a preference to non-AVX512VL forms. */ - types = &t->operand_types[op]; + types = &t_types[op]; if (types->bitfield.zmmword) bytes = 64; @@ -6877,7 +6891,7 @@ static INLINE bool may_need_pass2 (const { return t->opcode_modifier.sse2avx /* Note that all SSE2AVX templates have at least one operand. */ - ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD + ? get_operand_types (t)[t->operands - 1].bitfield.class == RegSIMD : (t->opcode_space == SPACE_0F && (t->base_opcode | 1) == 0xbf) || (t->opcode_space == SPACE_BASE @@ -7525,6 +7539,8 @@ i386_assemble (char *line) free (xstrdup_copy); + const i386_operand_type *t_types = get_operand_types (t); + if (sse_check != check_none /* The opcode space check isn't strictly needed; it's there only to bypass the logic below when easily possible. */ @@ -7538,9 +7554,9 @@ i386_assemble (char *line) for (j = 0; j < t->operands; ++j) { - if (t->operand_types[j].bitfield.class == RegMMX) + if (t_types[j].bitfield.class == RegMMX) break; - if (t->operand_types[j].bitfield.class == RegSIMD) + if (t_types[j].bitfield.class == RegSIMD) simd = true; } @@ -8654,10 +8670,10 @@ optimize_imm (void) break; } - allowed = operand_type_and (t->operand_types[op], mask); + allowed = operand_type_and (get_operand_types (t)[op], mask); while (++t < current_templates.end) { - allowed = operand_type_or (allowed, t->operand_types[op]); + allowed = operand_type_or (allowed, get_operand_types (t)[op]); allowed = operand_type_and (allowed, mask); } @@ -8803,6 +8819,7 @@ check_VecOperands (const insn_template * { unsigned int op; i386_cpu_flags cpu; + const i386_operand_type *t_types = get_operand_types (t); /* Templates allowing for ZMMword as well as YMMword and/or XMMword for any one operand are implicity requiring AVX512VL support if the actual @@ -8822,7 +8839,7 @@ check_VecOperands (const insn_template * { for (op = 0; op < t->operands; ++op) { - if (t->operand_types[op].bitfield.zmmword + if (t_types[op].bitfield.zmmword && (i.types[op].bitfield.ymmword || i.types[op].bitfield.xmmword)) { @@ -8839,7 +8856,7 @@ check_VecOperands (const insn_template * { for (op = 0; op < t->operands; ++op) { - if (t->operand_types[op].bitfield.xmmword + if (t_types[op].bitfield.xmmword && i.types[op].bitfield.ymmword) { i.error = operand_size_mismatch; @@ -8931,7 +8948,7 @@ check_VecOperands (const insn_template * /* For AMX instructions with 3 TMM register operands, all operands must be distinct. */ if (i.reg_operands == 3 - && t->operand_types[0].bitfield.tmmword + && t_types[0].bitfield.tmmword && (i.op[0].regs == i.op[1].regs || i.op[0].regs == i.op[2].regs || i.op[1].regs == i.op[2].regs)) @@ -9006,12 +9023,12 @@ check_VecOperands (const insn_template * goto bad_broadcast; } - overlap = operand_type_and (type, t->operand_types[op]); - if (t->operand_types[op].bitfield.class == RegSIMD - && t->operand_types[op].bitfield.byte - + t->operand_types[op].bitfield.word - + t->operand_types[op].bitfield.dword - + t->operand_types[op].bitfield.qword > 1) + overlap = operand_type_and (type, t_types[op]); + if (t_types[op].bitfield.class == RegSIMD + && t_types[op].bitfield.byte + + t_types[op].bitfield.word + + t_types[op].bitfield.dword + + t_types[op].bitfield.qword > 1) { overlap.bitfield.xmmword = 0; overlap.bitfield.ymmword = 0; @@ -9029,9 +9046,9 @@ check_VecOperands (const insn_template * { if (j != op && !operand_type_register_match(i.types[j], - t->operand_types[j], + t_types[j], type, - t->operand_types[op])) + t_types[op])) goto bad_broadcast; } } @@ -9071,7 +9088,7 @@ check_VecOperands (const insn_template * - scatter/gather insns (i.e. ones using vSIB) only allow merging- masking. */ if (i.mask.zeroing - && (t->operand_types[t->operands - 1].bitfield.class == RegMask + && (t_types[t->operands - 1].bitfield.class == RegMask || (i.flags[t->operands - 1] & Operand_Mem) || t->opcode_modifier.sib)) { @@ -9155,14 +9172,14 @@ check_VecOperands (const insn_template * { if (t->opcode_modifier.evex == EVEXLIG) i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); - else if (t->operand_types[op].bitfield.xmmword - + t->operand_types[op].bitfield.ymmword - + t->operand_types[op].bitfield.zmmword <= 1) - type = &t->operand_types[op]; + else if (t_types[op].bitfield.xmmword + + t_types[op].bitfield.ymmword + + t_types[op].bitfield.zmmword <= 1) + type = &t_types[op]; else if (!i.types[op].bitfield.unspecified) type = &i.types[op]; else /* Ambiguities get resolved elsewhere. */ - fallback = &t->operand_types[op]; + fallback = &t_types[op]; } else if (i.types[op].bitfield.class == RegSIMD && t->opcode_modifier.evex != EVEXLIG) @@ -9510,18 +9527,21 @@ match_template (char mnem_suffix) if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) continue; + const i386_operand_type *t_types = get_operand_types (t); + for (j = 0; j < t->operands; ++j) + operand_types[j] = t_types[j]; + for (; j < MAX_OPERANDS; ++j) + operand_types[j] = (i386_operand_type){ .array[0] = 0 }; + /* In Intel syntax, normally we can check for memory operand size when there is no mnemonic suffix. But jmp and call have 2 different encodings with Dword memory operand size. Skip the "near" one (permitting a register operand) when "far" was requested. */ if (i.far_branch && t->opcode_modifier.jump == JUMP_ABSOLUTE - && t->operand_types[0].bitfield.class == Reg) + && operand_types[0].bitfield.class == Reg) continue; - for (j = 0; j < MAX_OPERANDS; j++) - operand_types[j] = t->operand_types[j]; - /* In general, don't allow 32-bit operands on pre-386. */ specific_error = progress (mnem_suffix ? invalid_instruction_suffix : operand_size_mismatch); @@ -9983,13 +10003,12 @@ match_template (char mnem_suffix) size_match = true; /* We ensure that the next template has the same input operands as the original matching template by the first - opernd (ATT). To avoid someone support new NDD insns and + operand (ATT). To avoid someone support new NDD insns and put it in the wrong position. */ - overlap0 = operand_type_and (i.types[0], - t[1].operand_types[0]); + const i386_operand_type *t1_types = get_operand_types (&t[1]); + overlap0 = operand_type_and (i.types[0], t1_types[0]); if (t->opcode_modifier.d) - overlap1 = operand_type_and (i.types[0], - t[1].operand_types[1]); + overlap1 = operand_type_and (i.types[0], t1_types[1]); if (!operand_type_match (overlap0, i.types[0]) && (!t->opcode_modifier.d || !operand_type_match (overlap1, i.types[0]))) @@ -15294,6 +15313,7 @@ i386_index_check (const char *operand_st if (t->opcode_modifier.isstring) { + const i386_operand_type *t_types = get_operand_types (t); /* Memory operands of string insns are special in that they only allow a single register (rDI or rSI) as their memory address. */ const reg_entry *expected_reg; @@ -15319,22 +15339,22 @@ i386_index_check (const char *operand_st int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0; int op = 0; - if (!t->operand_types[0].bitfield.baseindex + if (!t_types[0].bitfield.baseindex || ((!i.mem_operands != !intel_syntax) - && t->operand_types[1].bitfield.baseindex)) + && t_types[1].bitfield.baseindex)) op = 1; expected_reg = str_hash_find (reg_hash, di_si[addr_mode][op == es_op]); } else { - unsigned int op = t->operand_types[0].bitfield.baseindex ? 0 : 1; + unsigned int op = t_types[0].bitfield.baseindex ? 0 : 1; - if (!t->operand_types[op].bitfield.instance) + if (!t_types[op].bitfield.instance) return 1; /* Operand mismatch will be detected elsewhere. */ expected_reg = str_hash_find (reg_hash, - loregs[addr_mode][t->operand_types[op] + loregs[addr_mode][t_types[op] .bitfield.instance - 1]); } --- a/gas/config/tc-i386-intel.c +++ b/gas/config/tc-i386-intel.c @@ -923,9 +923,11 @@ i386_intel_operand (char *operand_string i.types[this_operand].bitfield.tbyte = 1; if (got_a_float) break; + const i386_operand_type *t_types + = get_operand_types (current_templates.start); if (flag_code == CODE_64BIT - && (current_templates.start->operand_types[0].bitfield.fword - || current_templates.start->operand_types[0].bitfield.tbyte + && (t_types[0].bitfield.fword + || t_types[0].bitfield.tbyte || current_templates.start->opcode_modifier.jump == JUMP_DWORD || current_templates.start->opcode_modifier.jump == JUMP)) suffix = QWORD_MNEM_SUFFIX; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957b842691sm45603285e9.1.2026.07.24.03.19.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:19:55 -0700 (PDT) Message-ID: <48ecade1-d5f0-4620-a028-bece8d2b90cb@suse.com> Date: Fri, 24 Jul 2026 12:19:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 4/4] x86: move operand_types[] out of struct insn_template From: Jan Beulich To: Binutils Cc: "H.J. Lu" References: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <4bce97ee-c8d1-44f8-8c61-4ec3a5b91b4f@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Most insns have fewer than 5 operands, so the extra slots are wasted there. Many insns also have identical operand combinations, so there is a lot of redundancy as well. Introduce a separate array holding all the operand combinations, but before adding new sets check whether the same set was seen before. Put the index into the new array into the struct insn_template instances. At the time of writing we're going down from 22,880 i386_operand_type instances (of which 10,006 are actually used) to just 770. --- Note: When merging operands directly while parsing, their amount went down to only 934. With the re-use of i386-mnem.h here we may want to rename it (to e.g. i386-defs.h). Subsequently we could consider to fold mnem_off and operand_ref into a single 32-bit field, as for both 16 bits (for the latter even fewer) are going to be sufficient for quite some time. Subsequently we could do the same to the CPU specifiers, perhaps to also do away again with the distinction between i386_cpu_flags and i386_cpu_attr (accepting the somewhat bigger data size, but which then wouldn't grow with every addition of a new template). Doing so may then also pave the road towards more complex combinations of CPU specifiers (we're already in trouble expressing some, and ACE looks to be making the situation worse). --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1376,6 +1376,8 @@ static htab_t op_hash; /* Hash table for register lookup. */ static htab_t reg_hash; +#include "opcodes/i386-tbl.h" + #if (defined (OBJ_ELF) || defined (OBJ_MACH_O) || defined (TE_PE)) static const struct { @@ -2551,7 +2553,7 @@ operand_type_check (i386_operand_type t, static INLINE const i386_operand_type * get_operand_types (const insn_template *t) { - return t->operand_types; + return &i386_operand_types[t->operand_ref]; } /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit size @@ -3647,8 +3649,6 @@ i386_mach (void) as_fatal (_("unknown architecture")); } -#include "opcodes/i386-tbl.h" - static void op_lookup (const char *mnemonic) { --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -621,6 +621,17 @@ static bitfield operand_types[] = #endif }; +/* Class and instance are small non-negative numbers, while the other fields + have boolean type. Use the smallest available type for latching the values + out of struct bitfield. */ +typedef unsigned char opval_t; + +/* Number of opval_t in a single operand representation. */ +#define OPVAL_COUNT (2 + ARRAY_SIZE (operand_types)) + +static const opval_t **operands[MAX_OPERANDS + 1]; +static unsigned int nr_operands[MAX_OPERANDS + 1]; + static const char *filename; static i386_cpu_flags active_cpu_flags; static int active_isstring; @@ -1386,7 +1397,7 @@ output_operand_type (FILE *table, enum o fprintf (table, "%d } }", types[i].value); } -static void +static const opval_t * process_i386_operand_type (FILE *table, char *op, enum stage stage, const char *indent, int lineno) { @@ -1449,8 +1460,35 @@ process_i386_operand_type (FILE *table, set_bitfield("Disp32", types, 1, ARRAY_SIZE (types), lineno); } } + + if (!table) + { + opval_t *op = XNEWVEC (opval_t, OPVAL_COUNT); + + op[0] = class; + op[1] = instance; + + /* Check for no truncation. */ + if (op[0] != class || op[1] != instance) + fail ("%s: %d: class (%u) or instance (%u) out of range\n", + filename, lineno); + + for (unsigned int i = 0; i < ARRAY_SIZE (types); ++i) + { + op[i + 2] = types[i].value; + + /* Check for no truncation. */ + if (op[i + 2] != types[i].value) + fail ("%s: %d: `%s' value out of range: %d\n", + filename, lineno, types[i].name, types[i].value); + } + + return op; + } + output_operand_type (table, class, instance, types, ARRAY_SIZE (types), stage, indent); + return NULL; } static char *mkident (const char *mnem) @@ -1467,13 +1505,53 @@ static char *mkident (const char *mnem) return ident; } +static unsigned int +get_opref (const opval_t *op[], unsigned int nr, bool parse) +{ + static unsigned int slots_operands[MAX_OPERANDS + 1]; + unsigned int i, lst, step; + + /* While parsing templates, insert into the respective list. In this phase + also only consider whole groups of operands for merging. + + On the final merging pass everything goes onto the MAX_OPERANDS list. */ + if (parse) + lst = step = nr; + else + lst = MAX_OPERANDS, step = 1; + + /* Brute force lookup for now. */ + for (unsigned int ref = 0; ref + nr <= nr_operands[lst]; ref += step) + { + for (i = 0; i < nr; ++i) + if (memcmp (operands[lst][ref + i], op[i], OPVAL_COUNT)) + break; + if (i == nr) + { + while (i--) + free ((void *)op[i]); + return ref; + } + } + + if (nr_operands[lst] + nr > slots_operands[lst]) + operands[lst] = XRESIZEVEC (const opval_t *, operands[lst], + slots_operands[lst] += 16 * nr); + + for (i = 0; i < nr; ++i) + operands[lst][nr_operands[lst]++] = op[i]; + + return nr_operands[lst] - nr; +} + static void output_i386_opcode (FILE *table, const char *name, char *str, char *last, int lineno) { - unsigned int i, length, prefix = 0, space = 0; + unsigned int i, length, prefix = 0, space = 0, ref; char *base_opcode, *extension_opcode, *end, *ident; char *cpu_flags, *opcode_modifier, *operand_types [MAX_OPERANDS]; + const opval_t *op [MAX_OPERANDS]; unsigned long long opcode; /* Find base_opcode. */ @@ -1578,25 +1656,29 @@ output_i386_opcode (FILE *table, const c process_i386_cpu_flag (table, cpu_flags, NULL, ",", " ", lineno, CpuMax); - fprintf (table, " { "); - for (i = 0; i < ARRAY_SIZE (operand_types); i++) { if (!operand_types[i]) - { - if (i == 0) - process_i386_operand_type (table, "0", stage_opcodes, "\t ", - lineno); - break; - } + break; - if (i != 0) - fprintf (table, ",\n "); + op[i] = process_i386_operand_type (NULL, operand_types[i], stage_opcodes, + NULL, lineno); + } - process_i386_operand_type (table, operand_types[i], stage_opcodes, - "\t ", lineno); + if (i == 0) + { + fprintf (table, " 0 },\n"); + return; } - fprintf (table, " } },\n"); + + ref = get_opref (op, i, true); + /* The MAX_OPERANDS list won't further be altered, so the reference can be + recorded directly. All other lists will be merged into the main list + later, and the reference to store will be known only then. */ + if (i == MAX_OPERANDS) + fprintf (table, " %u },\n", ref); + else + fprintf (table, " OPREF_%u_%u },\n", i, ref); } struct opcode_hash_entry @@ -2118,10 +2200,41 @@ process_i386_opcodes (FILE *table) } fprintf (table, " \"\\0\"\".insn\"\n"); - fprintf (fp, "#define MN__insn %#x\n", offs + 1); + fprintf (fp, "#define MN__insn %#x\n\n", offs + 1); fprintf (table, ";\n"); + for (i = MAX_OPERANDS - 1; i > 0; --i) + { + for (j = 0, nr = nr_operands[i]; j < nr; j += i) + { + unsigned int ref = get_opref (&operands[i][j], i, false); + + fprintf (fp, "#define OPREF_%u_%u %u\n", i, j, ref); + } + } + + fprintf (table, "\n/* i386 operand types table. */\n\n"); + fprintf (table, "static const i386_operand_type i386_operand_types[] =\n{\n"); + + for (i = 0; i < nr_operands[MAX_OPERANDS]; ++i) + { + const opval_t *op = operands[MAX_OPERANDS][i]; + bitfield types[ARRAY_SIZE (operand_types)] = { [0] = { .name = NULL } }; + + fprintf (table, " "); + + for (j = 0; j < ARRAY_SIZE (types); ++j) + types[j].value = op[j + 2]; + + output_operand_type (table, op[0], op[1], types, ARRAY_SIZE (types), + stage_opcodes, " "); + + fprintf (table, ",\n"); + } + + fprintf (table, "};\n"); + fclose (fp); } --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1104,11 +1104,11 @@ typedef struct insn_template /* cpu feature attributes */ i386_cpu_attr cpu, cpu_any; - /* operand_types[i] describes the type of operand i. This is made - by OR'ing together all of the possible type masks. (e.g. + /* i386_operand_types[operand_ref + i] describes the type of operand i. + This is made by OR'ing together all of the possible type masks. (e.g. 'operand_types[i] = Reg|Imm' specifies that operand i can be either a register or an immediate operand. */ - i386_operand_type operand_types[MAX_OPERANDS]; + unsigned int operand_ref; } insn_template;