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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85c53052sm22490618f8f.18.2026.07.24.03.02.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:02:03 -0700 (PDT) Message-ID: <2fa75e19-4d95-403b-876a-eeab235ddf64@suse.com> Date: Fri, 24 Jul 2026 12:02:02 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 01/12] bfd/RISC-V: Zv{b,k}* imply Zve32x From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org The specification is quite explicit about this. Since only forward references are permitted within the table, the pre-existing Zv{b,k} block needs moving up. --- Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it seems unlikely to be mere chance that Zve* come ahead of all other Zv* in riscv_supported_std_z_ext[]. --- v4: Put table entries into required order. v3: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1244,15 +1244,35 @@ static const struct riscv_implicit_subse {"zvfqwdota8f", "+zve32f", check_implicit_always}, {"zvfwbdota16bf", "+zve32f", check_implicit_always}, {"zvfwdota16bf", "+zve32f", check_implicit_always}, + + {"zvbb", "+zvkb", check_implicit_always}, + {"zvkng", "+zvkn,+zvkg", check_implicit_always}, + {"zvknc", "+zvkn,+zvbc", check_implicit_always}, + {"zvkn", "+zvkned,+zvknhb,+zvkb,+zvkt", check_implicit_always}, + {"zvksg", "+zvks,+zvkg", check_implicit_always}, + {"zvksc", "+zvks,+zvbc", check_implicit_always}, + {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always}, + + {"zvbc", "+zve32x", check_implicit_always}, + {"zvkb", "+zve32x", check_implicit_always}, + {"zvkg", "+zve32x", check_implicit_always}, + {"zvkned", "+zve32x", check_implicit_always}, + {"zvknha", "+zve32x", check_implicit_always}, + {"zvknhb", "+zve32x", check_implicit_always}, + {"zvksed", "+zve32x", check_implicit_always}, + {"zvksh", "+zve32x", check_implicit_always}, + {"zvqwbdota8i", "+zve32x", check_implicit_always}, {"zvqwbdota16i", "+zve64x", check_implicit_always}, {"zvqwdota8i", "+zve32x", check_implicit_always}, {"zvqwdota16i", "+zve64x", check_implicit_always}, + {"zve64d", "+d,+zve64f", check_implicit_always}, {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always}, {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always}, {"zve64x", "+zve32x,+zvl64b", check_implicit_always}, {"zve32x", "+zvl32b,+zicsr", check_implicit_always}, + {"zvl65536b", "+zvl32768b", check_implicit_always}, {"zvl32768b", "+zvl16384b", check_implicit_always}, {"zvl16384b", "+zvl8192b", check_implicit_always}, @@ -1312,13 +1332,6 @@ static const struct riscv_implicit_subse {"zk", "+zkn,+zkr,+zkt", check_implicit_always}, {"zkn", "+zbkb,+zbkc,+zbkx,+zkne,+zknd,+zknh", check_implicit_always}, {"zks", "+zbkb,+zbkc,+zbkx,+zksed,+zksh", check_implicit_always}, - {"zvbb", "+zvkb", check_implicit_always}, - {"zvkng", "+zvkn,+zvkg", check_implicit_always}, - {"zvknc", "+zvkn,+zvbc", check_implicit_always}, - {"zvkn", "+zvkned,+zvknhb,+zvkb,+zvkt", check_implicit_always}, - {"zvksg", "+zvks,+zvkg", check_implicit_always}, - {"zvksc", "+zvks,+zvbc", check_implicit_always}, - {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always}, {"sdtrig", "+zicsr", check_implicit_always}, --- a/gas/testsuite/gas/riscv/imply.d +++ b/gas/testsuite/gas/riscv/imply.d @@ -87,13 +87,13 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0 From patchwork Fri Jul 24 10:02:27 2026 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af5d8c1sm68418245e9.1.2026.07.24.03.02.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:02:29 -0700 (PDT) Message-ID: <93e2c76e-edd5-4293-9d99-04d6bf30b1f4@suse.com> Date: Fri, 24 Jul 2026 12:02:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 02/12] bfd/RISC-V: Zve{32,64}f don't need to explicitly imply Zvl{32,64}b From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org The former referencing Zve{32,64}x already ensures the wanted implication. No need to perform excess processing. --- v4: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1268,8 +1268,8 @@ static const struct riscv_implicit_subse {"zvqwdota16i", "+zve64x", check_implicit_always}, {"zve64d", "+d,+zve64f", check_implicit_always}, - {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always}, - {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always}, + {"zve64f", "+zve32f,+zve64x", check_implicit_always}, + {"zve32f", "+f,+zve32x", check_implicit_always}, {"zve64x", "+zve32x,+zvl64b", check_implicit_always}, {"zve32x", "+zvl32b,+zicsr", check_implicit_always}, From patchwork Fri Jul 24 10:02:51 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 139876 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D2F254BA79B6 for ; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85c531basm23206180f8f.19.2026.07.24.03.02.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:02:52 -0700 (PDT) Message-ID: <36f87cee-df61-46de-8919-83ff26fda06f@suse.com> Date: Fri, 24 Jul 2026 12:02:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 03/12] RISC-V: replace INSN_V_EEW64 From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Introduce INSN_CLASS_ZVE64X instead, making the respective insns (and diagnostics on their inappropriate use) less special. --- v4: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -3001,6 +3001,9 @@ riscv_multi_subset_supports (riscv_parse return (riscv_subset_supports (rps, "v") || riscv_subset_supports (rps, "zve64x") || riscv_subset_supports (rps, "zve32x")); + case INSN_CLASS_ZVE64X: + return (riscv_subset_supports (rps, "v") + || riscv_subset_supports (rps, "zve64x")); case INSN_CLASS_ZVEF: return (riscv_subset_supports (rps, "v") || riscv_subset_supports (rps, "zve64d") @@ -3355,6 +3358,8 @@ riscv_multi_subset_supports_ext (riscv_p return "zksh"; case INSN_CLASS_V: return _("v' or `zve64x' or `zve32x"); + case INSN_CLASS_ZVE64X: + return _("v' or `zve64x"); case INSN_CLASS_ZVEF: return _("v' or `zve64d' or `zve64f' or `zve32f"); case INSN_CLASS_ZVABD: --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -3039,15 +3039,6 @@ riscv_ip (char *str, struct riscv_cl_ins as_warn (_("read-only CSR is written `%s'"), str); insn_with_csr = false; } - - /* The (segment) load and store with EEW 64 cannot be used - when zve32x is enabled. */ - if ((ip->insn_mo->pinfo & INSN_V_EEW64) - && !riscv_subset_supports (&riscv_rps_as, "zve64x")) - { - error.msg = _("illegal opcode for zve32x"); - break; - } } if (*asarg != '\0') break; --- a/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l +++ b/gas/testsuite/gas/riscv/vector-insns-fail-zve32xf.l @@ -1,225 +1,225 @@ .*Assembler messages: -.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vle64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vle64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vse64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vse64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlse64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlse64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vsse64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vsse64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vle64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vle64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg2e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg2e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vsseg2e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vsseg2e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg3e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg3e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vsseg3e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vsseg3e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg4e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg4e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vsseg4e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vsseg4e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg5e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg5e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vsseg5e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vsseg5e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg6e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg6e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vsseg6e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vsseg6e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg7e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg7e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vsseg7e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vsseg7e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg8e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg8e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vsseg8e64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vsseg8e64.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg2e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg2e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg2e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg3e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg3e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg3e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg4e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg4e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg4e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg5e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg5e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg5e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg6e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg6e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg6e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg7e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg7e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg7e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vlsseg8e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg8e64.v v4,0\(a0\),a1' -.*Error: illegal opcode for zve32x `vssseg8e64.v v4,\(a0\),a1,v0.t' -.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg2ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg2ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg3ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg3ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg4ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg4ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg5ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg5ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg6ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg6ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg7ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg7ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vloxseg8ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsoxseg8ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg2ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg2ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg3ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg3ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg4ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg4ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg5ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg5ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg6ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg6ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg7ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg7ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vluxseg8ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,0\(a0\),v12' -.*Error: illegal opcode for zve32x `vsuxseg8ei64.v v4,\(a0\),v12,v0.t' -.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg2e64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg3e64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg4e64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg5e64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg6e64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg7e64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vlseg8e64ff.v v4,\(a0\),v0.t' -.*Error: illegal opcode for zve32x `vl1re64.v v3,\(a0\)' -.*Error: illegal opcode for zve32x `vl1re64.v v3,0\(a0\)' -.*Error: illegal opcode for zve32x `vl2re64.v v2,\(a0\)' -.*Error: illegal opcode for zve32x `vl2re64.v v2,0\(a0\)' -.*Error: illegal opcode for zve32x `vl4re64.v v4,\(a0\)' -.*Error: illegal opcode for zve32x `vl4re64.v v4,0\(a0\)' -.*Error: illegal opcode for zve32x `vl8re64.v v8,\(a0\)' -.*Error: illegal opcode for zve32x `vl8re64.v v8,0\(a0\)' +.*Error: unrecognized opcode `vle64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vle64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vle64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vse64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vse64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vse64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlse64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlse64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlse64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsse64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsse64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsse64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vle64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vle64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vle64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg2e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg2e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg2e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg2e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg2e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg2e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg3e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg3e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg3e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg3e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg3e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg3e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg4e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg4e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg4e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg4e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg4e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg4e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg5e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg5e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg5e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg5e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg5e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg5e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg6e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg6e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg6e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg6e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg6e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg6e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg7e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg7e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg7e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg7e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg7e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg7e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg8e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg8e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg8e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg8e64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg8e64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsseg8e64.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg2e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg2e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg2e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg2e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg3e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg3e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg3e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg3e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg4e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg4e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg4e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg4e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg5e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg5e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg5e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg5e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg6e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg6e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg6e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg6e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg7e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg7e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg7e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg7e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg8e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlsseg8e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg8e64.v v4,0\(a0\),a1', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vssseg8e64.v v4,\(a0\),a1,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vloxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsoxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg2ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg2ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg3ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg3ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg4ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg4ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg5ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg5ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg6ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg6ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg7ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg7ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vluxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg8ei64.v v4,0\(a0\),v12', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vsuxseg8ei64.v v4,\(a0\),v12,v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg2e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg2e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg3e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg3e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg4e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg4e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg5e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg5e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg6e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg6e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg7e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg7e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg8e64ff.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vlseg8e64ff.v v4,\(a0\),v0.t', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl1re64.v v3,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl1re64.v v3,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl2re64.v v2,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl2re64.v v2,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl4re64.v v4,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl4re64.v v4,0\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl8re64.v v8,\(a0\)', extension `v' or `zve64x' required +.*Error: unrecognized opcode `vl8re64.v v8,0\(a0\)', extension `v' or `zve64x' required --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -560,6 +560,7 @@ enum riscv_insn_class INSN_CLASS_ZBC_OR_ZBKC, INSN_CLASS_ZKND_OR_ZKNE, INSN_CLASS_V, + INSN_CLASS_ZVE64X, INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, @@ -698,8 +699,6 @@ struct riscv_opcode #define INSN_JSR 0x00000006 /* Instruction is a data reference. */ #define INSN_DREF 0x00000008 -/* Instruction is allowed when eew >= 64. */ -#define INSN_V_EEW64 0x10000000 /* We have 5 data reference sizes, which we can encode in 3 bits. */ #define INSN_DATA_SIZE 0x00000070 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -1133,10 +1133,6 @@ riscv_disassemble_insn (bfd_vma memaddr, if (!riscv_multi_subset_supports (&pd->riscv_rps_dis, op->insn_class)) continue; - - if ((op->pinfo & INSN_V_EEW64) - && !riscv_subset_supports (&pd->riscv_rps_dis, "zve64x")) - continue; } /* It's a match. */ --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1493,47 +1493,47 @@ const struct riscv_opcode riscv_opcodes[ {"vle8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8V, MASK_VLE8V, match_opcode, INSN_DREF }, {"vle16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16V, MASK_VLE16V, match_opcode, INSN_DREF }, {"vle32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32V, MASK_VLE32V, match_opcode, INSN_DREF }, -{"vle64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vle64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLE64V, MASK_VLE64V, match_opcode, INSN_DREF }, {"vse8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE8V, MASK_VSE8V, match_opcode, INSN_DREF }, {"vse16.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE16V, MASK_VSE16V, match_opcode, INSN_DREF }, {"vse32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE32V, MASK_VSE32V, match_opcode, INSN_DREF }, -{"vse64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vse64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSE64V, MASK_VSE64V, match_opcode, INSN_DREF }, {"vlse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE8V, MASK_VLSE8V, match_opcode, INSN_DREF }, {"vlse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE16V, MASK_VLSE16V, match_opcode, INSN_DREF }, {"vlse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE32V, MASK_VLSE32V, match_opcode, INSN_DREF }, -{"vlse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vlse64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSE64V, MASK_VLSE64V, match_opcode, INSN_DREF }, {"vsse8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE8V, MASK_VSSE8V, match_opcode, INSN_DREF }, {"vsse16.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE16V, MASK_VSSE16V, match_opcode, INSN_DREF }, {"vsse32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE32V, MASK_VSSE32V, match_opcode, INSN_DREF }, -{"vsse64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vsse64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSE64V, MASK_VSSE64V, match_opcode, INSN_DREF }, {"vloxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI8V, MASK_VLOXEI8V, match_opcode, INSN_DREF }, {"vloxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI16V, MASK_VLOXEI16V, match_opcode, INSN_DREF }, {"vloxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI32V, MASK_VLOXEI32V, match_opcode, INSN_DREF }, -{"vloxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vloxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXEI64V, MASK_VLOXEI64V, match_opcode, INSN_DREF }, {"vsoxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI8V, MASK_VSOXEI8V, match_opcode, INSN_DREF }, {"vsoxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI16V, MASK_VSOXEI16V, match_opcode, INSN_DREF }, {"vsoxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI32V, MASK_VSOXEI32V, match_opcode, INSN_DREF }, -{"vsoxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vsoxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXEI64V, MASK_VSOXEI64V, match_opcode, INSN_DREF }, {"vluxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI8V, MASK_VLUXEI8V, match_opcode, INSN_DREF }, {"vluxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI16V, MASK_VLUXEI16V, match_opcode, INSN_DREF }, {"vluxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI32V, MASK_VLUXEI32V, match_opcode, INSN_DREF }, -{"vluxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vluxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXEI64V, MASK_VLUXEI64V, match_opcode, INSN_DREF }, {"vsuxei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI8V, MASK_VSUXEI8V, match_opcode, INSN_DREF }, {"vsuxei16.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI16V, MASK_VSUXEI16V, match_opcode, INSN_DREF }, {"vsuxei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI32V, MASK_VSUXEI32V, match_opcode, INSN_DREF }, -{"vsuxei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vsuxei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXEI64V, MASK_VSUXEI64V, match_opcode, INSN_DREF }, {"vle8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE8FFV, MASK_VLE8FFV, match_opcode, INSN_DREF }, {"vle16ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE16FFV, MASK_VLE16FFV, match_opcode, INSN_DREF }, {"vle32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE32FFV, MASK_VLE32FFV, match_opcode, INSN_DREF }, -{"vle64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vle64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLE64FFV, MASK_VLE64FFV, match_opcode, INSN_DREF }, {"vlseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8V, MASK_VLSEG2E8V, match_opcode, INSN_DREF }, {"vsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E8V, MASK_VSSEG2E8V, match_opcode, INSN_DREF }, @@ -1580,20 +1580,20 @@ const struct riscv_opcode riscv_opcodes[ {"vlseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32V, MASK_VLSEG8E32V, match_opcode, INSN_DREF }, {"vsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E32V, MASK_VSSEG8E32V, match_opcode, INSN_DREF }, -{"vlseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vlseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG2E64V, MASK_VLSEG2E64V, match_opcode, INSN_DREF }, +{"vsseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG2E64V, MASK_VSSEG2E64V, match_opcode, INSN_DREF }, +{"vlseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG3E64V, MASK_VLSEG3E64V, match_opcode, INSN_DREF }, +{"vsseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG3E64V, MASK_VSSEG3E64V, match_opcode, INSN_DREF }, +{"vlseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG4E64V, MASK_VLSEG4E64V, match_opcode, INSN_DREF }, +{"vsseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG4E64V, MASK_VSSEG4E64V, match_opcode, INSN_DREF }, +{"vlseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG5E64V, MASK_VLSEG5E64V, match_opcode, INSN_DREF }, +{"vsseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG5E64V, MASK_VSSEG5E64V, match_opcode, INSN_DREF }, +{"vlseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG6E64V, MASK_VLSEG6E64V, match_opcode, INSN_DREF }, +{"vsseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG6E64V, MASK_VSSEG6E64V, match_opcode, INSN_DREF }, +{"vlseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG7E64V, MASK_VLSEG7E64V, match_opcode, INSN_DREF }, +{"vsseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG7E64V, MASK_VSSEG7E64V, match_opcode, INSN_DREF }, +{"vlseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG8E64V, MASK_VLSEG8E64V, match_opcode, INSN_DREF }, +{"vsseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VSSEG8E64V, MASK_VSSEG8E64V, match_opcode, INSN_DREF }, {"vlsseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E8V, MASK_VLSSEG2E8V, match_opcode, INSN_DREF }, {"vssseg2e8.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E8V, MASK_VSSSEG2E8V, match_opcode, INSN_DREF }, @@ -1640,20 +1640,20 @@ const struct riscv_opcode riscv_opcodes[ {"vlsseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E32V, MASK_VLSSEG8E32V, match_opcode, INSN_DREF }, {"vssseg8e32.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E32V, MASK_VSSSEG8E32V, match_opcode, INSN_DREF }, -{"vlsseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vssseg2e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlsseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vssseg3e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlsseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vssseg4e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlsseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vssseg5e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlsseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vssseg6e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlsseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vssseg7e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlsseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vssseg8e64.v", 0, INSN_CLASS_V, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vlsseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG2E64V, MASK_VLSSEG2E64V, match_opcode, INSN_DREF }, +{"vssseg2e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG2E64V, MASK_VSSSEG2E64V, match_opcode, INSN_DREF }, +{"vlsseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG3E64V, MASK_VLSSEG3E64V, match_opcode, INSN_DREF }, +{"vssseg3e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG3E64V, MASK_VSSSEG3E64V, match_opcode, INSN_DREF }, +{"vlsseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG4E64V, MASK_VLSSEG4E64V, match_opcode, INSN_DREF }, +{"vssseg4e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG4E64V, MASK_VSSSEG4E64V, match_opcode, INSN_DREF }, +{"vlsseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG5E64V, MASK_VLSSEG5E64V, match_opcode, INSN_DREF }, +{"vssseg5e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG5E64V, MASK_VSSSEG5E64V, match_opcode, INSN_DREF }, +{"vlsseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG6E64V, MASK_VLSSEG6E64V, match_opcode, INSN_DREF }, +{"vssseg6e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG6E64V, MASK_VSSSEG6E64V, match_opcode, INSN_DREF }, +{"vlsseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG7E64V, MASK_VLSSEG7E64V, match_opcode, INSN_DREF }, +{"vssseg7e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG7E64V, MASK_VSSSEG7E64V, match_opcode, INSN_DREF }, +{"vlsseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VLSSEG8E64V, MASK_VLSSEG8E64V, match_opcode, INSN_DREF }, +{"vssseg8e64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),tVm", MATCH_VSSSEG8E64V, MASK_VSSSEG8E64V, match_opcode, INSN_DREF }, {"vloxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI8V, MASK_VLOXSEG2EI8V, match_opcode, INSN_DREF }, {"vsoxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI8V, MASK_VSOXSEG2EI8V, match_opcode, INSN_DREF }, @@ -1700,20 +1700,20 @@ const struct riscv_opcode riscv_opcodes[ {"vloxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI32V, MASK_VLOXSEG8EI32V, match_opcode, INSN_DREF }, {"vsoxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI32V, MASK_VSOXSEG8EI32V, match_opcode, INSN_DREF }, -{"vloxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsoxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vloxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsoxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vloxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsoxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vloxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsoxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vloxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsoxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vloxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsoxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vloxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsoxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vloxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG2EI64V, MASK_VLOXSEG2EI64V, match_opcode, INSN_DREF }, +{"vsoxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG2EI64V, MASK_VSOXSEG2EI64V, match_opcode, INSN_DREF }, +{"vloxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG3EI64V, MASK_VLOXSEG3EI64V, match_opcode, INSN_DREF }, +{"vsoxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG3EI64V, MASK_VSOXSEG3EI64V, match_opcode, INSN_DREF }, +{"vloxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG4EI64V, MASK_VLOXSEG4EI64V, match_opcode, INSN_DREF }, +{"vsoxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG4EI64V, MASK_VSOXSEG4EI64V, match_opcode, INSN_DREF }, +{"vloxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG5EI64V, MASK_VLOXSEG5EI64V, match_opcode, INSN_DREF }, +{"vsoxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG5EI64V, MASK_VSOXSEG5EI64V, match_opcode, INSN_DREF }, +{"vloxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG6EI64V, MASK_VLOXSEG6EI64V, match_opcode, INSN_DREF }, +{"vsoxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG6EI64V, MASK_VSOXSEG6EI64V, match_opcode, INSN_DREF }, +{"vloxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG7EI64V, MASK_VLOXSEG7EI64V, match_opcode, INSN_DREF }, +{"vsoxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG7EI64V, MASK_VSOXSEG7EI64V, match_opcode, INSN_DREF }, +{"vloxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLOXSEG8EI64V, MASK_VLOXSEG8EI64V, match_opcode, INSN_DREF }, +{"vsoxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSOXSEG8EI64V, MASK_VSOXSEG8EI64V, match_opcode, INSN_DREF }, {"vluxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI8V, MASK_VLUXSEG2EI8V, match_opcode, INSN_DREF }, {"vsuxseg2ei8.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI8V, MASK_VSUXSEG2EI8V, match_opcode, INSN_DREF }, @@ -1760,20 +1760,20 @@ const struct riscv_opcode riscv_opcodes[ {"vluxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI32V, MASK_VLUXSEG8EI32V, match_opcode, INSN_DREF }, {"vsuxseg8ei32.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI32V, MASK_VSUXSEG8EI32V, match_opcode, INSN_DREF }, -{"vluxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsuxseg2ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vluxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsuxseg3ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vluxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsuxseg4ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vluxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsuxseg5ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vluxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsuxseg6ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vluxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsuxseg7ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vluxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vsuxseg8ei64.v", 0, INSN_CLASS_V, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vluxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG2EI64V, MASK_VLUXSEG2EI64V, match_opcode, INSN_DREF }, +{"vsuxseg2ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG2EI64V, MASK_VSUXSEG2EI64V, match_opcode, INSN_DREF }, +{"vluxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG3EI64V, MASK_VLUXSEG3EI64V, match_opcode, INSN_DREF }, +{"vsuxseg3ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG3EI64V, MASK_VSUXSEG3EI64V, match_opcode, INSN_DREF }, +{"vluxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG4EI64V, MASK_VLUXSEG4EI64V, match_opcode, INSN_DREF }, +{"vsuxseg4ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG4EI64V, MASK_VSUXSEG4EI64V, match_opcode, INSN_DREF }, +{"vluxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG5EI64V, MASK_VLUXSEG5EI64V, match_opcode, INSN_DREF }, +{"vsuxseg5ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG5EI64V, MASK_VSUXSEG5EI64V, match_opcode, INSN_DREF }, +{"vluxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG6EI64V, MASK_VLUXSEG6EI64V, match_opcode, INSN_DREF }, +{"vsuxseg6ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG6EI64V, MASK_VSUXSEG6EI64V, match_opcode, INSN_DREF }, +{"vluxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG7EI64V, MASK_VLUXSEG7EI64V, match_opcode, INSN_DREF }, +{"vsuxseg7ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG7EI64V, MASK_VSUXSEG7EI64V, match_opcode, INSN_DREF }, +{"vluxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VLUXSEG8EI64V, MASK_VLUXSEG8EI64V, match_opcode, INSN_DREF }, +{"vsuxseg8ei64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s),VtVm", MATCH_VSUXSEG8EI64V, MASK_VSUXSEG8EI64V, match_opcode, INSN_DREF }, {"vlseg2e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E8FFV, MASK_VLSEG2E8FFV, match_opcode, INSN_DREF }, {"vlseg3e8ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E8FFV, MASK_VLSEG3E8FFV, match_opcode, INSN_DREF }, @@ -1799,37 +1799,37 @@ const struct riscv_opcode riscv_opcodes[ {"vlseg7e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E32FFV, MASK_VLSEG7E32FFV, match_opcode, INSN_DREF }, {"vlseg8e32ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF }, -{"vlseg2e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg3e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg4e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg5e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg6e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg7e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, -{"vlseg8e64ff.v", 0, INSN_CLASS_V, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vlseg2e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG2E64FFV, MASK_VLSEG2E64FFV, match_opcode, INSN_DREF }, +{"vlseg3e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG3E64FFV, MASK_VLSEG3E64FFV, match_opcode, INSN_DREF }, +{"vlseg4e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG4E64FFV, MASK_VLSEG4E64FFV, match_opcode, INSN_DREF }, +{"vlseg5e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG5E64FFV, MASK_VLSEG5E64FFV, match_opcode, INSN_DREF }, +{"vlseg6e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG6E64FFV, MASK_VLSEG6E64FFV, match_opcode, INSN_DREF }, +{"vlseg7e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG7E64FFV, MASK_VLSEG7E64FFV, match_opcode, INSN_DREF }, +{"vlseg8e64ff.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF }, {"vl1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, {"vl1re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE8V, MASK_VL1RE8V, match_opcode, INSN_DREF }, {"vl1re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE16V, MASK_VL1RE16V, match_opcode, INSN_DREF }, {"vl1re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE32V, MASK_VL1RE32V, match_opcode, INSN_DREF }, -{"vl1re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vl1re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL1RE64V, MASK_VL1RE64V, match_opcode, INSN_DREF }, {"vl2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, {"vl2re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE8V, MASK_VL2RE8V, match_opcode, INSN_DREF }, {"vl2re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE16V, MASK_VL2RE16V, match_opcode, INSN_DREF }, {"vl2re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE32V, MASK_VL2RE32V, match_opcode, INSN_DREF }, -{"vl2re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vl2re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL2RE64V, MASK_VL2RE64V, match_opcode, INSN_DREF }, {"vl4r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, {"vl4re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE8V, MASK_VL4RE8V, match_opcode, INSN_DREF }, {"vl4re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE16V, MASK_VL4RE16V, match_opcode, INSN_DREF }, {"vl4re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE32V, MASK_VL4RE32V, match_opcode, INSN_DREF }, -{"vl4re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vl4re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL4RE64V, MASK_VL4RE64V, match_opcode, INSN_DREF }, {"vl8r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF|INSN_ALIAS }, {"vl8re8.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE8V, MASK_VL8RE8V, match_opcode, INSN_DREF }, {"vl8re16.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE16V, MASK_VL8RE16V, match_opcode, INSN_DREF }, {"vl8re32.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE32V, MASK_VL8RE32V, match_opcode, INSN_DREF }, -{"vl8re64.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF|INSN_V_EEW64 }, +{"vl8re64.v", 0, INSN_CLASS_ZVE64X, "Vd,0(s)", MATCH_VL8RE64V, MASK_VL8RE64V, match_opcode, INSN_DREF }, {"vs1r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS1RV, MASK_VS1RV, match_opcode, INSN_DREF }, {"vs2r.v", 0, INSN_CLASS_V, "Vd,0(s)", MATCH_VS2RV, MASK_VS2RV, match_opcode, INSN_DREF }, From patchwork Fri Jul 24 10:03:23 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 139877 Return-Path: X-Original-To: patchwork@sourceware.org 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af78845sm55748435e9.8.2026.07.24.03.03.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:03:24 -0700 (PDT) Message-ID: Date: Fri, 24 Jul 2026 12:03:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 04/12] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Like FCVT.D.W{,U} and FCVT.Q.W{,U} these also are unaffected by rounding mode, and hence allowing for a respective operand is bogus. (Otherwise MASK_RM should also be used in the match field for the respectively other forms.) --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1189,9 +1189,7 @@ const struct riscv_opcode riscv_opcodes[ {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, {"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, {"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_ZCA, "", 0, 0xffffU, match_opcode, 0 }, From patchwork Fri Jul 24 10:03:43 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 139878 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8BF974BA9013 for ; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af5d4e4sm68053045e9.2.2026.07.24.03.03.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:03:44 -0700 (PDT) Message-ID: <34185d40-e19d-48e3-a6a5-f48ef4a54ebd@suse.com> Date: Fri, 24 Jul 2026 12:03:43 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 05/12] RISC-V: make FP rounding mode an optional operand From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3016.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, UPPERCASE_50_75 shortcircuit=no autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Model this after Vm (and somewhat after its VM counterpart): It's similarly always last, and we can hence similarly reduce the number of entries in the opcode table. The exception being FCVTMOD.W.D, where M needs using. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1614,6 +1614,7 @@ validate_riscv_insn (const struct riscv_ case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; case 'R': /* RS3, floating point. */ case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; + case 'M': case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; @@ -3601,7 +3602,17 @@ riscv_ip (char *str, struct riscv_cl_ins } continue; - case 'm': /* Rounding mode. */ + case 'm': /* Optional rounding mode. */ + if (*asarg == '\0') + { + INSERT_OPERAND (RM, *ip, OP_MASK_RM); + continue; + } + if (*asarg != ',') + break; + ++asarg; + /* Fall through. */ + case 'M': /* Rounding mode. */ if (arg_lookup (&asarg, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) { --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -573,6 +573,11 @@ print_insn_args (const char *oparg, insn break; case 'm': + if (EXTRACT_OPERAND (RM, l) == OP_MASK_RM) + break; + print (info->stream, dis_style_text, ","); + /* Fall through. */ + case 'M': arg_print (info, EXTRACT_OPERAND (RM, l), riscv_rm, ARRAY_SIZE (riscv_rm)); break; --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -939,61 +939,40 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 }, {"fsgnjn.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 }, {"fsgnjx.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 }, -{"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 }, -{"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 }, -{"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 }, -{"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 }, -{"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 }, -{"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 }, -{"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 }, -{"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 }, -{"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 }, -{"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 }, +{"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 }, +{"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 }, +{"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 }, +{"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 }, +{"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,Sm", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 }, {"fmin.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 }, {"fmax.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 }, -{"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 }, -{"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 }, -{"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 }, -{"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 }, -{"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 }, -{"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 }, -{"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 }, -{"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 }, -{"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 }, -{"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 }, -{"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 }, -{"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 }, -{"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, -{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, +{"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 }, +{"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 }, +{"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 }, +{"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 }, +{"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 }, +{"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 }, +{"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, +{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, {"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, {"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, -{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 }, -{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, -{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, +{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,Sm", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, +{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, +{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, {"fclass.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, {"flt.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, {"fle.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, {"fgt.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, INSN_ALIAS }, {"fge.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, INSN_ALIAS }, -{"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 }, -{"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, -{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 }, -{"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 }, -{"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 }, -{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, +{"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, +{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 }, +{"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 }, +{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, /* Zfbfmin instructions. */ -{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, -{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,Sm", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, {"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, /* Single-precision floating-point instruction subset. */ @@ -1031,48 +1010,31 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, {"fsgnjn.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, {"fsgnjx.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, -{"fadd.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 }, -{"fadd.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, -{"fsub.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 }, -{"fsub.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, -{"fmul.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 }, -{"fmul.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, -{"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 }, -{"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, -{"fsqrt.s", 0, INSN_CLASS_F_INX, "D,S", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 }, -{"fsqrt.s", 0, INSN_CLASS_F_INX, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, +{"fadd.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, +{"fsub.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, +{"fmul.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, +{"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, +{"fsqrt.s", 0, INSN_CLASS_F_INX, "D,Sm", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, {"fmin.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, {"fmax.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, -{"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 }, -{"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, -{"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 }, -{"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, -{"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 }, -{"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, -{"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 }, -{"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, -{"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 }, -{"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, -{"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, -{"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, -{"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, -{"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, +{"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, +{"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, +{"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, +{"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, +{"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, +{"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, +{"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, +{"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, {"fclass.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, {"feq.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, {"flt.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, {"fle.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, {"fgt.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, INSN_ALIAS }, {"fge.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, INSN_ALIAS }, -{"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 }, -{"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, -{"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, -{"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, -{"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, -{"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, +{"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, +{"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, +{"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, +{"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, /* Double-precision floating-point instruction subset. */ {"fld", 0, INSN_CLASS_ZCD, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, @@ -1089,35 +1051,23 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, {"fsgnjn.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, {"fsgnjx.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, {"fmin.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, {"fmax.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, {"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, {"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, {"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, {"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, {"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, {"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, @@ -1126,14 +1076,10 @@ const struct riscv_opcode riscv_opcodes[ {"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,sm", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,sm", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, /* Quad-precision floating-point instruction subset. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, @@ -1146,48 +1092,33 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, {"fsgnjn.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, {"fsgnjx.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, +{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, +{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, +{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, +{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, +{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, {"fmin.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, {"fmax.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, +{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, +{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, +{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, +{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, {"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, {"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, {"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, {"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, {"fclass.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, {"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, {"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, {"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, {"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS }, {"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS }, -{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, {"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, {"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, @@ -1330,23 +1261,15 @@ const struct riscv_opcode riscv_opcodes[ {"fmaxm.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,T", MATCH_FMAXM_Q, MASK_FMAXM_Q, match_opcode, 0 }, {"fminm.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMINM_H, MASK_FMINM_H, match_opcode, 0 }, {"fmaxm.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMAXM_H, MASK_FMAXM_H, match_opcode, 0 }, -{"fround.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUND_S|MASK_RM, MASK_FROUND_S|MASK_RM, match_opcode, 0 }, -{"fround.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUND_S, MASK_FROUND_S, match_opcode, 0 }, -{"froundnx.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUNDNX_S|MASK_RM, MASK_FROUNDNX_S|MASK_RM, match_opcode, 0 }, -{"froundnx.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUNDNX_S, MASK_FROUNDNX_S, match_opcode, 0 }, -{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUND_D|MASK_RM, MASK_FROUND_D|MASK_RM, match_opcode, 0 }, -{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUND_D, MASK_FROUND_D, match_opcode, 0 }, -{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUNDNX_D|MASK_RM, MASK_FROUNDNX_D|MASK_RM, match_opcode, 0 }, -{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUNDNX_D, MASK_FROUNDNX_D, match_opcode, 0 }, -{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUND_Q|MASK_RM, MASK_FROUND_Q|MASK_RM, match_opcode, 0 }, -{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUND_Q, MASK_FROUND_Q, match_opcode, 0 }, -{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUNDNX_Q|MASK_RM, MASK_FROUNDNX_Q|MASK_RM, match_opcode, 0 }, -{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, match_opcode, 0 }, -{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUND_H|MASK_RM, MASK_FROUND_H|MASK_RM, match_opcode, 0 }, -{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUND_H, MASK_FROUND_H, match_opcode, 0 }, -{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUNDNX_H|MASK_RM, MASK_FROUNDNX_H|MASK_RM, match_opcode, 0 }, -{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUNDNX_H, MASK_FROUNDNX_H, match_opcode, 0 }, -{"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,m", MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, match_opcode, 0 }, +{"fround.s", 0, INSN_CLASS_ZFA, "D,Sm", MATCH_FROUND_S, MASK_FROUND_S, match_opcode, 0 }, +{"froundnx.s", 0, INSN_CLASS_ZFA, "D,Sm", MATCH_FROUNDNX_S, MASK_FROUNDNX_S, match_opcode, 0 }, +{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,Sm", MATCH_FROUND_D, MASK_FROUND_D, match_opcode, 0 }, +{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,Sm", MATCH_FROUNDNX_D, MASK_FROUNDNX_D, match_opcode, 0 }, +{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,Sm", MATCH_FROUND_Q, MASK_FROUND_Q, match_opcode, 0 }, +{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,Sm", MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, match_opcode, 0 }, +{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,Sm", MATCH_FROUND_H, MASK_FROUND_H, match_opcode, 0 }, +{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,Sm", MATCH_FROUNDNX_H, MASK_FROUNDNX_H, match_opcode, 0 }, +{"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,M", MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, match_opcode, 0 }, {"fmvh.x.d", 32, INSN_CLASS_D_AND_ZFA, "d,S", MATCH_FMVH_X_D, MASK_FMVH_X_D, match_opcode, 0 }, {"fmvp.d.x", 32, INSN_CLASS_D_AND_ZFA, "D,s,t", MATCH_FMVP_D_X, MASK_FMVP_D_X, match_opcode, 0 }, {"fmvh.x.q", 64, INSN_CLASS_Q_AND_ZFA, "d,S", MATCH_FMVH_X_Q, MASK_FMVH_X_Q, match_opcode, 0 }, From patchwork Fri Jul 24 10:04:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 139879 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 96AE34BA79AE for ; Fri, 24 Jul 2026 10:05:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 96AE34BA79AE Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957af16f72sm64734715e9.0.2026.07.24.03.04.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:04:14 -0700 (PDT) Message-ID: <8873df38-aa72-4643-91b3-4037643b2717@suse.com> Date: Fri, 24 Jul 2026 12:04:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 06/12] RISC-V: check operands for Zdinx in RV32 From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Like for Zilsd, register pair operands are required to be encoded with the low bit clear. Since match functions don't have XLEN available, introduce respective flags, to be used explicitly in assembler and disassembler. --- No similar checking is easily possible for scalar vector insns, as element width there isn't encoded in the insn. (Plus V and Zdinx can't be enabled together right now anyway.) We could further use RV32_EVEN_CHECK for Zilsd as well, then allowing to eliminate one or two match functions. (Hence RV32_EVEN_CHECK()'s scope is pretty wide.) --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -3004,6 +3004,12 @@ riscv_ip (char *str, struct riscv_cl_ins *imm_reloc = BFD_RELOC_UNUSED; p = percent_op_null; +#define RV32_EVEN_CHECK(form, rclass, regno) \ + (!(ip->insn_mo->pinfo & INSN_RV32_EVEN_##form) \ + || xlen != 32 \ + || (rclass) != RCLASS_GPR \ + || !((regno) & 1)) + for (oparg = insn->args;; ++oparg) { opargStart = oparg; @@ -3011,6 +3017,8 @@ riscv_ip (char *str, struct riscv_cl_ins ++asarg; switch (*oparg) { + enum reg_class rclass; + case '\0': /* End of args. */ if (insn->match_func && !insn->match_func (insn, ip->insn_opcode)) break; @@ -3670,32 +3678,40 @@ riscv_ip (char *str, struct riscv_cl_ins case 'T': /* Floating point RS2. */ case 'U': /* Floating point RS1 and RS2. */ case 'R': /* Floating point RS3. */ - if (reg_lookup (&asarg, - (riscv_subset_supports (&riscv_rps_as, "zfinx") - ? RCLASS_GPR : RCLASS_FPR), ®no)) + rclass = riscv_subset_supports (&riscv_rps_as, "zfinx") + ? RCLASS_GPR : RCLASS_FPR; + if (reg_lookup (&asarg, rclass, ®no)) { char c = *oparg; if (is_whitespace (*asarg)) ++asarg; + switch (c) { case 'D': + if (!RV32_EVEN_CHECK (D, rclass, regno)) + break; INSERT_OPERAND (RD, *ip, regno); - break; + continue; case 'S': + if (!RV32_EVEN_CHECK (S, rclass, regno)) + break; INSERT_OPERAND (RS1, *ip, regno); - break; + continue; case 'U': INSERT_OPERAND (RS1, *ip, regno); /* Fall through. */ case 'T': + if (!RV32_EVEN_CHECK (T, rclass, regno)) + break; INSERT_OPERAND (RS2, *ip, regno); - break; + continue; case 'R': + if (!RV32_EVEN_CHECK (R, rclass, regno)) + break; INSERT_OPERAND (RS3, *ip, regno); - break; + continue; } - continue; } break; @@ -4530,6 +4546,8 @@ riscv_ip (char *str, struct riscv_cl_ins insn_with_csr = false; } +#undef RV32_EVEN_CHECK + out: /* Restore the character we might have clobbered above. */ if (save_c) --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32.d @@ -0,0 +1,52 @@ +#as: -march=rv32i_zdinx +#objdump: -dwr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e60553[ ]+fadd\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae60553[ ]+fsub\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e60553[ ]+fmul\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae60553[ ]+fdiv\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a060553[ ]+fsqrt\.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60543[ ]+fmadd\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054f[ ]+fnmadd\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60547[ ]+fmsub\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054b[ ]+fnmsub\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt\.w\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20605d3[ ]+fcvt\.w\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt\.wu\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21605d3[ ]+fcvt\.wu\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt\.d\.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt\.d\.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt\.d\.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt\.s\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401605d3[ ]+fcvt\.s\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42258553[ ]+fcvt\.d\.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+441675d3[ ]+fcvt\.h\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+441605d3[ ]+fcvt\.h\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq\.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt\.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle\.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt\.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle\.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass\.d[ ]+a1,a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32.s @@ -0,0 +1,52 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rne + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rne + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rne + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rne + fsqrt.d a0, a2 + fsqrt.d a0, a2, rne + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rne + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rne + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rne + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rne + + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rne + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rne + fcvt.d.w a0, a1 + fcvt.d.wu a0, a1 + + fcvt.d.s a0, a1 + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rne + + .option push + .option arch, +zhinxmin + fcvt.d.h a0, a1 + fcvt.h.d a1, a2 + fcvt.h.d a1, a2, rne + .option pop + + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a1, a2, a4 + fle.d a1, a2, a4 + fgt.d a1, a2, a4 + fge.d a1, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + fclass.d a1, a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zdinx +#source: zdinx.s +#error_output: zdinx-rv32-fail.l --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32-fail.l @@ -0,0 +1,47 @@ +.*: Assembler messages: +.*: Error: illegal operands `fadd\.d .*' +.*: Error: illegal operands `fadd\.d .*' +.*: Error: illegal operands `fsub\.d .*' +.*: Error: illegal operands `fsub\.d .*' +.*: Error: illegal operands `fmul\.d .*' +.*: Error: illegal operands `fmul\.d .*' +.*: Error: illegal operands `fdiv\.d .*' +.*: Error: illegal operands `fdiv\.d .*' +.*: Error: illegal operands `fsqrt\.d .*' +.*: Error: illegal operands `fsqrt\.d .*' +.*: Error: illegal operands `fmin\.d .*' +.*: Error: illegal operands `fmax\.d .*' +.*: Error: illegal operands `fmadd\.d .*' +.*: Error: illegal operands `fmadd\.d .*' +.*: Error: illegal operands `fnmadd\.d .*' +.*: Error: illegal operands `fnmadd\.d .*' +.*: Error: illegal operands `fmsub\.d .*' +.*: Error: illegal operands `fmsub\.d .*' +.*: Error: illegal operands `fnmsub\.d .*' +.*: Error: illegal operands `fnmsub\.d .*' +.*: Error: illegal operands `fcvt\.w\.d .*' +.*: Error: illegal operands `fcvt\.w\.d .*' +.*: Error: illegal operands `fcvt\.wu\.d .*' +.*: Error: illegal operands `fcvt\.wu\.d .*' +.*: Error: unrecognized opcode `fcvt\.l\.d .*' +.*: Error: unrecognized opcode `fcvt\.l\.d .*' +.*: Error: unrecognized opcode `fcvt\.lu\.d .*' +.*: Error: unrecognized opcode `fcvt\.lu\.d .*' +.*: Error: unrecognized opcode `fcvt\.d\.l .*' +.*: Error: unrecognized opcode `fcvt\.d\.l .*' +.*: Error: unrecognized opcode `fcvt\.d\.lu .*' +.*: Error: unrecognized opcode `fcvt\.d\.lu .*' +.*: Error: illegal operands `fcvt\.s\.d .*' +.*: Error: illegal operands `fcvt\.s\.d .*' +.*: Error: illegal operands `fsgnj\.d .*' +.*: Error: illegal operands `fsgnjn\.d .*' +.*: Error: illegal operands `fsgnjx\.d .*' +.*: Error: illegal operands `feq\.d .*' +.*: Error: illegal operands `flt\.d .*' +.*: Error: illegal operands `fle\.d .*' +.*: Error: illegal operands `fgt\.d .*' +.*: Error: illegal operands `fge\.d .*' +.*: Error: illegal operands `fmv\.d .*' +.*: Error: illegal operands `fneg\.d .*' +.*: Error: illegal operands `fabs\.d .*' +.*: Error: illegal operands `fclass\.d .*' --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -709,6 +709,18 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Operands required to be an even-numbered register (pair) in RV32. */ +#define INSN_RV32_EVEN_D 0x00000100 +#define INSN_RV32_EVEN_S 0x00000200 +#define INSN_RV32_EVEN_T 0x00000400 /* Also covering U. */ +#define INSN_RV32_EVEN_R 0x00000800 +/* Shorthands for combinations of the above. */ +#define INSN_RV32_EVEN_DS (INSN_RV32_EVEN_D | INSN_RV32_EVEN_S) +#define INSN_RV32_EVEN_DST (INSN_RV32_EVEN_DS | INSN_RV32_EVEN_T) +#define INSN_RV32_EVEN_DSTR (INSN_RV32_EVEN_DST | INSN_RV32_EVEN_R) +#define INSN_RV32_EVEN_DU (INSN_RV32_EVEN_D | INSN_RV32_EVEN_T) +#define INSN_RV32_EVEN_ST (INSN_RV32_EVEN_S | INSN_RV32_EVEN_T) + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -1138,6 +1138,23 @@ riscv_disassemble_insn (bfd_vma memaddr, if (!riscv_multi_subset_supports (&pd->riscv_rps_dis, op->insn_class)) continue; + + if (pd->xlen == 32 + && riscv_subset_supports (&pd->riscv_rps_dis, "zdinx")) + { + if ((op->pinfo & INSN_RV32_EVEN_D) + && (word & (1u << OP_SH_RD))) + continue; + if ((op->pinfo & INSN_RV32_EVEN_S) + && (word & (1u << OP_SH_RS1))) + continue; + if ((op->pinfo & INSN_RV32_EVEN_T) + && (word & (1u << OP_SH_RS2))) + continue; + if ((op->pinfo & INSN_RV32_EVEN_R) + && (word & (1u << OP_SH_RS3))) + continue; + } } /* It's a match. */ --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -955,10 +955,10 @@ const struct riscv_opcode riscv_opcodes[ {"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, -{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, -{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, +{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,Sm", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, +{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S }, {"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, {"fclass.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, @@ -1045,35 +1045,35 @@ const struct riscv_opcode riscv_opcodes[ {"fsd", 0, INSN_CLASS_ZCD, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_ALIAS }, -{"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU }, +{"fneg.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU }, +{"fabs.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU }, +{"fsgnj.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsgnjn.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsgnjx.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_RV32_EVEN_DS }, +{"fmin.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fmax.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_RV32_EVEN_S }, +{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_RV32_EVEN_S }, +{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_RV32_EVEN_S }, +{"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_RV32_EVEN_S }, +{"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_RV32_EVEN_ST }, +{"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_RV32_EVEN_ST }, +{"fle.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_RV32_EVEN_ST }, +{"fgt.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_ALIAS|INSN_RV32_EVEN_ST }, +{"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS|INSN_RV32_EVEN_ST }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, {"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, From patchwork Fri Jul 24 10:04:32 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 139880 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957afac187sm56615335e9.11.2026.07.24.03.04.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:04:33 -0700 (PDT) Message-ID: Date: Fri, 24 Jul 2026 12:04:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 07/12] RISC-V: check operands for Zqinx From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org By analogy to Zdinx on RV32, register pair operands are presumably (there not being any formal spec afaict) required to be encoded with the low bit clear in RV64; in RV32 the low two bits need to be clear. Since match functions don't have XLEN available, introduce respective flags, to be used explicitly in assembler and disassembler. --- Does Zqinx actually make much sense in RV32? Function argument passing, for example, ends up odd: a0..a3 aren't suitable to hold an argument. Hence only a single argument can be passed in registers (a2..a5). No similar checking is easily possible for scalar vector insns, as element width there isn't encoded in the insn. (Plus V and Zqinx can't be enabled together right now anyway.) --- v3: Fix typo in comment. v2: New. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -3010,6 +3010,12 @@ riscv_ip (char *str, struct riscv_cl_ins || (rclass) != RCLASS_GPR \ || !((regno) & 1)) +#define RV64_EVEN_CHECK(form, rclass, regno) \ + (!(ip->insn_mo->pinfo & INSN_RV64_EVEN_##form) \ + || xlen > 64 \ + || (rclass) != RCLASS_GPR \ + || !((regno) & (xlen == 32 ? 3 : 1))) + for (oparg = insn->args;; ++oparg) { opargStart = oparg; @@ -3689,12 +3695,14 @@ riscv_ip (char *str, struct riscv_cl_ins switch (c) { case 'D': - if (!RV32_EVEN_CHECK (D, rclass, regno)) + if (!RV32_EVEN_CHECK (D, rclass, regno) + || !RV64_EVEN_CHECK (D, rclass, regno)) break; INSERT_OPERAND (RD, *ip, regno); continue; case 'S': - if (!RV32_EVEN_CHECK (S, rclass, regno)) + if (!RV32_EVEN_CHECK (S, rclass, regno) + || !RV64_EVEN_CHECK (S, rclass, regno)) break; INSERT_OPERAND (RS1, *ip, regno); continue; @@ -3702,12 +3710,14 @@ riscv_ip (char *str, struct riscv_cl_ins INSERT_OPERAND (RS1, *ip, regno); /* Fall through. */ case 'T': - if (!RV32_EVEN_CHECK (T, rclass, regno)) + if (!RV32_EVEN_CHECK (T, rclass, regno) + || !RV64_EVEN_CHECK (T, rclass, regno)) break; INSERT_OPERAND (RS2, *ip, regno); continue; case 'R': - if (!RV32_EVEN_CHECK (R, rclass, regno)) + if (!RV32_EVEN_CHECK (R, rclass, regno) + || !RV64_EVEN_CHECK (R, rclass, regno)) break; INSERT_OPERAND (RS3, *ip, regno); continue; @@ -4547,6 +4557,7 @@ riscv_ip (char *str, struct riscv_cl_ins } #undef RV32_EVEN_CHECK +#undef RV64_EVEN_CHECK out: /* Restore the character we might have clobbered above. */ --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32.d @@ -0,0 +1,52 @@ +#as: -march=rv32i_zqinx +#objdump: -dwr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+078a7453[ ]+fadd\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+078a0453[ ]+fadd\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+0f8a7453[ ]+fsub\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+0f8a0453[ ]+fsub\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+178a7453[ ]+fmul\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+178a0453[ ]+fmul\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+1f8a7453[ ]+fdiv\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+1f8a0453[ ]+fdiv\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+5e0a7453[ ]+fsqrt\.q[ ]+s0,s4 +[ ]+[0-9a-f]+:[ ]+5e0a0453[ ]+fsqrt\.q[ ]+s0,s4,rne +[ ]+[0-9a-f]+:[ ]+2f8a0453[ ]+fmin\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+2f8a1453[ ]+fmax\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+678a7443[ ]+fmadd\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a0443[ ]+fmadd\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+678a744f[ ]+fnmadd\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a044f[ ]+fnmadd\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+678a7447[ ]+fmsub\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a0447[ ]+fmsub\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+678a744b[ ]+fnmsub\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a044b[ ]+fnmsub\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+c60a75d3[ ]+fcvt\.w\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+c60a05d3[ ]+fcvt\.w\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+c61a75d3[ ]+fcvt\.wu\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+c61a05d3[ ]+fcvt\.wu\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+d6058453[ ]+fcvt\.q\.w[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+d6158453[ ]+fcvt\.q\.wu[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+46058453[ ]+fcvt\.q\.s[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+403a75d3[ ]+fcvt\.s\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+403a05d3[ ]+fcvt\.s\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+46150453[ ]+fcvt\.q\.d[ ]+s0,a0 +[ ]+[0-9a-f]+:[ ]+423a7553[ ]+fcvt\.d\.q[ ]+a0,s4 +[ ]+[0-9a-f]+:[ ]+423a0553[ ]+fcvt\.d\.q[ ]+a0,s4,rne +[ ]+[0-9a-f]+:[ ]+46258453[ ]+fcvt\.q\.h[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+443a75d3[ ]+fcvt\.h\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+443a05d3[ ]+fcvt\.h\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+278a0453[ ]+fsgnj\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+278a1453[ ]+fsgnjn\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+278a2453[ ]+fsgnjx\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+a78a25d3[ ]+feq\.q[ ]+a1,s4,s8 +[ ]+[0-9a-f]+:[ ]+a78a15d3[ ]+flt\.q[ ]+a1,s4,s8 +[ ]+[0-9a-f]+:[ ]+a78a05d3[ ]+fle\.q[ ]+a1,s4,s8 +[ ]+[0-9a-f]+:[ ]+a74c15d3[ ]+flt\.q[ ]+a1,s8,s4 +[ ]+[0-9a-f]+:[ ]+a74c05d3[ ]+fle\.q[ ]+a1,s8,s4 +[ ]+[0-9a-f]+:[ ]+274a0453[ ]+fmv\.q[ ]+s0,s4 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32.s @@ -0,0 +1,54 @@ +target: + fadd.q s0, s4, s8 + fadd.q s0, s4, s8, rne + fsub.q s0, s4, s8 + fsub.q s0, s4, s8, rne + fmul.q s0, s4, s8 + fmul.q s0, s4, s8, rne + fdiv.q s0, s4, s8 + fdiv.q s0, s4, s8, rne + fsqrt.q s0, s4 + fsqrt.q s0, s4, rne + fmin.q s0, s4, s8 + fmax.q s0, s4, s8 + fmadd.q s0, s4, s8, a2 + fmadd.q s0, s4, s8, a2, rne + fnmadd.q s0, s4, s8, a2 + fnmadd.q s0, s4, s8, a2, rne + fmsub.q s0, s4, s8, a2 + fmsub.q s0, s4, s8, a2, rne + fnmsub.q s0, s4, s8, a2 + fnmsub.q s0, s4, s8, a2, rne + + fcvt.w.q a1, s4 + fcvt.w.q a1, s4, rne + fcvt.wu.q a1, s4 + fcvt.wu.q a1, s4, rne + fcvt.q.w s0, a1 + fcvt.q.wu s0, a1 + + fcvt.q.s s0, a1 + fcvt.s.q a1, s4 + fcvt.s.q a1, s4, rne + + fcvt.q.d s0, a0 + fcvt.d.q a0, s4 + fcvt.d.q a0, s4, rne + + .option push + .option arch, +zhinxmin + fcvt.q.h s0, a1 + fcvt.h.q a1, s4 + fcvt.h.q a1, s4, rne + .option pop + + fsgnj.q s0, s4, s8 + fsgnjn.q s0, s4, s8 + fsgnjx.q s0, s4, s8 + feq.q a1, s4, s8 + flt.q a1, s4, s8 + fle.q a1, s4, s8 + fgt.q a1, s4, s8 + fge.q a1, s4, s8 + + fmv.q s0, s4 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zqinx +#source: zqinx.s +#error_output: zqinx-rv32-fail.l --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.l @@ -0,0 +1,42 @@ +.*: Assembler messages: +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: unrecognized opcode `fcvt\.l\.q .*' +.*: Error: unrecognized opcode `fcvt\.l\.q .*' +.*: Error: unrecognized opcode `fcvt\.lu\.q .*' +.*: Error: unrecognized opcode `fcvt\.lu\.q .*' +.*: Error: illegal operands `fcvt\.q\.w .*' +.*: Error: illegal operands `fcvt\.q\.wu .*' +.*: Error: unrecognized opcode `fcvt\.q\.l .*' +.*: Error: unrecognized opcode `fcvt\.q\.lu .*' +.*: Error: illegal operands `fcvt\.q\.s .*' +.*: Error: illegal operands `fcvt\.q\.d .*' +.*: Error: illegal operands `fsgnj\.q .*' +.*: Error: illegal operands `fsgnjn\.q .*' +.*: Error: illegal operands `fsgnjx\.q .*' +.*: Error: illegal operands `feq\.q .*' +.*: Error: illegal operands `flt\.q .*' +.*: Error: illegal operands `fle\.q .*' +.*: Error: illegal operands `fgt\.q .*' +.*: Error: illegal operands `fge\.q .*' +.*: Error: illegal operands `fmv\.q .*' +.*: Error: illegal operands `fneg\.q .*' +.*: Error: illegal operands `fabs\.q .*' --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.d @@ -0,0 +1,2 @@ +#as: -march=rv64i_zqinx +#error_output: zqinx-rv64-fail.l --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.l @@ -0,0 +1,62 @@ +.*: Assembler messages: +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fcvt\.w\.q .*' +.*: Error: illegal operands `fcvt\.wu\.q .*' +.*: Error: illegal operands `fcvt\.q\.w .*' +.*: Error: illegal operands `fcvt\.q\.wu .*' +.*: Error: illegal operands `fcvt\.q\.s .*' +.*: Error: illegal operands `fcvt\.s\.q .*' +.*: Error: illegal operands `fcvt\.q\.d .*' +.*: Error: illegal operands `fcvt\.d\.q .*' +.*: Error: illegal operands `fcvt\.q\.h .*' +.*: Error: illegal operands `fcvt\.h\.q .*' +.*: Error: illegal operands `fsgnj\.q .*' +.*: Error: illegal operands `fsgnjn\.q .*' +.*: Error: illegal operands `fsgnjx\.q .*' +.*: Error: illegal operands `feq\.q .*' +.*: Error: illegal operands `flt\.q .*' +.*: Error: illegal operands `fle\.q .*' +.*: Error: illegal operands `fgt\.q .*' +.*: Error: illegal operands `fge\.q .*' +.*: Error: illegal operands `fmv\.q .*' +.*: Error: illegal operands `fmv\.q .*' +.*: Error: illegal operands `fneg\.q .*' +.*: Error: illegal operands `fneg\.q .*' +.*: Error: illegal operands `fabs\.q .*' +.*: Error: illegal operands `fabs\.q .*' +.*: Error: illegal operands `fclass\.q .*' --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.s @@ -0,0 +1,70 @@ +target: + fadd.q s1, s4, s8 + fadd.q s0, s5, s8 + fadd.q s0, s4, s9 + fsub.q s1, s4, s8 + fsub.q s0, s5, s8 + fsub.q s0, s4, s9 + fmul.q s1, s4, s8 + fmul.q s0, s5, s8 + fmul.q s0, s4, s9 + fdiv.q s1, s4, s8 + fdiv.q s0, s5, s8 + fdiv.q s0, s4, s9 + fsqrt.q s1, s4 + fsqrt.q s0, s5 + fmin.q s1, s4, s8 + fmin.q s0, s5, s8 + fmin.q s0, s4, s9 + fmax.q s1, s4, s8 + fmax.q s0, s5, s8 + fmax.q s0, s4, s9 + fmadd.q s1, s4, s8, a2 + fmadd.q s0, s5, s8, a2 + fmadd.q s0, s4, s9, a2 + fmadd.q s0, s4, s8, a3 + fnmadd.q s1, s4, s8, a2 + fnmadd.q s0, s5, s8, a2 + fnmadd.q s0, s4, s9, a2 + fnmadd.q s0, s4, s8, a3 + fmsub.q s1, s4, s8, a2 + fmsub.q s0, s5, s8, a2 + fmsub.q s0, s4, s9, a2 + fmsub.q s0, s4, s8, a3 + fnmsub.q s1, s4, s8, a2 + fnmsub.q s0, s5, s8, a2 + fnmsub.q s0, s4, s9, a2 + fnmsub.q s0, s4, s8, a3 + + fcvt.w.q a0, s5 + fcvt.wu.q a0, s5 + fcvt.q.w s1, a0 + fcvt.q.wu s1, a0 + + fcvt.q.s s1, a0 + fcvt.s.q a0, s5 + + fcvt.q.d s1, a0 + fcvt.d.q a0, s5 + + .option push + .option arch, +zhinxmin + fcvt.q.h s1, a0 + fcvt.h.q a0, s5 + .option pop + + fsgnj.q s1, s4, s8 + fsgnjn.q s0, s5, s8 + fsgnjx.q s0, s4, s9 + feq.q a0, s5, s8 + flt.q a0, s4, s9 + fle.q a0, s5, s8 + fgt.q a0, s4, s9 + fge.q a0, s5, s8 + fmv.q s1, s4 + fmv.q s0, s5 + fneg.q s1, s4 + fneg.q s0, s5 + fabs.q s1, s4 + fabs.q s0, s5 + fclass.q a0, s5 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -721,6 +721,19 @@ struct riscv_opcode #define INSN_RV32_EVEN_DU (INSN_RV32_EVEN_D | INSN_RV32_EVEN_T) #define INSN_RV32_EVEN_ST (INSN_RV32_EVEN_S | INSN_RV32_EVEN_T) +/* Operands required to be an even-numbered register (pair) in RV64, and one + divisible by 4 on RV32. */ +#define INSN_RV64_EVEN_D 0x00001000 +#define INSN_RV64_EVEN_S 0x00002000 +#define INSN_RV64_EVEN_T 0x00004000 /* Also covering U. */ +#define INSN_RV64_EVEN_R 0x00008000 +/* Shorthands for combinations of the above. */ +#define INSN_RV64_EVEN_DS (INSN_RV64_EVEN_D | INSN_RV64_EVEN_S) +#define INSN_RV64_EVEN_DST (INSN_RV64_EVEN_DS | INSN_RV64_EVEN_T) +#define INSN_RV64_EVEN_DSTR (INSN_RV64_EVEN_DST | INSN_RV64_EVEN_R) +#define INSN_RV64_EVEN_DU (INSN_RV64_EVEN_D | INSN_RV64_EVEN_T) +#define INSN_RV64_EVEN_ST (INSN_RV64_EVEN_S | INSN_RV64_EVEN_T) + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -1155,6 +1155,25 @@ riscv_disassemble_insn (bfd_vma memaddr, && (word & (1u << OP_SH_RS3))) continue; } + + if (pd->xlen <= 64 + && riscv_subset_supports (&pd->riscv_rps_dis, "zqinx")) + { + unsigned int mask = pd->xlen == 32 ? 3 : 1; + + if ((op->pinfo & INSN_RV64_EVEN_D) + && (word & (mask << OP_SH_RD))) + continue; + if ((op->pinfo & INSN_RV64_EVEN_S) + && (word & (mask << OP_SH_RS1))) + continue; + if ((op->pinfo & INSN_RV64_EVEN_T) + && (word & (mask << OP_SH_RS2))) + continue; + if ((op->pinfo & INSN_RV64_EVEN_R) + && (word & (mask << OP_SH_RS3))) + continue; + } } /* It's a match. */ --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -956,10 +956,10 @@ const struct riscv_opcode riscv_opcodes[ {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, {"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, -{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, +{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,Sm", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S }, -{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, +{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, INSN_RV64_EVEN_S }, {"fclass.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, {"flt.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, @@ -1086,41 +1086,41 @@ const struct riscv_opcode riscv_opcodes[ {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS }, -{"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS }, -{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU }, +{"fneg.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU }, +{"fabs.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU }, +{"fsgnj.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsgnjn.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsgnjx.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_RV64_EVEN_DS }, +{"fmin.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fmax.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_RV64_EVEN_D|INSN_RV32_EVEN_S }, +{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_RV32_EVEN_D|INSN_RV64_EVEN_S }, +{"fclass.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_RV64_EVEN_S }, +{"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_RV64_EVEN_ST }, +{"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_RV64_EVEN_ST }, +{"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_RV64_EVEN_ST }, +{"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST }, +{"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST }, +{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_ZCA, "", 0, 0xffffU, match_opcode, 0 }, From patchwork Fri Jul 24 10:05:04 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957afac44bsm66580985e9.9.2026.07.24.03.05.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:05:05 -0700 (PDT) Message-ID: <79efa0c6-7c9a-4b95-8404-d983e62790ed@suse.com> Date: Fri, 24 Jul 2026 12:05:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 08/12] RISC-V/gas: .attribute vs .insn From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org "... before any instruction", as the diagnostic from s_riscv_attribute() says, presumably ought to include also insns resulting from .insn. Make a small helper function. Reviewed-by: Jiawei --- RFC: I can't quite figure why this constraint exists, so there may also be the option of relaxing things (up to fully dropping start_assemble). --- v2: Style correction. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -4650,6 +4650,18 @@ riscv_ip_hardcode (char *str, return NULL; } +/* The architecture and privileged elf attributes should be set before + assembling. */ +static bool +start_assembly (void) +{ + start_assemble = true; + + riscv_set_abi_by_arch (); + + return riscv_set_default_priv_spec (NULL); +} + void md_assemble (char *str) { @@ -4657,16 +4669,8 @@ md_assemble (char *str) expressionS imm_expr; bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; - /* The architecture and privileged elf attributes should be set - before assembling. */ - if (!start_assemble) - { - start_assemble = true; - - riscv_set_abi_by_arch (); - if (!riscv_set_default_priv_spec (NULL)) - return; - } + if (!start_assemble && !start_assembly()) + return; riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); @@ -5875,6 +5879,9 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; char save_c; + if (!start_assemble && !start_assembly()) + return; + while (!is_end_of_stmt (*input_line_pointer)) ++input_line_pointer; From patchwork Fri Jul 24 10:05:39 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 139883 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 458094BA23DD for ; Fri, 24 Jul 2026 10:11:22 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by sourceware.org (Postfix) with ESMTPS id 2B24E4BA2E11 for ; Fri, 24 Jul 2026 10:05:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2B24E4BA2E11 Authentication-Results: sourceware.org; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4957afb9b29sm63157135e9.14.2026.07.24.03.05.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:05:40 -0700 (PDT) Message-ID: <90b222f1-b4b0-4748-ba83-3143d8f363d0@suse.com> Date: Fri, 24 Jul 2026 12:05:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 09/12] RISC-V/gas: warn about non-boolean unaligned-access attribute From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org The attribute being a boolean one, values should be solely 0 or 1. Reviewed-by: Jiawei --- Shouldn't settings accumulate, much like what riscv_merge_attributes() does? --- v2: New. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -6105,14 +6105,13 @@ s_riscv_attribute (int ignored ATTRIBUTE { obj_attr_tag_t tag = obj_attr_process_attribute (OBJ_ATTR_PROC); unsigned old_xlen; - obj_attribute *attr; + const obj_attribute *attr = elf_known_obj_attributes_proc (stdoutput); explicit_attr = true; switch (tag) { case Tag_RISCV_arch: old_xlen = xlen; - attr = elf_known_obj_attributes_proc (stdoutput); if (!start_assemble) riscv_set_arch (attr[Tag_RISCV_arch].s); else @@ -6138,6 +6137,11 @@ s_riscv_attribute (int ignored ATTRIBUTE "any instructions")); break; + case Tag_RISCV_unaligned_access: + if (attr[Tag_RISCV_unaligned_access].i > 1) + as_warn (_("`unaligned_access' attribute with non-boolean value")); + break; + default: break; } --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-warn.d @@ -0,0 +1,7 @@ +#as: -march-attr +#readelf: -A +#warning_output: attribute-warn.l + +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-warn.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*:2: Warning: `unaligned_access' attribute with non-boolean value --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-warn.s @@ -0,0 +1,3 @@ + .attribute unaligned_access, 1 + .attribute unaligned_access, 0x1234 + .attribute unaligned_access, 0 From patchwork Fri Jul 24 10:06:03 2026 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f85b9a596sm23323893f8f.4.2026.07.24.03.06.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:06:03 -0700 (PDT) Message-ID: <6f5e4577-ec5e-4393-9df0-3b9c50de7d81@suse.com> Date: Fri, 24 Jul 2026 12:06:03 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 10/12] RISC-V/gas: warn about non-power-of-2 stack-align attribute From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Only power-of-2 values are sensible for alignment. Reviewed-by: Jiawei --- Should we reject changing an already set non-zero value, like riscv_merge_attributes() does? Should we permit 0 as an explicit indication of "attribute not set"? --- v2: New. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -6137,6 +6137,13 @@ s_riscv_attribute (int ignored ATTRIBUTE "any instructions")); break; + case Tag_RISCV_stack_align: + if (!attr[Tag_RISCV_stack_align].i + || (attr[Tag_RISCV_stack_align].i & + (attr[Tag_RISCV_stack_align].i - 1))) + as_warn (_("`stack_align' attribute with non-power-of-2 value")); + break; + case Tag_RISCV_unaligned_access: if (attr[Tag_RISCV_unaligned_access].i > 1) as_warn (_("`unaligned_access' attribute with non-boolean value")); --- a/gas/testsuite/gas/riscv/attribute-warn.d +++ b/gas/testsuite/gas/riscv/attribute-warn.d @@ -4,4 +4,5 @@ Attribute Section: riscv File Attributes + Tag_RISCV_stack_align: 65536-bytes Tag_RISCV_arch: [a-zA-Z0-9_\"].* --- a/gas/testsuite/gas/riscv/attribute-warn.l +++ b/gas/testsuite/gas/riscv/attribute-warn.l @@ -1,2 +1,4 @@ .*: Assembler messages: .*:2: Warning: `unaligned_access' attribute with non-boolean value +.*:5: Warning: `stack_align' attribute with non-power-of-2 value +.*:6: Warning: `stack_align' attribute with non-power-of-2 value --- a/gas/testsuite/gas/riscv/attribute-warn.s +++ b/gas/testsuite/gas/riscv/attribute-warn.s @@ -1,3 +1,7 @@ .attribute unaligned_access, 1 .attribute unaligned_access, 0x1234 .attribute unaligned_access, 0 + + .attribute stack_align, 0 + .attribute stack_align, 0x4444 + .attribute stack_align, 0x10000 From patchwork Fri Jul 24 10:06:22 2026 Content-Type: text/plain; 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Convert other non-zero values to 1. Reviewed-by: Jiawei jiawei@iscas.ac.cn --- v4: Add underscore in diagnostic. v3: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -3892,6 +3892,23 @@ riscv_merge_attributes (bfd *ibfd, struc initialized. */ out_attr[0].i = 1; + for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++) + { + switch (i) + { + case Tag_RISCV_unaligned_access: + if (out_attr[i].i <= 1) + break; + + _bfd_error_handler + (_("warning: %pB uses non-boolean `unaligned_access' attribute; " + "converting to boolean"), + ibfd); + out_attr[i].i = 1; + break; + } + } + return true; } @@ -3980,7 +3997,12 @@ riscv_merge_attributes (bfd *ibfd, struc break; case Tag_RISCV_unaligned_access: - out_attr[i].i |= in_attr[i].i; + if (in_attr[i].i > 1) + _bfd_error_handler + (_("warning: %pB uses non-boolean `unaligned_access' attribute; " + "converting to boolean"), + ibfd); + out_attr[i].i |= !!in_attr[i].i; break; case Tag_RISCV_stack_align: From patchwork Fri Jul 24 10:06:41 2026 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f96b9abc0sm4748661f8f.32.2026.07.24.03.06.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 24 Jul 2026 03:06:42 -0700 (PDT) Message-ID: <9ab61932-ebdf-4136-bb1f-b9482aa75ea7@suse.com> Date: Fri, 24 Jul 2026 12:06:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v4 12/12] RISC-V/bfd: warn about non-power-of-2 stack-align attribute From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <6801be76-4052-4c49-87f2-6a08950368c0@suse.com> X-Spam-Status: No, score=-3015.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Only power-of-2 values are sensible for alignment. Reject other values. While there also drop a redundant part of a related conditional. Reviewed-by: Jiawei jiawei@iscas.ac.cn --- v4: Add underscore in diagnostic. v3: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -3906,6 +3906,17 @@ riscv_merge_attributes (bfd *ibfd, struc ibfd); out_attr[i].i = 1; break; + + case Tag_RISCV_stack_align: + if (!(out_attr[i].i & (out_attr[i].i - 1))) + break; + + _bfd_error_handler + (_("warning: %pB uses non-power-of-2 `stack_align' attribute; " + "ignoring"), + ibfd); + out_attr[i].i = 0; + break; } } @@ -4006,10 +4017,14 @@ riscv_merge_attributes (bfd *ibfd, struc break; case Tag_RISCV_stack_align: - if (out_attr[i].i == 0) + if ((in_attr[i].i & (in_attr[i].i - 1)) != 0) + _bfd_error_handler + (_("warning: %pB uses non-power-of-2 `stack_align' attribute; " + "ignoring"), + ibfd); + else if (out_attr[i].i == 0) out_attr[i].i = in_attr[i].i; else if (in_attr[i].i != 0 - && out_attr[i].i != 0 && out_attr[i].i != in_attr[i].i) { _bfd_error_handler