From patchwork Fri Jul 17 10:38:53 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsing X-Patchwork-Id: 139395 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 20F8C4BA2E04 for ; Fri, 17 Jul 2026 10:43:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 20F8C4BA2E04 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=aJJ8mKSe X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from va-2-29.ptr.blmpb.com (va-2-29.ptr.blmpb.com [209.127.231.29]) by sourceware.org (Postfix) with ESMTPS id 924454BA2E10 for ; Fri, 17 Jul 2026 10:39:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 924454BA2E10 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 924454BA2E10 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=209.127.231.29 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284770; cv=none; b=fpU8p3E2jOxuYzU5B914prE0RjOrmeqPK1TCr77MRPKLB7Jz6c7Jd16cZhY7bg/0ZyBUpZsAaDFFG1PWa6YVJf9bTGVCIo79nU9iwOcul2VUNglNv7ISZemP6YRRLurpivprlPFJF7M+RxoYgqO48Faf8/qXiQvCsJuphbNt1P0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284770; c=relaxed/simple; bh=xnaXKZ3k1o1Pksk/lG2dNdcZ72VgXDfNNWpsHC3jlDU=; h=DKIM-Signature:Date:From:Message-Id:Mime-Version:To:Subject; b=XmvV5lTcQr6amILzIK4pfcPaXltp2CrmqspIvm+PJ0O5snVHQmLxFNU5SgkpbUrctdUYL0BT9g+bSvL7/4o5MuKDjpETFPYxkl2miPWhdxtGcVLWooG/lNBlRp3KWUKr1VCYprOEQIhIzSEOq9NItQ0JfhdA8QP3y0TUR2nydaM= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=aJJ8mKSe DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 924454BA2E10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1784284762; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=JP10DkB6RZjHOImzzC0WitP67WQjm8bo5waskkfBj5A=; b=aJJ8mKSeGaV3qm54WCj4vrhv8atdXbCvvgPqZ05sMpEUl9QnPTWfmK6IefmPeA17CqpozE 3a5tPrn/qdtHcC/yJ9rZUYcMNTpgJLwqS784uXJgyJm1MmgQGLpRxLALMjyZ2NwAHI4OBt R4nfE7LxJL4DRR3QBOeff6W0B+B+sy2xknXf23lzXMPo5Hx484/0IOpYXx9KVq+OGbBpIc T+zcFWdd2wuuQQcRfsOCB9tJt2gJdqqpCHHPegMLMI2NCC0TTajRxpatzcusIUGAmklC3f Z2tZo3TJAo6Kg/UWl5cwGd/orwVLsOxr0QJ8Bx9rlwbnPZVQIgDSe3RqcNWxpA== Date: Fri, 17 Jul 2026 18:38:53 +0800 References: <20260717103858.199743-1-lei.wang@oss.cipunited.com> From: "Tsing" Message-Id: <20260717103858.199743-2-lei.wang@oss.cipunited.com> Mime-Version: 1.0 X-Lms-Return-Path: X-Original-From: Tsing To: Subject: [PATCH 1/6] Gas changes for nanoMIPS support. X-Mailer: git-send-email 2.39.5 Received: from B1.wok.cipunited.com ([123.52.17.40]) by smtp.feishu.cn with ESMTPS; Fri, 17 Jul 2026 18:39:18 +0800 In-Reply-To: <20260717103858.199743-1-lei.wang@oss.cipunited.com> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_STOCKGEN, MSGID_FROM_MTA_HEADER, RCVD_IN_PBL, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: tsing / * configure.ac: Add nanoMIPS target. * config.sub: Likewise. * configure: Regenerate. config/ * mt-nanomips: New file. gas/ * Makefile.am: Add nanomips files. * Makefile.in: Regenerate. * config.in: Define a default architecture. * configure: Regenerate. * configure.ac: Likewise. * configure.tgt: Add entries for nanomips. * read.c: Likewise. * config/obj-elf.h: Likewise. * config/tc-nanomips.c: New file. * config/tc-nanomips.h: New file. ld/ * configure.tgt: Add nanomips entries. --- config/mt-nanomips | 3 + configure | 9 + configure.ac | 9 + gas/Makefile.am | 2 + gas/Makefile.in | 5 + gas/config.in | 9 + gas/config/obj-elf.h | 5 + gas/config/tc-nanomips.c | 11667 +++++++++++++++++++++++++++++++++++++ gas/config/tc-nanomips.h | 187 + gas/configure | 54 + gas/configure.ac | 45 + gas/configure.tgt | 5 + gas/read.c | 2 +- ld/configure.tgt | 2 + 14 files changed, 12003 insertions(+), 1 deletion(-) create mode 100644 config/mt-nanomips create mode 100644 gas/config/tc-nanomips.c create mode 100644 gas/config/tc-nanomips.h diff --git a/config/mt-nanomips b/config/mt-nanomips new file mode 100644 index 00000000000..48037c5001e --- /dev/null +++ b/config/mt-nanomips @@ -0,0 +1,3 @@ +# We default to building libraries optimised for size. +CFLAGS_FOR_TARGET += -Os -mno-gpopt +CXXFLAGS_FOR_TARGET += -Os -mno-gpopt diff --git a/configure b/configure index 4c2aa195810..4efb0bacc9a 100755 --- a/configure +++ b/configure @@ -4194,6 +4194,12 @@ case "${target}" in mips*-*-*) noconfigdirs="$noconfigdirs gprof" ;; + nanomips*-*-elf*) + noconfigdirs="$noconfigdirs gprof gdb sim" + ;; + nanomips*-*-linux*) + noconfigdirs="$noconfigdirs gprof gdb sim" + ;; nvptx*-*-*) noconfigdirs="$noconfigdirs target-libssp" ;; @@ -10895,6 +10901,9 @@ case "${target}" in mips*-*-*linux* | mips*-*-gnu*) target_makefile_frag="config/mt-mips-gnu" ;; + nanomips*-*-*linux*) + target_makefile_frag="config/mt-nanomips" + ;; *-*-linux-android*) target_makefile_frag="config/mt-android" ;; diff --git a/configure.ac b/configure.ac index cae0042411b..7b2481d35f4 100644 --- a/configure.ac +++ b/configure.ac @@ -1363,6 +1363,12 @@ case "${target}" in mips*-*-*) noconfigdirs="$noconfigdirs gprof" ;; + nanomips*-*-elf*) + noconfigdirs="$noconfigdirs gprof gdb sim" + ;; + nanomips*-*-linux*) + noconfigdirs="$noconfigdirs gprof gdb sim" + ;; nvptx*-*-*) noconfigdirs="$noconfigdirs target-libssp" ;; @@ -3079,6 +3085,9 @@ case "${target}" in mips*-*-*linux* | mips*-*-gnu*) target_makefile_frag="config/mt-mips-gnu" ;; + nanomips*-*-*linux*) + target_makefile_frag="config/mt-nanomips" + ;; *-*-linux-android*) target_makefile_frag="config/mt-android" ;; diff --git a/gas/Makefile.am b/gas/Makefile.am index 9f90a1de50e..e954f671eb9 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -179,6 +179,7 @@ TARGET_CPU_CFILES = \ config/tc-metag.c \ config/tc-microblaze.c \ config/tc-mips.c \ + config/tc-nanomips.c \ config/tc-mmix.c \ config/tc-mn10200.c \ config/tc-mn10300.c \ @@ -253,6 +254,7 @@ TARGET_CPU_HFILES = \ config/tc-metag.h \ config/tc-microblaze.h \ config/tc-mips.h \ + config/tc-nanomips.h \ config/tc-mmix.h \ config/tc-mn10200.h \ config/tc-mn10300.h \ diff --git a/gas/Makefile.in b/gas/Makefile.in index b2bb505cc69..ec8ee0fbd54 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -687,6 +687,7 @@ TARGET_CPU_CFILES = \ config/tc-moxie.c \ config/tc-msp430.c \ config/tc-mt.c \ + config/tc-nanomips.c \ config/tc-nds32.c \ config/tc-ns32k.c \ config/tc-or1k.c \ @@ -760,6 +761,7 @@ TARGET_CPU_HFILES = \ config/tc-mn10300.h \ config/tc-msp430.h \ config/tc-mt.h \ + config/tc-nanomips.h \ config/tc-nds32.h \ config/tc-ns32k.h \ config/tc-or1k.h \ @@ -1187,6 +1189,8 @@ config/tc-msp430.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-mt.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) +config/tc-nanomips.$(OBJEXT): config/$(am__dirstamp) \ + config/$(DEPDIR)/$(am__dirstamp) config/tc-nds32.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-ns32k.$(OBJEXT): config/$(am__dirstamp) \ @@ -1421,6 +1425,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-moxie.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-msp430.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-mt.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-nanomips.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-nds32.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-ns32k.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-or1k.Po@am__quote@ diff --git a/gas/config.in b/gas/config.in index ae5f41f7058..cc5a759ef84 100644 --- a/gas/config.in +++ b/gas/config.in @@ -176,6 +176,15 @@ /* Choose a default ABI for MIPS targets. */ #undef MIPS_DEFAULT_ABI +/* Default CPU for nanoMIPS targets. */ +#undef NANOMIPS_CPU_STRING_DEFAULT + +/* Generate 64-bit code by default on nanoMIPS targets. */ +#undef NANOMIPS_DEFAULT_64BIT + +/* Choose a default ABI for nanoMIPS targets. */ +#undef NANOMIPS_DEFAULT_ABI + /* Define value for nds32_arch_name */ #undef NDS32_DEFAULT_ARCH_NAME diff --git a/gas/config/obj-elf.h b/gas/config/obj-elf.h index 910b743a442..c2b0308ca1c 100644 --- a/gas/config/obj-elf.h +++ b/gas/config/obj-elf.h @@ -49,6 +49,11 @@ extern int alpha_flag_mdebug; extern int mips_flag_mdebug; #endif /* TC_MIPS */ +/* Always disable ECOFF_DEBUGGING for nanoMIPS target. */ +#ifdef TC_NANOMIPS +#define ECOFF_DEBUGGING 0 +#endif /* TC_NANOMIPS */ + #ifdef OBJ_MAYBE_ECOFF #ifndef ECOFF_DEBUGGING #define ECOFF_DEBUGGING 1 diff --git a/gas/config/tc-nanomips.c b/gas/config/tc-nanomips.c new file mode 100644 index 00000000000..be2ab339a06 --- /dev/null +++ b/gas/config/tc-nanomips.c @@ -0,0 +1,11667 @@ +/* tc-nanomips.c -- assemble code for a nanoMIPS chip. + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "as.h" +#include "config.h" +#include "subsegs.h" +#include "safe-ctype.h" + +#include "opcode/nanomips.h" +#include "dwarf2dbg.h" +#include "dw2gencfi.h" +#include + +/* Check assumptions made in this file. */ +typedef char static_assert1[sizeof (offsetT) < 8 ? -1 : 1]; +typedef char static_assert2[sizeof (valueT) < 8 ? -1 : 1]; + +#ifdef DEBUG +#define DBG(x) printf x +#else +#define DBG(x) +#endif + +#define streq(a, b) (strcmp (a, b) == 0) + +#define SKIP_SPACE_TABS(S) \ + do { while (is_whitespace (*(S))) ++(S); } while (0) + +/* Clean up namespace so we can include obj-elf.h too. */ +static int nanomips_output_flavor (void); +static int +nanomips_output_flavor (void) +{ + return OUTPUT_FLAVOR; +} + +#undef OBJ_PROCESS_STAB +#undef OUTPUT_FLAVOR +#undef S_GET_ALIGN +#undef S_GET_SIZE +#undef S_SET_ALIGN +#undef S_SET_SIZE +#undef obj_frob_file +#undef obj_frob_file_after_relocs +#undef obj_frob_symbol +#undef obj_pop_insert +#undef obj_sec_sym_ok_for_reloc +#undef OBJ_COPY_SYMBOL_ATTRIBUTES + +#include "obj-elf.h" +/* Fix any of them that we actually care about. */ +#undef OUTPUT_FLAVOR +#define OUTPUT_FLAVOR nanomips_output_flavor() + +#include "elf/nanomips.h" + +#ifndef ECOFF_DEBUGGING +#define NO_ECOFF_DEBUGGING +#define ECOFF_DEBUGGING 0 +#endif + +#include "ecoff.h" + +#define ZERO 0 +#define AT 1 +#define S0 16 +#define S7 23 +#define PIC_CALL_REG 25 +#define KT0 26 +#define KT1 27 +#define GP 28 +#define SP 29 +#define FP 30 +#define RA 31 + +#define ILLEGAL_REG (32) + +extern int target_big_endian; + +/* The name of the readonly data section. */ +#define RDATA_SECTION_NAME ".rodata" + +/* Information about an instruction, including its format, operands + and fixups. */ +struct nanomips_cl_insn +{ + /* The opcode's entry in nanomips_opcodes. */ + const struct nanomips_opcode *insn_mo; + + /* The 16-bit or 32-bit bitstring of the instruction itself. This is + a copy of INSN_MO->match with the operands filled in. */ + unsigned long insn_opcode; + + /* The lower 32-bits of a 48-bit instruction. */ + unsigned long insn_opcode_ext; + + /* The frag that contains the instruction. */ + struct frag *frag; + + /* The offset into FRAG of the first instruction byte. */ + long where; + + /* The relocs associated with the instruction, if any. */ + fixS *fixp[3]; + + /* True if this entry cannot be moved from its current position. */ + unsigned int fixed_p:1; + + /* True if this instruction occurred in a .set noreorder block. */ + unsigned int noreorder_p:1; + + /* True if this instruction is complete. */ + unsigned int complete_p:1; +}; + +/* The ABI to use. */ +enum nanomips_abi_level +{ + NO_ABI = 0, + P32_ABI, + P64_ABI, +}; + +/* The ABI to use. */ +enum mc_model_type +{ + MC_AUTO = 0, + MC_MEDIUM, + MC_LARGE, +}; + +/* nanoMIPS ABI we are using for this output file. */ +static enum nanomips_abi_level nanomips_abi = NO_ABI; + +/* nanoMIPS PIC level. */ + +enum nanomips_pic_level +{ + /* Do not generate PIC code. */ + NO_PIC, + + /* Generate medium model PIC code as in the nanoMIPS ABI. */ + SVR4_PIC, + + /* Generate large model PIC code as in the nanoMIPS ABI. */ + SVR4_LARGE_PIC, +}; + +/* This is the set of options which may be modified by the .set + pseudo-op. We use a struct so that .set push and .set pop are more + reliable. */ + +struct nanomips_set_options +{ + /* nanoMIPS ISA (Instruction Set Architecture) level. This is set to -1 + if it has not been initialized. */ + int isa; + + /* Enabled Application Specific Extensions (ASEs). Changed by `.set + ', by command line options, and based on the default + architecture. */ + int ase; + + /* Non-zero if we should not reorder instructions. Changed by `.set + reorder' and `.set noreorder'. */ + int noreorder; + + /* Non-zero if we should not permit the $at ($1) register to be used + in instructions. Changed by `.set at' and `.set noat'. */ + int noat; + + /* Non-zero if we should warn when a macro instruction expands into + more than one machine instruction. Changed by `.set nomacro' and + `.set macro'. */ + int nomacro; + + /* True if we should only emit 32-bit nanoMIPS instructions. + Changed by `.set insn32' and `.set noinsn32', and the -minsn32 + and -mno-insn32 command line options. */ + bool insn32; + + /* Restrict general purpose registers and floating point registers + to 32 bit. This is initially determined when -mgp32 or -mfp32 + is passed but can changed. */ + int gp; + int fp; + + /* nanoMIPS architecture (CPU) type. Changed by .set arch=FOO, the -march + command line option, and the default CPU. */ + int arch; + + /* True if floating-point operations are not allowed. Changed by .set + softfloat or .set hardfloat, by command line options -msoft-float or + -mhard-float. The default is false. */ + bool soft_float; + + /* True if only single-precision floating-point operations are allowed. + Changed by .set singlefloat or .set doublefloat, command-line options + -msingle-float or -mdouble-float. The default is false. */ + bool single_float; + + /* The set of ASEs that should be enabled for the user specified + architecture. This cannot be inferred from 'arch' for all cores + as processors only have a unique 'arch' if they add architecture + specific instructions (UDI). */ + int init_ase; + + /* Enable/disable balc stub optimization. */ + bool no_balc_stubs; + + /* Enable/disable register names, only for nanoMIPS. */ + bool legacyregs; + + /* Enable/disable PC-relative expansion. */ + bool pcrel; + + /* Enable/disable Position Independent data. */ + bool pid; + + /* Select PIC code. */ + enum nanomips_pic_level pic; + + /* Code/data memory model. */ + enum mc_model_type mc_model; +}; + +/* Specifies whether module level options have been checked yet. */ +static bool file_nanomips_opts_checked = false; + +/* This is the struct we use to hold the module level set of options. + Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and + fp fields to -1 to indicate that they have not been initialized. */ + +static struct nanomips_set_options file_nanomips_opts = { + /* isa */ ISA_UNKNOWN, /* ase */ 0, /* noreorder */ 0, /* at */ 0, + /* nomacro */ 0, /* insn32 */ false, /* gp */ -1, /* fp */ -1, + /* arch */ CPU_UNKNOWN, /* soft_float */ false, /* single_float */ false, + /* init_ase */ 0, /* no_balc_stubs */ true, /* legacyregs */ false, + /* pcrel */ false, /* pid */ false, /* pic */ NO_PIC, + /* mc_model */ MC_AUTO +}; + +/* This is similar to file_nanomips_opts, but for the current set of options. */ + +static struct nanomips_set_options nanomips_opts = { + /* isa */ ISA_UNKNOWN, /* ase */ 0, /* noreorder */ 0, /* at */ 0, + /* nomacro */ 0, /* insn32 */ false, /* gp */ -1, /* fp */ -1, + /* arch */ CPU_UNKNOWN, /* soft_float */ false, /* single_float */ false, + /* init_ase */ 0, /* no_balc_stubs */ true, /* legacyregs */ false, + /* pcrel */ false, /* pid */ false, /* pic */ NO_PIC, + /* mc_model */ MC_AUTO +}; + +/* Which bits of file_ase were explicitly set or cleared by ASE options. */ +static unsigned int file_ase_explicit; + +/* The argument of the -march= flag. The architecture we are assembling. */ +static const char *nanomips_arch_string; + +/* The argument of the -mtune= flag. The architecture for which we + are optimizing. */ +static int nanomips_tune = CPU_UNKNOWN; +static const char *nanomips_tune_string; + +/* True when generating 32-bit code for a 64-bit processor. */ +static int nanomips_32bitmode = 0; + +/* True if the given ABI requires 32-bit registers. */ +#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == P32_ABI) + +/* Likewise 64-bit registers. */ +#define ABI_NEEDS_64BIT_REGS(ABI) ((ABI) == P64_ABI) + +/* Return true if ISA supports 64 bit wide gp registers. */ +#define ISA_HAS_64BIT_REGS(ISA) ((ISA) == ISA_NANOMIPS64R6) + +#define GPR_SIZE nanomips_opts.gp + +#define HAVE_64BIT_OBJECTS (nanomips_abi == P64_ABI) + +/* The ABI-derived address size. */ +#define HAVE_64BIT_ADDRESSES (GPR_SIZE == 64 && nanomips_abi == P64_ABI) +#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) + +/* The size of symbolic constants (i.e., expressions of the form + "SYMBOL" or "SYMBOL + OFFSET"). */ +#define HAVE_32BIT_SYMBOLS \ + (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS) +#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS) + +/* Maximum symbol offset that can be encoded in a BFD_RELOC_GPREL16 + relocation. */ +#define MAX_GPREL_OFFSET (0x1fffc) + +/* Addresses are loaded in different ways, depending on the address size + in use. */ +#define ADDRESS_ADD_INSN "addu" + +#define ADDRESS_ADDI_INSN "addiu" + +#define ADDRESS_LOAD_INSN "lw" + +#define ADDRESS_STORE_INSN "sw" + +#define PCREL_LOAD_INSN "lwpc" + +/* The minimum and maximum signed values that can be stored in a GPR. */ +#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) +#define GPR_SMIN (-GPR_SMAX - 1) + +/* 1 if trap instructions should used for overflow rather than break + instructions. */ +static int nanomips_trap = 0; + +/* 1 if double width floating point constants should not be constructed + by assembling two single width halves within the instruction stream, + but instead loaded from memory. */ +static int nanomips_disable_float_construction; + +/* Non-zero if .set [no]relax directive was used */ +static bool toggle_linkrelax_p = false; +static bool nanomips_linkrelax_p = false; + +/* The size of objects in the small data section. */ +static unsigned int g_switch_value = 8; +/* Whether the -G option was used. */ +static int g_switch_seen = 0; + +/* If we can determine in advance that GP optimization won't be + possible, we can skip the relaxation stuff that tries to produce + GP-relative references. + + This function can only provide a guess, but it seems to work for + gcc output. It needs to guess right for gcc, otherwise gcc + will put what it thinks is a GP-relative instruction in a branch + delay slot. */ +static int nopic_need_relax (symbolS *, int); + +/* handle of the OPCODE hash table */ +static htab_t op_hash = NULL; + +/* The opcode hash table we use for the nanoMIPS ASE. */ +static htab_t nanomips_op_hash = NULL; + +/* This array holds the chars that always start a comment. If the + pre-processor is disabled, these aren't very useful */ +const char comment_chars[] = "#"; + +/* This array holds the chars that only start a comment at the beginning of + a line. If the line seems to have the form '# 123 filename' + .line and .file directives will appear in the pre-processed output */ +/* Note that input_file.c hand checks for '#' at the beginning of the + first line of the input file. This is because the compiler outputs + #NO_APP at the beginning of its output. */ +/* Also note that C style comments are always supported. */ +const char line_comment_chars[] = "#"; + +/* This array holds machine specific line separator characters. */ +const char line_separator_chars[] = ";"; + +/* Chars that can be used to separate mant from exp in floating point nums */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant */ +/* As in 0f12.456 */ +/* or 0d1.2345e12 */ +const char FLT_CHARS[] = "rRsSfFdDxXpP"; + +/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be + changed in read.c . Ideally it shouldn't have to know about it at all, + but nothing is ideal around here. */ + +/* Types of printf format used for instruction-related error messages. + "I" means int ("%d") and "S" means string ("%s"). */ +enum nanomips_insn_error_format +{ + ERR_FMT_PLAIN, + ERR_FMT_I, + ERR_FMT_SS, + ERR_FMT_SI, +}; + +/* Information about an error that was found while assembling the current + instruction. */ +struct nanomips_insn_error +{ + /* We sometimes need to match an instruction against more than one + opcode table entry. Errors found during this matching are reported + against a particular syntactic argument rather than against the + instruction as a whole. We grade these messages so that errors + against argument N have a greater priority than an error against + any argument < N, since the former implies that arguments up to N + were acceptable and that the opcode entry was therefore a closer match. + If several matches report an error against the same argument, + we only use that error if it is the same in all cases. + + min_argnum is the minimum argument number for which an error message + should be accepted. It is 0 if MSG is against the instruction as + a whole. */ + int min_argnum; + + /* The printf()-style message, including its format and arguments. */ + enum nanomips_insn_error_format format; + const char *msg; + union + { + int i; + const char *ss[2]; + struct + { + const char *s1; + int u1; + } si; + } u; +}; + +/* The error that should be reported for the current instruction. */ +static struct nanomips_insn_error insn_error; + +static int auto_align = 1; + +static int nanomips_gp_register = GP; + +/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is + equivalent to seeing no -g option at all. */ +static int nanomips_debug = 0; + +/* A list of previous instructions, with index 0 being the most recent. + We need to look back MAX_NOPS instructions when filling delay slots + or working around processor errata. We need to look back one + instruction further if we're thinking about using history to + fill a branch delay slot. */ +static struct nanomips_cl_insn history; + +/* Arrays of operands for each instruction. */ +#define MAX_OPERANDS 6 +struct nanomips_operand_array +{ + const struct nanomips_operand *operand[MAX_OPERANDS]; +}; +static struct nanomips_operand_array *nanomips_operands; + +/* Nop instructions used by emit_nop. */ +static struct nanomips_cl_insn nanomips_nop16_insn; +static struct nanomips_cl_insn nanomips_nop32_insn; + +/* The appropriate nop for the current mode. */ +#define NOP_INSN (nanomips_opts.insn32 \ + ? &nanomips_nop32_insn \ + : &nanomips_nop16_insn) + +/* The size of NOP_INSN in bytes. */ +#define NOP_INSN_SIZE (nanomips_opts.insn32? 4 : 2) + +/* If this is set, it points to a frag holding nop instructions which + were inserted before the start of a noreorder section. If those + nops turn out to be unnecessary, the size of the frag can be + decreased. */ +static fragS *prev_nop_frag; + +/* Map 3-bit register numbers to normal nanoMIPS register numbers. */ + +static const unsigned int nanomips_to_32_reg_d_map[] = { + 16, 17, 18, 19, 4, 5, 6, 7 +}; + +/* The expansion of many macros depends on the type of symbol that + they refer to. For example, when generating position-dependent code, + a macro that refers to a symbol may have two different expansions, + one which uses GP-relative addresses and one which uses absolute + addresses. When generating SVR4-style PIC, a macro may have + different expansions for local and global symbols. + + We handle these situations by generating both sequences and putting + them in variant frags. In position-dependent code, the first sequence + will be the GP-relative one and the second sequence will be the + absolute one. In SVR4 PIC, the first sequence will be for global + symbols and the second will be for local symbols. + + The frag's "subtype" is RELAX_ENCODE (FIRST, SECOND), where FIRST and + SECOND are the lengths of the two sequences in bytes. These fields + can be extracted using RELAX_FIRST() and RELAX_SECOND(). In addition, + the subtype has the following flags: + + RELAX_USE_SECOND + Set if it has been decided that we should use the second + sequence instead of the first. + + RELAX_SECOND_LONGER + Set in the first variant frag if the macro's second implementation + is longer than its first. This refers to the macro as a whole, + not an individual relaxation. + + RELAX_NOMACRO + Set in the first variant frag if the macro appeared in a .set nomacro + block and if one alternative requires a warning but the other does not. + + The frag's "opcode" points to the first fixup for relaxable code. + + Relaxable macros are generated using a sequence such as: + + relax_start (SYMBOL); + ... generate first expansion ... + relax_switch (); + ... generate second expansion ... + relax_end (); + + The code and fixups for the unwanted alternative are discarded + by md_convert_frag. */ +#define RELAX_ENCODE(FIRST, SECOND) (((FIRST) << 8) | (SECOND)) + +#define RELAX_FIRST(X) (((X) >> 8) & 0xff) +#define RELAX_SECOND(X) ((X) & 0xff) +#define RELAX_USE_SECOND 0x10000 +#define RELAX_SECOND_LONGER 0x20000 +#define RELAX_NOMACRO 0x40000 + +/* For nanoMIPS code, we use relaxation similar to one we use for + microMIPS code. Some instructions that take immediate values support + two encodings: a small one which takes some small value, and a + larger one which takes a 16 bit value. As some branches also follow + this pattern, relaxing these values is required. + + There are no delayed branches in nanoMIPS and we do not relax + 32-bit branch instructions that do not fit within 32-bit range at + assembly, so attributes related to those features are removed. + Instead we relax 32-bit calls that do not fit within 16-bit range + in to calls to 32-bit unconditional branch stubs which can fit within + 16-bit range. + + USESTUB and ONCESTUB track calls which can be relaxed to stubs. KEEPSTUB + tracks stubs that have sufficient calls (at least 3) against them to be + instantiated for reducing code size. + + TOOFAR16/NEGOFF are for relaxation of the ADDIU opcode in to + 32/NEG/R2/RS5 variants. + !TOOFAR16 && NEGOFF => ADDIU[RS5], consequent to operand constraints + !TOOFAR16 && !NEGOFF => ADDIU[R2], consequent to operand constraints + TOOFAR16 && NEGOFF => ADDIU[NEG] + TOOFAR16 && !NEGOFF => ADDIU[32] +*/ + +enum +{ + RT_ADDIU = 1, + RT_BRANCH_UCND, + RT_BRANCH_CNDZ, + RT_BRANCH_CND, + RT_BALC_STUB, +}; + +#define RELAX_MD_ENCODE(type, link, ext) \ + (0x20000000 \ + | ((type) & 0xff) \ + | ((ext) ? 0x100 : 0) \ + | ((link) ? 0x2000 : 0)) +#define RELAX_MD_P(i) (((i) & 0xe0000000) == 0x20000000) +#define RELAX_MD_TYPE(i) ((i) & 0xff) +#define RELAX_MD_LINK(i) (((i) & 0x100) != 0) + +#define RELAX_MD_BALC_STUB_P(i) \ + (RELAX_MD_P (i) && ((i) & 0xff) == RT_BALC_STUB) + +#define RELAX_MD_BRANCH_P(i) \ + (RELAX_MD_P (i) && (((i) & 0xff) == RT_BRANCH_UCND \ + || ((i) & 0xff) == RT_BRANCH_CNDZ \ + || ((i) & 0xff) == RT_BRANCH_CND)) + +#define RELAX_MD_ADDIU_P(i) \ + (RELAX_MD_P (i) && ((i) & 0xff) == RT_ADDIU) + +#define RELAX_MD_KEEPSTUB(i) (((i) & 0x200) != 0) +#define RELAX_MD_MARK_KEEPSTUB(i) ((i) | 0x200) +#define RELAX_MD_CLEAR_KEEPSTUB(i) ((i) & ~0x200) + +#define RELAX_MD_USESTUB(i) (((i) & 0x400) != 0) +#define RELAX_MD_MARK_USESTUB(i) ((i) | 0x400) +#define RELAX_MD_CLEAR_USESTUB(i) ((i) & ~0x400) + +#define RELAX_MD_ONCESTUB(i) (((i) & 0x800) != 0) +#define RELAX_MD_MARK_ONCESTUB(i) ((i) | 0x800) +#define RELAX_MD_CLEAR_ONCESTUB(i) ((i) & ~0x800) + +#define RELAX_MD_TOOFAR16(i) (((i) & 0x1000) != 0) +#define RELAX_MD_MARK_TOOFAR16(i) ((i) | 0x1000) +#define RELAX_MD_CLEAR_TOOFAR16(i) ((i) & ~0x1000) + +#define RELAX_MD_TOOFAR32(i) (((i) & 0x2000) != 0) +#define RELAX_MD_MARK_TOOFAR32(i) ((i) | 0x2000) +#define RELAX_MD_CLEAR_TOOFAR32(i) ((i) & ~0x2000) + +#define RELAX_MD_NEGOFF(i) (((i) & 0x4000) != 0) +#define RELAX_MD_MARK_NEGOFF(i) ((i) | 0x4000) +#define RELAX_MD_CLEAR_NEGOFF(i) ((i) & ~0x4000) + +#define RELAX_MD_FIXED(i) (((i) & 0x1000) != 0) + +/* Sign-extend 16-bit value X. */ +#define SEXT_16BIT(X) ((((X) + 0x8000) & 0xffff) - 0x8000) + +/* Is the given value a sign-extended 32-bit value? */ +#define IS_SEXT_32BIT_NUM(x) \ + (((x) &~ (offsetT) 0x7fffffff) == 0 \ + || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) + +/* Is the given value an unsigned 16-bit value? */ +#define IS_SEXT_16BIT_UINT(x) (((x) &~ (offsetT) 0xffff) == 0) + +/* Is the given value a sign-extended 12-bit value? */ +#define IS_SEXT_12BIT_NUM(x) (((((x) & 0xfff) ^ 0x800LL) - 0x800LL) == (x)) + +/* Is the given value a sign-extended 9-bit value? */ +#define IS_SEXT_9BIT_NUM(x) (((((x) & 0x1ff) ^ 0x100LL) - 0x100LL) == (x)) + +/* Is the given value a zero-extended 32-bit value? Or a negated one? */ +#define IS_ZEXT_32BIT_NUM(x) \ + (((x) &~ (offsetT) 0xffffffff) == 0 \ + || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) + +/* Extract bits MASK << SHIFT from STRUCT and shift them right + SHIFT places. */ +#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \ + (((STRUCT) >> (SHIFT)) & (MASK)) + +/* Global variables used when generating relaxable macros. See the + comment above RELAX_ENCODE for more details about how relaxation + is used. */ +static struct +{ + /* 0 if we're not emitting a relaxable macro. + 1 if we're emitting the first of the two relaxation alternatives. + 2 if we're emitting the second alternative. */ + int sequence; + + /* The first relaxable fixup in the current frag. (In other words, + the first fixup that refers to relaxable code.) */ + fixS *first_fixup; + + /* sizes[0] says how many bytes of the first alternative are stored in + the current frag. Likewise sizes[1] for the second alternative. */ + unsigned int sizes[2]; + + /* The symbol on which the choice of sequence depends. */ + symbolS *symbol; +} nanomips_relax; + +/* Global variables used to decide whether a macro needs a warning. */ +static struct +{ + /* For relaxable macros, sizes[0] is the length of the first alternative + in bytes and sizes[1] is the length of the second alternative. + For non-relaxable macros, both elements give the length of the + macro in bytes. */ + unsigned int sizes[2]; + + /* For relaxable macros, first_insn_sizes[0] is the length of the first + instruction of the first alternative in bytes and first_insn_sizes[1] + is the length of the first instruction of the second alternative. + For non-relaxable macros, both elements give the length of the first + instruction in bytes. + + Set to zero if we haven't yet seen the first instruction. */ + unsigned int first_insn_sizes[2]; + + /* For relaxable macros, insns[0] is the number of instructions for the + first alternative and insns[1] is the number of instructions for the + second alternative. + + For non-relaxable macros, both elements give the number of + instructions for the macro. */ + unsigned int insns[2]; + + /* The first variant frag for this macro. */ + fragS *first_frag; +} nanomips_macro_warning; + +/* Prototypes for static functions. */ + +enum nanomips_regclass + { NANOMIPS_GR_REG, NANOMIPS_FP_REG }; + +static void append_insn + (struct nanomips_cl_insn *, expressionS *, bfd_reloc_code_real_type *, + bool expansionp); +static void macro_build (expressionS *, const char *, const char *, ...); +static void load_register (int, expressionS *, int); +static void macro_start (void); +static void macro_end (bool); +static void macro (struct nanomips_cl_insn *ip, char *str); +static void nanomips_ip (char *str, struct nanomips_cl_insn *ip); +static size_t my_getSmallExpression + (expressionS *, bfd_reloc_code_real_type *, char *); +static void my_getExpression (expressionS *, char *); +static void s_align (int); +static void s_change_sec (int); +static void s_change_section (int); +static void s_cons (int); +static void s_float_cons (int); +static void s_nanomipsset (int); +static void s_cpsetup (int); +static void s_dtprelword (int); +static void s_dtpreldword (int); +static void s_ehword (int); +static void s_insn (int); +static void s_module (int); +static void s_nanomips_ent (int); +static void s_nanomips_end (int); +static void s_nanomips_frame (int); +static void s_nanomips_mask (int reg_type); +static void s_nanomips_file (int); +static void s_nanomips_loc (int); +static void s_linkrelax (int); +static bool pic_need_relax (symbolS *, asection *); +static void file_check_options (void); +static void stubgroup_new (asection *); +static void s_sign_cons (int); +static bool nanomips_allow_local_subtract_symbols (symbolS *, + symbolS *, + bool); + +/* Table and functions used to map between CPU/ISA names, and + ISA levels, and CPU numbers. */ + +struct nanomips_cpu_info +{ + const char *name; /* CPU or ISA name. */ + int flags; /* NANOMIPS_CPU_* flags. */ + int ase; /* Set of ASEs implemented by the CPU. */ + int isa; /* ISA level. */ + int cpu; /* CPU number (default CPU if ISA). */ +}; + +#define NANOMIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */ + +static const struct nanomips_cpu_info *nanomips_parse_cpu + (const char *, const char *); +static const struct nanomips_cpu_info *nanomips_cpu_info_from_isa + (int, bool); +static const struct nanomips_cpu_info *nanomips_cpu_info_from_arch (int); + +/* Command-line options. */ +const char md_shortopts[] = "O::g::G:"; + +enum options +{ + OPTION_MARCH = OPTION_MD_BASE, + OPTION_MTUNE, + OPTION_NO_MIPS16, + OPTION_MT, + OPTION_NO_MT, + OPTION_VIRT, + OPTION_NO_VIRT, + OPTION_NO_MICROMIPS, + OPTION_TRAP, + OPTION_BREAK, + OPTION_EB, + OPTION_EL, + OPTION_CONSTRUCT_FLOATS, + OPTION_NO_CONSTRUCT_FLOATS, + OPTION_INSN32, + OPTION_NO_INSN32, + OPTION_SOFT_FLOAT, + OPTION_HARD_FLOAT, + OPTION_SINGLE_FLOAT, + OPTION_DOUBLE_FLOAT, + OPTION_32, + OPTION_64, + OPTION_M32, + OPTION_M64, + OPTION_BALC_STUBS, + OPTION_NO_BALC_STUBS, + OPTION_LEGACY_REGS, + OPTION_NO_LEGACY_REGS, + OPTION_LINKRELAX, + OPTION_PCREL, + OPTION_NO_PCREL, + OPTION_PID, + OPTION_NO_PID, + OPTION_PIC, + OPTION_NOPIC, + OPTION_LARGE_PIC, + OPTION_MCMODEL, + OPTION_END_OF_ENUM +}; + +const struct option md_longopts[] = +{ + /* Options which specify architecture. */ + {"march", required_argument, NULL, OPTION_MARCH}, + {"mtune", required_argument, NULL, OPTION_MTUNE}, + + /* Options which specify Application Specific Extensions (ASEs). */ + {"mmt", no_argument, NULL, OPTION_MT}, + {"mno-mt", no_argument, NULL, OPTION_NO_MT}, + {"mvirt", no_argument, NULL, OPTION_VIRT}, + {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, + + /* Miscellaneous options. */ + {"32", no_argument, NULL, OPTION_32}, + {"64", no_argument, NULL, OPTION_64}, + {"m32", no_argument, NULL, OPTION_M32}, + {"m64", no_argument, NULL, OPTION_M64}, + {"EB", no_argument, NULL, OPTION_EB}, + {"EL", no_argument, NULL, OPTION_EL}, + {"mcmodel", required_argument, NULL, OPTION_MCMODEL}, + {"mpic", no_argument, NULL, OPTION_PIC}, + {"mno-pic", no_argument, NULL, OPTION_NOPIC}, + {"mPIC", no_argument, NULL, OPTION_LARGE_PIC}, + {"mno-PIC", no_argument, NULL, OPTION_NOPIC}, + {"mpid", no_argument, NULL, OPTION_PID}, + {"mno-pid", no_argument, NULL, OPTION_NO_PID}, + {"mpcrel", no_argument, NULL, OPTION_PCREL}, + {"mno-pcrel", no_argument, NULL, OPTION_NO_PCREL}, + {"minsn32", no_argument, NULL, OPTION_INSN32}, + {"mno-insn32", no_argument, NULL, OPTION_NO_INSN32}, + {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, + {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, + {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, + {"msoft-float", no_argument, NULL, OPTION_SOFT_FLOAT}, + {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, + {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, + {"mbalc-stubs", no_argument, NULL, OPTION_BALC_STUBS}, + {"mno-balc-stubs", no_argument, NULL, OPTION_NO_BALC_STUBS}, + {"mlegacyregs", no_argument, NULL, OPTION_LEGACY_REGS}, + {"mno-legacyregs", no_argument, NULL, OPTION_NO_LEGACY_REGS}, + {"linkrelax", no_argument, NULL, OPTION_LINKRELAX}, + {"break", no_argument, NULL, OPTION_BREAK}, + {"no-break", no_argument, NULL, OPTION_TRAP}, + {"trap", no_argument, NULL, OPTION_TRAP}, + {"no-trap", no_argument, NULL, OPTION_BREAK}, + + {NULL, no_argument, NULL, 0} +}; + +const size_t md_longopts_size = sizeof (md_longopts); + +/* Information about either an Application Specific Extension or an + optional architecture feature that, for simplicity, we treat in the + same way as an ASE. */ +struct nanomips_ase +{ + /* The name of the ASE, used in both the command-line and .set options. */ + const char *name; + + /* The associated ASE_* flags. If the ASE is available on both 32-bit + and 64-bit architectures, the flags here refer to the subset that + is available on both. */ + unsigned int flags; + + /* The ASE_* flag used for instructions that are available on 64-bit + architectures but that are not included in FLAGS. */ + unsigned int flags64; + + /* The command-line options that turn the ASE on and off. */ + int option_on; + int option_off; + + int nanomips32_rev; + int nanomips64_rev; + + /* The architecture where the ASE was removed or -1 if the extension has not + been removed. */ + int rem_rev; +}; + +/* A table of all supported ASEs. */ +static const struct nanomips_ase nanomips_ases[] = { + {"mt", ASE_MT, 0, + OPTION_MT, OPTION_NO_MT, + 6, 6, + -1}, + + {"virt", ASE_VIRT, ASE_VIRT64, + OPTION_VIRT, OPTION_NO_VIRT, + 6, 6, + -1}, +}; + +/* Pseudo-op table. */ + +static const pseudo_typeS nanomips_pseudo_table[] = { + /* nanoMIPS specific pseudo-ops. */ + {"set", s_nanomipsset, 0}, + {"rdata", s_change_sec, 'r'}, + {"sdata", s_change_sec, 's'}, + {"cpload", s_ignore, 0}, + {"cpsetup", s_cpsetup, 0}, + {"cplocal", s_ignore, 0}, + {"cprestore", s_ignore, 0}, + {"cpreturn", s_ignore, 0}, + {"dtprelword", s_dtprelword, 0}, + {"dtpreldword", s_dtpreldword, 0}, + {"ehword", s_ehword, 0}, + {"cpadd", s_ignore, 0}, + {"insn", s_insn, 0}, + {"module", s_module, 0}, + + /* Relatively generic pseudo-ops that happen to be used on MIPS. */ + {"bss", s_change_sec, 'b'}, + {"err", s_err, 0}, + {"half", s_cons, 1}, + {"dword", s_cons, 3}, + {"origin", s_org, 0}, + {"repeat", s_rept, 0}, + + /* This is non-standard, but we define it for consistency. */ + {"sbss", s_change_sec, 'B'}, + + /* These pseudo-ops are defined in read.c, but must be overridden + here for one reason or another. */ + {"align", s_align, 0}, + {"byte", s_cons, 0}, + {"data", s_change_sec, 'd'}, + {"double", s_float_cons, 'd'}, + {"float", s_float_cons, 'f'}, + {"hword", s_cons, 1}, + {"int", s_cons, 2}, + {"long", s_cons, 2}, + {"octa", s_cons, 4}, + {"quad", s_cons, 3}, + {"section", s_change_section, 0}, + {"short", s_cons, 1}, + {"single", s_float_cons, 'f'}, + {"text", s_change_sec, 't'}, + {"word", s_cons, 2}, + {"uleb128", s_leb128, 0}, + {"sleb128", s_leb128, 1}, + + {"extern", ecoff_directive_extern, 0}, + + /* These psuedo-ops are specific to nanoMIPS relocatable expression + for jump offset tables. */ + {"sbyte", s_sign_cons, 0}, + {"shword", s_sign_cons, 1}, + + /* Control linker-relaxation for nanoMIPS */ + {"linkrelax", s_linkrelax, 0}, + + {NULL, NULL, 0}, +}; + +static const pseudo_typeS nanomips_nonecoff_pseudo_table[] = { + /* These pseudo-ops should be defined by the object file format. + However, a.out doesn't support them, so we have versions here. */ + {"aent", s_nanomips_ent, 1}, + {"bgnb", s_ignore, 0}, + {"end", s_nanomips_end, 0}, + {"endb", s_ignore, 0}, + {"ent", s_nanomips_ent, 0}, + {"file", s_nanomips_file, 0}, + {"fmask", s_nanomips_mask, 'F'}, + {"frame", s_nanomips_frame, 0}, + {"loc", s_nanomips_loc, 0}, + {"mask", s_nanomips_mask, 'R'}, + {"verstamp", s_ignore, 0}, + {NULL, NULL, 0}, +}; + +/* Data structures for BALC stub optimization for nanoMIPS ISA. */ +/* List of call-sites to be resolved by a stub. */ +struct call_list +{ + bfd_vma callsite; + struct call_list *next; +}; + +/* Tracking info for each planned stub. */ +struct balc_stub +{ + unsigned int numcalls; + struct call_list *first_call; + struct call_list *last_call; + fragS *fragp; + symbolS *sym; +}; + +/* Doubly linked list of all planned stubs groups. */ +typedef struct stub_group_s +{ + htab_t stubtable; + bfd_vma next_offset; + fragS *fragp; + struct stub_group_s *prev; + struct stub_group_s *next; + asection *seg; +} stub_group; + +/* Master-table of all stubgroups by section-name. */ +static htab_t balc_stubgroup_table = NULL; +/* Quick pointer to the stubgroup currently under consideration + for relaxation. */ +static stub_group *stubg_now = NULL; +/* Flag to check when we are in function-less mode. */ +static bool stub_funcless_mode = false; +/* BC32 to be used as a call-stub. */ +static struct nanomips_cl_insn nanomips_bc32_insn; +typedef struct proc +{ + symbolS *func_sym; + symbolS *func_end_sym; + unsigned long reg_mask; + unsigned long reg_offset; + unsigned long fpreg_mask; + unsigned long fpreg_offset; + unsigned long frame_offset; + unsigned long frame_reg; + unsigned long pc_reg; +} procS; +static procS *cur_proc_ptr; + +/* Tracking state for signed cons expression. */ +static bool sign_cons = false; + +/* Local and reversed copy of the explicit relocation list. */ +static struct reloc_list *reloc_list_copy; +/* Last explicit relocation pointer matched to a frag. */ +static struct reloc_list *reloc_list_iter; +/* Whether the order of explicit relocations in the source match + the order of the corresponding offset symbols. The order is + typically guaranteed by how the compiler generates explicit + relocations, we provide a fail-safe for handwritten assembly. */ +bool reloc_ordered = true; + +/* Export the ABI address size for use by TC_ADDRESS_BYTES for the + purpose of the `.dc.a' internal pseudo-op. */ + +int +nanomips_address_bytes (void) +{ + file_check_options (); + return HAVE_64BIT_ADDRESSES ? 8 : 4; +} + +void +nanomips_pop_insert (void) +{ + pop_insert (nanomips_pseudo_table); + if (!ECOFF_DEBUGGING) + pop_insert (nanomips_nonecoff_pseudo_table); +} + +/* Symbols labelling the current insn. */ + +struct insn_label_list +{ + struct insn_label_list *next; + symbolS *label; +}; + +static struct insn_label_list *free_insn_labels; +#define label_list tc_segment_info_data + +static void nanomips_clear_insn_labels (void); + +static inline void +nanomips_clear_insn_labels (void) +{ + register struct insn_label_list **pl; + segment_info_type *si; + + if (now_seg) + { + for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) + ; + + si = seg_info (now_seg); + *pl = si->label_list; + si->label_list = NULL; + } +} + +static char *expr_parse_end; + +/* An expression in a macro instruction. This is set by nanomips_ip and + when populated is always an O_constant. */ + +static expressionS imm_expr; + +/* The relocatable field in an instruction and the relocs associated + with it. These variables are used for instructions like LUI and + JAL as well as true offsets. They are also used for address + operands in macros. */ + +static expressionS offset_expr; +static bfd_reloc_code_real_type offset_reloc[3] + = { BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED }; + +/* This is set to the resulting size of the instruction to be produced + by nanomips_ip if an explicit size is supplied. */ + +static unsigned int forced_insn_length; + +/* This is set if the mnemonic includes a specific [xx] format + notation from the architecture reference manual. */ + +static bool forced_insn_format; + +/* The default target format to use. */ + +#if defined (TE_FreeBSD) +#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "nanomips-freebsd" +#elif defined (TE_TMIPS) +#define ELF_TARGET(PREFIX, ENDIAN) PREFIX "trad" ENDIAN "nanomips" +#else +#define ELF_TARGET(PREFIX, ENDIAN) PREFIX ENDIAN "nanomips" +#endif + +#define ELF_NTARGET(PREFIX, ENDIAN) PREFIX ENDIAN "nanomips" + +const char * +nanomips_target_format (void) +{ + switch (OUTPUT_FLAVOR) + { + case bfd_target_elf_flavour: + return (target_big_endian + ? (HAVE_64BIT_OBJECTS + ? ELF_NTARGET ("elf64-", "big") + : ELF_NTARGET ("elf32-", "big")) + : (HAVE_64BIT_OBJECTS + ? ELF_NTARGET ("elf64-", "little") + : ELF_NTARGET ("elf32-", "little"))); + default: + abort (); + return NULL; + } +} + +/* Return the ISA revision that is currently in use. */ + +static inline int +nanomips_isa_rev (void) +{ + return 6; +} + +/* Check whether the current ISA supports ASE. Issue a warning if + appropriate. */ + +static void +check_isa_supports_ase (const struct nanomips_ase *ase) +{ + int min_rev, size; + + if (ISA_HAS_64BIT_REGS (nanomips_opts.isa)) + min_rev = ase->nanomips64_rev; + else + min_rev = ase->nanomips32_rev; + + if (min_rev < 0 || nanomips_isa_rev () < min_rev) + { + size = ISA_HAS_64BIT_REGS (nanomips_opts.isa) ? 64 : 32; + if (min_rev < 0) + as_warn (_("the %d-bit nanoMIPS architecture does not support the" + " `%s' extension"), size, ase->name); + else + as_warn (_("the `%s' extension requires nanoMIPS%d revision %d or " + "greater"), ase->name, size, min_rev); + } +} + +/* Check all enabled ASEs to see whether they are supported by the + chosen architecture. */ + +static void +check_isa_supports_ases (void) +{ + unsigned int i, mask; + + for (i = 0; i < ARRAY_SIZE (nanomips_ases); i++) + { + mask = nanomips_ases[i].flags; + if ((nanomips_opts.ase & mask) == nanomips_ases[i].flags) + check_isa_supports_ase (&nanomips_ases[i]); + } +} + +/* Set the state of ASE to ENABLED_P. Return the mask of ASE_* flags + that were affected. */ + +static unsigned int +nanomips_set_ase (const struct nanomips_ase *ase, + struct nanomips_set_options *opts, bool enabled_p) +{ + unsigned int mask; + + mask = ase->flags; + opts->ase &= ~mask; + + if (enabled_p) + opts->ase |= ase->flags; + + return mask; +} + +/* Return the ASE called NAME, or null if none. */ + +static const struct nanomips_ase * +nanomips_lookup_ase (const char *name) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (nanomips_ases); i++) + if (strcmp (name, nanomips_ases[i].name) == 0) + return &nanomips_ases[i]; + return NULL; +} + +/* Return the length of a nanoMIPS instruction in bytes. */ + +static inline unsigned int +insn_length (const struct nanomips_opcode *mo) +{ + return (opcode_48bit_p (mo) ? 6 : (nanomips_opcode_32bit_p (mo) ? 4 : 2)); +} + +/* Initialise INSN from opcode entry MO. Leave its position unspecified. */ + +static void +create_insn (struct nanomips_cl_insn *insn, const struct nanomips_opcode *mo) +{ + size_t i; + + insn->insn_mo = mo; + insn->insn_opcode = mo->match; + insn->frag = NULL; + insn->where = 0; + for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) + insn->fixp[i] = NULL; + insn->fixed_p = (nanomips_opts.noreorder > 0); + insn->noreorder_p = (nanomips_opts.noreorder > 0); + insn->complete_p = 0; +} + +/* Get a list of all the operands in INSN. */ + +static const struct nanomips_operand_array * +insn_operands (const struct nanomips_cl_insn *insn) +{ + if (insn->insn_mo >= &nanomips_opcodes[0] + && insn->insn_mo < &nanomips_opcodes[bfd_nanomips_num_opcodes]) + return &nanomips_operands[insn->insn_mo - &nanomips_opcodes[0]]; + + abort (); +} + +/* Install UVAL as the value of OPERAND in INSN. */ + +static inline void +insn_insert_operand (struct nanomips_cl_insn *insn, + const struct nanomips_operand *operand, + unsigned int uval) +{ + insn->insn_opcode = nanomips_insert_operand (operand, insn->insn_opcode, + uval); +} + +/* Extract the value of OPERAND from INSN. */ + +static inline unsigned +insn_extract_operand (const struct nanomips_cl_insn *insn, + const struct nanomips_operand *operand) +{ + return nanomips_extract_operand (operand, insn->insn_opcode); +} + +/* Read a compressed instruction of length LENGTH. */ + +static unsigned long +read_compressed_insn (char *buf, unsigned int length) +{ + unsigned long insn; + unsigned int i; + + insn = 0; + for (i = 0; i < length; i += 2) + { + insn <<= 16; + if (target_big_endian) + insn |= bfd_getb16 ((char *) buf); + else + insn |= bfd_getl16 ((char *) buf); + buf += 2; + } + return insn; +} + +/* Write compressed instruction INSN to BUF, given that the + instruction is LENGTH bytes long. Return a pointer to the next byte. */ + +static char * +write_compressed_insn (char *buf, unsigned int insn, unsigned int length) +{ + unsigned int i; + + for (i = 0; i < length; i += 2) + md_number_to_chars (buf + i, insn >> ((length - i - 2) * 8), 2); + + return buf + length; +} + +/* Install INSN at the location specified by its "frag" and "where" fields. */ + +static void +install_insn (const struct nanomips_cl_insn *insn) +{ + char *f = insn->frag->fr_literal + insn->where; + + if (insn_length (insn->insn_mo) == 6) + { + write_compressed_insn (f, insn->insn_opcode, 2); + write_compressed_insn (f + 2, insn->insn_opcode_ext, 4); + } + else + write_compressed_insn (f, insn->insn_opcode, insn_length (insn->insn_mo)); +} + +static void +toggle_linkrelax (fragS *frag, long where) +{ + nanomips_linkrelax_p = !nanomips_linkrelax_p; + toggle_linkrelax_p = false; + fix_new (frag, where, 0, &abs_symbol, 0, false, + (nanomips_linkrelax_p + ? BFD_RELOC_NANOMIPS_RELAX + : BFD_RELOC_NANOMIPS_NORELAX)); +} + +/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly + and install the opcode in the new location. */ + +static void +move_insn (struct nanomips_cl_insn *insn, fragS *frag, long where) +{ + size_t i; + + insn->frag = frag; + insn->where = where; + + if (toggle_linkrelax_p) + toggle_linkrelax (frag, where); + + for (i = 0; i < ARRAY_SIZE (insn->fixp); i++) + if (insn->fixp[i] != NULL) + { + insn->fixp[i]->fx_frag = frag; + insn->fixp[i]->fx_where = where; + } + install_insn (insn); +} + +/* Add INSN to the end of the output. */ + +static void +add_fixed_insn (struct nanomips_cl_insn *insn) +{ + char *f = frag_more (insn_length (insn->insn_mo)); + move_insn (insn, frag_now, f - frag_now->fr_literal); +} + +/* Start a variant frag and move INSN to the start of the variant part, + marking it as fixed. The other arguments are as for frag_var. */ + +static void +add_relaxed_insn (struct nanomips_cl_insn *insn, int max_chars, int var, + relax_substateT subtype, symbolS *symbol, offsetT offset) +{ + frag_grow (max_chars); + move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); + insn->fixed_p = 1; + frag_var (rs_machine_dependent, max_chars, var, subtype, symbol, + offset, NULL); +} + +/* Insert N copies of INSN into the history buffer, starting at + position FIRST. Neither FIRST nor N need to be clipped. */ + +static void +insert_into_history (const struct nanomips_cl_insn *insn) +{ + if (nanomips_relax.sequence != 2) + history = *insn; +} + +/* Clear the error in insn_error. */ + +static void +clear_insn_error (void) +{ + memset (&insn_error, 0, sizeof (insn_error)); +} + +/* Possibly record error message MSG for the current instruction. + If the error is about a particular argument, ARGNUM is the 1-based + number of that argument, otherwise it is 0. FORMAT is the format + of MSG. Return true if MSG was used, false if the current message + was kept. */ + +static bool +set_insn_error_format (int argnum, enum nanomips_insn_error_format format, + const char *msg) +{ + if (argnum == 0) + { + /* Give priority to errors against specific arguments, and to + the first whole-instruction message. */ + if (insn_error.msg) + return false; + } + else + { + /* Keep insn_error if it is against a later argument. */ + if (argnum < insn_error.min_argnum) + return false; + + /* If both errors are against the same argument but are different, + give up on reporting a specific error for this argument. + See the comment about nanomips_insn_error for details. */ + if (argnum == insn_error.min_argnum + && insn_error.msg + && strcmp (insn_error.msg, msg) != 0) + { + insn_error.msg = 0; + insn_error.min_argnum += 1; + return false; + } + } + insn_error.min_argnum = argnum; + insn_error.format = format; + insn_error.msg = msg; + return true; +} + +/* Record an instruction error with no % format fields. ARGNUM and MSG are + as for set_insn_error_format. */ + +static void +set_insn_error (int argnum, const char *msg) +{ + set_insn_error_format (argnum, ERR_FMT_PLAIN, msg); +} + +/* Record an instruction error with one %d field I. ARGNUM and MSG are + as for set_insn_error_format. */ + +static void +set_insn_error_i (int argnum, const char *msg, int i) +{ + if (set_insn_error_format (argnum, ERR_FMT_I, msg)) + insn_error.u.i = i; +} + +/* Record an instruction error with two %s fields S1 and S2. ARGNUM and MSG + are as for set_insn_error_format. */ + +static void +set_insn_error_ss (int argnum, const char *msg, const char *s1, + const char *s2) +{ + if (set_insn_error_format (argnum, ERR_FMT_SS, msg)) + { + insn_error.u.ss[0] = s1; + insn_error.u.ss[1] = s2; + } +} + +static void +set_insn_error_si (int argnum, const char *msg, const char *s1, const int i) +{ + if (set_insn_error_format (argnum, ERR_FMT_SI, msg)) + { + insn_error.u.si.s1 = s1; + insn_error.u.si.u1 = i; + } +} + +/* Report the error in insn_error, which is against assembly code STR. */ + +static void +report_insn_error (const char *str) +{ + const char *msg = concat (insn_error.msg, " `%s'", (const char *) NULL); + + switch (insn_error.format) + { + case ERR_FMT_PLAIN: + as_bad (msg, str); + break; + + case ERR_FMT_I: + as_bad (msg, insn_error.u.i, str); + break; + + case ERR_FMT_SS: + as_bad (msg, insn_error.u.ss[0], insn_error.u.ss[1], str); + break; + + case ERR_FMT_SI: + as_bad (msg, insn_error.u.si.s1, insn_error.u.si.u1, str); + break; + } +} + +struct regname +{ + const char *name; + unsigned int num; +}; + +#define RNUM_MASK 0x00003ff +#define RTYPE_MASK 0x7fffc00 +#define RTYPE_NUM 0x0000400 +#define RTYPE_FPU 0x0000800 +#define RTYPE_FCC 0x0001000 +#define RTYPE_VEC 0x0002000 +#define RTYPE_GP 0x0004000 +#define RTYPE_CP0 0x0008000 +#define RTYPE_PC 0x0010000 +#define RTYPE_ACC 0x0020000 +#define RTYPE_CCC 0x0040000 +#define RTYPE_CP0SEL 0x0300000 +#define RTYPE_CP0SEL_EVEN 0x0100000 +#define RTYPE_CP0SEL_ODD 0x0200000 +#define RWARN 0x8000000 + +#define GENERIC_REGISTER_NUMBERS \ + {"$0", RTYPE_NUM | 0}, \ + {"$1", RTYPE_NUM | 1}, \ + {"$2", RTYPE_NUM | 2}, \ + {"$3", RTYPE_NUM | 3}, \ + {"$4", RTYPE_NUM | 4}, \ + {"$5", RTYPE_NUM | 5}, \ + {"$6", RTYPE_NUM | 6}, \ + {"$7", RTYPE_NUM | 7}, \ + {"$8", RTYPE_NUM | 8}, \ + {"$9", RTYPE_NUM | 9}, \ + {"$10", RTYPE_NUM | 10}, \ + {"$11", RTYPE_NUM | 11}, \ + {"$12", RTYPE_NUM | 12}, \ + {"$13", RTYPE_NUM | 13}, \ + {"$14", RTYPE_NUM | 14}, \ + {"$15", RTYPE_NUM | 15}, \ + {"$16", RTYPE_NUM | 16}, \ + {"$17", RTYPE_NUM | 17}, \ + {"$18", RTYPE_NUM | 18}, \ + {"$19", RTYPE_NUM | 19}, \ + {"$20", RTYPE_NUM | 20}, \ + {"$21", RTYPE_NUM | 21}, \ + {"$22", RTYPE_NUM | 22}, \ + {"$23", RTYPE_NUM | 23}, \ + {"$24", RTYPE_NUM | 24}, \ + {"$25", RTYPE_NUM | 25}, \ + {"$26", RTYPE_NUM | 26}, \ + {"$27", RTYPE_NUM | 27}, \ + {"$28", RTYPE_NUM | 28}, \ + {"$29", RTYPE_NUM | 29}, \ + {"$30", RTYPE_NUM | 30}, \ + {"$31", RTYPE_NUM | 31} + +#define FPU_REGISTER_NAMES \ + {"$f0", RTYPE_FPU | 0}, \ + {"$f1", RTYPE_FPU | 1}, \ + {"$f2", RTYPE_FPU | 2}, \ + {"$f3", RTYPE_FPU | 3}, \ + {"$f4", RTYPE_FPU | 4}, \ + {"$f5", RTYPE_FPU | 5}, \ + {"$f6", RTYPE_FPU | 6}, \ + {"$f7", RTYPE_FPU | 7}, \ + {"$f8", RTYPE_FPU | 8}, \ + {"$f9", RTYPE_FPU | 9}, \ + {"$f10", RTYPE_FPU | 10}, \ + {"$f11", RTYPE_FPU | 11}, \ + {"$f12", RTYPE_FPU | 12}, \ + {"$f13", RTYPE_FPU | 13}, \ + {"$f14", RTYPE_FPU | 14}, \ + {"$f15", RTYPE_FPU | 15}, \ + {"$f16", RTYPE_FPU | 16}, \ + {"$f17", RTYPE_FPU | 17}, \ + {"$f18", RTYPE_FPU | 18}, \ + {"$f19", RTYPE_FPU | 19}, \ + {"$f20", RTYPE_FPU | 20}, \ + {"$f21", RTYPE_FPU | 21}, \ + {"$f22", RTYPE_FPU | 22}, \ + {"$f23", RTYPE_FPU | 23}, \ + {"$f24", RTYPE_FPU | 24}, \ + {"$f25", RTYPE_FPU | 25}, \ + {"$f26", RTYPE_FPU | 26}, \ + {"$f27", RTYPE_FPU | 27}, \ + {"$f28", RTYPE_FPU | 28}, \ + {"$f29", RTYPE_FPU | 29}, \ + {"$f30", RTYPE_FPU | 30}, \ + {"$f31", RTYPE_FPU | 31} + +#define FPU_CONDITION_CODE_NAMES \ + {"$fcc0", RTYPE_FCC | 0}, \ + {"$fcc1", RTYPE_FCC | 1}, \ + {"$fcc2", RTYPE_FCC | 2}, \ + {"$fcc3", RTYPE_FCC | 3}, \ + {"$fcc4", RTYPE_FCC | 4}, \ + {"$fcc5", RTYPE_FCC | 5}, \ + {"$fcc6", RTYPE_FCC | 6}, \ + {"$fcc7", RTYPE_FCC | 7} + +#define COPROC_CONDITION_CODE_NAMES \ + {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \ + {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \ + {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \ + {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \ + {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \ + {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \ + {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \ + {"$cc7", RTYPE_FCC | RTYPE_CCC | 7} + +#define NANOMIPS_SYMBOLIC_REG_NAMES \ + {"$zero", RTYPE_GP | 0}, \ + {"$at", RTYPE_GP | 1}, \ + {"$t4", RTYPE_GP | 2}, \ + {"$t5", RTYPE_GP | 3}, \ + {"$a0", RTYPE_GP | 4}, \ + {"$a1", RTYPE_GP | 5}, \ + {"$a2", RTYPE_GP | 6}, \ + {"$a3", RTYPE_GP | 7}, \ + {"$a4", RTYPE_GP | 8}, \ + {"$a5", RTYPE_GP | 9}, \ + {"$a6", RTYPE_GP | 10}, \ + {"$a7", RTYPE_GP | 11}, \ + {"$t0", RTYPE_GP | 12}, \ + {"$t1", RTYPE_GP | 13}, \ + {"$t2", RTYPE_GP | 14}, \ + {"$t3", RTYPE_GP | 15}, \ + {"$s0", RTYPE_GP | 16}, \ + {"$s1", RTYPE_GP | 17}, \ + {"$s2", RTYPE_GP | 18}, \ + {"$s3", RTYPE_GP | 19}, \ + {"$s4", RTYPE_GP | 20}, \ + {"$s5", RTYPE_GP | 21}, \ + {"$s6", RTYPE_GP | 22}, \ + {"$s7", RTYPE_GP | 23}, \ + {"$t8", RTYPE_GP | 24}, \ + {"$t9", RTYPE_GP | 25}, \ + {"$k0", RTYPE_GP | 26}, \ + {"$k1", RTYPE_GP | 27}, \ + {"$gp", RTYPE_GP | 28}, \ + {"$sp", RTYPE_GP | 29}, \ + {"$fp", RTYPE_GP | 30}, \ + {"$ra", RTYPE_GP | 31}, \ + {"$AT", RTYPE_GP | 1} + +#define NANOMIPS_NUMERIC_REG_NAMES \ + {"$r0", RTYPE_GP | 0}, \ + {"$r1", RTYPE_GP | 1}, \ + {"$r2", RTYPE_GP | 2}, \ + {"$r3", RTYPE_GP | 3}, \ + {"$r4", RTYPE_GP | 4}, \ + {"$r5", RTYPE_GP | 5}, \ + {"$r6", RTYPE_GP | 6}, \ + {"$r7", RTYPE_GP | 7}, \ + {"$r8", RTYPE_GP | 8}, \ + {"$r9", RTYPE_GP | 9}, \ + {"$r10", RTYPE_GP | 10}, \ + {"$r11", RTYPE_GP | 11}, \ + {"$r12", RTYPE_GP | 12}, \ + {"$r13", RTYPE_GP | 13}, \ + {"$r14", RTYPE_GP | 14}, \ + {"$r15", RTYPE_GP | 15}, \ + {"$r16", RTYPE_GP | 16}, \ + {"$r17", RTYPE_GP | 17}, \ + {"$r18", RTYPE_GP | 18}, \ + {"$r19", RTYPE_GP | 19}, \ + {"$r20", RTYPE_GP | 20}, \ + {"$r21", RTYPE_GP | 21}, \ + {"$r22", RTYPE_GP | 22}, \ + {"$r23", RTYPE_GP | 23}, \ + {"$r24", RTYPE_GP | 24}, \ + {"$r25", RTYPE_GP | 25}, \ + {"$r26", RTYPE_GP | 26}, \ + {"$r27", RTYPE_GP | 27}, \ + {"$r28", RTYPE_GP | 28}, \ + {"$r29", RTYPE_GP | 29}, \ + {"$r30", RTYPE_GP | 30}, \ + {"$r31", RTYPE_GP | 31} + +#define NANOMIPS_DSP_ACCUMULATOR_NAMES \ + {"$ac0", RTYPE_ACC | 0}, \ + {"$ac1", RTYPE_ACC | 1}, \ + {"$ac2", RTYPE_ACC | 2}, \ + {"$ac3", RTYPE_ACC | 3} + +static const struct regname nanomips_reg_names[] = { + GENERIC_REGISTER_NUMBERS, + NANOMIPS_SYMBOLIC_REG_NAMES, + NANOMIPS_NUMERIC_REG_NAMES, + FPU_REGISTER_NAMES, + FPU_CONDITION_CODE_NAMES, + COPROC_CONDITION_CODE_NAMES, + NANOMIPS_DSP_ACCUMULATOR_NAMES, + {0, 0} +}; + +/* Register symbols $v0 and $v1 map to GPRs 2 and 3, but they can also be + interpreted as vector registers 0 and 1. If SYMVAL is the value of one + of these register symbols, return the associated vector register, + otherwise return SYMVAL itself. */ + +static unsigned int +nanomips_prefer_vec_regno (unsigned int symval) +{ + if ((symval & -2) == (RTYPE_GP | 2)) + return RTYPE_VEC | (symval & 1); + return symval; +} + +/* Return true if string [S, E) is a valid register name, storing its + symbol value in *SYMVAL_PTR if so. */ + +static bool +nanomips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr) +{ + char save_c; + symbolS *symbol; + + /* Terminate name. */ + save_c = *e; + *e = '\0'; + + /* Look up the name. */ + symbol = symbol_find (s); + *e = save_c; + + if (!symbol || S_GET_SEGMENT (symbol) != reg_section) + return false; + + *symval_ptr = S_GET_VALUE (symbol); + return true; +} + +/* Return true if the string at *SPTR is a valid register name. + + When returning true, move *SPTR past the register, store the + register's symbol value in *SYMVAL_PTR. */ + +static bool +nanomips_parse_register (char **sptr, unsigned int *symval_ptr) +{ + char *s, *e; + unsigned int symval; + + /* Find end of name. */ + s = e = *sptr; + if (is_name_beginner (*e)) + ++e; + while (is_part_of_name (*e)) + ++e; + + if (!nanomips_parse_register_1 (s, e, &symval)) + return false; + + *sptr = e; + *symval_ptr = symval; + return true; +} + +/* Check if SPTR points at a valid register specifier according to TYPES. + If so, then return 1, advance S to consume the specifier and store + the register's number in REGNOP, otherwise return 0. */ + +static int +reg_lookup (char **s, unsigned int types, unsigned int *regnop) +{ + unsigned int regno; + + if (nanomips_parse_register (s, ®no)) + { + if (types & RTYPE_VEC) + regno = nanomips_prefer_vec_regno (regno); + if (regno & types) + regno &= RNUM_MASK; + else + regno = ~0; + } + else + { + if (types & RWARN) + as_warn (_("unrecognized register name `%s'"), *s); + regno = ~0; + } + if (regnop) + *regnop = regno; + return regno <= RNUM_MASK; +} + +/* Token types for parsed operand lists. */ +enum nanomips_operand_token_type +{ + /* A plain register, e.g. $f2. */ + OT_REG, + + /* A constant vector index, e.g. [1]. */ + OT_INTEGER_INDEX, + + /* A register vector index, e.g. [$2]. */ + OT_REG_INDEX, + + /* A continuous range of registers, e.g. $s0-$s4. */ + OT_REG_RANGE, + + /* A (possibly relocated) expression. */ + OT_INTEGER, + + /* A floating-point value. */ + OT_FLOAT, + + /* A single character. This can be '(', ')' or ',', but '(' only appears + before OT_REGs. */ + OT_CHAR, + + /* A doubled character, either "--" or "++". */ + OT_DOUBLE_CHAR, + + /* The end of the operand list. */ + OT_END +}; + +/* A parsed operand token. */ +struct nanomips_operand_token +{ + /* The type of token. */ + enum nanomips_operand_token_type type; + union + { + /* The register symbol value for an OT_REG or OT_REG_INDEX. */ + unsigned int regno; + + /* The integer value of an OT_INTEGER_INDEX. */ + addressT index; + + /* The two register symbol values involved in an OT_REG_RANGE. */ + struct + { + unsigned int regno1; + unsigned int regno2; + } reg_range; + + /* The value of an OT_INTEGER. The value is represented as an + expression and the relocation operators that were applied to + that expression. The reloc entries are BFD_RELOC_UNUSED if no + relocation operators were used. */ + struct + { + expressionS value; + bfd_reloc_code_real_type relocs[3]; + } integer; + + /* The binary data for an OT_FLOAT constant, and the number of bytes + in the constant. */ + struct + { + unsigned char data[8]; + int length; + } flt; + + /* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */ + char ch; + } u; +}; + +/* An obstack used to construct lists of nanomips_operand_tokens. */ +static struct obstack nanomips_operand_tokens; + +/* Give TOKEN type TYPE and add it to nanomips_operand_tokens. */ + +static void +nanomips_add_token (struct nanomips_operand_token *token, + enum nanomips_operand_token_type type) +{ + token->type = type; + obstack_grow (&nanomips_operand_tokens, token, sizeof (*token)); +} + +/* Check whether S is '(' followed by a register name. Add OT_CHAR + and OT_REG tokens for them if so, and return a pointer to the first + unconsumed character. Return null otherwise. */ + +static char * +nanomips_parse_base_start (char *s) +{ + struct nanomips_operand_token token; + unsigned int regno; + bool decrement_p; + + if (*s != '(') + return 0; + + ++s; + SKIP_SPACE_TABS (s); + + /* Only match "--" as part of a base expression. In other contexts "--X" + is a double negative. */ + decrement_p = (s[0] == '-' && s[1] == '-'); + if (decrement_p) + { + s += 2; + SKIP_SPACE_TABS (s); + } + + /* Allow a channel specifier because that leads to better error messages + than treating something like "$vf0x++" as an expression. */ + if (!nanomips_parse_register (&s, ®no)) + return 0; + + token.u.ch = '('; + nanomips_add_token (&token, OT_CHAR); + + if (decrement_p) + { + token.u.ch = '-'; + nanomips_add_token (&token, OT_DOUBLE_CHAR); + } + + token.u.regno = regno; + nanomips_add_token (&token, OT_REG); + + /* For consistency, only match "++" as part of base expressions too. */ + SKIP_SPACE_TABS (s); + if (s[0] == '+' && s[1] == '+') + { + s += 2; + token.u.ch = '+'; + nanomips_add_token (&token, OT_DOUBLE_CHAR); + } + return s; +} + +/* Parse one or more tokens from S. Return a pointer to the first + unconsumed character on success. Return null if an error was found + and store the error text in insn_error. FLOAT_FORMAT is as for + nanomips_parse_arguments. */ + +static char * +nanomips_parse_argument_token (char *s, char float_format) +{ + char *end, *save_in; + const char *err; + unsigned int regno1, regno2; + struct nanomips_operand_token token; + + /* First look for "($reg", since we want to treat that as an + OT_CHAR and OT_REG rather than an expression. */ + end = nanomips_parse_base_start (s); + if (end) + return end; + + /* Handle other characters that end up as OT_CHARs. */ + if (*s == ')' || *s == ',') + { + token.u.ch = *s; + nanomips_add_token (&token, OT_CHAR); + ++s; + return s; + } + + /* Handle tokens that start with a register. */ + if (nanomips_parse_register (&s, ®no1)) + { + SKIP_SPACE_TABS (s); + if (*s == '-') + { + /* A register range. */ + ++s; + SKIP_SPACE_TABS (s); + if (!nanomips_parse_register (&s, ®no2)) + { + set_insn_error (0, _("invalid register range")); + return 0; + } + + token.u.reg_range.regno1 = regno1; + token.u.reg_range.regno2 = regno2; + nanomips_add_token (&token, OT_REG_RANGE); + return s; + } + + /* Add the register itself. */ + token.u.regno = regno1; + nanomips_add_token (&token, OT_REG); + + /* Check for a vector index. */ + if (*s == '[') + { + ++s; + SKIP_SPACE_TABS (s); + if (nanomips_parse_register (&s, &token.u.regno)) + nanomips_add_token (&token, OT_REG_INDEX); + else + { + expressionS element; + + my_getExpression (&element, s); + if (element.X_op != O_constant) + { + set_insn_error (0, _("vector element must be constant")); + return 0; + } + s = expr_parse_end; + token.u.index = element.X_add_number; + nanomips_add_token (&token, OT_INTEGER_INDEX); + } + SKIP_SPACE_TABS (s); + if (*s != ']') + { + set_insn_error (0, _("missing `]'")); + return 0; + } + ++s; + } + return s; + } + + if (float_format) + { + /* First try to treat expressions as floats. */ + save_in = input_line_pointer; + input_line_pointer = s; + err = md_atof (float_format, (char *) token.u.flt.data, + &token.u.flt.length); + end = input_line_pointer; + input_line_pointer = save_in; + if (err && *err) + { + set_insn_error (0, err); + return 0; + } + if (s != end) + { + nanomips_add_token (&token, OT_FLOAT); + return end; + } + } + + /* Treat everything else as an integer expression. */ + token.u.integer.relocs[0] = BFD_RELOC_UNUSED; + token.u.integer.relocs[1] = BFD_RELOC_UNUSED; + token.u.integer.relocs[2] = BFD_RELOC_UNUSED; + my_getSmallExpression (&token.u.integer.value, token.u.integer.relocs, s); + s = expr_parse_end; + nanomips_add_token (&token, OT_INTEGER); + return s; +} + +/* S points to the operand list for an instruction. FLOAT_FORMAT is 'f' + if expressions should be treated as 32-bit floating-point constants, + 'd' if they should be treated as 64-bit floating-point constants, + or 0 if they should be treated as integer expressions (the usual case). + + Return a list of tokens on success, otherwise return 0. The caller + must obstack_free the list after use. */ + +static struct nanomips_operand_token * +nanomips_parse_arguments (char *s, char float_format) +{ + struct nanomips_operand_token token; + + SKIP_SPACE_TABS (s); + while (*s) + { + s = nanomips_parse_argument_token (s, float_format); + if (!s) + { + obstack_free (&nanomips_operand_tokens, + obstack_base (&nanomips_operand_tokens)); + return 0; + } + SKIP_SPACE_TABS (s); + } + nanomips_add_token (&token, OT_END); + return obstack_finish (&nanomips_operand_tokens); +} + +/* Return true if opcode MO is valid for the currently selected + floating point configuration. */ + +static bool +is_opcode_valid_for_fp (const struct nanomips_opcode *mo) +{ + int fp_s, fp_d; + + /* Check whether the instruction or macro requires single-precision or + double-precision floating-point support. Note that this information is + stored differently in the opcode table for insns and macros. */ + if (mo->pinfo == INSN_MACRO) + { + fp_s = mo->pinfo2 & INSN2_M_FP_S; + fp_d = mo->pinfo2 & INSN2_M_FP_D; + } + else + { + fp_s = mo->pinfo & INSN_FP_S; + fp_d = mo->pinfo & INSN_FP_D; + } + + if (fp_d && (nanomips_opts.soft_float || nanomips_opts.single_float)) + return false; + + if (fp_s && nanomips_opts.soft_float) + return false; + + return true; +} + +/* Return true if opcode MO is valid for the currently selected ISA + with the specified ASE. */ + +static bool +is_opcode_valid_for_ase (const struct nanomips_opcode *mo, int ase) +{ + int isa = nanomips_opts.isa; + unsigned int i; + + if (ISA_HAS_64BIT_REGS (isa)) + for (i = 0; i < ARRAY_SIZE (nanomips_ases); i++) + if ((ase & nanomips_ases[i].flags) == nanomips_ases[i].flags) + ase |= nanomips_ases[i].flags64; + + return nanomips_opcode_is_member (mo, isa, ase, nanomips_opts.arch); +} + +/* Return true if opcode MO is valid for the currently selected ISA, + ASE and floating point configuration. */ + +static bool +is_opcode_valid (const struct nanomips_opcode *mo) +{ + return (is_opcode_valid_for_ase (mo, nanomips_opts.ase) + && is_opcode_valid_for_fp (mo)); +} + +/* Return true if opcode MO is valid for the currently selected ISA + and architecture with a default ASE selection. */ + +static bool +is_opcode_valid_def_ase (const struct nanomips_opcode *mo) +{ + const struct nanomips_cpu_info *info; + int ase; + + info = nanomips_cpu_info_from_isa (nanomips_opts.isa, + (nanomips_opts.ase & ASE_xNMS) == 0); + ase = info->ase | nanomips_opts.ase; + + return is_opcode_valid_for_ase (mo, ase); +} + +/* Return true if the size of the nanoMIPS opcode MO matches one + explicitly requested. */ + +static bool +is_size_valid (const struct nanomips_opcode *mo) +{ + if (nanomips_opts.insn32 && mo->pinfo != INSN_MACRO && insn_length (mo) != 4) + return false; + + if (!forced_insn_length) + return true; + + if (mo->pinfo == INSN_MACRO) + return false; + + return forced_insn_length == insn_length (mo); +} + +/* For consistency checking, verify that all bits of OPCODE are specified + either by the match/mask part of the instruction definition, or by the + operand list. Also build up a list of operands in OPERANDS. + + INSN_BITS says which bits of the instruction are significant. + DECODE_OPERAND rovides the nanomips_operand description of each operand. */ + +static int +validate_insn (const struct nanomips_opcode *opcode, unsigned long insn_bits, + struct nanomips_operand_array *operands) +{ + const char *s; + unsigned long used_bits, doubled, undefined, opno, mask; + const struct nanomips_operand *operand; + + mask = (opcode->pinfo == INSN_MACRO ? 0 : opcode->mask); + if ((mask & opcode->match) != opcode->match) + { + as_bad (_("internal: bad nanomips opcode (mask error): %s %s"), + opcode->name, opcode->args); + return 0; + } + used_bits = 0; + opno = 0; + + for (s = opcode->args; *s; ++s) + switch (*s) + { + case ',': + case '(': + case ')': + break; + + case '#': + s++; + break; + + default: + operand = decode_nanomips_operand (s); + if (!operand && opcode->pinfo != INSN_MACRO) + { + as_bad (_("internal: unknown operand type: %s %s"), + opcode->name, opcode->args); + return 0; + } + gas_assert (opno < MAX_OPERANDS); + operands->operand[opno] = operand; + if (operand != NULL) + used_bits = nanomips_insert_operand (operand, used_bits, -1); + /* Skip prefix characters. */ + if (*s == '+' || *s == 'm' || *s == '-') + ++s; + opno += 1; + break; + } + doubled = used_bits & mask & insn_bits; + if (doubled) + { + as_bad (_("internal: bad nanomips opcode (bits 0x%08lx doubly defined):" + " %s %s"), doubled, opcode->name, opcode->args); + return 0; + } + used_bits |= mask; + undefined = ~used_bits & insn_bits; + if (opcode->pinfo != INSN_MACRO && undefined) + { + as_bad (_("internal: bad nanomips opcode (bits 0x%08lx undefined): " + "%s %s"), undefined, opcode->name, opcode->args); + return 0; + } + used_bits &= ~insn_bits; + if (used_bits) + { + as_bad (_("internal: bad nanomips opcode (bits 0x%08lx defined): " + "%s %s"), used_bits, opcode->name, opcode->args); + return 0; + } + return 1; +} + +static int +validate_nanomips_insn (const struct nanomips_opcode *opc, + struct nanomips_operand_array *operands) +{ + unsigned long insn_bits; + unsigned long major; + unsigned int length; + + if (opc->pinfo == INSN_MACRO) + return validate_insn (opc, 0xffffffff, operands); + + length = insn_length (opc); + if (length != 2 && length != 4 && length != 6) + { + as_bad (_("internal error: bad nanoMIPS opcode (incorrect length: %u): " + "%s %s"), length, opc->name, opc->args); + return 0; + } + + if (length == 6) + /* 48-bit instruction is encoded as 16-bits in the opcode table. */ + major = opc->match >> 10; + else + major = opc->match >> (10 + 8 * (length - 2)); + + if ((length == 2 && !(major & 4)) + || (length == 4 && (major & 4)) + || (length == 6 && !(major & 18))) + { + as_bad (_("internal error: bad nanoMIPS opcode " + "(opcode/length mismatch): %s %s"), opc->name, opc->args); + return 0; + } + + if (length == 6) + /* 48-bit instruction is encoded as 16-bits in the opcode table. */ + insn_bits = 1 << 16; + else + { + /* Shift piecewise to avoid an overflow where unsigned long is 32-bit. */ + insn_bits = 1 << 4 * length; + insn_bits <<= 4 * length; + } + + insn_bits -= 1; + return validate_insn (opc, insn_bits, operands); +} + +/* This function is called once, at assembler startup time. It should set up + all the tables, etc. that the MD part of the assembler will need. */ + +void +md_begin (void) +{ + int i = 0; + int broken = 0; + int count_marker = 0; + + if (nanomips_opts.pic != NO_PIC) + { + if (g_switch_seen && g_switch_value != 0) + as_bad (_("-G may not be used in position-independent code")); + g_switch_value = 0; + } + + if (!bfd_set_arch_mach (stdoutput, bfd_arch_nanomips, + file_nanomips_opts.arch)) + as_warn (_("could not set architecture and machine")); + + op_hash = str_htab_create (); + + nanomips_op_hash = str_htab_create (); + nanomips_operands = XCNEWVEC (struct nanomips_operand_array, + bfd_nanomips_num_opcodes); + + i = 0; + while (i < bfd_nanomips_num_opcodes) + { + const char *name = nanomips_opcodes[i].name; + + if (str_hash_insert (nanomips_op_hash, name, &nanomips_opcodes[i], 0)) + as_fatal (_("duplicate %s"), name); + do + { + struct nanomips_cl_insn *insn; + + if (!validate_nanomips_insn (&nanomips_opcodes[i], + &nanomips_operands[i])) + broken = 1; + + if (count_marker < 3 && nanomips_opcodes[i].pinfo != INSN_MACRO) + { + if (nanomips_nop16_insn.insn_mo == NULL + && insn_length (&nanomips_opcodes[i]) == 2 + && strcmp (name, "nop") == 0) + insn = &nanomips_nop16_insn; + else if (nanomips_nop32_insn.insn_mo == NULL + && insn_length (&nanomips_opcodes[i]) == 4 + && strcmp (name, "nop") == 0) + insn = &nanomips_nop32_insn; + else if (nanomips_bc32_insn.insn_mo == NULL + && insn_length (&nanomips_opcodes[i]) == 4 + && strcmp (name, "bc") == 0) + insn = &nanomips_bc32_insn; + else + continue; + + create_insn (insn, nanomips_opcodes + i); + insn->fixed_p = 1; + count_marker++; + } + } + while (++i < bfd_nanomips_num_opcodes + && strcmp (nanomips_opcodes[i].name, name) == 0); + } + + i = 0; + while (i < bfd_nanomips_num_opcodes) + { + const struct nanomips_opcode *opcode = &nanomips_opcodes[i]; + if (opcode->suffix[0] != '\0') + { + char *name; + name = xmalloc (strlen (opcode->name) + strlen (opcode->suffix) + 1); + name = strcpy (name, opcode->name); + name = strcat (name, opcode->suffix); + + if (str_hash_find (nanomips_op_hash, name) == NULL) + { + if (str_hash_insert (nanomips_op_hash, name, &nanomips_opcodes[i], 0)) + as_fatal (_("duplicate %s"), name); + } + } + i++; + } + + if (broken) + as_fatal (_("broken assembler, no assembly attempted")); + + /* We add all the general register names to the symbol table. This + helps us detect invalid uses of them. */ + for (i = 0; nanomips_reg_names[i].name; i++) + { + symbolS *regsym = symbol_new (nanomips_reg_names[i].name, reg_section, + &zero_address_frag, + nanomips_reg_names[i].num); + symbolS *defsym = symbol_find (nanomips_reg_names[i].name); + symbol_table_insert (regsym); + if (defsym) + as_warn ("Attempt to define internal register symbol %s ignored", + nanomips_reg_names[i].name); + } + + for (i = 0; nanomips_cp0_3264r6[i].name; i++) + { + /* 10-bit symbol value for CP0 named register consists of a 5-bit + register number and 5-bit fixed select value. */ + unsigned int value = (RTYPE_CP0 + | (nanomips_cp0_3264r6[i].num + << NANOMIPSOP_SH_CP0SEL) + | nanomips_cp0_3264r6[i].sel); + symbolS *regsym = symbol_new (nanomips_cp0_3264r6[i].name, reg_section, + &zero_address_frag, value); + symbolS *defsym = symbol_find (nanomips_cp0_3264r6[i].name); + symbol_table_insert (regsym); + if (defsym) + as_warn ("Attempt to define internal register symbol %s ignored", + nanomips_cp0_3264r6[i].name); + } + + for (i = 0; nanomips_cp0sel_3264r6[i].name; i++) + { + symbolS *regsym, *defsym; + unsigned value = nanomips_cp0sel_3264r6[i].num; + + switch (nanomips_cp0sel_3264r6[i].selmask) + { + case NANOMIPS_CP0SEL_MASK_EVEN: + value |= RTYPE_CP0SEL_EVEN; + break; + case NANOMIPS_CP0SEL_MASK_ODD: + value |= RTYPE_CP0SEL_ODD; + break; + case NANOMIPS_CP0SEL_MASK_ANY: + value |= RTYPE_CP0SEL; + break; + default: + break; + } + + regsym = symbol_new (nanomips_cp0sel_3264r6[i].name, reg_section, + &zero_address_frag, value); + defsym = symbol_find (nanomips_cp0sel_3264r6[i].name); + symbol_table_insert (regsym); + if (defsym) + as_warn ("Attempt to define internal register symbol %s ignored", + nanomips_cp0sel_3264r6[i].name); + } + + obstack_init (&nanomips_operand_tokens); + + nanomips_flush_pending_output (); + + bfd_set_gp_size (stdoutput, g_switch_value); + + { + segT seg; + subsegT subseg; + segT sec; + + seg = now_seg; + subseg = now_subseg; + + subseg_set (seg, subseg); + } +} + +static inline void +fpabi_incompatible_with (int fpabi, const char *what) +{ + as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), + Tag_GNU_NANOMIPS_ABI_FP, fpabi, what); +} + +static inline void +fpabi_requires (int fpabi, const char *what) +{ + as_warn (_(".gnu_attribute %d,%d requires `%s'"), + Tag_GNU_NANOMIPS_ABI_FP, fpabi, what); +} + +/* Check -mabi and register sizes against the specified FP ABI. */ +static void +check_fpabi (int fpabi) +{ + switch (fpabi) + { + case Val_GNU_NANOMIPS_ABI_FP_DOUBLE: + if (file_nanomips_opts.soft_float) + fpabi_incompatible_with (fpabi, "softfloat"); + else if (file_nanomips_opts.single_float) + fpabi_incompatible_with (fpabi, "singlefloat"); + break; + + case Val_GNU_NANOMIPS_ABI_FP_SINGLE: + if (file_nanomips_opts.soft_float) + fpabi_incompatible_with (fpabi, "softfloat"); + else if (!file_nanomips_opts.single_float) + fpabi_requires (fpabi, "singlefloat"); + break; + + case Val_GNU_NANOMIPS_ABI_FP_SOFT: + if (!file_nanomips_opts.soft_float) + fpabi_requires (fpabi, "softfloat"); + break; + + default: + as_warn (_(".gnu_attribute %d,%d is not a recognized" + " floating-point ABI"), Tag_GNU_NANOMIPS_ABI_FP, fpabi); + break; + } +} + +/* Perform consistency checks on the module level options exactly once. + This is a deferred check that happens: + at the first .set directive + or, at the first pseudo op that generates code (inc .dc.a) + or, at the first instruction + or, at the end. */ + +static void +file_check_options (void) +{ + const struct nanomips_cpu_info *arch_info = 0; + if (file_nanomips_opts_checked) + return; + + /* No user specified integer register size. */ + /* Infer the integer register size from the ABI. */ + if (file_nanomips_opts.gp < 0) + file_nanomips_opts.gp = ((ABI_NEEDS_32BIT_REGS (nanomips_abi)) ? 32 : 64); + + if (file_nanomips_opts.fp < 0) + /* No user specified float register size. */ + /* nanoMIPS implies 64-bit float registers. */ + file_nanomips_opts.fp = 64; + + /* This flag is set when we have a 64-bit capable CPU but use only + 32-bit wide registers. Note that EABI does not use it. */ + if (ISA_HAS_64BIT_REGS (file_nanomips_opts.isa) + && ((nanomips_abi == NO_ABI && file_nanomips_opts.gp == 32) + || nanomips_abi == P32_ABI)) + nanomips_32bitmode = 1; + + /* If the user didn't explicitly select or deselect a particular ASE, + use the default setting for the CPU. */ + file_nanomips_opts.ase |= + (file_nanomips_opts.init_ase & ~file_ase_explicit); + + /* Set up the current options. These may change throughout assembly. */ + nanomips_opts = file_nanomips_opts; + + check_isa_supports_ases (); + file_nanomips_opts_checked = true; + + if (!bfd_set_arch_mach (stdoutput, bfd_arch_nanomips, + file_nanomips_opts.arch)) + as_warn (_("could not set architecture and machine")); +} + +void +md_assemble (char *str) +{ + struct nanomips_cl_insn insn; + bfd_reloc_code_real_type unused_reloc[3] + = { BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED }; + + file_check_options (); + + imm_expr.X_op = O_absent; + offset_expr.X_op = O_absent; + offset_reloc[0] = BFD_RELOC_UNUSED; + offset_reloc[1] = BFD_RELOC_UNUSED; + offset_reloc[2] = BFD_RELOC_UNUSED; + + if (cur_proc_ptr == NULL && !stub_funcless_mode) + { + stubgroup_new (now_seg); + stub_funcless_mode = true; + } + + clear_insn_error (); + nanomips_ip (str, &insn); + + if (insn_error.msg) + report_insn_error (str); + else if (insn.insn_mo->pinfo == INSN_MACRO) + { + macro_start (); + macro (&insn, str); + macro_end ((insn.insn_mo->pinfo2 & INSN2_MACRO) != 0); + } + else + { + if (offset_expr.X_op != O_absent) + append_insn (&insn, &offset_expr, offset_reloc, false); + else + append_insn (&insn, NULL, unused_reloc, false); + } +} + +static inline bool +nanomips_reloc_p (bfd_reloc_code_real_type reloc) +{ + switch (reloc) + { + case BFD_RELOC_NANOMIPS_GPREL19_S2: + case BFD_RELOC_NANOMIPS_GPREL18_S3: + case BFD_RELOC_NANOMIPS_GPREL16_S2: + case BFD_RELOC_NANOMIPS_HI20: + case BFD_RELOC_NANOMIPS_LO12: + case BFD_RELOC_NANOMIPS_PCREL_HI20: + case BFD_RELOC_NANOMIPS_7_PCREL_S1: + case BFD_RELOC_NANOMIPS_10_PCREL_S1: + case BFD_RELOC_NANOMIPS_11_PCREL_S1: + case BFD_RELOC_NANOMIPS_21_PCREL_S1: + case BFD_RELOC_NANOMIPS_25_PCREL_S1: + case BFD_RELOC_NANOMIPS_14_PCREL_S1: + case BFD_RELOC_NANOMIPS_GOT_CALL: + case BFD_RELOC_NANOMIPS_GOTPC_HI20: + case BFD_RELOC_NANOMIPS_GOT_LO12: + case BFD_RELOC_NANOMIPS_GOT_PAGE: + case BFD_RELOC_NANOMIPS_GOT_OFST: + case BFD_RELOC_NANOMIPS_GOT_DISP: + case BFD_RELOC_NANOMIPS_IMM16: + case BFD_RELOC_NANOMIPS_NEG12: + case BFD_RELOC_NANOMIPS_I32: + case BFD_RELOC_NANOMIPS_TLS_GD: + case BFD_RELOC_NANOMIPS_TLS_GD_I32: + case BFD_RELOC_NANOMIPS_TLS_LD: + case BFD_RELOC_NANOMIPS_TLS_LD_I32: + case BFD_RELOC_NANOMIPS_TLS_DTPREL12: + case BFD_RELOC_NANOMIPS_TLS_DTPREL16: + case BFD_RELOC_NANOMIPS_TLS_DTPREL_I32: + case BFD_RELOC_NANOMIPS_TLS_TPREL12: + case BFD_RELOC_NANOMIPS_TLS_TPREL16: + case BFD_RELOC_NANOMIPS_TLS_TPREL_I32: + case BFD_RELOC_NANOMIPS_TLS_GOTTPREL: + case BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32: + case BFD_RELOC_NANOMIPS_PC_I32: + case BFD_RELOC_NANOMIPS_GOTPC_I32: + case BFD_RELOC_NANOMIPS_GPREL_I32: + case BFD_RELOC_NANOMIPS_GPREL18: + case BFD_RELOC_NANOMIPS_GPREL17_S1: + case BFD_RELOC_NANOMIPS_GPREL_HI20: + case BFD_RELOC_NANOMIPS_GPREL_LO12: + case BFD_RELOC_NANOMIPS_SIGNED_9: + return true; + + default: + return false; + } +} + +static inline bool +nanomips_48bit_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (reloc == BFD_RELOC_NANOMIPS_I32 + || reloc == BFD_RELOC_NANOMIPS_PC_I32 + || reloc == BFD_RELOC_NANOMIPS_GPREL_I32 + || reloc == BFD_RELOC_NANOMIPS_GOTPC_I32 + || reloc == BFD_RELOC_NANOMIPS_TLS_GD_I32 + || reloc == BFD_RELOC_NANOMIPS_TLS_LD_I32 + || reloc == BFD_RELOC_NANOMIPS_TLS_DTPREL_I32 + || reloc == BFD_RELOC_NANOMIPS_TLS_TPREL_I32 + || reloc == BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32); +} + +static inline bool +hi_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (reloc == BFD_RELOC_HI16_S + || reloc == BFD_RELOC_NANOMIPS_HI20 + || reloc == BFD_RELOC_NANOMIPS_GOTPC_HI20 + || reloc == BFD_RELOC_NANOMIPS_GPREL_HI20); +} + +static inline bool +lo_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (reloc == BFD_RELOC_LO16 + || reloc == BFD_RELOC_NANOMIPS_LO12 + || reloc == BFD_RELOC_NANOMIPS_GPREL_LO12 + || reloc == BFD_RELOC_NANOMIPS_GOT_LO12); +} + +static inline bool +gprel_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (reloc == BFD_RELOC_GPREL16 + || reloc == BFD_RELOC_NANOMIPS_GPREL7_S2 + || reloc == BFD_RELOC_NANOMIPS_GPREL18 + || reloc == BFD_RELOC_NANOMIPS_GPREL19_S2 + || reloc == BFD_RELOC_NANOMIPS_GPREL16_S2 + || reloc == BFD_RELOC_NANOMIPS_GPREL18_S3 + || reloc == BFD_RELOC_NANOMIPS_GPREL17_S1 + || reloc == BFD_RELOC_NANOMIPS_TLS_GD + || reloc == BFD_RELOC_NANOMIPS_TLS_LD); +} + +static inline bool +pcrel16_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (reloc == BFD_RELOC_NANOMIPS_4_PCREL_S1 + || reloc == BFD_RELOC_NANOMIPS_7_PCREL_S1 + || reloc == BFD_RELOC_NANOMIPS_10_PCREL_S1); +} + +static inline bool +pcrel32_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (reloc == BFD_RELOC_32_PCREL + || reloc == BFD_RELOC_NANOMIPS_11_PCREL_S1 + || reloc == BFD_RELOC_NANOMIPS_14_PCREL_S1 + || reloc == BFD_RELOC_NANOMIPS_21_PCREL_S1 + || reloc == BFD_RELOC_NANOMIPS_25_PCREL_S1 + || reloc == BFD_RELOC_NANOMIPS_PCREL_HI20 + || reloc == BFD_RELOC_NANOMIPS_GOTPC_HI20); +} + +static inline bool +pcrel_branch_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (pcrel16_reloc_p (reloc) + || (pcrel32_reloc_p (reloc) + && reloc != BFD_RELOC_NANOMIPS_PCREL_HI20 + && reloc != BFD_RELOC_NANOMIPS_GOTPC_HI20)); +} + +static inline bool +pcrel48_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (reloc == BFD_RELOC_NANOMIPS_PC_I32 + || reloc == BFD_RELOC_NANOMIPS_GOTPC_I32 + || reloc == BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32); +} + +static inline bool +pcrel_reloc_p (bfd_reloc_code_real_type reloc) +{ + return (pcrel16_reloc_p (reloc) + || pcrel32_reloc_p (reloc) + || pcrel48_reloc_p (reloc)); +} + +/* Return true if RELOC is a PC-relative relocation that does not have + full address range. */ + +static inline bool +limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc) +{ + switch (reloc) + { + case BFD_RELOC_NANOMIPS_4_PCREL_S1: + case BFD_RELOC_NANOMIPS_7_PCREL_S1: + case BFD_RELOC_NANOMIPS_10_PCREL_S1: + case BFD_RELOC_NANOMIPS_11_PCREL_S1: + case BFD_RELOC_NANOMIPS_14_PCREL_S1: + case BFD_RELOC_NANOMIPS_21_PCREL_S1: + case BFD_RELOC_NANOMIPS_25_PCREL_S1: + return true; + + case BFD_RELOC_32_PCREL: + case BFD_RELOC_NANOMIPS_PCREL_HI20: + return HAVE_64BIT_ADDRESSES; + + default: + return false; + } +} + +/* Return true if RELOC is a place-holder for linker relaxation and + not associated with a particular instruction. */ + +static inline bool +linkrelax_reloc_p (bfd_reloc_code_real_type reloc) +{ + switch (reloc) + { + case BFD_RELOC_NANOMIPS_ALIGN: + case BFD_RELOC_NANOMIPS_FILL: + case BFD_RELOC_NANOMIPS_MAX: + case BFD_RELOC_NANOMIPS_FIXED: + case BFD_RELOC_NANOMIPS_RELAX: + case BFD_RELOC_NANOMIPS_NORELAX: + return true; + default: + return false; + } +} + +/* Return true if R is an initial selected relocation that has multiple + size variants. */ + +static bool +flex_reloc_p (bfd_reloc_code_real_type r) +{ + return (r == BFD_RELOC_NANOMIPS_GPREL18 + || r == BFD_RELOC_NANOMIPS_TLS_LD + || r == BFD_RELOC_NANOMIPS_TLS_GD + || r == BFD_RELOC_NANOMIPS_TLS_TPREL12 + || r == BFD_RELOC_NANOMIPS_TLS_DTPREL12); +} + + +/* Return true if R is GP-relative relocation that takes 32-bit + immediate displacement. */ + +static bool +gprel_i32_reloc_p (bfd_reloc_code_real_type r) +{ + return (r == BFD_RELOC_NANOMIPS_GPREL_I32 + || r == BFD_RELOC_NANOMIPS_TLS_LD_I32 + || r == BFD_RELOC_NANOMIPS_TLS_GD_I32); +} + +/* Return the type of %lo() reloc needed by RELOC, given that + reloc_needs_lo_p. */ + +static inline bfd_reloc_code_real_type +matching_lo_reloc (bfd_reloc_code_real_type reloc ATTRIBUTE_UNUSED) +{ + return (BFD_RELOC_LO16); +} + +/* Return true if the given fixup is followed by a matching %lo + relocation. */ + +static inline bool +fixup_has_matching_lo_p (fixS *fixp) +{ + return (fixp->fx_next != NULL + && fixp->fx_next->fx_r_type == matching_lo_reloc (fixp->fx_r_type) + && fixp->fx_addsy == fixp->fx_next->fx_addsy + && fixp->fx_offset == fixp->fx_next->fx_offset); +} + +/* Move all labels in LABELS to the current insertion point. */ + +static void +nanomips_move_labels (struct insn_label_list *labels) +{ + struct insn_label_list *l; + valueT val; + segment_info_type *si = seg_info (now_seg); + + if (toggle_linkrelax_p) + toggle_linkrelax (frag_now, frag_now_fix ()); + + for (l = si->label_list; l != NULL; l = l->next) + { + gas_assert (S_GET_SEGMENT (l->label) == now_seg); + symbol_set_frag (l->label, frag_now); + val = (valueT) frag_now_fix (); + S_SET_VALUE (l->label, val); + } +} + +static bool +s_is_linkonce (symbolS *sym, segT from_seg) +{ + bool linkonce = false; + segT symseg = S_GET_SEGMENT (sym); + + if (symseg != from_seg && !S_IS_LOCAL (sym)) + { + if ((bfd_section_flags (symseg) & SEC_LINK_ONCE)) + linkonce = true; + /* The GNU toolchain uses an extension for ELF: a section + beginning with the magic string .gnu.linkonce is a + linkonce section. */ + if (strncmp (segment_name (symseg), ".gnu.linkonce", + sizeof ".gnu.linkonce" - 1) == 0) + linkonce = true; + } + return linkonce; +} + +/* End the current frag. Make it a variant frag and record the + relaxation info. */ + +static void +relax_close_frag (void) +{ + nanomips_macro_warning.first_frag = frag_now; + frag_var (rs_machine_dependent, 0, 0, + RELAX_ENCODE (nanomips_relax.sizes[0], nanomips_relax.sizes[1]), + nanomips_relax.symbol, 0, (char *) nanomips_relax.first_fixup); + + memset (&nanomips_relax.sizes, 0, sizeof (nanomips_relax.sizes)); + nanomips_relax.first_fixup = 0; +} + +/* Start a new relaxation sequence whose expansion depends on SYMBOL. + See the comment above RELAX_ENCODE for more details. */ + +static void +relax_start (symbolS *symbol) +{ + gas_assert (nanomips_relax.sequence == 0); + nanomips_relax.sequence = 1; + nanomips_relax.symbol = symbol; +} + +/* Start generating the second version of a relaxable sequence. + See the comment above RELAX_ENCODE for more details. */ + +static void +relax_switch (void) +{ + gas_assert (nanomips_relax.sequence == 1); + nanomips_relax.sequence = 2; +} + +/* End the current relaxable sequence. */ + +static void +relax_end (void) +{ + gas_assert (nanomips_relax.sequence == 2); + relax_close_frag (); + nanomips_relax.sequence = 0; +} + +/* Return true if IP is a compact branch or jump. */ + +static inline bool +compact_branch_p (const struct nanomips_cl_insn *ip) +{ + return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH + | INSN2_COND_BRANCH)) != 0; +} + +/* Return true if IP is an unconditional branch or jump. */ + +static inline bool +uncond_branch_p (const struct nanomips_cl_insn *ip) +{ + return ((ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0); +} + +/* Information about an instruction argument that we're trying to match. */ +struct nanomips_arg_info +{ + /* The instruction so far. */ + struct nanomips_cl_insn *insn; + + /* The first unconsumed operand token. */ + struct nanomips_operand_token *token; + + /* The 1-based operand number, in terms of insn->insn_mo->args. */ + int opnum; + + /* The 1-based argument number, for error reporting. This does not + count elided optional registers, etc.. */ + int argnum; + + /* The last OP_REG operand seen, or ILLEGAL_REG if none. */ + unsigned int last_regno; + + /* If the first operand was an OP_REG, this is the register that it + specified, otherwise it is ILLEGAL_REG. */ + unsigned int dest_regno; + + /* The value of the last OP_INT operand. Used for OP_MSB, + where it gives the lsb position and to check stack frame size + for save/restore register list. */ + unsigned int last_op_int; + + /* If true, match routines should assume that no later instruction + alternative matches and should therefore be as accomodating as + possible. Match routines should not report errors if something + is only invalid for !LAX_MATCH. */ + bool lax_match; + + /* True if a reference to the current AT register was seen. */ + bool seen_at; + + /* CP0 select register mask. */ + unsigned int select_mask; +}; + +/* Record that the argument is out of range. */ + +static void +match_out_of_range (struct nanomips_arg_info *arg) +{ + set_insn_error_i (arg->argnum, _("operand %d out of range"), arg->argnum); +} + +/* Record that the argument isn't constant but needs to be. */ + +static void +match_not_constant (struct nanomips_arg_info *arg) +{ + set_insn_error_i (arg->argnum, _("operand %d must be constant"), + arg->argnum); +} + +/* Try to match an OT_CHAR token for character CH. Consume the token + and return true on success, otherwise return false. */ + +static bool +match_char (struct nanomips_arg_info *arg, char ch) +{ + if (arg->token->type == OT_CHAR && arg->token->u.ch == ch) + { + ++arg->token; + if (ch == ',') + arg->argnum += 1; + return true; + } + return false; +} + +/* Try to get an expression from the next tokens in ARG. Consume the + tokens and return true on success, storing the expression value in + VALUE and relocation types in R. */ + +static bool +match_expression (struct nanomips_arg_info *arg, expressionS *value, + bfd_reloc_code_real_type *r) +{ + /* If the next token is a '(' that was parsed as being part of a base + expression, assume we have an elided offset. The later match will fail + if this turns out to be wrong. */ + if (arg->token->type == OT_CHAR && arg->token->u.ch == '(') + { + value->X_op = O_constant; + value->X_add_number = 0; + r[0] = r[1] = r[2] = BFD_RELOC_UNUSED; + return true; + } + + /* Reject register-based expressions such as "0+$2" and "(($2))". + For plain registers the default error seems more appropriate. */ + if (arg->token->type == OT_INTEGER + && arg->token->u.integer.value.X_op == O_register) + { + set_insn_error (arg->argnum, _("register value used as expression")); + return false; + } + + if (arg->token->type == OT_INTEGER) + { + *value = arg->token->u.integer.value; + memcpy (r, arg->token->u.integer.relocs, 3 * sizeof (*r)); + ++arg->token; + return true; + } + + set_insn_error_i + (arg->argnum, _("operand %d must be an immediate expression"), + arg->argnum); + return false; +} + +/* Try to get a constant expression from the next tokens in ARG. Consume + the tokens and return return true on success, storing the constant value + in *VALUE. Use FALLBACK as the value if the match succeeded with an + error. */ + +static bool +match_const_int (struct nanomips_arg_info *arg, offsetT *value) +{ + expressionS ex; + bfd_reloc_code_real_type r[3]; + + if (!match_expression (arg, &ex, r)) + return false; + + if (r[0] == BFD_RELOC_UNUSED && ex.X_op == O_constant) + *value = ex.X_add_number; + else + { + match_not_constant (arg); + return false; + } + return true; +} + +/* Return the RTYPE_* flags for a register operand of type TYPE that + appears in instruction OPCODE. */ + +static unsigned int +convert_reg_type (const struct nanomips_opcode *opcode, + enum nanomips_reg_operand_type type) +{ + switch (type) + { + case OP_REG_GP: + default: + if (!nanomips_opts.legacyregs) + return RTYPE_GP; + else + return RTYPE_NUM | RTYPE_GP; + + case OP_REG_FP: + return RTYPE_FPU; + + case OP_REG_ACC: + return RTYPE_ACC; + + case OP_REG_COPRO: + if (opcode->name[strlen (opcode->name) - 1] == '0') + return RTYPE_NUM | RTYPE_CP0; + return RTYPE_NUM; + + case OP_REG_HW: + return RTYPE_NUM; + + case OP_REG_CP0: + /* CP0 register without select must be symbolic. */ + return RTYPE_CP0; + + case OP_REG_CP0SEL: + /* CP0 register with select may be numeric. */ + return RTYPE_CP0SEL | RTYPE_NUM; + } + abort (); +} + +/* ARG is register REGNO, of type TYPE. Warn about any dubious registers. */ + +static void +check_regno (struct nanomips_arg_info *arg, + enum nanomips_reg_operand_type type, unsigned int regno) +{ + if (AT && type == OP_REG_GP && regno == AT) + arg->seen_at = true; +} + +/* ARG is a register with symbol value SYMVAL. Try to interpret it as + a register of type TYPE. Return true on success, storing the register + number in *REGNO and warning about any dubious uses. */ + +static bool +match_regno (struct nanomips_arg_info *arg, + enum nanomips_reg_operand_type type, unsigned int symval, + unsigned int *regno) +{ + if (!(symval & convert_reg_type (arg->insn->insn_mo, type))) + return false; + + /* Remember if the register name matches a specific select mask type. + Otherwise fall-back to allowing all select values. */ + if (type == OP_REG_CP0SEL) + switch (symval & RTYPE_CP0SEL) + { + case RTYPE_CP0SEL_EVEN: + arg->select_mask = NANOMIPS_CP0SEL_MASK_EVEN; + break; + case RTYPE_CP0SEL_ODD: + arg->select_mask = NANOMIPS_CP0SEL_MASK_ODD; + break; + case RTYPE_CP0SEL: + default: + arg->select_mask = NANOMIPS_CP0SEL_MASK_ANY; + break; + } + + *regno = symval & RNUM_MASK; + check_regno (arg, type, *regno); + return true; +} + +/* Try to interpret the next token in ARG as a register of type TYPE. + Consume the token and return true on success, storing the register + number in *REGNO. Return false on failure. */ + +static bool +match_reg (struct nanomips_arg_info *arg, enum nanomips_reg_operand_type type, + unsigned int *regno) +{ + if (arg->token->type == OT_REG + && match_regno (arg, type, arg->token->u.regno, regno)) + { + ++arg->token; + return true; + } + return false; +} + +/* Try to interpret the next token in ARG as a range of registers of type TYPE. + Consume the token and return true on success, storing the register numbers + in *REGNO1 and *REGNO2. Return false on failure. */ + +static bool +match_reg_range (struct nanomips_arg_info *arg, + enum nanomips_reg_operand_type type, unsigned int *regno1, + unsigned int *regno2) +{ + if (match_reg (arg, type, regno1)) + { + *regno2 = *regno1; + return true; + } + if (arg->token->type == OT_REG_RANGE + && match_regno (arg, type, arg->token->u.reg_range.regno1, regno1) + && match_regno (arg, type, arg->token->u.reg_range.regno2, regno2) + && *regno1 <= *regno2) + { + ++arg->token; + return true; + } + return false; +} + +/* OP_INT matcher. */ + +static bool +match_relocatable_int_operand (const struct nanomips_operand *operand_base) +{ + const struct nanomips_int_operand *operand; + unsigned int op_size; + + operand = (const struct nanomips_int_operand *) operand_base; + op_size = operand_base->size; + + if ((op_size == 7 && operand->shift == 2) + || (op_size == 4 && operand->shift == 2) + || op_size == 12 + || op_size == 14 + || op_size == 16 + || op_size == 17 + || op_size == 18 + || op_size == 19 + || op_size == 20) + return true; + + return false; +} + +/* Negative 12-bit constant matcher. */ + +static bool +match_negative_int_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + offsetT sval; + + if (!match_const_int (arg, &sval)) + return false; + if ((int) sval > 0 || (int) sval < -4095) + return false; + sval = -(int) sval; + + insn_insert_operand (arg->insn, operand_base, sval); + return true; +} + +/* Check if OPERAND_BASE matches a suitable variant of relocation RTYPE. */ + +static bool +match_flex_reloc_for_int_operand (const struct nanomips_operand *operand_base, + bfd_reloc_code_real_type rtype) +{ + size_t i; + int opmask = nanomips_operand_mask (operand_base); + const bfd_reloc_code_real_type gp_relocs[] = { + BFD_RELOC_NANOMIPS_GPREL18, + BFD_RELOC_NANOMIPS_GPREL19_S2, + BFD_RELOC_NANOMIPS_GPREL18_S3, + BFD_RELOC_NANOMIPS_GPREL16_S2, + BFD_RELOC_NANOMIPS_GPREL17_S1, + BFD_RELOC_NANOMIPS_GPREL7_S2 + }; + const bfd_reloc_code_real_type tp_relocs[] = { + BFD_RELOC_NANOMIPS_TLS_TPREL12, + BFD_RELOC_NANOMIPS_TLS_TPREL16 + }; + const bfd_reloc_code_real_type dtp_relocs[] = { + BFD_RELOC_NANOMIPS_TLS_DTPREL12, + BFD_RELOC_NANOMIPS_TLS_DTPREL16 + }; + size_t rcount; + const bfd_reloc_code_real_type *rlist; + + switch (rtype) + { + case BFD_RELOC_NANOMIPS_GPREL18: + rlist = gp_relocs; + rcount = ARRAY_SIZE (gp_relocs); + break; + case BFD_RELOC_NANOMIPS_TLS_TPREL12: + rlist = tp_relocs; + rcount = ARRAY_SIZE (tp_relocs); + break; + case BFD_RELOC_NANOMIPS_TLS_DTPREL12: + rlist = dtp_relocs; + rcount = ARRAY_SIZE (dtp_relocs); + break; + default: + rlist = &rtype; + rcount = 1; + break; + } + + for (i = 0; i < rcount; i++) + { + reloc_howto_type *howto; + howto = bfd_reloc_type_lookup (stdoutput, rlist[i]); + + if ((howto->dst_mask & opmask) == howto->dst_mask + && howto->bitsize == operand_base->size) + return true; + } + return false; +} + +/* Generic INT matcher. */ + +static bool +match_int_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + const struct nanomips_int_operand *operand; + unsigned int uval; + int min_val, max_val, factor; + offsetT sval; + + operand = (const struct nanomips_int_operand *) operand_base; + factor = 1 << operand->shift; + min_val = nanomips_int_operand_min (operand); + max_val = nanomips_int_operand_max (operand); + + if (match_relocatable_int_operand (operand_base)) + { + /* The operand can be relocated. */ + if (!match_expression (arg, &offset_expr, offset_reloc)) + return false; + + if (offset_reloc[0] != BFD_RELOC_UNUSED + && !nanomips_48bit_reloc_p (offset_reloc[0])) + /* Relocation operators were used. Check if relocation + destination mask matches operand bits. */ + { + if (flex_reloc_p (offset_reloc[0])) + return match_flex_reloc_for_int_operand (operand_base, + offset_reloc[0]); + else + { + int opmask; + reloc_howto_type *howto; + + if (offset_reloc[0] == BFD_RELOC_NANOMIPS_LO12 + && (forced_insn_length == 2 + || (forced_insn_format + && insn_length (arg->insn->insn_mo) == 2))) + offset_reloc[0] = BFD_RELOC_NANOMIPS_LO4_S2; + + howto = bfd_reloc_type_lookup (stdoutput, offset_reloc[0]); + opmask = nanomips_operand_mask (operand_base); + /* This is not an direct mask comparison. In some cases + the relocation targets only a part of the operand bits. */ + return ((howto->dst_mask & opmask) == howto->dst_mask); + } + } + + if (offset_expr.X_op != O_constant) + { + /* Accept non-constant operands if no later alternative matches, + leaving it for the caller to process. */ + if (operand_base->size == 16 && offset_expr.X_op == O_subtract) + { + offset_reloc[0] = BFD_RELOC_UNUSED + RT_ADDIU; + return true; + } + else + { + offset_reloc[0] = BFD_RELOC_NANOMIPS_LO12; + return arg->lax_match; + } + } + + /* Clear the global state; we're going to install the operand + ourselves. */ + if (min_val < 0) + sval = (int) offset_expr.X_add_number; + else + sval = offset_expr.X_add_number; + + offset_expr.X_op = O_absent; + + /* For compatibility with older assemblers, we accept + 0x8000-0xffff as signed 16-bit numbers when only + signed numbers are allowed. */ + if (sval > max_val) + { + max_val = ((1 << operand_base->size) - 1) << operand->shift; + if (!arg->lax_match && sval <= max_val) + return false; + } + } + else + { + if (!match_const_int (arg, &sval)) + return false; + if (min_val < 0 && IS_ZEXT_32BIT_NUM (sval)) + sval = (int) sval; + } + + arg->last_op_int = sval; + + if (sval < min_val || sval > max_val || sval % factor) + { + match_out_of_range (arg); + return false; + } + + uval = (unsigned int) sval >> operand->shift; + uval -= operand->bias; + + insn_insert_operand (arg->insn, operand_base, uval); + return true; +} + +/* Match integer operand with no relocation. */ +static bool +match_imm_int_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + if (!match_int_operand (arg, operand_base)) + return false; + + return ((offset_expr.X_op == O_absent || offset_expr.X_op == O_constant) + && *offset_reloc == BFD_RELOC_UNUSED); +} + +#define MAX_ADDI_OFFSET (0xffff) + +#define MIN_ADDI_OFFSET (-4095) + +static bool +match_int_word (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand ATTRIBUTE_UNUSED) +{ + if (match_expression (arg, &offset_expr, offset_reloc)) + { + if (offset_reloc[0] != BFD_RELOC_UNUSED + && !nanomips_48bit_reloc_p (offset_reloc[0]) + && !flex_reloc_p (offset_reloc[0])) + /* Any other relocation operators not allowed in this position. */ + return false; + + if (offset_reloc[0] == BFD_RELOC_UNUSED) + offset_reloc[0] = BFD_RELOC_NANOMIPS_I32; + + /* We don't match symbol-difference expressions here. */ + if (offset_expr.X_op != O_constant && offset_expr.X_op_symbol == NULL) + { + arg->insn->insn_opcode_ext = 0; + return true; + } + else + if ((forced_insn_length == 6 + || forced_insn_format + || offset_expr.X_add_number > MAX_ADDI_OFFSET + || offset_expr.X_add_number < MIN_ADDI_OFFSET) + && offset_expr.X_op != O_big) + /* We don't match the 48-bit instruction, when we could make + do with a 32-bit one, unless explicitly required. */ + { + arg->last_op_int = offset_expr.X_add_number; + arg->insn->insn_opcode_ext = 0; + return true; + } + } + return false; +} + +/* Match an immediate 32-bit value with possible bias. */ +static bool +match_imm_word (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + const struct nanomips_int_operand *operand; + operand = (const struct nanomips_int_operand *) operand_base; + + if (match_expression (arg, &offset_expr, offset_reloc)) + { + if (offset_expr.X_op != O_constant || *offset_reloc != BFD_RELOC_UNUSED) + return false; + + if (offset_expr.X_op != O_big) + { + int sval = offset_expr.X_add_number - operand->bias; + arg->last_op_int = sval; + arg->insn->insn_opcode_ext = 0; + arg->insn->insn_opcode_ext = (((sval >> 16) & 0xffff) + | (sval << 16)); + offset_expr.X_op = O_absent; + return true; + } + } + return false; +} + +static bool +match_pcrel_word (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand ATTRIBUTE_UNUSED) +{ + if (match_expression (arg, &offset_expr, offset_reloc)) + { + if (offset_reloc[0] != BFD_RELOC_UNUSED + && !nanomips_48bit_reloc_p (offset_reloc[0])) + /* Any other relocation operators not allowed in this position. */ + return false; + + if (offset_reloc[0] == BFD_RELOC_UNUSED) + offset_reloc[0] = BFD_RELOC_NANOMIPS_PC_I32; + + arg->insn->insn_opcode_ext = 0; + return true; + } + return false; +} + +static bool +match_gprel_word (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand ATTRIBUTE_UNUSED) +{ + if (match_expression (arg, &offset_expr, offset_reloc)) + { + if (offset_reloc[0] != BFD_RELOC_UNUSED + && !gprel_i32_reloc_p (offset_reloc[0]) + && (forced_insn_length != 6 || !gprel_reloc_p (offset_reloc[0]))) + /* Any other relocation operators not allowed in this position. */ + return false; + + if (offset_reloc[0] == BFD_RELOC_UNUSED) + offset_reloc[0] = BFD_RELOC_NANOMIPS_GPREL_I32; + + arg->insn->insn_opcode_ext = 0; + return true; + } + return false; +} + +/* OP_MAPPED_INT matcher. */ +static bool +match_mapped_int_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + const struct nanomips_mapped_int_operand *operand; + unsigned int uval, num_vals; + offsetT sval; + + operand = (const struct nanomips_mapped_int_operand *) operand_base; + if (!match_const_int (arg, &sval)) + return false; + + num_vals = 1 << operand_base->size; + for (uval = 0; uval < num_vals; uval++) + if (operand->int_map[uval] == sval) + break; + if (uval == num_vals) + { + match_out_of_range (arg); + return false; + } + + insn_insert_operand (arg->insn, operand_base, uval); + return true; +} + +/* OP_MSB matcher. */ + +static bool +match_msb_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + const struct nanomips_msb_operand *operand; + int min_val, max_val, max_high; + offsetT size, sval, high; + + operand = (const struct nanomips_msb_operand *) operand_base; + min_val = operand->bias; + max_val = min_val + (1 << operand_base->size) - 1; + max_high = operand->opsize; + + if (!match_const_int (arg, &size)) + return false; + + high = size + arg->last_op_int; + sval = operand->add_lsb ? high : size; + + if (size < 0 || high > max_high || sval < min_val || sval > max_val) + { + match_out_of_range (arg); + return false; + } + insn_insert_operand (arg->insn, operand_base, sval - min_val); + return true; +} + +/* OP_REG matcher. */ + +static bool +match_reg_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + const struct nanomips_reg_operand *operand; + unsigned int regno, uval, num_vals; + + operand = (const struct nanomips_reg_operand *) operand_base; + if (!match_reg (arg, operand->reg_type, ®no)) + return false; + + if (operand->reg_map) + { + num_vals = 1 << operand->root.size; + for (uval = 0; uval < num_vals; uval++) + if (operand->reg_map[uval] == regno) + break; + if (num_vals == uval) + return false; + } + else + uval = regno; + + if (operand_base->size > 0 + && uval >= (unsigned int) (1 << operand_base->size)) + { + match_out_of_range (arg); + return false; + } + + arg->last_regno = regno; + if (arg->opnum == 1) + arg->dest_regno = regno; + insn_insert_operand (arg->insn, operand_base, uval); + return true; +} + +/* OP_REG_PAIR matcher. */ + +static bool +match_reg_pair_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + const struct nanomips_reg_pair_operand *operand; + unsigned int regno1, regno2, uval, num_vals; + + operand = (const struct nanomips_reg_pair_operand *) operand_base; + if (!match_reg (arg, operand->reg_type, ®no1) + || !match_char (arg, ',') + || !match_reg (arg, operand->reg_type, ®no2)) + return false; + + num_vals = 1 << operand_base->size; + for (uval = 0; uval < num_vals; uval++) + if (operand->reg1_map[uval] == regno1 + && operand->reg2_map[uval] == regno2) + break; + if (uval == num_vals) + return false; + + insn_insert_operand (arg->insn, operand_base, uval); + return true; +} + +/* OP_PCREL matcher. The caller chooses the relocation type. */ + +static bool +match_pcrel_operand (struct nanomips_arg_info *arg) +{ + bfd_reloc_code_real_type r[3]; + + return match_expression (arg, &offset_expr, r) && r[0] == BFD_RELOC_UNUSED; +} + +static bool +match_non_zero_pcrel_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + bfd_reloc_code_real_type r[3]; + + if (!match_expression (arg, &offset_expr, r) || r[0] != BFD_RELOC_UNUSED) + return false; + + if (!offset_expr.X_add_symbol && offset_expr.X_add_number == 0) + { + set_insn_error (arg->argnum, + _("the PC relative offset must not be $0")); + return false; + } + + /* Enforce operand bits in the instruction encoding as non-zero + so that it can be distinguished from another instructions with the same + encoding and 0 in these bit positions. Requires the relocation + scheme to be RELA, which is trivially true only for nanoMIPS. The check + for ISA just to be on the safe side. */ + insn_insert_operand (arg->insn, operand_base, + (1 << operand_base->size) - 1); + return true; +} + +/* OP_HI20_INT matcher. */ + +#define UNSIGNED_OPVALUE(OP) \ +{ { OP_INT, OP->size, OP->lsb, OP->size_top, OP->lsb_top }, \ + ((1 << OP->size) - 1), 0, 0, false } + +#define SIGNEX_OPVALUE(OP) { OP_INT, OP->size - 1, OP->lsb, 0, 0 } + +static bool +match_hi20_int_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base + ATTRIBUTE_UNUSED) +{ + offsetT uval = 0; + const struct nanomips_int_operand op_enc = { + {OP_INT, 20, 2, 1, 0}, (1 << 20) - 1, 12, 0, false + }; + const struct nanomips_int_operand op_shuffle = { + {OP_INT, 19, 10, 10, 0}, (1 << 19) - 1, 12, 0, false + }; + + if (!match_expression (arg, &offset_expr, offset_reloc)) + return false; + + /* 16-bit immediate without %hi reloc */ + if (offset_reloc[0] == BFD_RELOC_UNUSED && offset_expr.X_op == O_constant) + { + if ((offset_expr.X_add_number & ~0xffff) == 0) + uval = offset_expr.X_add_number << 4; + else + { + match_out_of_range (arg); + return false; + } + } + /* 20-bit high part using %hi */ + else if (hi_reloc_p (offset_reloc[0])) + uval = offset_expr.X_add_number >> 12; + else + { + /* Accept non-constant operands if no later alternative matches, + leaving it for the caller to process. */ + if (arg->lax_match) + offset_reloc[0] = BFD_RELOC_NANOMIPS_HI20; + return arg->lax_match; + } + + if (offset_expr.X_op == O_constant) + { + offset_expr.X_op = O_absent; + /* Re-shuffle and insert lower 19-bits, exluding sign. */ + uval = nanomips_insert_operand (&op_shuffle.root, + uval & 0x80000, uval & 0x7ffff); + + /* Insert 20-bits in to instruction. */ + insn_insert_operand (arg->insn, &op_enc.root, uval); + } + return true; +} + +/* OP_HI20_PCREL matcher. Relocation must be specified. */ +static bool +match_hi20_pcrel_operand (struct nanomips_arg_info *arg) +{ + const struct nanomips_int_operand op_enc = { + {OP_INT, 20, 2, 1, 0 }, (1 << 20) - 1, 0, 0, false + }; + const struct nanomips_int_operand op_shuffle = { + {OP_INT, 19, 10, 10, 0}, (1 << 19) - 1, 0, 0, false + }; + /* Encode full 20-bit signed value. */ + if (!match_expression (arg, &offset_expr, offset_reloc)) + return false; + + if (offset_reloc[0] == BFD_RELOC_UNUSED + || (hi_reloc_p (offset_reloc[0]) && offset_expr.X_op == O_constant)) + { + unsigned int uval = offset_expr.X_add_number; + + if (hi_reloc_p (offset_reloc[0])) + uval = uval >> 12; + + /* Re-shuffle and insert lower 19-bits, exluding sign. */ + uval = nanomips_insert_operand (&op_shuffle.root, + uval & 0x80000, uval & 0x7ffff); + /* Insert 20-bits in to instruction. */ + insn_insert_operand (arg->insn, &op_enc.root, uval); + /* Expression is completely handled, we don't want append_insn + messing up the opcode. */ + offset_expr.X_op = O_absent; + return true; + } + else + return (offset_reloc[0] == BFD_RELOC_NANOMIPS_PCREL_HI20 + || offset_reloc[0] == BFD_RELOC_NANOMIPS_GOTPC_HI20); +} + +static bool +match_hi20_scaled_operand (struct nanomips_arg_info *arg) +{ + const struct nanomips_int_operand op_enc = { + {OP_INT, 20, 2, 1, 0}, (1 << 20) - 1, 12, 0, false + }; + const struct nanomips_int_operand op_shuffle = { + {OP_INT, 19, 10, 10, 0}, (1 << 19) - 1, 12, 0, false + }; + offsetT uval = 0; + + if (!match_const_int (arg, &uval) || (uval & 0xfff) != 0) + return false; + + uval = uval >> 12; + offset_expr.X_op = O_absent; + + /* Re-shuffle and insert lower 19-bits, exluding sign. */ + uval = nanomips_insert_operand (&op_shuffle.root, + uval & 0x80000, uval & 0x7ffff); + + /* Insert 20-bits in to instruction. */ + insn_insert_operand (arg->insn, &op_enc.root, uval); + + return true; +} + +/* OP_CHECK_PREV matcher. */ + +static bool +match_check_prev_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + const struct nanomips_check_prev_operand *operand; + unsigned int regno; + + operand = (const struct nanomips_check_prev_operand *) operand_base; + + if (!match_reg (arg, OP_REG_GP, ®no)) + return false; + + if (!operand->zero_ok && regno == 0) + return false; + + if ((operand->less_than_ok && regno < arg->last_regno) + || (operand->greater_than_ok && regno > arg->last_regno) + || (operand->equal_ok && regno == arg->last_regno)) + { + arg->last_regno = regno; + insn_insert_operand (arg->insn, operand_base, regno); + return true; + } + return false; +} + +/* OP_MAPPED_CHECK_PREV matcher. */ + +static bool +match_mapped_check_prev_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + unsigned char uval, last_uval; + const struct nanomips_mapped_check_prev_operand *operand + = (const struct nanomips_mapped_check_prev_operand *) operand_base; + + last_uval = nanomips_encode_reg_operand (operand_base, arg->last_regno); + + if (!match_reg_operand (arg, operand_base)) + return false; + + if (!operand->zero_ok && arg->last_regno == 0) + return false; + + uval = nanomips_encode_reg_operand (operand_base, arg->last_regno); + + if ((operand->less_than_ok && uval < last_uval) + || (operand->greater_than_ok && uval > last_uval) + || (operand->equal_ok && uval == last_uval)) + return true; + + return false; +} + +/* OP_SAVE_RESTORE_FP_LIST matcher for nanoMIPS. */ + +static bool +match_save_restore_fp_list_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand) +{ + unsigned int opval; + unsigned int regno1, regno2; + + if (!match_reg_range (arg, OP_REG_FP, ®no1, ®no2)) + return false; + + if (regno1 != 0 || regno2 > 15) + return false; + + opval = (regno2 - regno1); + + insn_insert_operand (arg->insn, operand, opval); + return true; +} + +/* OP_SAVE_RESTORE_LIST matcher. */ + +static bool +match_save_restore_list_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand) +{ + unsigned int opval, count; + unsigned first_reg, last_reg; + bool mode16 = (insn_length (arg->insn->insn_mo) == 2); + bool gp = false; + + count = 0; + first_reg = last_reg = RNUM_MASK + 1; + do + { + unsigned int regno1 = 0, regno2 = 0; + bool first_range = false; + + if (!match_reg_range (arg, OP_REG_GP, ®no1, ®no2)) + { + arg->token--; + if (regno2 != 0 && regno2 < regno1) + set_insn_error_ss (count, + "register range (%s-%s) is not in " + "increasing order", + nanomips_reg_names[32 + regno1].name, + nanomips_reg_names[32 + regno2].name); + return false; + } + + if (regno1 <= 29 && regno2 >= 29) + { + set_insn_error_ss (regno1, + "%s register list should not contain $sp%s", + arg->insn->insn_mo->name, ""); + return false; + } + + if (first_reg == RNUM_MASK + 1) + { + first_reg = last_reg = regno1; + first_range = true; + } + + if ((regno1 != ((first_reg & 0x10) | (last_reg + 1) % 32)) + || first_range) + { + /* a non-contiguous sequence */ + if (regno1 == 28 && !mode16 && (nanomips_opts.ase & ASE_xNMS) != 0) + /* enable GP special casing if possible */ + gp = true; + else if (regno1 == 28 && (nanomips_opts.ase & ASE_xNMS) == 0) + { + set_insn_error_ss (count, + "non-contiguous %s of $gp is not available " + "for nanoMIPS subset%s", + arg->insn->insn_mo->name, ""); + return false; + } + else if (regno1 == 28 && mode16) + { + set_insn_error_ss (count, + "non-contiguous %s of $gp is not available " + "for 16-bit instructions%s", + arg->insn->insn_mo->name, ""); + return false; + } + else if (first_range) + ; + else + { + if (regno1 == 30 && first_reg != 30) + set_insn_error (count, "$fp must be the first register in " + "the list"); + else if (regno1 == 31 && first_reg != 30 && first_reg != 31) + set_insn_error (count, "$ra must be the first register in " + "the list"); + else if (last_reg == 31 && regno1 != 16) + set_insn_error_ss (count + 1, "%s must be followed by %s", + nanomips_reg_names[32 + last_reg].name, + nanomips_reg_names[32 + 16].name); + else + set_insn_error_ss (regno1, + "register list not contiguous between " + "%s and %s", + nanomips_reg_names[32 + last_reg].name, + nanomips_reg_names[32 + regno1].name); + return false; + } + } + + last_reg = regno2; + + /* sequence */ + while (regno1++ <= regno2) + count += 1; + } + while (match_char (arg, ',')); + + /* too few or too many registers in list */ + if (count >= 16) + { + set_insn_error_si (count, + "%s can handle a maximum of 16 register, %d requested", + arg->insn->insn_mo->name, count); + return false; + } + + if (mode16 && first_reg < 30) + { + set_insn_error_ss (count + 1, + "first register for 16-bit %s must be $fp or $ra%s", + arg->insn->insn_mo->name, ""); + return false; + } + + if (count * (GPR_SIZE / 8) > arg->last_op_int) + as_warn ("frame too small for save/restore register list"); + + if (mode16) + opval = ((first_reg & 0x1) << 4) | count; + else + opval = ((first_reg << 6) | (count << 1) | gp); + + /* Finally build the instruction. */ + insn_insert_operand (arg->insn, operand, opval); + + return true; +} + +/* OP_NON_ZERO_REG matcher. */ + +static bool +match_non_zero_reg_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand) +{ + unsigned int regno; + + if (!match_reg (arg, OP_REG_GP, ®no)) + return false; + + if (regno == 0) + { + const unsigned long pinfo = arg->insn->insn_mo->pinfo; + unsigned int regtype; + const char *regstr[] = { "source", "target" }; + + if ((arg->opnum == 1 && (pinfo & INSN_WRITE_1) != 0) + || (arg->opnum == 2 && (pinfo & INSN_WRITE_2) != 0)) + regtype = 1; + else + regtype = 0; + + set_insn_error_ss (arg->argnum, _("the %s register must not be $0%s"), + regstr[regtype], ""); + return false; + } + + arg->last_regno = regno; + insn_insert_operand (arg->insn, operand, regno); + return true; +} + +/* OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG matcher. OTHER_REGNO is the + register that we need to match. */ + +static bool +match_tied_reg_operand (struct nanomips_arg_info *arg, + unsigned int other_regno) +{ + unsigned int regno; + + return match_reg (arg, OP_REG_GP, ®no) && regno == other_regno; +} + +/* OP_BASE_CHECK_OFFSET matcher. */ + +static bool +match_base_checked_offset_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand_base) +{ + unsigned int regno; + const struct nanomips_base_check_offset_operand *operand + = (const struct nanomips_base_check_offset_operand *) operand_base; + + if (!match_reg (arg, OP_REG_GP, ®no)) + return false; + + if ((operand->const_ok + && (offset_expr.X_op == O_constant || offset_expr.X_op == O_absent)) + || (operand->expr_ok + && (offset_expr.X_op == O_symbol || offset_expr.X_op == O_absent)) + || (regno == 0) + || lo_reloc_p (offset_reloc[0])) + { + arg->last_regno = regno; + insn_insert_operand (arg->insn, operand_base, regno); + return true; + } + return false; +} + +/* Read a floating-point constant from S for LI.S or LI.D. LENGTH is + the length of the value in bytes (4 for float, 8 for double) and + USING_GPRS says whether the destination is a GPR rather than an FPR. + + Return the constant in IMM and OFFSET as follows: + + - If the constant should be loaded via memory, set IMM to O_absent and + OFFSET to the memory address. + + - Otherwise, if the constant should be loaded into two 32-bit registers, + set IMM to the O_constant to load into the high register and OFFSET + to the corresponding value for the low register. + + - Otherwise, set IMM to the full O_constant and set OFFSET to O_absent. + + These constants only appear as the last operand in an instruction, + and every instruction that accepts them in any variant accepts them + in all variants. This means we don't have to worry about backing out + any changes if the instruction does not match. We just match + unconditionally and report an error if the constant is invalid. */ + +static bool +match_float_constant (struct nanomips_arg_info *arg, expressionS *imm, + expressionS *offset, unsigned int length, + bool using_gprs) +{ + char *p; + segT seg; + subsegT subseg; + unsigned char *data; + + /* Where the constant is placed is based on how the nanoMIPS assembler + does things: + + length == 4 && using_gprs -- immediate value only + length == 8 && using_gprs -- .rdata or immediate value + length <= -Gnum -- .sdata + length >= -Gnum -- .rodata + + The .sdata sections are only used if permitted by the -G argument. */ + if (arg->token->type != OT_FLOAT) + { + set_insn_error (arg->argnum, _("floating-point expression required")); + return false; + } + + gas_assert (arg->token->u.flt.length == (int) length); + data = arg->token->u.flt.data; + ++arg->token; + + /* Handle 32-bit constants -- immediate value is best. */ + if (length == 4 + && !nanomips_disable_float_construction) + { + imm->X_op = O_constant; + if (!target_big_endian) + imm->X_add_number = bfd_getl32 (data); + else + imm->X_add_number = bfd_getb32 (data); + offset->X_op = O_absent; + return true; + } + + /* Handle 64-bit constants for which an immediate value is best. */ + if (length == 8 + && !nanomips_disable_float_construction + && ((data[0] == 0 && data[1] == 0) + || (data[2] == 0 && data[3] == 0) + || ((nanomips_opts.ase & ASE_xNMS) != 0 && using_gprs)) + && ((data[4] == 0 && data[5] == 0) + || (data[6] == 0 && data[7] == 0) + || ((nanomips_opts.ase & ASE_xNMS) != 0 && using_gprs))) + { + /* The value is simple enough to load with a couple of instructions. + If using 32-bit registers, set IMM to the high order 32 bits and + OFFSET to the low order 32 bits. Otherwise, set IMM to the entire + 64 bit constant. */ + if (GPR_SIZE == 32) + { + imm->X_op = O_constant; + offset->X_op = O_constant; + if (!target_big_endian) + { + imm->X_add_number = bfd_getl32 (data + 4); + offset->X_add_number = bfd_getl32 (data); + } + else + { + imm->X_add_number = bfd_getb32 (data); + offset->X_add_number = bfd_getb32 (data + 4); + } + if (offset->X_add_number == 0) + offset->X_op = O_absent; + } + else + { + imm->X_op = O_constant; + if (!target_big_endian) + imm->X_add_number = bfd_getl64 (data); + else + imm->X_add_number = bfd_getb64 (data); + offset->X_op = O_absent; + } + return true; + } + + /* Switch to the right section. */ + seg = now_seg; + subseg = now_subseg; + + if (!using_gprs && g_switch_value >= length && nanomips_opts.pic == NO_PIC) + s_change_sec ('s'); + else + s_change_sec ('r'); + + if (seg == now_seg) + as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name); + + /* Set the argument to the current address in the section. */ + imm->X_op = O_absent; + offset->X_op = O_symbol; + offset->X_add_symbol = symbol_temp_new_now (); + offset->X_add_number = 0; + + /* Put the floating point number into the section. */ + p = frag_more (length); + memcpy (p, data, length); + + /* Switch back to the original section. */ + subseg_set (seg, subseg); + return true; +} + +/* Copy bits from one part of an instruction to another part. + Source bits are specified by size & lsb. Destination bits + are specified by size_top and lsb_top. */ +static bool +match_copy_bits (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand) +{ + const struct nanomips_operand op_src = { + OP_INT, operand->size, operand->lsb, 0, 0 + }; + const struct nanomips_operand op_dest = { + OP_INT, operand->size_top, operand->lsb_top, 0, 0 + }; + unsigned int uval; + + uval = nanomips_extract_operand (&op_src, arg->insn->insn_opcode); + insn_insert_operand (arg->insn, &op_dest, uval); + return true; +} + +/* Select value for a named COP0 register. */ +static bool +match_cp0_select (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand) +{ + offsetT uval; + + /* Expect an immediate select value between 0 & 31. */ + if (!match_const_int (arg, &uval) + || uval < 0 + || uval >= (1 << NANOMIPSOP_SH_CP0SEL)) + return false; + + /* Check if this select value is allowed by the saved mask of the last + seen CP0 register. */ + if (((1 << uval) & arg->select_mask) == 0) + return false; + + insn_insert_operand (arg->insn, operand, uval); + return true; +} + +/* S is the text seen for ARG. Match it against OPERAND. Return the end + of the argument text if the match is successful, otherwise return null. */ + +static bool +match_operand (struct nanomips_arg_info *arg, + const struct nanomips_operand *operand) +{ + switch (operand->type) + { + case OP_INT: + return match_int_operand (arg, operand); + + case OP_MAPPED_INT: + return match_mapped_int_operand (arg, operand); + + case OP_MSB: + return match_msb_operand (arg, operand); + + case OP_REG: + case OP_OPTIONAL_REG: + return match_reg_operand (arg, operand); + + case OP_REG_PAIR: + return match_reg_pair_operand (arg, operand); + + case OP_PCREL: + return match_pcrel_operand (arg); + + case OP_SAVE_RESTORE_LIST: + return match_save_restore_list_operand (arg, operand); + + case OP_SAVE_RESTORE_FP_LIST: + return match_save_restore_fp_list_operand (arg, operand); + + case OP_REPEAT_DEST_REG: + return match_tied_reg_operand (arg, arg->dest_regno); + + case OP_REPEAT_PREV_REG: + return match_tied_reg_operand (arg, arg->last_regno); + + case OP_CHECK_PREV: + return match_check_prev_operand (arg, operand); + + case OP_NON_ZERO_REG: + return match_non_zero_reg_operand (arg, operand); + + case OP_NON_ZERO_PCREL_S1: + return match_non_zero_pcrel_operand (arg, operand); + + case OP_HI20_PCREL: + return match_hi20_pcrel_operand (arg); + + case OP_HI20_INT: + return match_hi20_int_operand (arg, operand); + + case OP_HI20_SCALE: + return match_hi20_scaled_operand (arg); + + case OP_MAPPED_CHECK_PREV: + return match_mapped_check_prev_operand (arg, operand); + + case OP_UINT_WORD: + case OP_INT_WORD: + return match_int_word (arg, operand); + + case OP_PC_WORD: + return match_pcrel_word (arg, operand); + + case OP_GPREL_WORD: + return match_gprel_word (arg, operand); + + case OP_DONT_CARE: + return false; + + case OP_NEG_INT: + return match_negative_int_operand (arg, operand); + + case OP_IMM_INT: + return match_imm_int_operand (arg, operand); + + case OP_IMM_WORD: + return match_imm_word (arg, operand); + + case OP_BASE_CHECK_OFFSET: + return match_base_checked_offset_operand (arg, operand); + + case OP_COPY_BITS: + return match_copy_bits (arg, operand); + + case OP_CP0SEL: + return match_cp0_select (arg, operand); + + default: + abort (); + } +} + +#define INSN_ERET 0x42000018 +#define INSN_DERET 0x4200001f +#define INSN_DMULT 0x1c +#define INSN_DMULTU 0x1d + +#define BASE_REG_EQ(INSN1, INSN2) \ + ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ + == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) + +/* For nanoMIPS macros, we need to generate a local number label + as the target of branches. */ +#define NANOMIPS_LABEL_CHAR '\037' +static unsigned long nanomips_target_label; +static char nanomips_target_name[32]; + +static char * +nanomips_label_name (void) +{ + char *p = nanomips_target_name; + char symbol_name_temporary[24]; + unsigned long l; + int i; + + if (*p) + return p; + + i = 0; + l = nanomips_target_label; +#ifdef LOCAL_LABEL_PREFIX + *p++ = LOCAL_LABEL_PREFIX; +#endif + *p++ = 'L'; + *p++ = NANOMIPS_LABEL_CHAR; + do + { + symbol_name_temporary[i++] = l % 10 + '0'; + l /= 10; + } + while (l != 0); + while (i > 0) + *p++ = symbol_name_temporary[--i]; + *p = '\0'; + + return nanomips_target_name; +} + +static void +nanomips_label_expr (expressionS *label_expr) +{ + label_expr->X_op = O_symbol; + label_expr->X_add_symbol = symbol_find_or_make (nanomips_label_name ()); + label_expr->X_add_number = 0; +} + +static void +nanomips_label_inc (void) +{ + nanomips_target_label++; + *nanomips_target_name = '\0'; +} + +static void +nanomips_add_label (void) +{ + colon (nanomips_label_name ()); + nanomips_label_inc (); +} + +/* If assembling nanoMIPS code, then return the nanoMIPS + reloc corresponding to the requested one if any. Otherwise + return the reloc unchanged. +*/ + +static bfd_reloc_code_real_type +nanomips_map_reloc (bfd_reloc_code_real_type reloc) +{ + static const bfd_reloc_code_real_type relocs[][2] = { + /* Keep sorted incrementally by the left-hand key. */ + {BFD_RELOC_GPREL16, BFD_RELOC_NANOMIPS_GPREL18}, + {BFD_RELOC_HI16, BFD_RELOC_NANOMIPS_HI20}, + {BFD_RELOC_HI16_S, BFD_RELOC_NANOMIPS_HI20}, + {BFD_RELOC_LO16, BFD_RELOC_NANOMIPS_LO12}, + }; + bfd_reloc_code_real_type r; + size_t i; + + for (i = 0; i < ARRAY_SIZE (relocs); i++) + { + r = relocs[i][0]; + if (r > reloc) + return reloc; + if (r == reloc) + return relocs[i][1]; + } + return reloc; +} + +/* Remove first call from call-list and decrement numcalls. */ +static void +stublist_pop_call (struct balc_stub *stub) +{ + struct call_list *ptr = stub->first_call; + + if (ptr) + { + if (stub->last_call == ptr) + stub->last_call = NULL; + + stub->first_call = ptr->next; + xfree (ptr); + stub->numcalls -= 1; + } + return; +} + +/* Remove all calls greater than or equal to CALLSITE + from call-list and decrement numcalls. LIST is guaranteed + to have at least 2 elements when this is called. */ +static void +stublist_trunc_calls (struct balc_stub *stub, bfd_vma callsite) +{ + struct call_list *list = stub->first_call; + + while (list && list->next) + { + if (list->next->callsite < callsite) + list = list->next; + else + break; + } + + if (list) + { + stub->last_call = list; + list = list->next; + stub->last_call->next = NULL; + while (list) + { + struct call_list *ptr = list; + list = list->next; + stub->numcalls -= 1; + xfree (ptr); + } + } + return; +} + +/* Add call to call-list. */ +static void +stublist_append_call (struct balc_stub *stub, bfd_vma callsite) +{ + struct call_list *next + = (struct call_list *) xmalloc (sizeof (struct call_list)); + memset (next, 0, sizeof (struct call_list)); + next->callsite = callsite; + + if (stub->first_call == NULL) + stub->first_call = stub->last_call = next; + else if (callsite < stub->first_call->callsite) + { + next->next = stub->first_call; + stub->first_call = next; + } + else if (callsite > stub->last_call->callsite) + { + stub->last_call->next = next; + stub->last_call = next; + } + else + { + struct call_list *list = stub->first_call; + + while (list && list->next) + { + if (list->next->callsite < callsite) + list = list->next; + else + break; + } + + next->next = list->next; + list->next = next; + } + + stub->numcalls += 1; + return; +} + +static void +stublist_merge_forward_calls (struct balc_stub *dest, struct balc_stub *src) +{ + src->last_call->next = dest->first_call; + dest->first_call = src->first_call; + if (dest->last_call == NULL) + dest->last_call = dest->first_call; + dest->numcalls += src->numcalls; +} + +static void +stublist_merge_backward_calls (struct balc_stub *dest, struct balc_stub *src) +{ + dest->last_call->next = src->first_call; + dest->last_call = src->last_call; + dest->numcalls += src->numcalls; +} + +/* FIXME: Using a hash-table as a stubtable for now. We ideally want + these to be sorted on first_offset, so a different data structure + is required to get the best possible results. */ +#define stubtable_find str_hash_find +#define stubtable_create str_htab_create +#define stubtable_insert str_hash_insert +#define stubtable_delete str_hash_delete +#define stubtable_traverse htab_traverse + +static bool +balc_in_stub_range (const bfd_vma callsite, const stub_group *stubg) +{ + fragS *fragp; + bfd_vma minaddr; + + if (stubg == NULL + || stubg->fragp == NULL + || stubg->fragp->fr_address + stubg->fragp->fr_fix == 0) + return false; + + fragp = stubg->fragp; + + /* 10-bit left shifted +ve offset taken from NextPC + gives a range of 1024 from current call-site. */ + if (fragp->fr_address + fragp->fr_fix >= 1024) + minaddr = (fragp->fr_address + fragp->fr_fix - 1024); + else + minaddr = 0; + + /* Only the lowest address of the stub needs to be reachable. */ + if (stubg->next_offset != 0) + minaddr += (stubg->next_offset - 4); + + /* 10-bit left shifted -ve offset taken from NextPC + gives a range of 1022 from the current call-site. */ + if (callsite > (fragp->fr_address + fragp->fr_fix + 1022) + || callsite < minaddr) + return false; + + return true; +} + +static bool +balc_in_stub_group (const char *func, const bfd_vma callsite, + const stub_group *stubg, struct balc_stub **stub) +{ + gas_assert (func != NULL && stubg != NULL); + + if (!balc_in_stub_range (callsite, stubg) || (stubg->stubtable == NULL)) + return false; + + *stub = stubtable_find (stubg->stubtable, func); + return (*stub != NULL); +} + +static bool +balc_add_stub (symbolS *sym, stub_group *stubg) +{ + struct balc_stub *stub = NULL; + const char *func = S_GET_NAME (sym); + + gas_assert (func != NULL && stubg != NULL); + + if (!stubg->stubtable) + stubg->stubtable = stubtable_create (); + + stub = (struct balc_stub *) stubtable_find (stubg->stubtable, func); + + if (stub == NULL) + { + stub = (struct balc_stub *) xmalloc (sizeof (struct balc_stub)); + + if (stub == NULL) + return false; + + memset (stub, 0, sizeof (struct balc_stub)); + stub->sym = sym; + } + return true; +} + +/* Consolidate this stub with a preceding or succeeding stub if all + calls to this stub can reach the alternative just as well. */ +static bool +balc_merge_stub (const char *func, stub_group *stubg, + struct balc_stub **stub_ptr_ptr) +{ + stub_group *next = stubg->next; + stub_group *prev = stubg->prev; + struct balc_stub *prevstub = NULL; + struct balc_stub *nextstub = NULL; + struct balc_stub *stub = *stub_ptr_ptr; + bfd_vma callsite = stub->first_call->callsite; + + /* Correction to account for the fact that the 4-byte stub will also move + forward from its current position to end of target stub-group. */ + if (stub->fragp && RELAX_MD_KEEPSTUB (stub->fragp->fr_subtype)) + callsite += 4; + + /* Any forward stub that we find can be the target for merge. */ + while (next && next->stubtable && balc_in_stub_range (callsite, next)) + { + nextstub = (struct balc_stub *) stubtable_find (next->stubtable, func); + + if (nextstub) + break; + next = next->next; + } + + callsite = stub->last_call->callsite; + + /* Correction to account for the fact that the 4-byte stub will also move + backward from its current position to end of target stub-group. */ + if (stub->fragp && RELAX_MD_KEEPSTUB (stub->fragp->fr_subtype) + && callsite > stub->fragp->fr_address) + callsite -= 4; + + /* A previous stub can be a target only if it already has calls. */ + while (prev && prev->stubtable && balc_in_stub_range (callsite, prev)) + { + struct balc_stub *pstub + = (struct balc_stub *) stubtable_find (prev->stubtable, func); + + if (pstub && pstub->numcalls) + { + prevstub = pstub; + break; + } + prev = prev->prev; + } + + /* If we have 2 candidates, then we favour the preceding one only if it + already has more calls than the succeeding one. */ + if (prevstub) + { + if (nextstub && (nextstub->numcalls >= prevstub->numcalls)) + { + stublist_merge_forward_calls (nextstub, stub); + *stub_ptr_ptr = nextstub; + } + else + { + stublist_merge_backward_calls (prevstub, stub); + *stub_ptr_ptr = prevstub; + } + stubtable_delete (stubg->stubtable, func); + return true; + } + else if (nextstub) + { + stublist_merge_forward_calls (nextstub, stub); + *stub_ptr_ptr = nextstub; + stubtable_delete (stubg->stubtable, func); + return true; + } + else + return false; +} + +/* hash traverse - add stub for each function to current stub-group. */ +static void +balc_add_traverse (const char *key, void *value) +{ + struct balc_stub *stub = (struct balc_stub *) value; + + if (stub->fragp != NULL) + { + symbolS *sym = stub->fragp->fr_symbol; + gas_assert (strcmp (key, S_GET_NAME (sym)) == 0); + balc_add_stub (sym, stubg_now); + } + return; +} + +/* hash traverse - create a frag stub for each function. */ +static void +balc_frag_traverse (const char *key ATTRIBUTE_UNUSED, void *value) +{ + struct balc_stub *stub = (struct balc_stub *) value; + symbolS *l; + fragS *old_frag = stub->fragp; + + if (old_frag) + { + old_frag->fr_subtype + = RELAX_MD_CLEAR_KEEPSTUB (old_frag->fr_subtype); + stub->sym = old_frag->fr_symbol; + } + + frag_grow (4); + l = symbol_new (nanomips_label_name (), now_seg, frag_now, frag_now->fr_fix); + nanomips_label_inc (); + stub->fragp = frag_now; + add_relaxed_insn (&nanomips_bc32_insn, 4, 0, + RELAX_MD_ENCODE (RT_BALC_STUB, 0, 1), + stub->sym, 0); + stub->sym = l; + if (stub->numcalls >= 3) + stub->fragp->fr_subtype + = RELAX_MD_MARK_KEEPSTUB (stub->fragp->fr_subtype); + if (stubg_now->fragp == NULL) + stubg_now->fragp = stub->fragp; + + return; +} + +/* Find an elligible stub for a function call. */ +static bool +balc_find_stub_inrange (const char *func, const bfd_vma callsite, + stub_group *stubg, struct balc_stub **stub) +{ + stub_group *plink; + stub_group *nlink; + struct balc_stub *pstub = NULL; + struct balc_stub *nstub = NULL; + + /* Search backwards within range. */ + plink = stubg->prev; + while (plink != NULL + && !balc_in_stub_group (func, callsite, plink, &pstub) + && balc_in_stub_range (callsite, plink)) + plink = plink->prev; + + /* Search forwards within range. */ + nlink = stubg; + while (nlink != NULL + && !balc_in_stub_group (func, callsite, nlink, &nstub) + && balc_in_stub_range (callsite, nlink)) + nlink = nlink->next; + + /* When 2 possible stub candidates are available, choose the preceeding one + only if it already has more associated calls than the suceeding one. */ + if (pstub) + { + if (nstub && (pstub->numcalls <= nstub->numcalls)) + *stub = nstub; + else + *stub = pstub; + + return true; + } + else if (nstub) + { + *stub = nstub; + return true; + } + return false; +} + +/* Find closest elligible stub for this function call. */ +static bool +balc_get_stub_for_symbol (const char *func, const bfd_vma callsite, + stub_group *stubg, symbolS **symbol) +{ + stub_group *plink = stubg->prev; + stub_group *nlink = stubg; + struct balc_stub *stub; + + while (plink != NULL || nlink != NULL) + { + if (((nlink && balc_in_stub_group (func, callsite, nlink, &stub)) + || (plink && balc_in_stub_group (func, callsite, plink, &stub))) + && stub->numcalls >= 3) + { + *symbol = stub->sym; + return true; + } + + if (plink != NULL) + plink = plink->prev; + if (nlink != NULL) + nlink = nlink->next; + } + return false; +} + +/* Initialize new stub-group at entry to a function. */ +static void +stubgroup_new (asection *sec) +{ + stub_group *stubg = NULL; + + /* Create the master table. */ + if (balc_stubgroup_table == NULL) + balc_stubgroup_table = str_htab_create (); + + if (stubg_now) + { + if (stubg_now->seg != sec) + { + /* Change of sections, find the end of correct list. */ + stubg_now = str_hash_find (balc_stubgroup_table, sec->name); + while (stubg_now && stubg_now->next) + stubg_now = stubg_now->next; + } + + /* Re-cycle the previous stubgroup, if unused. */ + if (stubg_now && stubg_now->stubtable == NULL) + stubg = stubg_now; + } + + if (stubg == NULL) + { + stubg = (stub_group *) xmalloc (sizeof (stub_group)); + memset (stubg, 0, sizeof (stub_group)); + stubg->seg = sec; + } + + if (stubg_now == NULL) + /* First stubgroup for this section, add to master table. */ + str_hash_insert (balc_stubgroup_table, sec->name, stubg, 0); + else if (stubg_now != stubg) + { + /* Link in with existing stub-groups for this section */ + stubg_now->next = stubg; + stubg->prev = stubg_now; + } + stubg_now = stubg; +} + +/* Finalize the stub-group at the end of each function. */ +static void +stubgroup_wane (void) +{ + frag_wane (frag_now); + frag_new (0); + /* Carry forward stubs for all previous function calls within + this section. */ + if (stubg_now != NULL + && stubg_now->prev != NULL + && stubg_now->prev->stubtable != NULL + && stubg_now->seg == now_seg) + stubtable_traverse (stubg_now->prev->stubtable, balc_add_traverse, 0); + + /* Create a frag for each stub - this must be done now and for *all* + possible called functions, because frags can not be inserted in a + position retroactively. This is also the reason why we include all + previously called functions within the section - to allow for forward + consolidation of stubs, knowing that many of these stubs will eventually + not be instantiated, due to either paucity of calls or consolidation. */ + if (stubg_now->stubtable && stubg_now->seg == now_seg) + stubtable_traverse (stubg_now->stubtable, balc_frag_traverse, 0); +} + +/* Check whether the last encountered label carried an + explicit relocation. */ + +static bool +explicit_reloc_label_p (fragS *fragP, asection *sec) +{ + if (reloc_list != NULL + && symbol_get_frag (reloc_list->u.a.offset_sym) == fragP) + { + segment_info_type *si = seg_info (sec); + + struct insn_label_list *iter = si->label_list; + while (iter != NULL) + { + if (iter->label == reloc_list->u.a.offset_sym) + return true; + iter = iter->next; + } + } + return false; +} + +/* Check whether the last encountered label carried an explicit + relocation of the specified type. */ + +static bool +explicit_reloc_type_p (fragS *fragP, asection *sec, + unsigned rtype) +{ + return (explicit_reloc_label_p (fragP, sec) + && reloc_list->u.a.howto->type == rtype); +} + +/* Output an instruction. IP is the instruction information. + ADDRESS_EXPR is an operand of the instruction to be used with + RELOC_TYPE. EXPANSIONP is true if the instruction is part of + a macro expansion. */ + +static void +append_insn (struct nanomips_cl_insn *ip, expressionS *address_expr, + bfd_reloc_code_real_type *reloc_type, + bool expansionp ATTRIBUTE_UNUSED) +{ + unsigned long pinfo; + + pinfo = ip->insn_mo->pinfo; + + if (address_expr == NULL) + ip->complete_p = 1; + else if (reloc_type[0] <= BFD_RELOC_UNUSED + && reloc_type[1] == BFD_RELOC_UNUSED + && reloc_type[2] == BFD_RELOC_UNUSED + && address_expr->X_op == O_constant) + { + switch (*reloc_type) + { + case BFD_RELOC_NANOMIPS_HI20: + case BFD_RELOC_NANOMIPS_GPREL_HI20: + ip->insn_opcode |= ((((address_expr->X_add_number >> 12) & 0x1ff) + << 12) + | (((address_expr->X_add_number >> 21) & 0x3ff) + << 2) + | ((address_expr->X_add_number >> 31) & 1)); + ip->complete_p = 1; + break; + + case BFD_RELOC_NANOMIPS_LO12: + case BFD_RELOC_NANOMIPS_GOT_LO12: + ip->insn_opcode |= address_expr->X_add_number & 0xfff; + ip->complete_p = 1; + break; + + case BFD_RELOC_NANOMIPS_IMM16: + ip->insn_opcode |= address_expr->X_add_number & 0xffff; + ip->complete_p = 1; + break; + + case BFD_RELOC_NANOMIPS_NEG12: + ip->insn_opcode |= (-address_expr->X_add_number) & 0xfff; + ip->complete_p = 1; + break; + + case BFD_RELOC_NANOMIPS_I32: + case BFD_RELOC_NANOMIPS_GPREL_I32: + ip->insn_opcode_ext = (((address_expr->X_add_number >> 16) & 0xffff) + | (address_expr->X_add_number << 16)); + ip->complete_p = 1; + break; + + case BFD_RELOC_NANOMIPS_GOT_CALL: + ip->complete_p = 1; + case BFD_RELOC_NANOMIPS_PC_I32: + case BFD_RELOC_NANOMIPS_GOTPC_I32: + break; + + case BFD_RELOC_NANOMIPS_SIGNED_9: + ip->insn_opcode |= ((address_expr->X_add_number & 0xff) + | ((address_expr->X_add_number & 0x100) << 7)); + ip->complete_p = 1; + break; + + default: + break; + } + } + + dwarf2_emit_insn (0); + + if (address_expr + && *reloc_type >= BFD_RELOC_UNUSED + RT_BRANCH_UCND + && !forced_insn_format) + { + int type = *reloc_type - BFD_RELOC_UNUSED; + int al = pinfo & INSN_WRITE_GPR_31; + + gas_assert (address_expr != NULL); + gas_assert (!nanomips_relax.sequence); + + add_relaxed_insn (ip, 4, 2, + RELAX_MD_ENCODE (type, al, 0), + address_expr->X_add_symbol, + address_expr->X_add_number); + /* Track this call for balcp-to-stub relaxation. */ + if (!nanomips_opts.no_balc_stubs + && stubg_now != NULL + && type == RT_BRANCH_UCND + && (ip->insn_mo->pinfo & INSN_WRITE_GPR_31) != 0) + balc_add_stub (address_expr->X_add_symbol, stubg_now); + + *reloc_type = BFD_RELOC_UNUSED; + } + else if (address_expr + && *reloc_type == BFD_RELOC_UNUSED + RT_ADDIU + && address_expr->X_op == O_subtract + && !forced_insn_format) + { + int type = RT_ADDIU; + bool fixed = (nanomips_opts.insn32 || (forced_insn_length == 4)); + + gas_assert (address_expr != NULL); + gas_assert (!nanomips_relax.sequence); + add_relaxed_insn (ip, 6, 4, + RELAX_MD_ENCODE (type, 0, fixed), + make_expr_symbol (address_expr), 0); + *reloc_type = BFD_RELOC_UNUSED; + } + else if (address_expr + && *reloc_type >= BFD_RELOC_UNUSED + RT_BRANCH_UCND + && forced_insn_format) + { + const bfd_reloc_code_real_type rtype[] = + { BFD_RELOC_NANOMIPS_10_PCREL_S1, + BFD_RELOC_NANOMIPS_7_PCREL_S1, + BFD_RELOC_NANOMIPS_4_PCREL_S1 }; + *reloc_type = rtype[*reloc_type - BFD_RELOC_UNUSED - RT_BRANCH_UCND]; + add_fixed_insn (ip); + } + else + { + if (nanomips_relax.sequence) + { + /* If we've reached the end of this frag, turn it into a variant + frag and record the information for the instructions we've + written so far. */ + if (frag_room () < insn_length (ip->insn_mo)) + relax_close_frag (); + nanomips_relax.sizes[nanomips_relax.sequence - 1] += + insn_length (ip->insn_mo); + } + + if (nanomips_relax.sequence != 2) + { + if (nanomips_macro_warning.first_insn_sizes[0] == 0) + nanomips_macro_warning.first_insn_sizes[0] = + insn_length (ip->insn_mo); + nanomips_macro_warning.sizes[0] += insn_length (ip->insn_mo); + nanomips_macro_warning.insns[0]++; + } + if (nanomips_relax.sequence != 1) + { + if (nanomips_macro_warning.first_insn_sizes[1] == 0) + nanomips_macro_warning.first_insn_sizes[1] = + insn_length (ip->insn_mo); + nanomips_macro_warning.sizes[1] += insn_length (ip->insn_mo); + nanomips_macro_warning.insns[1]++; + } + add_fixed_insn (ip); + } + + if (!ip->complete_p && *reloc_type < BFD_RELOC_UNUSED) + { + bfd_reloc_code_real_type final_type[3]; + reloc_howto_type *howto0; + reloc_howto_type *howto; + int i; + unsigned where; + + /* Perform any necessary conversion to nanoMIPS relocations + and find out how many relocations there actually are. */ + for (i = 0; i < 3 && reloc_type[i] != BFD_RELOC_UNUSED; i++) + final_type[i] = nanomips_map_reloc (reloc_type[i]); + + /* In a compound relocation, it is the final (outermost) + operator that determines the relocated field. */ + howto = howto0 = bfd_reloc_type_lookup (stdoutput, final_type[i - 1]); + if (!howto) + abort (); + + if (i > 1) + howto0 = bfd_reloc_type_lookup (stdoutput, final_type[0]); + + where = ip->where; + /* For 48-bit nanoMIPS instructions, we want the relocation + to be on the lower 32-bits of the instruction. */ + if (nanomips_48bit_reloc_p (final_type[0])) + where = ip->where + 2; + + ip->fixp[0] = fix_new_exp (ip->frag, where, + bfd_get_reloc_size (howto), + address_expr, + howto0 && howto0->pc_relative, + final_type[0]); + /* Remember the first fix-up in this frag. */ + if (ip->frag->tc_frag_data == NULL) + ip->frag->tc_frag_data = ip->fixp[0]; + + if (nanomips_relax.sequence) + { + if (nanomips_relax.first_fixup == 0) + nanomips_relax.first_fixup = ip->fixp[0]; + } + + /* Add fixups for the second and third relocations, if given. + Note that the ABI allows the second relocation to be + against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the + moment we only use RSS_UNDEF, but we could add support + for the others if it ever becomes necessary. */ + for (i = 1; i < 3; i++) + if (reloc_type[i] != BFD_RELOC_UNUSED) + { + ip->fixp[i] = fix_new (ip->frag, where, + ip->fixp[0]->fx_size, NULL, 0, + false, final_type[i]); + + /* Use fx_tcbit to mark compound relocs. */ + ip->fixp[0]->fx_tcbit = 1; + ip->fixp[i]->fx_tcbit = 1; + } + + if (nanomips_linkrelax_p && (insn_length (ip->insn_mo) != 6)) + { + if (forced_insn_format) + fix_new (ip->frag, ip->where, 0, &abs_symbol, 0, false, + BFD_RELOC_NANOMIPS_FIXED); + else if (forced_insn_length > 0) + fix_new (ip->frag, ip->where, 0, &abs_symbol, 0, false, + (forced_insn_length == 2 ? BFD_RELOC_NANOMIPS_INSN16 + : BFD_RELOC_NANOMIPS_INSN32)); + } + } + + install_insn (ip); + insert_into_history (ip); + + /* If we have just completed an unconditional branch, clear the history. */ + if ((compact_branch_p (&history) && uncond_branch_p (&history)) + && !(history.insn_mo->pinfo2 & INSN2_CONVERTED_TO_COMPACT)) + nanomips_flush_pending_output (); + + /* We just output an insn, so the next one doesn't have a label. */ + nanomips_clear_insn_labels (); +} + +/* Forget that there was any previous instruction or label. + When BRANCH is true, the branch history is also flushed. */ + +void +nanomips_flush_pending_output (void) +{ + prev_nop_frag = NULL; + insert_into_history (NOP_INSN); + nanomips_clear_insn_labels (); +} + +/* Start a (possibly nested) noreorder block. */ + +static void +start_noreorder (void) +{ + nanomips_opts.noreorder++; +} + +/* End a nested noreorder block. */ + +static void +end_noreorder (void) +{ + nanomips_opts.noreorder--; +} + +/* Sign-extend 32-bit mode constants that have bit 31 set and all + higher bits unset. */ + +static void +normalize_constant_expr (expressionS *ex) +{ + if (ex->X_op == O_constant && IS_ZEXT_32BIT_NUM (ex->X_add_number)) + ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) + - 0x80000000); +} + +/* Sign-extend 32-bit mode address offsets that have bit 31 set and + all higher bits unset. */ + +static void +normalize_address_expr (expressionS *ex) +{ + if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES) + || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS)) + && IS_ZEXT_32BIT_NUM (ex->X_add_number)) + ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) + - 0x80000000); +} + +struct gprel_insn_match +{ + /* Instruction. */ + const char *str; + /* Arch word size 32/64 if it matters, else 0. */ + int gpwidth; + /* Relocation. */ + bfd_reloc_code_real_type reloc; +}; + +static const struct gprel_insn_match nanomips_gprel_map[] = { + {"lw[gp]", 0, BFD_RELOC_NANOMIPS_GPREL19_S2}, + {"sw[gp]", 0, BFD_RELOC_NANOMIPS_GPREL19_S2}, + {"lh[gp]", 0, BFD_RELOC_NANOMIPS_GPREL17_S1}, + {"lhu[gp]", 0, BFD_RELOC_NANOMIPS_GPREL17_S1}, + {"sh[gp]", 0, BFD_RELOC_NANOMIPS_GPREL17_S1}, + {"lb[gp]", 0, BFD_RELOC_NANOMIPS_GPREL18}, + {"lbu[gp]", 0, BFD_RELOC_NANOMIPS_GPREL18}, + {"sb[gp]", 0, BFD_RELOC_NANOMIPS_GPREL18}, + {"addiu.b", 0, BFD_RELOC_NANOMIPS_GPREL18}, + {"addiu[gp.b]", 0, BFD_RELOC_NANOMIPS_GPREL18}, + {"addiu.w", 0, BFD_RELOC_NANOMIPS_GPREL19_S2}, + {"addiu[gp.w]", 0, BFD_RELOC_NANOMIPS_GPREL19_S2}, + {"ldc1[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"sdc1[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"l.d[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"s.d[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"swc1[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"lwc1[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"s.s[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"l.s[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"lwu[gp]", 0, BFD_RELOC_NANOMIPS_GPREL16_S2}, + {"ld[gp]", 32, BFD_RELOC_NANOMIPS_GPREL19_S2}, + {"sd[gp]", 32, BFD_RELOC_NANOMIPS_GPREL19_S2}, + {"ld[gp]", 64, BFD_RELOC_NANOMIPS_GPREL18_S3}, + {"sd[gp]", 64, BFD_RELOC_NANOMIPS_GPREL18_S3}, +}; + +static bfd_reloc_code_real_type +gprel_for_insn (const struct nanomips_opcode *insn) +{ + unsigned int i; + + if (forced_insn_length == 2 + || (forced_insn_format && insn_length (insn) == 2)) + return BFD_RELOC_NANOMIPS_GPREL7_S2; + if (insn_length (insn) == 6) + return BFD_RELOC_NANOMIPS_GPREL_I32; + + for (i = 0; i < ARRAY_SIZE (nanomips_gprel_map); i++) + if (strncasecmp (insn->name, nanomips_gprel_map[i].str, + strlen (insn->name)) == 0 + && strcmp (insn->suffix, + nanomips_gprel_map[i].str + strlen (insn->name)) == 0) + { + if (nanomips_gprel_map[i].gpwidth + && nanomips_gprel_map[i].gpwidth != GPR_SIZE) + continue; + + return nanomips_gprel_map[i].reloc; + } + + return BFD_RELOC_UNUSED; +} + +static bfd_reloc_code_real_type +tlsrel_for_insn (const struct nanomips_opcode *insn, + bfd_reloc_code_real_type rtype) +{ + unsigned int i; + static const struct + { + bfd_reloc_code_real_type key; + bfd_reloc_code_real_type value; + } reloc_map[] = { + { BFD_RELOC_NANOMIPS_TLS_GD, BFD_RELOC_NANOMIPS_TLS_GD_I32 }, + { BFD_RELOC_NANOMIPS_TLS_LD, BFD_RELOC_NANOMIPS_TLS_LD_I32 }, + { BFD_RELOC_NANOMIPS_TLS_TPREL12, BFD_RELOC_NANOMIPS_TLS_TPREL_I32 }, + { BFD_RELOC_NANOMIPS_TLS_DTPREL12, BFD_RELOC_NANOMIPS_TLS_DTPREL_I32 } + }; + + if (insn_length (insn) == 6) + for (i = 0; i < ARRAY_SIZE (reloc_map); i++) + if (rtype == reloc_map[i].key) + return reloc_map[i].value; + + if (strncmp (insn->name, "addiu", 5) == 0 + || strncmp (insn->name, "li", 2) == 0) + { + if (rtype == BFD_RELOC_NANOMIPS_TLS_TPREL12) + return BFD_RELOC_NANOMIPS_TLS_TPREL16; + if (rtype == BFD_RELOC_NANOMIPS_TLS_DTPREL12) + return BFD_RELOC_NANOMIPS_TLS_DTPREL16; + } + return rtype; +} + +static bool +match_insn (struct nanomips_cl_insn *insn, + const struct nanomips_opcode *opcode, + struct nanomips_operand_token *tokens, + unsigned int opcode_extra, bool lax_match) +{ + const char *args; + struct nanomips_arg_info arg; + const struct nanomips_operand *operand; + char c; + + imm_expr.X_op = O_absent; + offset_expr.X_op = O_absent; + offset_reloc[0] = BFD_RELOC_UNUSED; + offset_reloc[1] = BFD_RELOC_UNUSED; + offset_reloc[2] = BFD_RELOC_UNUSED; + + create_insn (insn, opcode); + /* When no opcode suffix is specified, assume ".xyzw". */ + insn->insn_opcode |= opcode_extra; + memset (&arg, 0, sizeof (arg)); + arg.insn = insn; + arg.token = tokens; + arg.argnum = 1; + arg.last_regno = ILLEGAL_REG; + arg.dest_regno = ILLEGAL_REG; + arg.lax_match = lax_match; + arg.select_mask = 0; + + for (args = opcode->args;; ++args) + { + if (arg.token->type == OT_END) + { + /* Handle unary instructions in which only one operand is given. + The source is then the same as the destination. */ + if ((*args == ',') || (arg.opnum == 0 && *args != 0)) + { + operand = decode_nanomips_operand (args + (arg.opnum ? 1 : 0)); + if (operand && nanomips_optional_operand_p (operand)) + { + arg.token = tokens; + arg.argnum = 1; + continue; + } + /* These optional types appear only as the last operand. */ + else if (operand && (operand->type == OP_CP0SEL + || operand->type == OP_DONT_CARE)) + return true; + } + + /* Treat elided base registers as $0. */ + if (strcmp (args, "(b)") == 0 || strcmp (args, "(c)") == 0) + args += 3; + + if ((args[0] == '+' && args[1] == 'N') + || (args[0] == 'm' && args[1] == 'K')) + /* The register suffix is optional. */ + args += 2; + + /* Fail the match if there were too few operands. */ + if (*args) + return false; + + clear_insn_error (); + return true; + } + + /* Fail the match if the line has too many operands. */ + if (*args == 0) + return false; + + /* Handle characters that need to match exactly. */ + if (*args == '(' || *args == ')' || *args == ',') + { + if (match_char (&arg, *args)) + continue; + return false; + } + if (*args == '#') + { + ++args; + if (arg.token->type == OT_DOUBLE_CHAR && arg.token->u.ch == *args) + { + ++arg.token; + continue; + } + return false; + } + + /* Handle special macro operands. Work out the properties of + other operands. */ + arg.opnum += 1; + + switch (*args) + { + case 'I': + if (!match_const_int (&arg, &imm_expr.X_add_number)) + return false; + imm_expr.X_op = O_constant; + if (GPR_SIZE == 32) + normalize_constant_expr (&imm_expr); + continue; + + case 'A': + if (arg.token->type == OT_CHAR && arg.token->u.ch == '(') + { + /* Assume that the offset has been elided and that what + we saw was a base register. The match will fail later + if that assumption turns out to be wrong. */ + offset_expr.X_op = O_constant; + offset_expr.X_add_number = 0; + } + else + { + if (!match_expression (&arg, &offset_expr, offset_reloc)) + return false; + normalize_address_expr (&offset_expr); + } + continue; + + case 'F': + if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8, true)) + return false; + continue; + + case 'L': + if (!match_float_constant (&arg, &imm_expr, &offset_expr, 8, false)) + return false; + continue; + + case 'f': + if (!match_float_constant (&arg, &imm_expr, &offset_expr, 4, true)) + return false; + continue; + + case 'l': + if (!match_float_constant (&arg, &imm_expr, &offset_expr, 4, false)) + return false; + continue; + } + + operand = decode_nanomips_operand (args); + if (!operand) + abort (); + + if (operand->type == OP_PCREL + || operand->type == OP_NON_ZERO_PCREL_S1 + || operand->type == OP_HI20_PCREL + || operand->type == OP_INT_WORD + || operand->type == OP_UINT_WORD + || operand->type == OP_PC_WORD + || operand->type == OP_INT + || operand->type == OP_GPREL_WORD) + switch (*args) + { + case '+': + switch (args[1]) + { + case 'u': + *offset_reloc = BFD_RELOC_NANOMIPS_25_PCREL_S1; + break; + + case 'r': + *offset_reloc = BFD_RELOC_NANOMIPS_21_PCREL_S1; + break; + + case 'Q': + case 'R': + *offset_reloc = BFD_RELOC_NANOMIPS_I32; + break; + } + break; + + case 'a': + *offset_reloc = BFD_RELOC_NANOMIPS_25_PCREL_S1; + break; + + case 'p': + *offset_reloc = BFD_RELOC_NANOMIPS_14_PCREL_S1; + break; + + case '~': + *offset_reloc = BFD_RELOC_NANOMIPS_11_PCREL_S1; + break; + + case 'm': + c = args[1]; + switch (c) + { + case 'D': + *offset_reloc = (forced_insn_length + ? BFD_RELOC_NANOMIPS_10_PCREL_S1 + : BFD_RELOC_UNUSED + RT_BRANCH_UCND); + break; + case 'E': + *offset_reloc = (forced_insn_length + ? BFD_RELOC_NANOMIPS_7_PCREL_S1 + : BFD_RELOC_UNUSED + RT_BRANCH_CNDZ); + break; + case 'F': + *offset_reloc = (forced_insn_length + ? BFD_RELOC_NANOMIPS_4_PCREL_S1 + : BFD_RELOC_UNUSED + RT_BRANCH_CND); + break; + } + break; + } + + /* Skip prefixes. */ + if (*args == '+' || *args == 'm' || *args == '-' || *args == '`') + args++; + + if (nanomips_optional_operand_p (operand) + && args[1] == ',' + && (arg.token[0].type != OT_REG || arg.token[1].type == OT_END)) + { + /* Assume that the register has been elided and is the + same as the first operand. */ + arg.token = tokens; + arg.argnum = 1; + } + + if (operand->type == OP_COPY_BITS) + args++; + + if (!match_operand (&arg, operand)) + return false; + + if (*offset_reloc == BFD_RELOC_NANOMIPS_GPREL18) + *offset_reloc = gprel_for_insn (insn->insn_mo); + else if (flex_reloc_p (*offset_reloc)) + *offset_reloc = tlsrel_for_insn (insn->insn_mo, *offset_reloc); + } +} + +/* Record that the current instruction is invalid for the current ISA. */ + +static void +match_invalid_for_isa (void) +{ + set_insn_error_ss + (0, _("opcode not supported on this processor: %s (%s)"), + nanomips_cpu_info_from_arch (nanomips_opts.arch)->name, + nanomips_cpu_info_from_isa (nanomips_opts.isa, false)); +} + +static bool +match_insns (struct nanomips_cl_insn *insn, + const struct nanomips_opcode *first, + const struct nanomips_opcode *past, + struct nanomips_operand_token *tokens, + int opcode_extra, bool lax_match) +{ + const struct nanomips_opcode *opcode; + bool seen_valid_for_isa, seen_valid_for_size; + bool seen_valid_for_ase, seen_valid_for_fp; + + seen_valid_for_isa = false; + seen_valid_for_size = false; + seen_valid_for_ase = false; + seen_valid_for_fp = false; + opcode = first; + + /* Search for a match, ignoring alternatives that don't satisfy the + current ISA or forced_length. */ + do + { + gas_assert (strcmp (opcode->name, first->name) == 0); + if (!forced_insn_format || strcmp (opcode->suffix, first->suffix) == 0) + { + if (is_opcode_valid (opcode)) + { + seen_valid_for_isa = true; + if (is_size_valid (opcode)) + { + seen_valid_for_size = true; + if (match_insn (insn, opcode, tokens, opcode_extra, + lax_match)) + return true; + } + } + else + { + /* If instruction is not valid for current ISA, try to guess + why for better error reporting. */ + if (is_opcode_valid_def_ase (opcode)) + seen_valid_for_ase = true; + if (is_opcode_valid_for_fp (opcode)) + seen_valid_for_fp = true; + } + } + ++opcode; + } + while (opcode < past && strcmp (opcode->name, first->name) == 0); + + /* Handle the case where we didn't try to match an instruction because + all the alternatives were incompatible with the current ISA. */ + if (!seen_valid_for_isa) + { + match_invalid_for_isa (); + return true; + } + + /* Handle the case where we didn't try to match an instruction because + all the alternatives were of the wrong size. */ + if (!seen_valid_for_size) + { + if (nanomips_opts.insn32) + set_insn_error (0, _("opcode not supported in the `insn32' mode")); + else + set_insn_error_i + (0, _("unrecognized %d-bit version of nanoMIPS opcode"), + 8 * forced_insn_length); + return true; + } + return false; +} + +/* Set up global variables for the start of a new macro. */ + +static void +macro_start (void) +{ + memset (&nanomips_macro_warning.sizes, 0, + sizeof (nanomips_macro_warning.sizes)); + memset (&nanomips_macro_warning.first_insn_sizes, 0, + sizeof (nanomips_macro_warning.first_insn_sizes)); + memset (&nanomips_macro_warning.insns, 0, + sizeof (nanomips_macro_warning.insns)); + nanomips_macro_warning.first_frag = NULL; +} + +/* Finish up a macro. Emit warnings as appropriate. */ + +static void +macro_end (bool allow_expansion) +{ + /* Relaxation warning flags. */ + relax_substateT subtype = 0; + + /* Check instruction count requirements. */ + if (nanomips_macro_warning.insns[0] > 1 + || nanomips_macro_warning.insns[1] > 1) + { + if (nanomips_macro_warning.insns[1] > nanomips_macro_warning.insns[0]) + subtype |= RELAX_SECOND_LONGER; + if (nanomips_opts.nomacro) + subtype |= RELAX_NOMACRO; + } + + /* If both implementations are longer than 1 instruction, then emit the + warning now. */ + if (nanomips_macro_warning.insns[0] > 1 + && nanomips_macro_warning.insns[1] > 1) + { + if (nanomips_opts.nomacro) + { + if (allow_expansion) + as_warn (_("macro instruction expanded into multiple " + "instructions")); + else + as_bad (_("macro instruction expanded into multiple " + "instructions")); + } + + subtype &= ~RELAX_NOMACRO; + } + + /* If any flags still set, then one implementation might need a warning + and the other either will need one of a different kind or none at all. + Pass any remaining flags over to relaxation. */ + if (nanomips_macro_warning.first_frag != NULL) + nanomips_macro_warning.first_frag->fr_subtype |= subtype; +} + +static const char *const brk_fmt[2] = { "mK", "+J" }; +static const char *const addiu_fmt[2] = { "+t,r,j", "t,r,i" }; +static const char *const mfhl_fmt[2] = { "mj", "s" }; + +#define BRK_FMT (brk_fmt[nanomips_opts.insn32]) +#define COP12_FMT "E,+j(b)" +#define JALR_FMT "t,s" +#define LUI_FMT "t,u" +#define DLUI_FMT "mp,+Q" + +#define ADDRESS_ADD_FMT "d,v,t" +#define ADDRESS_ADDI32_FMT "mp,mt,+R" + +#define ADDIU_FMT (addiu_fmt[HAVE_32BIT_ADDRESSES? 0 : 1]) +#define ADDIUGP_FMT "t,ma,." +#define LWGP_FMT "t,.(ma)" +#define LDGP_FMT "t,.(ma)" +#define LL_SC_FMT "t,+p(b)" +#define LLD_SCD_FMT "t,+q(b)" +#define LLE_SCE_FMT "t,+p(b)" +#define LWU_FMT "t,o(b)" +#define MFHL_FMT (mfhl_fmt[nanomips_opts.insn32]) +#define SHFT_FMT "t,r,<" +#define TRAP_FMT "s,t,|" +#define ACLR_FMT "\\,+j(b)" +#define BCONDZ1_FMT "s,p" +#define BCONDZ2_FMT "t,p" +#define B_FMT "+u" +#define JAL_FMT "+u" +#define OP_IMM_FMT "t,r,i" +#define BITOP_IMM_FMT "t,r,g" +#define PREF_FMT "k,+j(b)" +#define BITW_FMT "d,v,t" +#define DIV_FMT "d,v,t" +#define MOVE_FMT "mb,mj" +#define ISA_OFFBITS 12 +#define ISA_ADD_OFFBITS (HAVE_32BIT_ADDRESSES ? 16 : 12) +#define ISA_SIGNED_OFFBITS 9 +#define ISA_MULTI_OFFBITS 9 +#define ISA_COP2_OFFBITS 9 +#define ISA_LLSC_OFFBITS 9 + +#define ISA_LLDSCD_OFFBITS 6 + +#define ISA_CACHE_OFFBITS ISA_LLSC_OFFBITS + +#define MAX_PIC_OFFSET 0x1fffc + +#define MIN_PIC_OFFSET 0 + +#define ISA_UNSIGNED_LDST_RELOC BFD_RELOC_NANOMIPS_LO12 +#define ISA_SIGNED_LDST_RELOC BFD_RELOC_NANOMIPS_SIGNED_9 + +#define ISA_SIGNED_LDST_FMT "t,+j(b)" +#define ISA_MULTI_LDST_FMT "t,+j(b),|" +#define ISA_UNSIGNED_LDST_FMT "t,o(b)" +#define ISA_UNSIGNED_COP1_FMT "T,o(b)" +#define ISA_SIGNED_COP1_FMT "T,+j(b)" + +/* Read a macro's relocation codes from *ARGS and store them in *R. + The first argument in *ARGS will be either the code for a single + relocation or -1 followed by the three codes that make up a + composite relocation. */ + +static void +macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r) +{ + int i, next; + + next = va_arg (*args, int); + if (next >= 0) + r[0] = next; + else + { + for (i = 0; i < 3; i++) + r[i] = va_arg (*args, int); + /* This function is only used for 16-bit relocation fields. + To make the macro code simpler, treat an unrelocated value + in the same way as BFD_RELOC_LO16. */ + } + if (r[0] == BFD_RELOC_UNUSED) + r[0] = BFD_RELOC_LO16; +} + +/* Map an pair to nanoMIPS relocs. */ + +static void +macro_match_reloc (const char *fmt, bfd_reloc_code_real_type *r) +{ + if (*r == BFD_RELOC_LO16) + { + if (*fmt == 'o' || *fmt == 'g') + *r = BFD_RELOC_NANOMIPS_LO12; + else if (*fmt == 'j') + *r = BFD_RELOC_NANOMIPS_IMM16; + else if (*fmt == 'h') + *r = BFD_RELOC_NANOMIPS_NEG12; + } + else if (*r == BFD_RELOC_GPREL16) + { + if (*fmt == '.') + *r = BFD_RELOC_NANOMIPS_GPREL19_S2; + else if (*fmt == '+' && *(fmt + 1) == '2') + *r = BFD_RELOC_NANOMIPS_GPREL16_S2; + else if (*fmt == '+' && *(fmt + 1) == '1') + *r = BFD_RELOC_NANOMIPS_GPREL18; + else if (*fmt == '+' && *(fmt + 1) == '3') + *r = BFD_RELOC_NANOMIPS_GPREL17_S1; + else if (*fmt == '+' && *(fmt + 1) == '4') + *r = BFD_RELOC_NANOMIPS_GPREL18_S3; + else + gas_assert (false); + } + if (*r == _dummy_first_bfd_reloc_code_real) + *r = BFD_RELOC_UNUSED; + else if (!nanomips_reloc_p (*r)) + { + *r = nanomips_map_reloc (*r); + gas_assert (nanomips_reloc_p (*r)); + } +} + +/* Build an instruction created by a macro expansion. This is passed + a pointer to the count of instructions created so far, an + expression, the name of the instruction to build, an operand format + string, and corresponding arguments. */ + +static void +macro_build (expressionS *ep, const char *name, const char *fmt, ...) +{ + const struct nanomips_opcode *mo = NULL; + bfd_reloc_code_real_type r[3]; + const struct nanomips_opcode *amo; + const struct nanomips_operand *operand; + htab_t hash; + struct nanomips_cl_insn insn; + va_list args; + unsigned int uval; + + va_start (args, fmt); + + r[0] = BFD_RELOC_UNUSED; + r[1] = BFD_RELOC_UNUSED; + r[2] = BFD_RELOC_UNUSED; + hash = nanomips_op_hash; + + amo = str_hash_find (hash, name); + gas_assert (amo); + gas_assert (strcmp (name, amo->name) == 0); + + do + { + /* Search until we get a match for NAME. */ + if (strcmp (fmt, amo->args) == 0 + && amo->pinfo != INSN_MACRO + && is_opcode_valid (amo) + && is_size_valid (amo)) + { + if (!mo) + mo = amo; + } + + ++amo; + gas_assert (amo->name); + } + while (strcmp (name, amo->name) == 0); + + gas_assert (mo); + create_insn (&insn, mo); + for (; *fmt; ++fmt) + { + switch (*fmt) + { + case ',': + case '(': + case ')': + case 'z': + continue; + + case 'i': + case 'g': + case 'j': + case 'h': + macro_read_relocs (&args, r); + macro_match_reloc (fmt, r); + continue; + + case '~': + case 'o': + macro_read_relocs (&args, r); + macro_match_reloc (fmt, r); + continue; + + case 'u': + macro_read_relocs (&args, r); + gas_assert (ep != NULL + && (ep->X_op == O_constant + || (ep->X_op == O_symbol && hi_reloc_p (*r)))); + macro_match_reloc (fmt, r); + continue; + + case '+': + if ((*(fmt + 1) == 'm' + || *(fmt + 1) == 'j' + || *(fmt + 1) == '1' + || *(fmt + 1) == '2' + || *(fmt + 1) == '3' + || *(fmt + 1) == '4' + || *(fmt + 1) == 'K' + || *(fmt + 1) == 'Q' + || *(fmt + 1) == 'R' + || *(fmt + 1) == 'S') + && ep != NULL) + { + macro_read_relocs (&args, r); + macro_match_reloc (fmt, r); + if (*(fmt + 1) == 'Q' || *(fmt + 1) == 'R' || *(fmt + 1) == 'S') + break; + fmt++; + continue; + } + + if (*(fmt + 1) == 'r' || *(fmt + 1) == 'u') + { + if (*(fmt + 1) == 'u') + r[0] = BFD_RELOC_NANOMIPS_25_PCREL_S1; + else if (*(fmt + 1) == 'r') + r[0] = BFD_RELOC_NANOMIPS_21_PCREL_S1; + fmt++; + continue; + } + break; + + case 'p': + gas_assert (ep != NULL); + + /* + * This allows macro() to pass an immediate expression for + * creating short branches without creating a symbol. + * + * We don't allow branch relaxation for these branches, as + * they should only appear in ".set nomacro" anyway. + */ + *r = BFD_RELOC_NANOMIPS_14_PCREL_S1; + macro_match_reloc (fmt, r); + continue; + + case 'm': + if (*(fmt + 1) == 'Q') + { + macro_read_relocs (&args, r); + macro_match_reloc (fmt, r); + fmt++; + continue; + } + break; + + case '.': + macro_read_relocs (&args, r); + macro_match_reloc (fmt, r); + continue; + + case '-': + if (*(fmt + 1) == 'i') + macro_read_relocs (&args, r); + /* Fall through. */ + + default: + break; + } + + operand = decode_nanomips_operand (fmt); + if (!operand) + abort (); + + uval = va_arg (args, int); + + if (operand->type == OP_INT_WORD + || operand->type == OP_UINT_WORD + || operand->type == OP_PC_WORD + || operand->type == OP_GPREL_WORD + || operand->type == OP_IMM_WORD) + insn.insn_opcode_ext = 0; + else if (operand->type == OP_NEG_INT) + insn_insert_operand (&insn, operand, -uval); + else + insn_insert_operand (&insn, operand, uval); + + if ((*fmt == '+') || *fmt == 'm' || *fmt == '-' || *fmt == '`') + ++fmt; + } + + va_end (args); + gas_assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); + append_insn (&insn, ep, r, true); +} + +/* + * Generate an lui/dlui instruction. + */ +static void +macro_build_lui (expressionS *ep, int regnum) +{ + if (ep->X_op != O_constant) + gas_assert (ep->X_op == O_symbol); + + macro_build (ep, "lui", LUI_FMT, regnum, BFD_RELOC_NANOMIPS_HI20); +} + +/* Return the high part that should be loaded in order to make the low + part of VALUE accessible using an offset of OFFBITS bits. */ + +static offsetT +offset_high_part (offsetT value, unsigned int offbits) +{ + offsetT bias; + addressT low_mask; + + if (offbits == 0) + return value; + bias = 1 << (offbits - 1); + low_mask = bias * 2 - 1; + if (offbits == ISA_OFFBITS) + /* Low part is 12-bit unsigned, so no bias necessary. */ + return value & ~low_mask; + else + return (value + bias) & ~low_mask; +} + +/* Return the high part that should be loaded in order to make the low + part of VALUE accessible using an offset of OFFBITS bits. */ + +static offsetT +offset_high_unsigned (offsetT value, unsigned int offbits) +{ + addressT low_mask; + + if (offbits == 0) + return value; + low_mask = (1 << (offbits - 1)) * 2 - 1; + return value & ~low_mask; +} + +/* set_at() + * Generates code to set the $at register to true (one) + * if reg is less than the immediate expression. + */ +static void +set_at (int reg, int unsignedp) +{ + if (offset_high_part (imm_expr.X_add_number, ISA_OFFBITS) == 0) + macro_build (&imm_expr, unsignedp ? "sltiu" : "slti", OP_IMM_FMT, + AT, reg, BFD_RELOC_LO16); + else + { + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); + } +} + +/* Count the leading zeroes by performing a binary chop. This is a + bulky bit of source, but performance is a LOT better for the + majority of values than a simple loop to count the bits: + for (lcnt = 0; (lcnt < 32); lcnt++) + if ((v) & (1 << (31 - lcnt))) + break; + However it is not code size friendly, and the gain will drop a bit + on certain cached systems. +*/ +#define COUNT_TOP_ZEROES(v) \ + (((v) & ~0xffff) == 0 \ + ? ((v) & ~0xff) == 0 \ + ? ((v) & ~0xf) == 0 \ + ? ((v) & ~0x3) == 0 \ + ? ((v) & ~0x1) == 0 \ + ? !(v) \ + ? 32 \ + : 31 \ + : 30 \ + : ((v) & ~0x7) == 0 \ + ? 29 \ + : 28 \ + : ((v) & ~0x3f) == 0 \ + ? ((v) & ~0x1f) == 0 \ + ? 27 \ + : 26 \ + : ((v) & ~0x7f) == 0 \ + ? 25 \ + : 24 \ + : ((v) & ~0xfff) == 0 \ + ? ((v) & ~0x3ff) == 0 \ + ? ((v) & ~0x1ff) == 0 \ + ? 23 \ + : 22 \ + : ((v) & ~0x7ff) == 0 \ + ? 21 \ + : 20 \ + : ((v) & ~0x3fff) == 0 \ + ? ((v) & ~0x1fff) == 0 \ + ? 19 \ + : 18 \ + : ((v) & ~0x7fff) == 0 \ + ? 17 \ + : 16 \ + : ((v) & ~0xffffff) == 0 \ + ? ((v) & ~0xfffff) == 0 \ + ? ((v) & ~0x3ffff) == 0 \ + ? ((v) & ~0x1ffff) == 0 \ + ? 15 \ + : 14 \ + : ((v) & ~0x7ffff) == 0 \ + ? 13 \ + : 12 \ + : ((v) & ~0x3fffff) == 0 \ + ? ((v) & ~0x1fffff) == 0 \ + ? 11 \ + : 10 \ + : ((v) & ~0x7fffff) == 0 \ + ? 9 \ + : 8 \ + : ((v) & ~0xfffffff) == 0 \ + ? ((v) & ~0x3ffffff) == 0 \ + ? ((v) & ~0x1ffffff) == 0 \ + ? 7 \ + : 6 \ + : ((v) & ~0x7ffffff) == 0 \ + ? 5 \ + : 4 \ + : ((v) & ~0x3fffffff) == 0 \ + ? ((v) & ~0x1fffffff) == 0 \ + ? 3 \ + : 2 \ + : ((v) & ~0x7fffffff) == 0 \ + ? 1 \ + : 0) + +/* + * This routine generates the least number of instructions necessary to load + * an absolute expression value into a register. + */ +static void +load_register (int reg, expressionS *ep, int dbl) +{ + if (ep->X_op != O_big) + { + gas_assert (ep->X_op == O_constant); + + /* Sign-extending 32-bit constants makes their handling easier. */ + if (!dbl) + normalize_constant_expr (ep); + + if ((int)ep->X_add_number >= -1 + && ep->X_add_number <= 126 + && (reg >> 2 == 1 || reg >> 2 == 4)) + { + /* 7-bit values loaded using LI[16]. */ + macro_build (NULL, "li", "md,mI", reg, (int) ep->X_add_number); + return; + } + if (IS_SEXT_16BIT_UINT (ep->X_add_number)) + { + /* We can handle 16 bit unsigned values with an addiu to + $zero. No need to ever use daddiu here, since $zero and + the result are always correct in 32 bit mode. */ + macro_build (ep, ADDRESS_ADDI_INSN, ADDIU_FMT, reg, 0, + BFD_RELOC_NANOMIPS_IMM16); + return; + } + if (offset_high_unsigned (-ep->X_add_number, ISA_OFFBITS) == 0) + { + macro_build (ep, "addiu", "t,r,h", reg, 0, BFD_RELOC_NANOMIPS_NEG12); + return; + } + else if ((IS_SEXT_32BIT_NUM (ep->X_add_number))) + { + if ((nanomips_opts.ase & ASE_xNMS) != 0 + && (ep->X_add_number & 0xfff) != 0 + && (*offset_reloc == BFD_RELOC_UNUSED + || pcrel_reloc_p (*offset_reloc)) + && !nanomips_opts.insn32) + macro_build (ep, "li", "mp,+Q", reg, BFD_RELOC_NANOMIPS_I32); + else + { + /* 32 bit values require an lui. */ + macro_build (ep, "lui", "t,u", reg, BFD_RELOC_NANOMIPS_HI20); + if ((ep->X_add_number & 0xfff) != 0 + && !hi_reloc_p (*offset_reloc)) + macro_build (ep, "ori", BITOP_IMM_FMT, reg, reg, + BFD_RELOC_NANOMIPS_LO12); + } + return; + } + } + + return; +} + +/* Move the contents of register SOURCE into register DEST. */ + +static void +move_register (int dest, int source) +{ + /* Prefer to use a 16-bit instruction unless a 32-bit one + is specifically requested. */ + if (!nanomips_opts.insn32) + macro_build (NULL, "move", MOVE_FMT, dest, source); + else + macro_build (NULL, "or", "d,v,t", dest, source, 0); +} + +/* Emit a two-argument branch macro specified by TYPE, using SREG as + the register tested. EP specifies the branch target. */ + +static void +macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg) +{ + const char *br; + + switch (type) + { + case M_BGEZ: + br = "bgez"; + break; + case M_BGTZ: + br = "bgtz"; + break; + case M_BLEZ: + br = "blez"; + break; + case M_BLTZ: + br = "bltz"; + break; + default: + abort (); + } + + if (type == M_BGTZ || type == M_BLEZ) + macro_build (ep, br, BCONDZ2_FMT, sreg); + else + macro_build (ep, br, BCONDZ1_FMT, sreg); +} + +/* Emit a three-argument branch macro specified by TYPE, using SREG and + TREG as the registers tested. EP specifies the branch target. */ + +static void +macro_build_branch_rsrt (int type, expressionS *ep, + unsigned int sreg, unsigned int treg) +{ + const char *br; + + switch (type) + { + case M_BEQ: + case M_BEQ_I: + br = "beq"; + break; + case M_BNE: + case M_BNE_I: + br = "bne"; + break; + default: + abort (); + } + + if (treg == 0) + macro_build (ep, br, "s,t,p", treg, sreg); + else + macro_build (ep, br, "s,t,p", sreg, treg); +} + +/* Emit a three-argument branch macro specified by TYPE, using SREG and + TREG as the registers tested. EP specifies the branch target. */ + +static void +macro_build_branch_rtim (int type, expressionS *ep, + unsigned int sreg, expressionS *imex) +{ + const char *br; + int imm = imex->X_add_number; + + switch (type) + { + case M_BEQ_I: + br = "beqic"; + break; + case M_BGE_I: + br = "bgeic"; + break; + case M_BGEU_I: + case M_BGTU_I: + br = "bgeiuc"; + break; + case M_BLT_I: + case M_BLE_I: + br = "bltic"; + break; + case M_BLTU_I: + case M_BLEU_I: + br = "bltiuc"; + break; + case M_BNE_I: + br = "bneic"; + break; + default: + abort (); + } + + macro_build (ep, br, "t,+9,~", sreg, imm, BFD_RELOC_NANOMIPS_11_PCREL_S1); +} + +/* Return true if the value stored in offset_expr and offset_reloc + fits into a signed offset of OFFBITS bits. RANGE is the maximum + amount that the caller wants to add without inducing overflow + and ALIGN is the known alignment of the value in bytes. */ + +static bool +small_offset_p (unsigned int range, unsigned int align, unsigned int offbits) +{ + if (offbits == 16) + { + /* Accept any relocation operator if overflow isn't a concern. */ + if (range < align && *offset_reloc != BFD_RELOC_UNUSED) + return true; + + /* These relocations are guaranteed not to overflow in correct links. */ + if (gprel_reloc_p (*offset_reloc)) + return true; + } + + if (offset_expr.X_op == O_constant + && offset_high_part (offset_expr.X_add_number, offbits) == 0 + && offset_high_part (offset_expr.X_add_number + range, offbits) == 0 + && offset_expr.X_add_number % align == 0 + && range % align == 0) + return true; + + return false; +} + +static bool +small_poffset_p (unsigned int range, unsigned align, unsigned int offbits) +{ + if (offset_expr.X_op == O_constant + && offset_expr.X_add_number >= 0 + && offset_expr.X_add_number + range < (1 << offbits) + && offset_expr.X_add_number % align == 0 + && range % align == 0) + return true; + + if (lo_reloc_p (*offset_reloc)) + return true; + + return false; +} + +static bool +small_noffset_p (unsigned int range, unsigned int offbits) +{ + if (offset_expr.X_op == O_constant + && offset_expr.X_add_number < 0 + && -offset_expr.X_add_number + range < (1 << offbits)) + return true; + + return false; +} + +/* Check if RANGE fits in positive/negative add-immediate limits. */ + +static bool +small_add_offset_p (unsigned int range) +{ + return (small_poffset_p (range, 1, ISA_ADD_OFFBITS) + || (small_noffset_p (range, ISA_OFFBITS))); +} + +/* Check whether EXP is a valid expression for macro expansions + to handle in the current arch mode. */ + +static bool +macro_expression_valid (expressionS *exp, bfd_reloc_code_real_type rtype) +{ + if ((exp->X_op != O_constant && exp->X_op != O_symbol) + || (exp->X_op == O_symbol && hi_reloc_p (rtype))) + { + as_bad (_("expression too complex")); + exp->X_op = O_constant; + return false; + } + + if (HAVE_64BIT_ADDRESSES && nanomips_opts.insn32) + { + as_bad (_("Macro expansions for 64-bit addresses not supported" + "in insn32 mode")); + return false; + } + + if (exp->X_op == O_constant && hi_reloc_p (rtype)) + exp->X_add_number = offset_high_part (exp->X_add_number, ISA_OFFBITS); +} + +/* Expand the LA macro for PC-relative addressing. */ + +static void +macro_pcrel_la (unsigned int dest, expressionS *an_expr, + bfd_reloc_code_real_type r) +{ + if ((nanomips_opts.ase & ASE_xNMS) != 0 + && r == BFD_RELOC_UNUSED + && !nanomips_opts.insn32) + macro_build (an_expr, "lapc", "mp,+S", dest, + BFD_RELOC_NANOMIPS_PC_I32); + else + { + macro_build (an_expr, "aluipc", "t,+K", dest, + BFD_RELOC_NANOMIPS_PCREL_HI20); + macro_build (an_expr, ADDRESS_ADDI_INSN, ADDIU_FMT, + dest, dest, BFD_RELOC_NANOMIPS_LO12); + } +} + +/* Expand the LA macro for absolute addressing. */ + +static void +macro_absolute_la (unsigned int dest) +{ + if ((nanomips_opts.ase & ASE_xNMS) != 0 + && *offset_reloc == BFD_RELOC_UNUSED + && !nanomips_opts.insn32 + && !HAVE_64BIT_SYMBOLS) + macro_build (&offset_expr, "li", "mp,+Q", dest, BFD_RELOC_NANOMIPS_I32); + else + { + macro_build_lui (&offset_expr, dest); + if (!hi_reloc_p (*offset_reloc)) + macro_build (&offset_expr, "ori", BITOP_IMM_FMT, dest, dest, + ISA_UNSIGNED_LDST_RELOC); + } +} + +/* Expand the LA macro. */ + +static void +macro_la (unsigned int op[], unsigned int breg, int *used_at, + bool gprel_ok) +{ + unsigned int tempreg; + + if (small_poffset_p (0, 1, ISA_ADD_OFFBITS)) + { + macro_build (&offset_expr, ADDRESS_ADDI_INSN, ADDIU_FMT, op[0], breg, + -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); + return; + } + else if (small_noffset_p (0, ISA_OFFBITS)) + { + macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,h", op[0], breg, + -1, offset_reloc[0], offset_reloc[1], offset_reloc[2]); + return; + } + + if (!nanomips_opts.noat && (op[0] == breg)) + { + tempreg = AT; + *used_at = 1; + } + else + tempreg = op[0]; + + if (!macro_expression_valid (&offset_expr, offset_reloc[0])) + return; + + if (offset_expr.X_op == O_constant) + load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES); + else if (nanomips_opts.pic == NO_PIC) + { + if (gprel_ok + && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET + && !nopic_need_relax (offset_expr.X_add_symbol, 1) + && (nanomips_opts.mc_model == MC_MEDIUM + || nanomips_opts.mc_model == MC_AUTO)) + { + relax_start (offset_expr.X_add_symbol); + macro_build (&offset_expr, ADDRESS_ADDI_INSN, ADDIUGP_FMT, + op[0], nanomips_gp_register, BFD_RELOC_GPREL16); + relax_switch (); + } + + if (nanomips_opts.pcrel) + macro_pcrel_la (op[0], &offset_expr, *offset_reloc); + else + macro_absolute_la (op[0]); + + if (nanomips_relax.sequence) + relax_end (); + } + else + { + relax_start (offset_expr.X_add_symbol); + + if (nanomips_opts.pic == SVR4_PIC || linkrelax) + macro_build (&offset_expr, ADDRESS_LOAD_INSN, LWGP_FMT, tempreg, + BFD_RELOC_NANOMIPS_GOT_DISP, nanomips_gp_register); + else if ((nanomips_opts.ase & ASE_xNMS) != 0 && !nanomips_opts.insn32) + macro_build (&offset_expr, PCREL_LOAD_INSN, "mp,+S", tempreg, + BFD_RELOC_NANOMIPS_GOTPC_I32); + else + { + macro_build (&offset_expr, "aluipc", "t,+K", op[0], + BFD_RELOC_NANOMIPS_GOTPC_HI20); + macro_build (&offset_expr, ADDRESS_LOAD_INSN, ISA_UNSIGNED_LDST_FMT, + tempreg, BFD_RELOC_NANOMIPS_GOT_LO12, op[0]); + } + + relax_switch (); + /* Local symbols can be PC-relative. */ + macro_pcrel_la (op[0], &offset_expr, *offset_reloc); + relax_end (); + } + + if (breg != 0) + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", op[0], tempreg, breg); +} + +static void +macro_absolute_ld_st (const char *s, const char *fmt, unsigned int op[], + unsigned int tempreg, unsigned int breg) +{ + macro_build_lui (&offset_expr, tempreg); + + if (breg != 0) + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); + + macro_build (&offset_expr, s, fmt, op[0], BFD_RELOC_LO16, tempreg); +} + +static void +macro_pcrel_ld_st (const char *s, const char *fmt, unsigned int op[], + unsigned int tempreg, bool coproc) +{ + if ((nanomips_opts.ase & ASE_xNMS) != 0 + && *offset_reloc == BFD_RELOC_UNUSED + && !nanomips_opts.insn32 + && !coproc + && (s[0] == 's' || s[0] == 'l') + && (s[1] == 'w' || s[1] == 'd') + && s[2] == 0) + { + char insn[] = "xxpc"; + strncpy (insn, s, 2); + macro_build (&offset_expr, insn, "mp,+S", op[0], + BFD_RELOC_NANOMIPS_PC_I32); + } + else + { + macro_build (&offset_expr, "aluipc", "t,+K", tempreg, + BFD_RELOC_NANOMIPS_PCREL_HI20); + macro_build (&offset_expr, s, fmt, + op[0], BFD_RELOC_NANOMIPS_LO12, tempreg); + } +} + +static void +macro_ld_st (const char *s, const char *fmt, unsigned int op[], + const char *gpfmt, int align, int offbits, unsigned int breg, + unsigned int tempreg, int *used_at, bool coproc) +{ + expressionS expr1; + expr1.X_op = O_constant; + expr1.X_op_symbol = NULL; + expr1.X_add_symbol = NULL; + expr1.X_add_number = 1; + + if (small_add_offset_p (0)) + { + /* The first case exists for M_LD_AB and M_SD_AB, which are + macros for o32 but which should act like normal instructions + otherwise. */ + if ((offbits == ISA_OFFBITS || strncmp (s, "ua", 2) == 0) + && small_poffset_p (0, align, offbits)) + macro_build (&offset_expr, s, fmt, op[0], offset_reloc[0], breg); + else if (small_offset_p (0, align, offbits)) + macro_build (NULL, s, fmt, op[0], + (int) offset_expr.X_add_number, breg); + else + { + /* Source destroying loads do not need AT for expansion. */ + if (s[0] == 'l' && op[0] == breg && op[0] != 0) + tempreg = breg; + else if (tempreg == AT) + *used_at = 1; + + if (small_poffset_p (0, 1, ISA_ADD_OFFBITS)) + macro_build (&offset_expr, ADDRESS_ADDI_INSN, ADDIU_FMT, + tempreg, breg, -1, offset_reloc[0], + offset_reloc[1], offset_reloc[2]); + else if (small_noffset_p (0, ISA_OFFBITS)) + macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,h", + tempreg, breg, -1, offset_reloc[0], + offset_reloc[1], offset_reloc[2]); + macro_build (NULL, s, fmt, op[0], 0, tempreg); + } + return; + } + + if (tempreg == AT) + *used_at = 1; + + if (!macro_expression_valid (&offset_expr, offset_reloc[0])) + return; + + /* A constant expression in PIC code can be handled just as it + is in non PIC code. */ + if (offset_expr.X_op == O_constant) + { + if (op[0] == breg + && op[0] != 0 + && (nanomips_opts.ase & ASE_xNMS) != 0 + && (offset_high_part (offset_expr.X_add_number, offbits) + != offset_expr.X_add_number)) + { + *used_at = 0; + macro_build (&offset_expr, "addiu", "mp,mt,+R", op[0], op[0], + BFD_RELOC_NANOMIPS_I32); + macro_build (NULL, s, fmt, op[0], 0, op[0]); + } + else + { + expr1.X_add_number = offset_high_part (offset_expr.X_add_number, + offbits); + if (offbits != ISA_OFFBITS && (expr1.X_add_number & 0xfff) != 0) + expr1 = offset_expr; + offset_expr.X_add_number -= expr1.X_add_number; + + load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES); + if (breg != 0) + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, + tempreg, breg); + + if (offbits == ISA_OFFBITS) + macro_build (&offset_expr, s, fmt, op[0], + BFD_RELOC_NANOMIPS_LO12, tempreg); + else + macro_build (NULL, s, fmt, op[0], (int) offset_expr.X_add_number, + tempreg); + } + } + else if (offbits != ISA_OFFBITS) + { + /* The offset field is too narrow to be used for a low-part + relocation, so load the whole address into the auxillary + register. */ + macro_la (&tempreg, 0, used_at, strncmp (s, "ua", 2) != 0); + if (breg != 0) + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", tempreg, tempreg, breg); + macro_build (NULL, s, fmt, op[0], 0, tempreg); + } + else if (nanomips_opts.pic == NO_PIC) + { + if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET + && !nopic_need_relax (offset_expr.X_add_symbol, 1) + && (nanomips_opts.mc_model == MC_MEDIUM + || nanomips_opts.mc_model == MC_AUTO)) + { + relax_start (offset_expr.X_add_symbol); + if (gpfmt == NULL) + gpfmt = fmt; + macro_build (&offset_expr, s, gpfmt, op[0], + BFD_RELOC_GPREL16, nanomips_gp_register); + relax_switch (); + } + + if (nanomips_opts.pcrel) + macro_pcrel_ld_st (s, fmt, op, tempreg, coproc); + else + macro_absolute_ld_st (s, fmt, op, tempreg, breg); + + if (nanomips_relax.sequence) + relax_end (); + } + else + { + gas_assert (offset_expr.X_op == O_symbol); + + gpfmt = "t,.(ma)"; + relax_start (offset_expr.X_add_symbol); + + if (nanomips_opts.pic == SVR4_PIC || linkrelax) + macro_build (&offset_expr, ADDRESS_LOAD_INSN, gpfmt, tempreg, + BFD_RELOC_NANOMIPS_GOT_DISP, nanomips_gp_register); + else if ((nanomips_opts.ase & ASE_xNMS) != 0 && !nanomips_opts.insn32) + macro_build (&offset_expr, PCREL_LOAD_INSN, "mp,+S", tempreg, + BFD_RELOC_NANOMIPS_GOTPC_I32); + else + { + macro_build (&offset_expr, "aluipc", "t,+K", tempreg, + BFD_RELOC_NANOMIPS_GOTPC_HI20); + macro_build (&offset_expr, ADDRESS_LOAD_INSN, ISA_UNSIGNED_LDST_FMT, + tempreg, BFD_RELOC_NANOMIPS_GOT_LO12, tempreg); + } + macro_build (NULL, s, fmt, op[0], 0, tempreg); + + relax_switch (); + macro_pcrel_ld_st (s, fmt, op, tempreg, coproc); + relax_end (); + } +} + +/* Generate a pair of loads or stores, either as a multi-word instruction + derived from S or 2 subsequent instructions: S. If MULTI_OK, then + the EP admits no additional relocation, R can be ignored. */ +static void +macro_ld_st_pair (const char *s, const char *fmt, unsigned int op[], + unsigned int breg, expressionS *ep, + bfd_reloc_code_real_type r, bool multi_ok) +{ + if (multi_ok && (nanomips_opts.ase & ASE_xNMS) != 0) + { + char ms[10]; + if (snprintf (ms, sizeof(ms), "%sm", s) >= (int)sizeof(ms)) + gas_assert (false); + macro_build (ep, ms, ISA_MULTI_LDST_FMT, op[0], r, breg, 2); + } + else + { + macro_build (ep, s, fmt, op[0], r, breg); + ep->X_add_number += 4; + macro_build (ep, s, fmt, op[0] + 1, r, breg); + } +} + +static void +macro_absolute_ldd_std (const char *s, const char *fmt,unsigned int op[], + unsigned int breg, unsigned int offbits) +{ + if ((nanomips_opts.ase & ASE_xNMS) != 0 && !nanomips_opts.insn32) + { + macro_build (&offset_expr, "li", "mp,+Q", AT, BFD_RELOC_NANOMIPS_I32); + offset_expr.X_op = O_constant; + offset_expr.X_add_number = 0; + } + else + { + macro_build_lui (&offset_expr, AT); + + if (offbits != ISA_OFFBITS + || (offset_high_part (offset_expr.X_add_number, ISA_OFFBITS) + != offset_high_part (offset_expr.X_add_number + 4, ISA_OFFBITS))) + { + macro_build (&offset_expr, "ori", BITOP_IMM_FMT, AT, AT, + BFD_RELOC_NANOMIPS_LO12); + offset_expr.X_op = O_constant; + offset_expr.X_add_number = 0; + } + } + + if (breg != 0) + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); + + macro_ld_st_pair (s, fmt, op, AT, &offset_expr, BFD_RELOC_NANOMIPS_LO12, + offset_expr.X_op == O_constant); +} + +static void +macro_pcrel_ldd_std (const char *s, const char *fmt, + unsigned int op[], unsigned int offbits) +{ + if (offbits != ISA_OFFBITS) + { + expressionS an_expr; + an_expr.X_op = O_constant; + an_expr.X_op_symbol = NULL; + an_expr.X_add_symbol = NULL; + an_expr.X_add_number = 4; + macro_pcrel_la (AT, &offset_expr, *offset_reloc); + + macro_ld_st_pair (s, fmt, op, AT, &an_expr, + BFD_RELOC_NANOMIPS_SIGNED_9, true); + } + else if ((nanomips_opts.ase & ASE_xNMS) != 0 + && *offset_reloc == BFD_RELOC_UNUSED + && !nanomips_opts.insn32) + { + const char *insn = (strcmp (s, "lw") == 0 ? "lwpc" : "swpc"); + macro_build (&offset_expr, insn, "mp,+S", op[0], + BFD_RELOC_NANOMIPS_PC_I32); + offset_expr.X_add_number += 4; + macro_build (&offset_expr, insn, "mp,+S", op[0] + 1, + BFD_RELOC_NANOMIPS_PC_I32); + } + else + { + macro_build (&offset_expr, "aluipc", "t,+K", AT, + BFD_RELOC_NANOMIPS_PCREL_HI20); + macro_ld_st_pair (s, fmt, op, AT, &offset_expr, + BFD_RELOC_NANOMIPS_LO12, false); + } +} + +static void +macro_ldd_std (const char *s, const char *fmt, unsigned int op[], int align, + int offbits, unsigned int breg, int *used_at) +{ + expressionS expr1; + expressionS *ep; + + expr1.X_op = O_constant; + expr1.X_op_symbol = NULL; + expr1.X_add_symbol = NULL; + expr1.X_add_number = 1; + + if (small_add_offset_p (0)) + { + ep = &offset_expr; + if (offbits == ISA_OFFBITS && small_poffset_p (4, align, ISA_OFFBITS)) + offset_reloc[0] = ISA_UNSIGNED_LDST_RELOC; + else if (offbits == ISA_SIGNED_OFFBITS + && small_offset_p (4, align, ISA_SIGNED_OFFBITS)) + offset_reloc[0] = ISA_SIGNED_LDST_RELOC; + else + { + if (small_poffset_p (0, align, ISA_ADD_OFFBITS)) + macro_build (&offset_expr, ADDRESS_ADDI_INSN, ADDIU_FMT, AT, + breg, offset_reloc[0]); + else if (small_noffset_p (0, ISA_OFFBITS)) + macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,h", AT, + breg, offset_reloc[0]); + + expr1.X_add_number = 0; + ep = &expr1; + breg = AT; + *used_at = 1; + offset_reloc[0] = BFD_RELOC_UNUSED; + } + + if (strstr (s, "lw") != NULL && op[0] == breg) + { + ep->X_add_number += 4; + macro_build (ep, s, fmt, op[0] + 1, offset_reloc[0], breg); + ep->X_add_number -= 4; + macro_build (ep, s, fmt, op[0], offset_reloc[0], breg); + } + else + macro_ld_st_pair (s, fmt, op, breg, ep, offset_reloc[0], + (small_offset_p (0, align, ISA_MULTI_OFFBITS) + || expr1.X_add_number == 0)); + return; + } + + if (!macro_expression_valid (&offset_expr, offset_reloc[0])) + return; + + if (nanomips_opts.pic == NO_PIC || offset_expr.X_op == O_constant) + { + if (offset_expr.X_op == O_symbol + && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET + && strncmp (s, "ua", 2) != 0 + && (breg == 0 + && (gprel_reloc_p (*offset_reloc) + || *offset_reloc == BFD_RELOC_UNUSED)) + && !nopic_need_relax (offset_expr.X_add_symbol, 1)) + { + const char *sfmt = fmt; + unsigned int tempreg; + relax_start (offset_expr.X_add_symbol); + if (breg == 0) + { + tempreg = nanomips_gp_register; + sfmt = "t,.(ma)"; + } + else + { + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", + AT, breg, nanomips_gp_register); + tempreg = AT; + *used_at = 1; + } + + macro_build (&offset_expr, s, sfmt, op[0], BFD_RELOC_GPREL16, + tempreg); + offset_expr.X_add_number += 4; + macro_build (&offset_expr, s, sfmt, op[0] + 1, + BFD_RELOC_GPREL16, tempreg); + relax_switch (); + + offset_expr.X_add_number -= 4; + } + + *used_at = 1; + if (nanomips_opts.pcrel) + macro_pcrel_ldd_std (s, fmt, op, offbits); + else + macro_absolute_ldd_std (s, fmt, op, breg, offbits); + + + if (nanomips_relax.sequence) + relax_end (); + } + else if (offbits == ISA_OFFBITS) + { + *used_at = 1; + expr1.X_add_number = 0; + relax_start (offset_expr.X_add_symbol); + macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,.(ma)", AT, + BFD_RELOC_NANOMIPS_GOT_DISP, nanomips_gp_register); + if (breg != 0) + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); + + macro_ld_st_pair (s, fmt, op, AT, &expr1, BFD_RELOC_NANOMIPS_LO12, true); + + relax_switch (); + macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,.(ma)", AT, + BFD_RELOC_NANOMIPS_GOT_PAGE, nanomips_gp_register); + if (breg != 0) + macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT); + + macro_build (&offset_expr, s, fmt, op[0], + BFD_RELOC_NANOMIPS_GOT_OFST, AT); + offset_expr.X_add_number += 4; + macro_build (&offset_expr, s, fmt, op[0] + 1, + BFD_RELOC_NANOMIPS_GOT_OFST, AT); + relax_end (); + } + else + { + *used_at = 1; + expr1.X_add_number = 0; + macro_la (&nanomips_opts.noat, 0, used_at, true); + macro_ld_st_pair (s, fmt, op, AT, &expr1, + BFD_RELOC_NANOMIPS_LO12, true); + } +} + +/* Build macros */ + +static void +macro (struct nanomips_cl_insn *ip, char *str ATTRIBUTE_UNUSED) +{ + const struct nanomips_operand_array *operands; + + unsigned int breg, i; + unsigned int tempreg; + int mask; + int used_at = 0; + expressionS label_expr; + expressionS expr1; + const char *s = ip->insn_mo->name; + const char *s2 = NULL; + const char *fmt; + const char *gpfmt = NULL; + int coproc = 0; + int offbits = ISA_OFFBITS; + bool dbl = false; + int lp = 0; + unsigned int align; + unsigned int op[MAX_OPERANDS]; + + operands = insn_operands (ip); + for (i = 0; i < MAX_OPERANDS; i++) + if (operands->operand[i]) + op[i] = insn_extract_operand (ip, operands->operand[i]); + else + op[i] = -1; + + mask = ip->insn_mo->mask; + + label_expr.X_op = O_constant; + label_expr.X_op_symbol = NULL; + label_expr.X_add_symbol = NULL; + label_expr.X_add_number = 0; + + expr1.X_op = O_constant; + expr1.X_op_symbol = NULL; + expr1.X_add_symbol = NULL; + expr1.X_add_number = 1; + align = 1; + + switch (mask) + { + case M_ABS: + /* bgez $a0,1f + move v0,$a0 + sub v0,$zero,$a0 + 1: + */ + + nanomips_label_expr (&label_expr); + if (op[0] != op[1]) + move_register (op[0], op[1]); + macro_build (&label_expr, "bgezc", BCONDZ1_FMT, op[1]); + macro_build (NULL, "subu", "d,v,t", op[0], 0, op[1]); + nanomips_add_label (); + break; + + case M_ADD_I: + s = "addiu"; + s2 = "add"; + if (imm_expr.X_add_number == 0) + goto do_addi; + else + goto do_addi_i; + case M_ADDU_I: + s = "addiu"; + s2 = "addu"; + do_addi: + if (offset_high_unsigned (imm_expr.X_add_number, 16) == 0) + { + macro_build (&imm_expr, s, ADDIU_FMT, op[0], op[1], + BFD_RELOC_NANOMIPS_IMM16); + break; + } + else if (offset_high_unsigned (-imm_expr.X_add_number, 12) == 0) + { + macro_build (&imm_expr, s, "t,r,h", op[0], op[1], + BFD_RELOC_NANOMIPS_NEG12); + break; + } + else if ((nanomips_opts.ase & ASE_xNMS) != 0 + && op[0] == op[1] + && !nanomips_opts.insn32) + { + macro_build (&imm_expr, s, "mp,mt,+R", op[0], op[0], + BFD_RELOC_NANOMIPS_I32); + break; + } + do_addi_i: + used_at = 1; + load_register (AT, &imm_expr, dbl); + macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); + break; + + case M_AND_I: + s = "andi"; + s2 = "and"; + goto do_bit; + case M_OR_I: + s = "ori"; + s2 = "or"; + goto do_bit; + case M_NOR_I: + s = ""; + s2 = "nor"; + goto do_load_op; + case M_XOR_I: + s = "xori"; + s2 = "xor"; + do_bit: + if (offset_high_unsigned (imm_expr.X_add_number, 12) == 0) + { + if (mask != M_NOR_I) + macro_build (&imm_expr, s, BITOP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + else + { + macro_build (&imm_expr, "ori", BITOP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + macro_build (NULL, "nor", "d,v,t", op[0], op[0], 0); + } + break; + } + do_load_op: + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); + break; + + case M_BEQ_I: + case M_BNE_I: + if (imm_expr.X_add_number == 0) + op[1] = 0; + else if (offset_high_unsigned (imm_expr.X_add_number, 7) == 0) + { + macro_build_branch_rtim (mask, &offset_expr, op[0], &imm_expr); + break; + } + else + { + op[1] = AT; + used_at = 1; + load_register (op[1], &imm_expr, GPR_SIZE == 64); + } + macro_build_branch_rsrt (mask, &offset_expr, op[0], op[1]); + break; + + case M_BGE: + if (op[1] == 0) + macro_build_branch_rs (M_BGEZ, &offset_expr, op[0]); + else if (op[0] == 0) + macro_build_branch_rs (M_BLEZ, &offset_expr, op[1]); + else + { + used_at = 1; + macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); + macro_build_branch_rsrt (M_BEQ, &offset_expr, AT, ZERO); + } + break; + + case M_BGT: + if (op[1] == 0) + macro_build_branch_rs (M_BGTZ, &offset_expr, op[0]); + else if (op[0] == 0) + macro_build_branch_rs (M_BLTZ, &offset_expr, op[1]); + else + { + used_at = 1; + macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); + macro_build_branch_rsrt (M_BNE, &offset_expr, AT, ZERO); + } + break; + + case M_BLE: + if (op[1] == 0) + macro_build_branch_rs (M_BLEZ, &offset_expr, op[0]); + else if (op[0] == 0) + macro_build_branch_rs (M_BGEZ, &offset_expr, op[1]); + else + { + used_at = 1; + macro_build (NULL, "slt", "d,v,t", AT, op[1], op[0]); + macro_build_branch_rsrt (M_BEQ, &offset_expr, AT, ZERO); + } + break; + + case M_BLT: + if (op[1] == 0) + macro_build_branch_rs (M_BLTZ, &offset_expr, op[0]); + else if (op[0] == 0) + macro_build_branch_rs (M_BGTZ, &offset_expr, op[1]); + else + { + used_at = 1; + macro_build (NULL, "slt", "d,v,t", AT, op[0], op[1]); + macro_build_branch_rsrt (M_BNE, &offset_expr, AT, ZERO); + } + break; + + case M_BGEZAL: + s = "bltzc"; + goto brcond_al; + case M_BLTZAL: + s = "bgezc"; + brcond_al: + nanomips_label_expr (&label_expr); + macro_build (&label_expr, s, BCONDZ1_FMT, op[0]); + macro_build (&offset_expr, "bal", B_FMT); + nanomips_add_label (); + break; + + case M_BGT_I: + /* Check for > max integer. */ + if (imm_expr.X_add_number >= GPR_SMAX) + { + do_false: + /* Result is always false. */ + macro_build (NULL, "nop", ""); + break; + } + ++imm_expr.X_add_number; + /* Fall through. */ + case M_BGE_I: + if (imm_expr.X_add_number == 0) + macro_build_branch_rs (M_BGEZ, &offset_expr, op[0]); + else if (imm_expr.X_add_number == 1) + macro_build_branch_rs (M_BGTZ, &offset_expr, op[0]); + else if (imm_expr.X_add_number <= GPR_SMIN) + { + do_true: + /* result is always true */ + as_warn (_("branch %s is always true"), ip->insn_mo->name); + macro_build (&offset_expr, "b", B_FMT); + break; + } + else if (offset_high_unsigned (imm_expr.X_add_number, 7) == 0) + macro_build_branch_rtim (M_BGE_I, &offset_expr, op[0], &imm_expr); + else + { + used_at = 1; + set_at (op[0], 0); + macro_build_branch_rsrt (M_BEQ, &offset_expr, AT, ZERO); + } + break; + + case M_BGTU_I: + if (op[0] == 0 || (GPR_SIZE == 32 && imm_expr.X_add_number == -1)) + goto do_false; + ++imm_expr.X_add_number; + /* Fall through. */ + case M_BGEU_I: + if (imm_expr.X_add_number == 0) + goto do_true; + else if (imm_expr.X_add_number == 1) + macro_build_branch_rsrt (M_BNE, &offset_expr, op[0], ZERO); + else if (offset_high_unsigned (imm_expr.X_add_number, 7) == 0) + macro_build_branch_rtim (mask, &offset_expr, op[0], &imm_expr); + else + { + used_at = 1; + set_at (op[0], 1); + macro_build_branch_rsrt (M_BEQ, &offset_expr, AT, ZERO); + } + break; + + case M_BGTU: + if (op[1] == 0) + macro_build_branch_rsrt (M_BNE, &offset_expr, op[0], ZERO); + else if (op[0] == 0) + goto do_false; + else + { + used_at = 1; + macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); + macro_build_branch_rsrt (M_BNE, &offset_expr, AT, ZERO); + } + break; + + case M_BLE_I: + if (imm_expr.X_add_number >= GPR_SMAX) + goto do_true; + ++imm_expr.X_add_number; + /* Fall through. */ + case M_BLT_I: + if (imm_expr.X_add_number == 0) + macro_build_branch_rs (M_BLTZ, &offset_expr, op[0]); + else if (imm_expr.X_add_number == 1) + macro_build_branch_rs (M_BLEZ, &offset_expr, op[0]); + else if (offset_high_unsigned (imm_expr.X_add_number, 7) == 0) + macro_build_branch_rtim (mask, &offset_expr, op[0], &imm_expr); + else + { + used_at = 1; + set_at (op[0], 0); + macro_build_branch_rsrt (M_BNE, &offset_expr, AT, ZERO); + } + break; + + case M_BLEU: + if (op[1] == 0) + macro_build_branch_rsrt (M_BEQ, &offset_expr, op[0], ZERO); + else if (op[0] == 0) + goto do_true; + else + { + used_at = 1; + macro_build (NULL, "sltu", "d,v,t", AT, op[1], op[0]); + macro_build_branch_rsrt (M_BEQ, &offset_expr, AT, ZERO); + } + break; + + case M_BLEU_I: + if (op[0] == 0 || (GPR_SIZE == 32 && imm_expr.X_add_number == -1)) + goto do_true; + ++imm_expr.X_add_number; + /* Fall through. */ + case M_BLTU_I: + if (imm_expr.X_add_number == 0) + goto do_false; + else if (imm_expr.X_add_number == 1) + macro_build_branch_rsrt (M_BEQ, &offset_expr, op[0], ZERO); + else if (offset_high_unsigned (imm_expr.X_add_number, 7) == 0) + macro_build_branch_rtim (mask, &offset_expr, op[0], &imm_expr); + else + { + used_at = 1; + set_at (op[0], 1); + macro_build_branch_rsrt (M_BNE, &offset_expr, AT, ZERO); + } + break; + + case M_BLTU: + if (op[1] == 0) + goto do_false; + else if (op[0] == 0) + macro_build_branch_rsrt (M_BNE, &offset_expr, ZERO, op[1]); + else + { + used_at = 1; + macro_build (NULL, "sltu", "d,v,t", AT, op[0], op[1]); + macro_build_branch_rsrt (M_BNE, &offset_expr, AT, ZERO); + } + break; + + case M_EXT: + if (31 - op[2] - op[3] > 0) + { + macro_build (NULL, "sll", SHFT_FMT, op[0], op[1], + 31 - op[2] - op[3]); + macro_build (NULL, "srl", SHFT_FMT, op[0], op[0], 31 - op[3]); + } + else + macro_build (NULL, "srl", SHFT_FMT, op[0], op[1], op[2]); + break; + + case M_INS: + if (op[0] == op[1] && op[2] == 0) + { + macro_build (NULL, "nop", ""); + break; + } + else if (op[0] == op[1]) + { + used_at = 1; + macro_build (NULL, "extw", "d,s,t,+I", AT, op[0], op[0], op[2]); + macro_build (NULL, "extw", "d,s,t,+I", op[0], AT, op[0], + 1 + op[3] - op[2]); + } + else if (op[2] == 0 && op[3] == 31) + { + move_register (op[0], op[1]); + break; + } + else + { + if (op[2] != 0) + macro_build (NULL, "extw", "d,s,t,+I", op[0], op[0], + op[0], op[2]); + macro_build (NULL, "extw", "d,s,t,+I", op[0], op[0], op[1], + 1 + op[3] - op[2]); + } + if (op[3] < 31) + macro_build (NULL, "extw", "d,s,t,+I", op[0], op[0], op[0], + 31 - op[3]); + break; + + case M_DIV_I: + case M_DIVU_I: + goto do_divi; + + case M_REM_3I: + case M_MOD_I: + s = "mod"; + do_divi: + if (imm_expr.X_add_number == 0) + { + as_warn (_("divide by zero")); + if (nanomips_trap) + macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7); + else + macro_build (NULL, "break", BRK_FMT, 7); + break; + } + if (imm_expr.X_add_number == 1) + { + if (strncmp (s, "div", 3) == 0) + move_register (op[0], op[1]); + else + move_register (op[0], ZERO); + break; + } + if (imm_expr.X_add_number == -1 && s[strlen (s) - 1] != 'u') + { + if (strncmp (s, "div", 3) == 0) + macro_build (NULL, "neg", "d,w", op[0], op[1]); + else + move_register (op[0], ZERO); + break; + } + + used_at = 1; + load_register (AT, &imm_expr, dbl); + macro_build (NULL, s, DIV_FMT, op[0], op[1], AT); + break; + + case M_MODU_I: + s = "modu"; + goto do_divi; + + case M_LA_AB: + /* Load the address of a symbol into a register. If breg is not + zero, we then add a base register to it. */ + breg = op[2]; + macro_la (op, breg, &used_at, true); + break; + + case M_J_A: + /* The j instruction may not be used in PIC code, since it + requires an absolute address. We convert it to a b + instruction. */ + /* Likewise for nanoMIPS which has no absolute jump instruction. */ + macro_build (&offset_expr, "bc", B_FMT); + break; + + /* The jal instructions must be handled as macros because when + generating PIC code they expand to multi-instruction + sequences. Normally they are simple instructions. */ + case M_JAL_A: + if (nanomips_opts.pic == NO_PIC) + macro_build (&offset_expr, "jal", B_FMT); + else + { + macro_build (&offset_expr, ADDRESS_LOAD_INSN, LWGP_FMT, + AT, BFD_RELOC_NANOMIPS_GOT_CALL, nanomips_gp_register); + + if (nanomips_linkrelax_p) + { + if (nanomips_opts.insn32) + macro_build (&offset_expr, "jalrc", "s,-i", AT, + BFD_RELOC_NANOMIPS_JALR32); + else + macro_build (&offset_expr, "jalrc", "mp,-i", AT, + BFD_RELOC_NANOMIPS_JALR16); + } + else + macro_build (NULL, "jalrc", (nanomips_opts.insn32 ? "s" : "mp"), + AT); + } + + break; + + case M_LB_AC: + case M_LBU_AC: + case M_LH_AC: + case M_LHU_AC: + case M_LW_AC: + fmt = ISA_UNSIGNED_LDST_FMT; + switch (s[1]) + { + case 'b': + gpfmt = "t,+1(ma)"; + break; + case 'd': + gpfmt = "t,+4(ma)"; + break; + case 'h': + gpfmt = "t,+3(ma)"; + break; + default: + if (s[2] == 'u') + gpfmt = "t,+2(ma)"; + else + gpfmt = "t,.(ma)"; + break; + } + goto ld; + + case M_LL_AC: + fmt = LL_SC_FMT; + align = 4; + offbits = ISA_SIGNED_OFFBITS; + goto ld; + + ld: + if (op[2] == op[0] + lp) + goto ld_st; + else + tempreg = op[0] + lp; + goto ld_noat; + + case M_LBUE_AC: + case M_LHUE_AC: + case M_LBE_AC: + case M_LHE_AC: + case M_SHE_AC: + case M_SWE_AC: + case M_LWE_AC: + case M_SBE_AC: + fmt = ISA_SIGNED_LDST_FMT; + goto ld_st_signed_off; + + case M_SB_AC: + case M_SH_AC: + fmt = ISA_UNSIGNED_LDST_FMT; + gpfmt = "t,+1(ma)"; + goto ld_st; + + case M_SW_AC: + fmt = ISA_UNSIGNED_LDST_FMT; + gpfmt = "t,.(ma)"; + goto ld_st; + + case M_LLE_AC: + case M_SCE_AC: + case M_SC_AC: + fmt = LL_SC_FMT; + align = 4; + goto ld_st_signed_off; + + case M_CACHE_AC: + case M_PREF_AC: + case M_CACHEE_AC: + case M_PREFE_AC: + fmt = PREF_FMT; + goto ld_st_signed_off; + + case M_SWM_AC: + case M_SDM_AC: + case M_LWM_AC: + case M_LDM_AC: + fmt = ISA_SIGNED_LDST_FMT ",|"; + + ld_st_signed_off: + offbits = ISA_SIGNED_OFFBITS; + ld_st: + tempreg = AT; + ld_noat: + breg = op[2]; + macro_ld_st (s, fmt, op, gpfmt, align, offbits, breg, tempreg, + &used_at, coproc); + break; + + case M_JRADDIUSP: + offset_expr = imm_expr; + if (small_poffset_p (0, 1, ISA_ADD_OFFBITS)) + macro_build (&imm_expr, "addiu", ADDIU_FMT, SP, SP, + BFD_RELOC_NANOMIPS_IMM16); + else if (small_noffset_p (0, ISA_OFFBITS)) + macro_build (&imm_expr, "addiu", ADDIU_FMT, SP, SP, + BFD_RELOC_NANOMIPS_NEG12); + else + { + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "addu", "d,v,t", SP, SP, AT); + } + macro_build (NULL, "jrc", (nanomips_opts.insn32 ? "s" : "mp"), RA); + break; + + case M_LI: + if (imm_expr.X_op != O_absent) + load_register (op[0], &imm_expr, 0); + else + macro_la (op, 0, &used_at, false); + break; + + case M_LI_S: + if (imm_expr.X_op == O_constant) + { + load_register (op[0], &imm_expr, 0); + break; + } + + /* Loading from data section, fall-back to load-from-label + macro expansion. */ + used_at = 1; + align = 4; + offbits = ISA_OFFBITS; + fmt = ISA_UNSIGNED_LDST_FMT; + op[2] = 0; + s = "lw"; + gpfmt = LWGP_FMT; + tempreg = (op[0] != 0) ? op[0] : AT; + goto ld_noat; + + case M_LI_D: + /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits + wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high + order 32 bits of the value and the low order 32 bits are either + zero or in OFFSET_EXPR. */ + if (imm_expr.X_op == O_constant) + { + int hreg, lreg; + + if (target_big_endian) + { + hreg = op[0]; + lreg = op[0] + 1; + } + else + { + hreg = op[0] + 1; + lreg = op[0]; + } + + if (hreg <= 31) + load_register (hreg, &imm_expr, 0); + if (lreg <= 31) + { + if (offset_expr.X_op == O_absent) + move_register (lreg, 0); + else + { + gas_assert (offset_expr.X_op == O_constant); + load_register (lreg, &offset_expr, 0); + } + } + break; + } + + /* Loading from data section, fall-back to load-from-label + macro expansion. */ + gas_assert (imm_expr.X_op == O_absent); + used_at = 1; + align = 4; + offbits = ISA_OFFBITS; + fmt = ISA_UNSIGNED_LDST_FMT; + op[2] = 0; + s = "lw"; + gpfmt = LWGP_FMT; + tempreg = op[0]; + goto ldd_std; + + case M_LD_AC: + fmt = ISA_UNSIGNED_LDST_FMT; + gpfmt = "t,+2(ma)"; + s = "lw"; + goto ldd_std; + + case M_SD_AC: + fmt = ISA_UNSIGNED_LDST_FMT; + gpfmt = "t,+2(ma)"; + s = "sw"; + + ldd_std: + breg = op[2]; + macro_ldd_std (s, fmt, op, align, offbits, breg, &used_at); + break; + + case M_MUL: + macro_build (NULL, "multu", "s,t", op[1], op[2]); + macro_build (NULL, "mflo", MFHL_FMT, op[0]); + break; + + case M_MUL_I: + used_at = 1; + load_register (AT, &imm_expr, dbl); + macro_build (NULL, "mul", "d,v,t", op[0], op[1], AT); + break; + + case M_ROL: + if (op[0] == op[1]) + { + tempreg = AT; + used_at = 1; + } + else + tempreg = op[0]; + macro_build (NULL, "negu", "d,w", tempreg, op[2]); + macro_build (NULL, "rorv", BITW_FMT, op[0], op[1], tempreg); + break; + + case M_ROL_I: + { + unsigned int rot; + + rot = imm_expr.X_add_number & 0x1f; + macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], (32 - rot) & 0x1f); + break; + } + + case M_ROR_I: + { + unsigned int rot; + + rot = imm_expr.X_add_number & 0x1f; + macro_build (NULL, "ror", SHFT_FMT, op[0], op[1], rot); + break; + } + + case M_SEQ: + if (op[1] == 0) + macro_build (&expr1, "sltiu", OP_IMM_FMT, op[0], op[2], + BFD_RELOC_LO16); + else if (op[2] == 0) + macro_build (&expr1, "sltiu", OP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + else + { + macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); + macro_build (&expr1, "sltiu", OP_IMM_FMT, op[0], op[0], + BFD_RELOC_LO16); + } + break; + + case M_SEQ_I: + if (imm_expr.X_add_number == 0) + macro_build (&expr1, "sltiu", OP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + else if (op[1] == 0) + { + as_warn (_("instruction %s: result is always false"), + ip->insn_mo->name); + move_register (op[0], 0); + } + else if (offset_high_unsigned (imm_expr.X_add_number, ISA_OFFBITS) == 0) + macro_build (&imm_expr, "seqi", OP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + else + { + if (offset_high_unsigned (-imm_expr.X_add_number, + ISA_ADD_OFFBITS) == 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build (&imm_expr, "addiu", ADDIU_FMT, + op[0], op[1], BFD_RELOC_LO16); + } + else + { + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); + } + macro_build (&expr1, "sltiu", OP_IMM_FMT, op[0], op[0], + BFD_RELOC_LO16); + } + break; + + case M_SGE: /* X >= Y <==> not (X < Y) */ + s = "slt"; + goto sge; + case M_SGEU: + s = "sltu"; + sge: + macro_build (NULL, s, "d,v,t", op[0], op[1], op[2]); + macro_build (&expr1, "xori", BITOP_IMM_FMT, op[0], op[0], + BFD_RELOC_LO16); + break; + + case M_SGE_I: /* X >= I <==> not (X < I) */ + case M_SGEU_I: + if (offset_high_unsigned (imm_expr.X_add_number, ISA_OFFBITS) == 0) + macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", + OP_IMM_FMT, op[0], op[1], BFD_RELOC_LO16); + else + { + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", + op[0], op[1], AT); + } + macro_build (&expr1, "xori", BITOP_IMM_FMT, op[0], op[0], + BFD_RELOC_LO16); + break; + + case M_SGT: /* X > Y <==> Y < X */ + s = "slt"; + goto sgt; + case M_SGTU: + s = "sltu"; + sgt: + macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); + break; + + case M_SGT_I: /* X > I <==> I < X */ + s = "slt"; + goto sgti; + case M_SGTU_I: + s = "sltu"; + sgti: + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); + break; + + case M_SLE: /* X <= Y <==> Y >= X <==> not (Y < X) */ + s = "slt"; + goto sle; + case M_SLEU: + s = "sltu"; + sle: + macro_build (NULL, s, "d,v,t", op[0], op[2], op[1]); + macro_build (&expr1, "xori", BITOP_IMM_FMT, op[0], op[0], + BFD_RELOC_LO16); + break; + + case M_SLE_I: /* X <= I <==> I >= X <==> not (I < X) */ + s = "slt"; + goto slei; + case M_SLEU_I: + s = "sltu"; + slei: + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); + macro_build (&expr1, "xori", BITOP_IMM_FMT, op[0], op[0], + BFD_RELOC_LO16); + break; + + case M_SLT_I: + if (offset_high_unsigned (imm_expr.X_add_number, ISA_OFFBITS) == 0) + { + macro_build (&imm_expr, "slti", OP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + break; + } + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); + break; + + case M_SLTU_I: + if (offset_high_unsigned (imm_expr.X_add_number, ISA_OFFBITS) == 0) + { + macro_build (&imm_expr, "sltiu", OP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + break; + } + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); + break; + + case M_SNE: + if (op[1] == 0) + macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[2]); + else if (op[2] == 0) + macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); + else + { + macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); + macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); + } + break; + + case M_SNE_I: + if (imm_expr.X_add_number == 0) + macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[1]); + else if (op[1] == 0) + { + as_warn (_("instruction %s: result is always true"), + ip->insn_mo->name); + load_register (op[0], &expr1, GPR_SIZE == 64); + } + else + { + if (offset_high_unsigned (imm_expr.X_add_number, + ISA_ADD_OFFBITS) == 0) + macro_build (&imm_expr, "xori", BITOP_IMM_FMT, op[0], op[1], + BFD_RELOC_LO16); + else if (offset_high_unsigned (-imm_expr.X_add_number, + ISA_ADD_OFFBITS) == 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build (&imm_expr, "addiu", ADDIU_FMT, op[0], op[1], + BFD_RELOC_LO16); + } + else + { + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "xor", "d,v,t", op[0], op[1], op[2]); + } + macro_build (NULL, "sltu", "d,v,t", op[0], 0, op[0]); + } + break; + + case M_SUB_I: + s = "addiu"; + s2 = "sub"; + goto do_subi_i; + case M_SUBU_I: + s = "addiu"; + s2 = "subu"; + if (offset_high_unsigned (-imm_expr.X_add_number, 16) == 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build (&imm_expr, s, ADDIU_FMT, op[0], op[1], + BFD_RELOC_NANOMIPS_IMM16); + break; + } + else if (offset_high_unsigned (imm_expr.X_add_number, 12) == 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build (&imm_expr, s, "t,r,h", op[0], op[1], + BFD_RELOC_NANOMIPS_NEG12); + break; + } + else if ((nanomips_opts.ase & ASE_xNMS) != 0 + && op[0] == op[1] + && !nanomips_opts.insn32) + { + imm_expr.X_add_number = -imm_expr.X_add_number; + macro_build (&imm_expr, s, "mp,mt,+R", op[0], op[0], + BFD_RELOC_NANOMIPS_I32); + break; + } + + do_subi_i: + used_at = 1; + load_register (AT, &imm_expr, dbl); + macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); + break; + + case M_TEQ_I: + case M_TNE_I: + used_at = 1; + load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s, "s,t", op[0], AT); + break; + + case M_ULH_AC: + s = "ualh"; + goto uld_st; + + case M_ULW_AC: + s = "ualw"; + goto uld_st; + + case M_USH_AC: + s = "uash"; + goto uld_st; + + case M_USW_AC: + s = "uasw"; + goto uld_st; + + case M_ULD_AC: + s = "uald"; + s2 = "ualw"; + goto uld_st; + + case M_USD_AC: + s = "uasd"; + s2 = "uasw"; + + uld_st: + fmt = ISA_SIGNED_LDST_FMT; + offbits = ISA_SIGNED_OFFBITS; + if (s[3] == 'd' && GPR_SIZE == 32) + { + s = s2; + goto ldd_std; + } + else + goto ld_st; + break; + + default: + as_bad (_("macro %s not implemented yet"), ip->insn_mo->name); + break; + } + if (nanomips_opts.noat && used_at) + as_bad (_("macro used $at after \".set noat\"")); +} + +/* Look up instruction [START, START + LENGTH) in HASH. Record any extra + opcode bits in *OPCODE_EXTRA. */ + +static struct nanomips_opcode * +nanomips_lookup_insn (htab_t hash, const char *start, + ssize_t length, + unsigned int *opcode_extra ATTRIBUTE_UNUSED) +{ + char *name, *dot; + unsigned int suffix; + ssize_t opend; + struct nanomips_opcode *insn; + + /* Make a copy of the instruction so that we can fiddle with it. */ + name = xstrndup (start, length); + + forced_insn_format = (strchr (start, '[') != NULL + && strchr (strchr (start, '['), ']') != NULL); + + /* Look up the instruction as-is. */ + insn = str_hash_find (hash, name); + if (insn) + return insn; + + if (strchr (name, ']')) + dot = strchr (strchr (name, ']'), '.'); + else + dot = strchr (name, '.'); + + /* See if there's an instruction size override suffix, + either `16' or `32', at the end of the mnemonic proper, + that defines the operation, i.e. before the first `.' + character if any. Strip it and retry. */ + opend = dot != NULL ? dot - name : length; + if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6') + suffix = 2; + else if (opend >= 2 && name[opend - 2] == '3' && name[opend - 1] == '2') + suffix = 4; + else if (opend >= 3 && name[opend - 2] == '4' && name[opend - 1] == '8') + suffix = 6; + else + suffix = 0; + if (suffix) + { + memmove (name + opend - 2, name + opend, length - opend + 1); + insn = str_hash_find (hash, name); + while (insn) + if (insn_length (insn) == suffix) + { + forced_insn_length = suffix; + return insn; + } + else if (forced_insn_format) + break; + else + insn++; + } + return NULL; +} + +/* Assemble an instruction into its binary format. If the instruction + is a macro, set imm_expr and offset_expr to the values associated + with "I" and "A" operands respectively. Otherwise store the value + of the relocatable field (if any) in offset_expr. In both cases + set offset_reloc to the relocation operators applied to offset_expr. */ + +static void +nanomips_ip (char *str, struct nanomips_cl_insn *insn) +{ + const struct nanomips_opcode *first, *past; + htab_t hash; + char format; + size_t end; + struct nanomips_operand_token *tokens; + unsigned int opcode_extra; + + hash = nanomips_op_hash; + past = &nanomips_opcodes[bfd_nanomips_num_opcodes]; + forced_insn_length = 0; + forced_insn_format = false; + opcode_extra = 0; + + /* We first try to match an instruction up to a space or to the end. */ + for (end = 0; !is_end_of_stmt (str[end]) && !is_whitespace (str[end]); end++) + continue; + + first = nanomips_lookup_insn (hash, str, end, &opcode_extra); + if (first == NULL) + { + set_insn_error (0, _("unrecognized opcode")); + return; + } + + if (strcmp (first->name, "li.s") == 0) + format = 'f'; + else if (strcmp (first->name, "li.d") == 0) + format = 'd'; + else + format = 0; + tokens = nanomips_parse_arguments (str + end, format); + if (!tokens) + return; + + if (!match_insns (insn, first, past, tokens, opcode_extra, false) + && !match_insns (insn, first, past, tokens, opcode_extra, true)) + set_insn_error (0, _("invalid operands")); + + obstack_free (&nanomips_operand_tokens, tokens); +} + +struct percent_op_match +{ + const char *str; + bfd_reloc_code_real_type reloc; +}; + +static const struct percent_op_match nanomips_percent_op[] = { + {"%lo", BFD_RELOC_NANOMIPS_LO12}, + {"%call16", BFD_RELOC_NANOMIPS_GOT_CALL}, + {"%got_call", BFD_RELOC_NANOMIPS_GOT_CALL}, + {"%got_disp", BFD_RELOC_NANOMIPS_GOT_DISP}, + {"%got_page", BFD_RELOC_NANOMIPS_GOT_PAGE}, + {"%got_ofst", BFD_RELOC_NANOMIPS_GOT_OFST}, + {"%got", BFD_RELOC_NANOMIPS_GOT_DISP}, + {"%gp_rel", BFD_RELOC_NANOMIPS_GPREL18}, + {"%gprel", BFD_RELOC_NANOMIPS_GPREL18}, + {"%gprel_hi", BFD_RELOC_NANOMIPS_GPREL_HI20}, + {"%gprel_lo", BFD_RELOC_NANOMIPS_GPREL_LO12}, + {"%gprel32", BFD_RELOC_NANOMIPS_GPREL_I32}, + {"%hi", BFD_RELOC_NANOMIPS_HI20}, + {"%pcrel_hi", BFD_RELOC_NANOMIPS_PCREL_HI20}, + {"%pcrel_lo", BFD_RELOC_NANOMIPS_LO12}, + {"%got_pcrel_hi", BFD_RELOC_NANOMIPS_GOTPC_HI20}, + {"%got_pcrel_lo", BFD_RELOC_NANOMIPS_GOT_LO12}, + {"%got_lo", BFD_RELOC_NANOMIPS_GOT_LO12}, + {"%got_pcrel32", BFD_RELOC_NANOMIPS_GOTPC_I32}, + {"%tlsgd", BFD_RELOC_NANOMIPS_TLS_GD}, + {"%tlsld", BFD_RELOC_NANOMIPS_TLS_LD}, + {"%dtprel", BFD_RELOC_NANOMIPS_TLS_DTPREL12}, + {"%tprel", BFD_RELOC_NANOMIPS_TLS_TPREL12}, + {"%gottprel", BFD_RELOC_NANOMIPS_TLS_GOTTPREL}, + {"%gottprel_pc32", BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32}, + /* These are currently not supported for nanoMIPS. */ + {"%call_hi", BFD_RELOC_UNUSED}, + {"%call_lo", BFD_RELOC_UNUSED} +}; + +/* Return true if *STR points to a relocation operator. When returning true, + move *STR over the operator and store its relocation code in *RELOC. + Leave both *STR and *RELOC alone when returning false. */ + +static bool +parse_relocation (char **str, bfd_reloc_code_real_type *reloc) +{ + const struct percent_op_match *percent_op; + size_t limit, i; + + percent_op = nanomips_percent_op; + limit = ARRAY_SIZE (nanomips_percent_op); + + for (i = 0; i < limit; i++) + if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) + == 0) + { + int len = strlen (percent_op[i].str); + + if (!is_end_of_stmt ((*str)[len]) + && !is_whitespace ((*str)[len]) + && (*str)[len] != '(') + continue; + + *str += strlen (percent_op[i].str); + *reloc = percent_op[i].reloc; + + /* Check whether the output BFD supports this relocation. + If not, issue an error and fall back on something safe. */ + if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc)) + { + as_bad (_("relocation %s isn't supported by the current ABI"), + percent_op[i].str); + *reloc = BFD_RELOC_UNUSED; + } + return true; + } + return false; +} + +/* Parse string STR as a 16-bit relocatable operand. Store the + expression in *EP and the relocations in the array starting + at RELOC. Return the number of relocation operators used. + + On exit, EXPR_END points to the first character after the expression. */ + +static size_t +my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, + char *str) +{ + bfd_reloc_code_real_type reversed_reloc[3]; + size_t reloc_index, i; + int crux_depth, str_depth; + char *crux; + + memset (reversed_reloc, 0, sizeof (reversed_reloc)); + /* Search for the start of the main expression, recoding relocations + in REVERSED_RELOC. End the loop with CRUX pointing to the start + of the main expression and with CRUX_DEPTH containing the number + of open brackets at that point. */ + reloc_index = -1; + str_depth = 0; + do + { + reloc_index++; + crux = str; + crux_depth = str_depth; + + /* Skip over whitespace and brackets, keeping count of the number + of brackets. */ + while (is_whitespace (*str) || *str == '(') + if (*str++ == '(') + str_depth++; + } + while (*str == '%' + && reloc_index < 1 + && parse_relocation (&str, &reversed_reloc[reloc_index])); + + my_getExpression (ep, crux); + str = expr_parse_end; + + /* Match every open bracket. */ + while (crux_depth > 0 && (*str == ')' || is_whitespace (*str))) + if (*str++ == ')') + crux_depth--; + + if (crux_depth > 0) + as_bad (_("unclosed '('")); + + expr_parse_end = str; + + for (i = 0; i < reloc_index; i++) + reloc[i] = reversed_reloc[reloc_index - 1 - i]; + + return reloc_index; +} + +static void +my_getExpression (expressionS *ep, char *str) +{ + char *save_in; + + save_in = input_line_pointer; + input_line_pointer = str; + expression (ep); + expr_parse_end = input_line_pointer; + input_line_pointer = save_in; +} + +const char * +md_atof (int type, char *litP, int *sizeP) +{ + return ieee_md_atof (type, litP, sizeP, target_big_endian); +} + +void +md_number_to_chars (char *buf, valueT val, int n) +{ + if (target_big_endian) + number_to_chars_bigendian (buf, val, n); + else + number_to_chars_littleendian (buf, val, n); +} + +static int +support_64bit_objects (void) +{ + const char **list, **l; + int yes; + + list = bfd_target_list (); + for (l = list; *l != NULL; l++) + if (strcmp (*l, ELF_NTARGET ("elf64-", "big")) == 0 + || strcmp (*l, ELF_NTARGET ("elf64-", "little")) == 0) + break; + yes = (*l != NULL); + free (list); + return yes; +} + +/* Set STRING_PTR (either &nanomips_arch_string or &nanomips_tune_string) to + NEW_VALUE. Warn if another value was already specified. Note: + we have to defer parsing the -march and -mtune arguments in order + to handle 'from-abi' correctly, since the ABI might be specified + in a later argument. */ + +static void +nanomips_set_option_string (const char **string_ptr, const char *new_value) +{ + if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0) + as_warn (_("a different %s was already specified, is now %s"), + string_ptr == &nanomips_arch_string ? "-march" : "-mtune", + new_value); + + *string_ptr = new_value; +} + +static void +nanomips_set_mcmodel (enum mc_model_type *model, const char *arg) +{ + if (strcmp (arg, "large")) + *model = MC_LARGE; + else if (strcmp (arg, "medium")) + *model = MC_LARGE; + else if (strcmp (arg, "auto")) + *model = MC_AUTO; + else + as_fatal (_("Request for unsupported memory model %s"), arg); +} + +int +md_parse_option (int c, const char *arg) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE (nanomips_ases); i++) + if (c == nanomips_ases[i].option_on || c == nanomips_ases[i].option_off) + { + file_ase_explicit |= + nanomips_set_ase (&nanomips_ases[i], &file_nanomips_opts, + c == nanomips_ases[i].option_on); + return 1; + } + + switch (c) + { + case OPTION_CONSTRUCT_FLOATS: + nanomips_disable_float_construction = 0; + break; + + case OPTION_NO_CONSTRUCT_FLOATS: + nanomips_disable_float_construction = 1; + break; + + case OPTION_TRAP: + nanomips_trap = 1; + break; + + case OPTION_BREAK: + nanomips_trap = 0; + break; + + case OPTION_EB: + target_big_endian = 1; + break; + + case OPTION_EL: + target_big_endian = 0; + break; + + case 'g': + if (arg == NULL) + nanomips_debug = 2; + else + nanomips_debug = atoi (arg); + break; + + case OPTION_MTUNE: + nanomips_set_option_string (&nanomips_tune_string, arg); + break; + + case OPTION_MARCH: + nanomips_set_option_string (&nanomips_arch_string, arg); + break; + + case OPTION_NO_MICROMIPS: + case OPTION_NO_MIPS16: + break; + + case OPTION_INSN32: + file_nanomips_opts.insn32 = true; + break; + + case OPTION_NO_INSN32: + file_nanomips_opts.insn32 = false; + break; + + case OPTION_PIC: + file_nanomips_opts.pic = SVR4_PIC; + break; + + case OPTION_NOPIC: + file_nanomips_opts.pic = NO_PIC; + break; + + case OPTION_LARGE_PIC: + file_nanomips_opts.pic = SVR4_LARGE_PIC; + break; + + case 'G': + g_switch_value = atoi (arg); + g_switch_seen = 1; + break; + + /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32 + and -mabi=64. */ + case OPTION_32: + case OPTION_64: + as_fatal (_("Request for unsupported ABI")); + break; + + case OPTION_M32: + nanomips_abi = P32_ABI; + break; + + case OPTION_M64: + nanomips_abi = P64_ABI; + if (!support_64bit_objects ()) + as_fatal (_("no compiled in support for 64 bit object file format")); + break; + + case OPTION_BALC_STUBS: + file_nanomips_opts.no_balc_stubs = false; + break; + + case OPTION_NO_BALC_STUBS: + file_nanomips_opts.no_balc_stubs = true; + break; + + case OPTION_LEGACY_REGS: + file_nanomips_opts.legacyregs = true; + break; + + case OPTION_NO_LEGACY_REGS: + file_nanomips_opts.legacyregs = false; + break; + + case OPTION_LINKRELAX: + s_linkrelax (0); + break; + + case OPTION_SINGLE_FLOAT: + file_nanomips_opts.single_float = 1; + break; + + case OPTION_DOUBLE_FLOAT: + file_nanomips_opts.single_float = 0; + break; + + case OPTION_SOFT_FLOAT: + file_nanomips_opts.soft_float = 1; + break; + + case OPTION_HARD_FLOAT: + file_nanomips_opts.soft_float = 0; + break; + + case OPTION_PCREL: + file_nanomips_opts.pcrel = true; + break; + + case OPTION_NO_PCREL: + file_nanomips_opts.pcrel = false; + break; + + case OPTION_PID: + file_nanomips_opts.pid = true; + break; + + case OPTION_NO_PID: + file_nanomips_opts.pid = false; + break; + + case OPTION_MCMODEL: + nanomips_set_mcmodel (&file_nanomips_opts.mc_model, arg); + break; + + default: + return 0; + } + + return 1; +} + +/* Set up globals to tune for the ISA or processor described by INFO. */ + +static void +nanomips_set_tune (const struct nanomips_cpu_info *info) +{ + if (info != 0) + nanomips_tune = info->cpu; +} + +void +nanomips_after_parse_args (void) +{ + const struct nanomips_cpu_info *arch_info = 0; + const struct nanomips_cpu_info *tune_info = 0; + + if (nanomips_arch_string != 0) + arch_info = nanomips_parse_cpu ("-march", nanomips_arch_string); + + if (arch_info == 0) + { + arch_info = nanomips_parse_cpu ("default CPU", + NANOMIPS_CPU_STRING_DEFAULT); + gas_assert (arch_info); + } + + if (nanomips_abi == NO_ABI) + nanomips_abi = NANOMIPS_DEFAULT_ABI; + + if (ABI_NEEDS_64BIT_REGS (nanomips_abi) + && !ISA_HAS_64BIT_REGS (arch_info->isa)) + as_bad (_("-march=%s is not compatible with the selected ABI"), + arch_info->name); + + file_nanomips_opts.arch = arch_info->cpu; + file_nanomips_opts.isa = arch_info->isa; + file_nanomips_opts.init_ase = arch_info->ase; + + /* Set up initial nanomips_opts state. */ + nanomips_opts = file_nanomips_opts; + + /* Optimize for file_nanomips_opts.arch, unless -mtune selects a different + processor. */ + if (nanomips_tune_string != 0) + tune_info = nanomips_parse_cpu ("-mtune", nanomips_tune_string); + + if (tune_info == 0) + nanomips_set_tune (arch_info); + else + nanomips_set_tune (tune_info); +} + +/* This is called before the symbol table is processed. In order to + work with gcc when using mips-tfile, we must keep all local labels. + However, in other cases, we want to discard them. If we were + called with -g, but we didn't see any debugging information, it may + mean that gcc is smuggling debugging information through to + mips-tfile, in which case we must generate all local labels. */ + +void +nanomips_frob_file_before_adjust (void) +{ +#ifndef NO_ECOFF_DEBUGGING + if (ECOFF_DEBUGGING && nanomips_debug != 0 && !ecoff_debugging_seen) + flag_keep_locals = 1; +#endif +} + +static bool +frag_in_section_p (fragS *fragp, const char *secname) +{ + asection *sec = bfd_get_section_by_name (stdoutput, secname); + + while (sec != NULL) + { + fragS *iter = seg_info (sec)->frchainP->frch_root; + while (iter != NULL) + { + if (iter == fragp) + return true; + iter = iter->fr_next; + } + sec = bfd_get_next_section_by_name (NULL, sec); + } + return false; +} + +int +nanomips_force_relocation (fixS *fixp) +{ + if (generic_force_reloc (fixp)) + return 1; + + if (linkrelax_reloc_p (fixp->fx_r_type) + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_INSN32 + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_INSN16 + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_SAVERESTORE + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_JALR32 + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_JALR16) + return 1; + + /* and for nanoMIPS expansions */ + if (pcrel_branch_reloc_p (fixp->fx_r_type) + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_PCREL_HI20 + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_PC_I32 + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_GOTPC_HI20 + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_GOTPC_I32 + || fixp->fx_r_type == BFD_RELOC_NANOMIPS_GOT_LO12) + return 1; + + if (linkrelax + && fixp->fx_subsy + && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_CODE) != 0 + && (S_GET_SEGMENT (fixp->fx_subsy)->flags & SEC_CODE) != 0) + { + /* For lable-difference relocations in .debug_info sections, we + want to force a relocation, even if the difference is link-time + invariant so that the linker has the opportunity to zero-out + AT_high_pc expressions when the corresponding sections get + garbage-collected. Spurious non-zero AT_high_pc fields of + garbage-collected sections can trip-up GDB source disassembly. */ + if (frag_in_section_p (fixp->fx_frag, ".debug_info")) + return 1; + else + return (!nanomips_allow_local_subtract_symbols (fixp->fx_addsy, + fixp->fx_subsy, + false)); + } + return 0; +} + +/* Find the size of an instruction relocated by RELOC, default to 4. */ +static unsigned int +get_reloc_size (bfd_reloc_code_real_type reloc) +{ + if (pcrel16_reloc_p (reloc)) + return 2; + else + return 4; +} + +/* Read the instruction associated with RELOC from BUF. */ + +static unsigned int +read_reloc_insn (char *buf, bfd_reloc_code_real_type reloc) +{ + return read_compressed_insn (buf, get_reloc_size (reloc)); +} + +/* Write instruction INSN to BUF, given that it has been relocated + by RELOC. */ + +static void +write_reloc_insn (char *buf, bfd_reloc_code_real_type reloc, + unsigned long insn) +{ + write_compressed_insn (buf, insn, get_reloc_size (reloc)); +} + +/* Apply a fixup to the object file. */ + +void +md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) +{ + char *buf; + unsigned long insn; + reloc_howto_type *howto = NULL; + + /* We ignore generic BFD relocations we don't know about. */ + howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); + if (! howto) + + if (fixP->fx_pcrel) + switch (fixP->fx_r_type) + { + case BFD_RELOC_NANOMIPS_PC_I32: + case BFD_RELOC_NANOMIPS_GOTPC_HI20: + case BFD_RELOC_NANOMIPS_GOTPC_I32: + case BFD_RELOC_NANOMIPS_GOT_LO12: + case BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32: + break; + + case BFD_RELOC_8: + fixP->fx_r_type = BFD_RELOC_8_PCREL; + break; + } + + if (linkrelax_reloc_p (fixP->fx_r_type) + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_INSN32 + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_INSN16 + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_SAVERESTORE + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_JALR32 + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_JALR16) + { + fixP->fx_addnumber = *valP; + return; + } + + gas_assert (fixP->fx_size == 2 + || fixP->fx_size == 4 + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_I32 + || fixP->fx_r_type == BFD_RELOC_8 + || fixP->fx_r_type == BFD_RELOC_16 + || fixP->fx_r_type == BFD_RELOC_64 + || fixP->fx_r_type == BFD_RELOC_CTOR + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_NEG + || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_UNSIGNED_8 + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_SIGNED_8 + || fixP->fx_r_type == BFD_RELOC_NANOMIPS_ASHIFTR_1 + || (fixP->fx_size == 1 && fixP->fx_r_type == BFD_RELOC_32)); + + buf = fixP->fx_frag->fr_literal + fixP->fx_where; + + /* Don't treat parts of a composite relocation as done. There are two + reasons for this: + + (1) The second and third parts will be against 0 (RSS_UNDEF) but + should nevertheless be emitted if the first part is. + + (2) In normal usage, composite relocations are never assembly-time + constants. The easiest way of dealing with the pathological + exceptions is to generate a relocation against STN_UNDEF and + leave everything up to the linker. */ + if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0) + fixP->fx_done = 1; + + switch (fixP->fx_r_type) + { + case BFD_RELOC_NANOMIPS_TLS_DTPREL: + case BFD_RELOC_NANOMIPS_TLS_TPREL: + case BFD_RELOC_NANOMIPS_TLS_GD: + case BFD_RELOC_NANOMIPS_TLS_LD: + case BFD_RELOC_NANOMIPS_TLS_GD_I32: + case BFD_RELOC_NANOMIPS_TLS_LD_I32: + case BFD_RELOC_NANOMIPS_TLS_DTPREL12: + case BFD_RELOC_NANOMIPS_TLS_DTPREL16: + case BFD_RELOC_NANOMIPS_TLS_DTPREL_I32: + case BFD_RELOC_NANOMIPS_TLS_TPREL12: + case BFD_RELOC_NANOMIPS_TLS_TPREL16: + case BFD_RELOC_NANOMIPS_TLS_TPREL_I32: + case BFD_RELOC_NANOMIPS_TLS_GOTTPREL: + case BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32: + if (!fixP->fx_addsy) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("TLS relocation against a constant")); + break; + } + S_SET_THREAD_LOCAL (fixP->fx_addsy); + /* fall through */ + + case BFD_RELOC_HI16: + case BFD_RELOC_HI16_S: + case BFD_RELOC_LO16: + case BFD_RELOC_GPREL16: + case BFD_RELOC_GPREL32: + case BFD_RELOC_NANOMIPS_EH: + case BFD_RELOC_NANOMIPS_NEG: + case BFD_RELOC_NANOMIPS_GOT_CALL: + case BFD_RELOC_NANOMIPS_GOT_DISP: + case BFD_RELOC_NANOMIPS_GOT_PAGE: + case BFD_RELOC_NANOMIPS_GOT_OFST: + case BFD_RELOC_NANOMIPS_GPREL19_S2: + case BFD_RELOC_NANOMIPS_GPREL18_S3: + case BFD_RELOC_NANOMIPS_GPREL18: + case BFD_RELOC_NANOMIPS_GPREL16_S2: + case BFD_RELOC_NANOMIPS_GPREL7_S2: + case BFD_RELOC_NANOMIPS_GPREL17_S1: + case BFD_RELOC_NANOMIPS_GOT_LO12: + if (fixP->fx_done) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("unsupported constant in relocation")); + break; + + case BFD_RELOC_64: + /* This is handled like BFD_RELOC_32, but we output a sign + extended value if we are only 32 bits. */ + if (fixP->fx_done) + { + if (8 <= sizeof (valueT)) + md_number_to_chars (buf, *valP, 8); + else + { + valueT hiv; + + if ((*valP & 0x80000000) != 0) + hiv = 0xffffffff; + else + hiv = 0; + md_number_to_chars (buf + (target_big_endian ? 4 : 0), + *valP, 4); + md_number_to_chars (buf + (target_big_endian ? 0 : 4), hiv, 4); + } + } + break; + + case BFD_RELOC_RVA: + case BFD_RELOC_32: + case BFD_RELOC_32_PCREL: + case BFD_RELOC_16: + case BFD_RELOC_8: + case BFD_RELOC_NANOMIPS_UNSIGNED_8: + case BFD_RELOC_NANOMIPS_UNSIGNED_16: + case BFD_RELOC_NANOMIPS_SIGNED_8: + case BFD_RELOC_NANOMIPS_SIGNED_16: + /* If we are deleting this reloc entry, we must fill in the + value now. This can happen if we have a .word which is not + resolved when it appears but is later defined. */ + if (fixP->fx_done) + md_number_to_chars (buf, *valP, fixP->fx_size); + break; + + case BFD_RELOC_NANOMIPS_ASHIFTR_1: + if (fixP->fx_done) + *valP = (*valP >> 1); + break; + + case BFD_RELOC_NANOMIPS_HI20: + case BFD_RELOC_NANOMIPS_GPREL_HI20: + if (!fixP->fx_done) + break; + + insn = read_reloc_insn (buf, fixP->fx_r_type); + + insn |= ((*valP >> 12) & 0x1ff) << 12 + | ((*valP >> 21) & 0x3ff) << 2 + | ((*valP >> 31) & 1); + + write_reloc_insn (buf, fixP->fx_r_type, insn); + break; + + case BFD_RELOC_NANOMIPS_I32: + case BFD_RELOC_NANOMIPS_GPREL_I32: + if (fixP->fx_done) + write_compressed_insn (buf, *valP & 0xffffffff, 4); + break; + + case BFD_RELOC_NANOMIPS_LO12: + case BFD_RELOC_NANOMIPS_GPREL_LO12: + if (fixP->fx_done) + { + insn = read_reloc_insn (buf, fixP->fx_r_type); + insn |= *valP & 0xfff; + write_reloc_insn (buf, fixP->fx_r_type, insn); + } + break; + + case BFD_RELOC_NANOMIPS_LO4_S2: + if (fixP->fx_done) + { + if ((*valP & 0xfc3) != 0) + as_bad_where (fixP->fx_file, fixP->fx_line, + _("offset out of range (0x%lx)"), + (long) fixP->fx_offset); + insn = read_reloc_insn (buf, fixP->fx_r_type); + insn |= (*valP >> 2) & 0xf; + write_reloc_insn (buf, fixP->fx_r_type, insn); + } + break; + + case BFD_RELOC_NANOMIPS_NEG12: + if (fixP->fx_done) + { + insn = read_reloc_insn (buf, fixP->fx_r_type); + insn |= (-*valP) & 0xfff; + write_reloc_insn (buf, fixP->fx_r_type, insn); + } + break; + + case BFD_RELOC_NANOMIPS_IMM16: + if (fixP->fx_done) + { + insn = read_reloc_insn (buf, fixP->fx_r_type); + insn |= *valP & 0xffff; + write_reloc_insn (buf, fixP->fx_r_type, insn); + } + break; + + case BFD_RELOC_NANOMIPS_PC_I32: + case BFD_RELOC_NANOMIPS_PCREL_HI20: + case BFD_RELOC_NANOMIPS_GOTPC_I32: + case BFD_RELOC_NANOMIPS_GOTPC_HI20: + gas_assert (!fixP->fx_done); + break; + + case BFD_RELOC_NANOMIPS_4_PCREL_S1: + case BFD_RELOC_NANOMIPS_7_PCREL_S1: + case BFD_RELOC_NANOMIPS_10_PCREL_S1: + case BFD_RELOC_NANOMIPS_11_PCREL_S1: + case BFD_RELOC_NANOMIPS_14_PCREL_S1: + case BFD_RELOC_NANOMIPS_21_PCREL_S1: + case BFD_RELOC_NANOMIPS_25_PCREL_S1: + if (!fixP->fx_done) + break; + + case BFD_RELOC_VTABLE_INHERIT: + fixP->fx_done = 0; + if (fixP->fx_addsy + && !S_IS_DEFINED (fixP->fx_addsy) + && !S_IS_WEAK (fixP->fx_addsy)) + S_SET_WEAK (fixP->fx_addsy); + break; + + case BFD_RELOC_VTABLE_ENTRY: + fixP->fx_done = 0; + break; + + default: + abort (); + } + + /* Remember value for tc_gen_reloc. */ + fixP->fx_addnumber = *valP; +} + +static symbolS * +get_symbol (void) +{ + int c; + char *name; + symbolS *p; + + c = get_symbol_name (&name); + p = symbol_find_or_make (name); + (void) restore_line_pointer (c); + return p; +} + +/* Create R_NANOMIPS_ALIGN to record the alignment request. Value of the + absolute symbol gives alignment requested. The relocation is created at + the start of padding bytes. Create R_NANOMIPS_FILL and R_NANOMIPS_MAX + to record fill value and maximum alignment respectively. */ + +static void +create_align_relocs (fragS *fragp, int align_to, unsigned int fill_value, + int fill_length, int max_fill) +{ + static int symidx = 1; + symbolS *sym; + char sname[30]; + fixS *fixp; + int where; + + if (fragp == frag_now) + where = frag_now_fix (); + else + where = fragp->fr_fix; + + /* The '\2' ensures that no other symbol will get the + same name as this. */ + sprintf (sname, "__reloc_align_\2_%d", symidx++); + sym = symbol_find (sname); + sym = symbol_new (sname, absolute_section, &zero_address_frag, align_to); + symbol_table_insert (sym); + + fixp = fix_new (fragp, where, 0, sym, 0, false, BFD_RELOC_NANOMIPS_ALIGN); + if (fragp->tc_frag_data == NULL) + fragp->tc_frag_data = fixp; + + /* Generate fill reloc. Default fill value is nop32. */ + if (fill_length) + { + sprintf (sname, "__reloc_fill_\2_%x", fill_value); + sym = symbol_find (sname); + if (sym == NULL) + { + sym = symbol_new (sname, absolute_section, &zero_address_frag, fill_value); + symbol_table_insert (sym); + elf_symbol (symbol_get_bfdsym (sym))->internal_elf_sym.st_size + = fill_length; + } + + fix_new (fragp, where, 0, sym, 0, false, BFD_RELOC_NANOMIPS_FILL); + } + + /* Generate max reloc. */ + if (max_fill != 0) + { + sprintf (sname, "__reloc_max_\2_%x", max_fill); + sym = symbol_find (sname); + if (sym == NULL) + { + sym = symbol_new (sname, absolute_section, &zero_address_frag, max_fill); + symbol_table_insert (sym); + } + fix_new (fragp, where, 0, sym, 0, false, BFD_RELOC_NANOMIPS_MAX); + } +} + +/* Align the current frag to a given power of two. If a particular + fill byte should be used, FILL points to an integer that contains + that byte, otherwise FILL is null. */ + +static void +nanomips_align (int to, int *fill, symbolS *label) +{ + nanomips_flush_pending_output (); + struct insn_label_list *l; + + if (fill == NULL && subseg_text_p (now_seg)) + frag_align_code (to, 0); + else + frag_align (to, fill ? *fill : 0, 0); + record_alignment (now_seg, to); + if (label != NULL) + { + gas_assert (S_GET_SEGMENT (label) == now_seg); + symbol_set_frag (label, frag_now); + S_SET_VALUE (label, (valueT) frag_now_fix ()); + } +} + +/* Align to a given power of two. .align 0 turns off the automatic + alignment used by the data creating pseudo-ops. */ + +static void +s_align (int x ATTRIBUTE_UNUSED) +{ + int temp, fill_value, *fill_ptr; + long max_alignment = 15; + + /* Note that the assembler pulls down any immediately preceding label + to the aligned address. */ + + temp = get_absolute_expression (); + if (temp > max_alignment) + as_bad (_("alignment too large, %d assumed"), temp = max_alignment); + else if (temp < 0) + { + as_warn (_("alignment negative, 0 assumed")); + temp = 0; + } + if (*input_line_pointer == ',') + { + ++input_line_pointer; + fill_value = get_absolute_expression (); + fill_ptr = &fill_value; + } + else + fill_ptr = 0; + if (temp) + { + segment_info_type *si = seg_info (now_seg); + struct insn_label_list *l = si->label_list; + + if (nanomips_linkrelax_p + && (bfd_section_flags (now_seg) & SEC_CODE) != 0 + && temp > 1) + { + int fill_length = 0; + + if (fill_ptr == NULL && subseg_text_p (now_seg)) + frag_grow (MAX_MEM_FOR_RS_ALIGN_CODE(p2align, max)); + else + { + fill_length = 1; + frag_grow (1); + } + + create_align_relocs (frag_now, temp, fill_value, fill_length, 0); + } + + /* Auto alignment should be switched on by next section change. */ + auto_align = 1; + nanomips_align (temp, fill_ptr, l != NULL ? l->label : NULL); + } + else + { + auto_align = 0; + } + demand_empty_rest_of_line (); +} + +static void +s_change_sec (int sec) +{ + segT seg; + + if ((now_seg->flags & SHF_EXECINSTR) != 0 + && stub_funcless_mode + && !nanomips_opts.no_balc_stubs + && stubg_now != NULL) + { + stub_funcless_mode = false; + stubgroup_wane (); + } + + /* The ELF backend needs to know that we are changing sections, so + that .previous works correctly. We could do something like check + for an obj_section_change_hook macro, but that might be confusing + as it would not be appropriate to use it in the section changing + functions in read.c, since obj-elf.c intercepts those. FIXME: + This should be cleaner, somehow. */ + obj_elf_section_change_hook (); + + nanomips_flush_pending_output (); + + switch (sec) + { + case 't': + s_text (0); + break; + case 'd': + s_data (0); + break; + case 'b': + subseg_set (bss_section, (subsegT) get_absolute_expression ()); + demand_empty_rest_of_line (); + break; + + case 'r': + seg = subseg_new (RDATA_SECTION_NAME, + get_absolute_expression ()); + bfd_set_section_flags (seg, (SEC_ALLOC | SEC_LOAD + | SEC_READONLY | SEC_RELOC + | SEC_DATA)); + if (strncmp (TARGET_OS, "elf", 3) != 0) + record_alignment (seg, 4); + demand_empty_rest_of_line (); + break; + + case 's': + seg = subseg_new (".sdata", get_absolute_expression ()); + bfd_set_section_flags (seg, + SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA); + if (strncmp (TARGET_OS, "elf", 3) != 0) + record_alignment (seg, 4); + demand_empty_rest_of_line (); + break; + + case 'B': + seg = subseg_new (".sbss", get_absolute_expression ()); + bfd_set_section_flags (seg, SEC_ALLOC); + if (strncmp (TARGET_OS, "elf", 3) != 0) + record_alignment (seg, 4); + demand_empty_rest_of_line (); + break; + } + auto_align = 1; +} + +void +s_change_section (int ignore ATTRIBUTE_UNUSED) +{ + char *saved_ilp; + const char *section_name; + char c, next_c = 0; + int section_type; + int section_flag; + int section_entry_size; + + saved_ilp = input_line_pointer; + section_name = obj_elf_section_name (); + if (section_name == NULL) + return; + c = input_line_pointer[0]; + if (c) + next_c = input_line_pointer[1]; + + if ((now_seg->flags & SHF_EXECINSTR) != 0 + && stub_funcless_mode + && !nanomips_opts.no_balc_stubs + && stubg_now != NULL) + { + stub_funcless_mode = false; + stubgroup_wane (); + } + + /* Do we have .section Name<,"flags">? */ + if (c != ',' || (c == ',' && next_c == '"')) + { + input_line_pointer = saved_ilp; + obj_elf_section (ignore); + return; + } + input_line_pointer++; + + /* Do we have .section Name<,type><,flag><,entry_size><,alignment> */ + if (c == ',') + section_type = get_absolute_expression (); + else + section_type = 0; + if (*input_line_pointer++ == ',') + section_flag = get_absolute_expression (); + else + section_flag = 0; + if (*input_line_pointer++ == ',') + section_entry_size = get_absolute_expression (); + else + section_entry_size = 0; + + section_name = xstrdup (section_name); + + if ((now_seg->flags & SHF_EXECINSTR) != 0 + && stub_funcless_mode + && !nanomips_opts.no_balc_stubs + && stubg_now != NULL) + { + stub_funcless_mode = false; + stubgroup_wane (); + } + obj_elf_change_section (section_name, section_type, section_flag, + section_entry_size, 0, false); +} + +void +nanomips_enable_auto_align (void) +{ + auto_align = 1; +} + +static void +s_cons (int log_size) +{ + segment_info_type *si = seg_info (now_seg); + struct insn_label_list *l = si->label_list; + symbolS *label; + + label = l != NULL ? l->label : NULL; + nanomips_flush_pending_output (); + if (log_size > 0 + && auto_align) + nanomips_align (log_size, 0, label); + cons (1 << log_size); + nanomips_clear_insn_labels (); +} + +static void +s_sign_cons (int log_size) +{ + sign_cons = true; + s_cons (log_size); + sign_cons = false; +} + +static void +s_float_cons (int type) +{ + segment_info_type *si = seg_info (now_seg); + struct insn_label_list *l = si->label_list; + symbolS *label; + + label = l != NULL ? l->label : NULL; + nanomips_flush_pending_output (); + + if (auto_align) + { + if (type == 'd') + nanomips_align (3, 0, label); + else + nanomips_align (2, 0, label); + } + float_cons (type); + nanomips_clear_insn_labels (); +} + +/* This structure is used to hold a stack of .set values. */ + +struct nanomips_option_stack +{ + struct nanomips_option_stack *next; + struct nanomips_set_options options; +}; + +static struct nanomips_option_stack *nanomips_opts_stack; + +static bool +parse_code_option (char *name) +{ + const struct nanomips_ase *ase; + if (strcmp (name, "at") == 0) + nanomips_opts.noat = 0; + else if (strcmp (name, "noat") == 0) + nanomips_opts.noat = 1; + else if (strcmp (name, "softfloat") == 0) + nanomips_opts.soft_float = 1; + else if (strcmp (name, "hardfloat") == 0) + nanomips_opts.soft_float = 0; + else if (strcmp (name, "singlefloat") == 0) + nanomips_opts.single_float = 1; + else if (strcmp (name, "doublefloat") == 0) + nanomips_opts.single_float = 0; + else if (strcmp (name, "nooddspreg") == 0) + as_bad (_("nanoMIPS allows odd single-precision FP registers")); + else if (strcmp (name, "mips16") == 0 || strcmp (name, "MIPS-16") == 0) + as_bad (_("nanoMIPS does not support MIPS16 ASE")); + else if (strcmp (name, "micromips") == 0) + as_bad (_("micromips is incompatible with nanoMIPS")); + else if (name[0] == 'n' + && name[1] == 'o' + && (ase = nanomips_lookup_ase (name + 2))) + nanomips_set_ase (ase, &nanomips_opts, false); + else if ((ase = nanomips_lookup_ase (name))) + nanomips_set_ase (ase, &nanomips_opts, true); + else if (strncmp (name, "mips", 4) == 0) + as_bad (_("cannot change ISA from nanoMIPS to %s"), name); + else if (strncmp (name, "arch=mips", 9) == 0) + as_bad (_("cannot change ISA from nanoMIPS to %s"), name + 5); + else if (strncmp (name, "arch=", 5) == 0) + { + /* Permit the user to change the ISA and architecture on the fly. + Needless to say, misuse can cause serious problems. */ + const struct nanomips_cpu_info *p; + + p = nanomips_parse_cpu ("internal use", name + 5); + if (!p) + as_bad (_("unknown architecture %s"), name + 5); + else + { + nanomips_opts.arch = p->cpu; + nanomips_opts.isa = p->isa; + nanomips_opts.init_ase = p->ase; + } + } + else if (strcmp (name, "insn32") == 0) + nanomips_opts.insn32 = true; + else if (strcmp (name, "noinsn32") == 0) + nanomips_opts.insn32 = false; + else if (strncmp (name, "mcmodel=", 8) == 0) + { + if (strcmp (name + 8, "auto") == 0) + nanomips_opts.mc_model = MC_AUTO; + else if (strcmp (name + 8, "medium") == 0) + nanomips_opts.mc_model = MC_MEDIUM; + else if (strcmp (name + 8, "large") == 0) + nanomips_opts.mc_model = MC_LARGE; + else + as_bad (_("invalid memory model setting %s"), name); + } + else if (strncmp (name, "pic", 3) == 0) + { + int i = atoi (name + 3); + if (i == 0) + nanomips_opts.pic = NO_PIC; + else if (i == 1) + nanomips_opts.pic = SVR4_PIC; + else if (i == 2) + nanomips_opts.pic = SVR4_LARGE_PIC; + else + as_bad (_(".set pic%d not supported"), i); + } + else if (strcmp (name, "nopic") == 0) + nanomips_opts.pic = NO_PIC; + else if (strcmp (name, "pid") == 0) + nanomips_opts.pid = true; + else if (strcmp (name, "nopic") == 0) + nanomips_opts.pid = false; + else if (strcmp (name, "pcrel") == 0) + nanomips_opts.pcrel = true; + else if (strcmp (name, "nopcrel") == 0) + nanomips_opts.pcrel = false; + else + return (strcmp (name, "oddspreg") == 0 + || strcmp (name, "nomips16") == 0 + || strcmp (name, "noMIPS-16") == 0 + || strcmp (name, "nomicromips") == 0 + || strcmp (name, "nobopt") == 0 + || strcmp (name, "noforbidden-slots") == 0 + || strcmp (name, "move") == 0 + || strcmp (name, "nomove") == 0 + || strcmp (name, "novolatile") == 0 + || strcmp (name, "volatile") == 0); + + return true; +} + +/* Handle the .set pseudo-op. */ + +static void +s_nanomipsset (int x ATTRIBUTE_UNUSED) +{ + char *name = input_line_pointer, ch; + int prev_isa = nanomips_opts.isa; + + file_check_options (); + + while (!is_end_of_stmt (*input_line_pointer)) + ++input_line_pointer; + ch = *input_line_pointer; + *input_line_pointer = '\0'; + + if (strchr (name, ',')) + { + /* Generic ".set" directive; use the generic handler. */ + *input_line_pointer = ch; + input_line_pointer = name; + s_set (0); + return; + } + + if (strcmp (name, "reorder") == 0) + { + if (nanomips_opts.noreorder) + end_noreorder (); + } + else if (strcmp (name, "noreorder") == 0) + { + if (!nanomips_opts.noreorder) + start_noreorder (); + } + else if (strcmp (name, "macro") == 0) + nanomips_opts.nomacro = 0; + else if (strcmp (name, "nomacro") == 0) + nanomips_opts.nomacro = 1; + else if (strcmp (name, "arch=default") == 0) + { + nanomips_opts.isa = file_nanomips_opts.isa; + nanomips_opts.arch = file_nanomips_opts.arch; + nanomips_opts.init_ase = file_nanomips_opts.init_ase; + nanomips_opts.gp = file_nanomips_opts.gp; + nanomips_opts.fp = file_nanomips_opts.fp; + } + else if (strcmp (name, "push") == 0) + { + struct nanomips_option_stack *s; + + s = (struct nanomips_option_stack *) xmalloc (sizeof *s); + s->next = nanomips_opts_stack; + s->options = nanomips_opts; + nanomips_opts_stack = s; + } + else if (strcmp (name, "pop") == 0) + { + struct nanomips_option_stack *s; + + s = nanomips_opts_stack; + if (s == NULL) + as_bad (_(".set pop with no .set push")); + else + { + /* If we're changing the reorder mode we need to handle + delay slots correctly. */ + if (s->options.noreorder && !nanomips_opts.noreorder) + start_noreorder (); + else if (!s->options.noreorder && nanomips_opts.noreorder) + end_noreorder (); + + nanomips_opts = s->options; + nanomips_opts_stack = s->next; + free (s); + } + } + else if (strcmp (name, "nolinkrelax") == 0) + toggle_linkrelax_p = (linkrelax && nanomips_linkrelax_p); + else if (strcmp (name, "linkrelax") == 0) + toggle_linkrelax_p = (linkrelax && !nanomips_linkrelax_p); + else if (strcmp (name, "legacyregs") == 0) + nanomips_opts.legacyregs = true; + else if (strcmp (name, "nolegacyregs") == 0) + nanomips_opts.legacyregs = false; + else if (!parse_code_option (name)) + as_warn (_("tried to set unrecognized symbol: %s\n"), name); + + /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp + registers based on what is supported by the arch/cpu. */ + if (nanomips_opts.isa != prev_isa) + { + switch (nanomips_opts.isa) + { + case 0: + break; + case ISA_NANOMIPS32R6: + nanomips_opts.gp = 32; + nanomips_opts.fp = 64; + break; + case ISA_NANOMIPS64R6: + nanomips_opts.gp = 64; + nanomips_opts.fp = 64; + break; + default: + as_bad (_("unknown ISA level %s"), name + 4); + break; + } + } + check_isa_supports_ases (); + *input_line_pointer = ch; + demand_empty_rest_of_line (); +} + +/* Handle the .module pseudo-op. */ + +static void +s_module (int ignore ATTRIBUTE_UNUSED) +{ + char *name = input_line_pointer, ch; + + while (!is_end_of_stmt (*input_line_pointer)) + ++input_line_pointer; + ch = *input_line_pointer; + *input_line_pointer = '\0'; + + if (!file_nanomips_opts_checked) + { + if (!parse_code_option (name)) + as_bad (_(".module used with unrecognized symbol: %s\n"), name); + + /* Update module level settings from nanomips_opts. */ + file_nanomips_opts = nanomips_opts; + } + else + as_bad (_(".module is not permitted after generating code")); + + *input_line_pointer = ch; + demand_empty_rest_of_line (); +} + +/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is: + .cpsetup $reg1, offset|$reg2, label */ + +static void +s_cpsetup (int ignore ATTRIBUTE_UNUSED) +{ + expressionS ex; + file_check_options (); + + /* If we are not generating SVR4 PIC code, .cpsetup is ignored. */ + if (nanomips_opts.pic == NO_PIC) + { + s_ignore (0); + return; + } + + ex.X_op = O_symbol; + ex.X_add_symbol = symbol_find_or_make ("_gp"); + ex.X_op_symbol = NULL; + ex.X_add_number = 0; + symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT; + + macro_start (); + macro_pcrel_la (nanomips_gp_register, &ex, BFD_RELOC_UNUSED); + macro_end (true); + ignore_rest_of_line (); + + return; +} + +/* Handle a .dtprelword, .dtpreldword, .tprelword, or .tpreldword + pseudo-op; DIRSTR says which. The pseudo-op generates a BYTES-size + DTP- or TP-relative relocation of type RTYPE, for use in DWARF + debug information. */ + +static void +s_tls_rel_directive (const size_t bytes, const char *dirstr, + bfd_reloc_code_real_type rtype) +{ + expressionS ex; + char *p; + + expression (&ex); + + if (ex.X_op != O_symbol) + { + as_bad (_("unsupported use of %s"), dirstr); + ignore_rest_of_line (); + } + + p = frag_more (bytes); + md_number_to_chars (p, 0, bytes); + fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false, rtype); + demand_empty_rest_of_line (); +} + +/* Handle .dtprelword. */ + +static void +s_dtprelword (int ignore ATTRIBUTE_UNUSED) +{ + s_tls_rel_directive (4, ".dtprelword", BFD_RELOC_NANOMIPS_TLS_DTPREL); +} + +/* Handle .dtpreldword. */ + +static void +s_dtpreldword (int ignore ATTRIBUTE_UNUSED) +{ + s_tls_rel_directive (8, ".dtpreldword", BFD_RELOC_NANOMIPS_TLS_DTPREL); +} + +/* Handle the .ehword pseudo-op. This is used when generating unwinding + tables. It generates a PC32 reloc. */ + +static void +s_ehword (int ignore ATTRIBUTE_UNUSED) +{ + expressionS ex; + char *p; + + nanomips_flush_pending_output (); + + expression (&ex); + nanomips_clear_insn_labels (); + + if (ex.X_op != O_symbol || ex.X_add_number != 0) + { + as_bad (_("unsupported use of .ehword")); + ignore_rest_of_line (); + } + + p = frag_more (4); + md_number_to_chars (p, 0, 4); + fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, false, + BFD_RELOC_NANOMIPS_EH); + + demand_empty_rest_of_line (); +} + +/* Handle the .insn pseudo-op, retained for compatibility. */ + +static void +s_insn (int ignore ATTRIBUTE_UNUSED) +{ + demand_empty_rest_of_line (); +} + +/* Parse a register string into a number. Called from the ECOFF code + to parse .frame. The argument is non-zero if this is the frame + register, so that we can record it in nanomips_frame_reg. */ + +int +tc_get_register (int frame ATTRIBUTE_UNUSED) +{ + unsigned int reg; + + SKIP_WHITESPACE (); + if (!reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, ®)) + reg = 0; + + return reg; +} + +/* Utility routine, called from above as well. If called while the + input file is still being read, it's only an approximation. (For + example, a symbol may later become defined which appeared to be + undefined earlier.) */ + +static int +nopic_need_relax (symbolS *sym, int before_relaxing) +{ + if (sym == 0) + return 0; + + if (g_switch_value > 0) + { + const char *symname; + int change; + + /* Find out whether this symbol can be referenced off the $gp + register. It can be if it is smaller than the -G size or if + it is in the .sdata or .sbss section. Certain symbols can + not be referenced off the $gp, although it appears as though + they can. */ + symname = S_GET_NAME (sym); + if (symname != (const char *) NULL + && (strcmp (symname, "eprol") == 0 + || strcmp (symname, "etext") == 0 + || strcmp (symname, "_gp") == 0 + || strcmp (symname, "edata") == 0 + || strcmp (symname, "_fbss") == 0 + || strcmp (symname, "_fdata") == 0 + || strcmp (symname, "_ftext") == 0 + || strcmp (symname, "end") == 0 + || strcmp (symname, "_gp_disp") == 0)) + change = 1; + else if ((! S_IS_DEFINED (sym) || S_IS_COMMON (sym)) + && (0 +#ifndef NO_ECOFF_DEBUGGING + || (symbol_get_obj (sym)->ecoff_extern_size != 0 + && (symbol_get_obj (sym)->ecoff_extern_size + <= g_switch_value)) +#endif + /* We must defer this decision until after the whole + file has been read, since there might be a .extern + after the first use of this symbol. */ + || (before_relaxing +#ifndef NO_ECOFF_DEBUGGING + && symbol_get_obj (sym)->ecoff_extern_size == 0 +#endif + && S_GET_VALUE (sym) == 0) + || (S_GET_VALUE (sym) != 0 + && S_GET_VALUE (sym) <= g_switch_value))) + change = 0; + else + { + const char *segname; + segname = segment_name (S_GET_SEGMENT (sym)); + change = (strcmp (segname, ".sdata") != 0 + && strcmp (segname, ".sbss") != 0 + && strncmp (segname, ".sdata.", 7) != 0 + && strncmp (segname, ".sbss.", 6) != 0 + && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0 + && strncmp (segname, ".gnu.linkonce.s.", 16) != 0); + } + return change; + } + else + /* We are not optimizing for the $gp register. */ + return 1; +} + +/* Return true if the given symbol should be considered local for SVR4 PIC. */ + +static bool +pic_need_relax (symbolS *sym, asection *segtype) +{ + asection *symsec; + + if (nanomips_opts.mc_model == MC_AUTO && linkrelax) + return false; + + /* Handle the case of a symbol equated to another symbol. */ + while (symbol_equated_reloc_p (sym)) + { + symbolS *n; + + /* It's possible to get a loop here in a badly written program. */ + n = symbol_get_value_expression (sym)->X_add_symbol; + if (n == sym) + break; + sym = n; + } + + if (symbol_section_p (sym)) + return true; + + symsec = S_GET_SEGMENT (sym); + + /* This must duplicate the test in adjust_reloc_syms. */ + return (!bfd_is_und_section (symsec) + && !bfd_is_abs_section (symsec) + && !bfd_is_com_section (symsec) + && !s_is_linkonce (sym, segtype) + /* A global or weak symbol is treated as external. */ + && !S_IS_WEAK (sym) + && !S_IS_EXTERNAL (sym)); +} + +/* Check if relocation in HEAD refers to an address immediately following + instruction in an adjacent frag. 16-bit conditional branches cannot + reach the immediate next instruction and must be relaxed. */ +static bool +nanomips_frag_match (fragS *head, fragS *matchP) +{ + bfd_vma val = S_GET_VALUE (head->fr_symbol); + + /* Typically, a match is as easy as checking that the frags are adjacent + and the symbol refered to is at the very beginning of the target frag. */ + if (matchP == head->fr_next && val == matchP->fr_address) + return true; + + /* The tricky part: when doing assembly listings all sorts of fillers are + generated between what would be adjacent frags. So we need to look + through the frag list, until we come to a non-empty frag that either + matches or exceeds our target. */ + if (listing) + { + head = head->fr_next; + while (head && head != matchP && head->fr_fix + head->fr_var == 0) + { + /* Unlikely, but just in case we came too far, bail out! */ + if (head->fr_line > matchP->fr_line) + break; + else + head = head->fr_next; + } + + return (head == matchP); + } + return false; +} + +/* Check if a frag is variable due to explicit relocations. */ + +static bool +reloc_variable_frag_p (fragS *fragp, asection *sec) +{ + struct reloc_list *rp; + /* Trivial for frags that are already marked. */ + if (fragp->tc_frag_data) + return true; + + rp = reloc_list; + + /* Now look for fixups in the explicit relocation list. + Update tc_frag_data.link_var here and now so the iteration doesn't + have to be repeated, at least for this frag. */ + if (rp != NULL + && symbol_get_frag (rp->u.a.offset_sym) == fragp) + { + fragp->tc_frag_data = 1; + return true; + } + return false; +} + +/* Compute the length of a branch, and adjust the RELAX_MD_TOOFAR16 + bit accordingly. */ + +static int +relaxed_16bit_branch_length (fragS *fragp, asection *sec, int update) +{ + bool toofar; + + if (fragp + && fragp->fr_symbol + && S_IS_DEFINED (fragp->fr_symbol) + && !S_IS_WEAK (fragp->fr_symbol) + && sec == S_GET_SEGMENT (fragp->fr_symbol)) + { + addressT addr; + offsetT val; + int type; + + val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; + + /* Assume this is a 2-byte branch. */ + addr = fragp->fr_address + fragp->fr_fix + 2; + + val -= addr; + + type = RELAX_MD_TYPE (fragp->fr_subtype); + if (type == RT_BRANCH_UCND || type == RT_BALC_STUB) + toofar = val < -(0x200 << 1) || val >= (0x200 << 1); + else if (type == RT_BRANCH_CNDZ) + toofar = val < -(0x40 << 1) || val >= (0x40 << 1); + else if (type == RT_BRANCH_CND) + toofar = (val <= 0 + || val > 30 + || (val == 2 + && RELAX_MD_TOOFAR16 (fragp->fr_subtype) + && nanomips_frag_match (fragp, symbol_get_frag + (fragp->fr_symbol)))); + else + abort (); + } + else + /* If the symbol is not defined or it's in a different segment, + we emit a normal 32-bit branch. */ + toofar = true; + + if (fragp && update + && toofar != RELAX_MD_TOOFAR16 (fragp->fr_subtype)) + fragp->fr_subtype + = (toofar + ? RELAX_MD_MARK_TOOFAR16 (fragp->fr_subtype) + : RELAX_MD_CLEAR_TOOFAR16 (fragp->fr_subtype)); + + if (toofar) + return 4; + + return 2; +} + +/* Compute the length of a call potentially going through a BALC stub + and adjust the RELAX_MD_USESTUB bit accordingly. */ + +static int +relaxed_stub_call_length (fragS *fragp, asection *sec, bool toofar16, + bool update) +{ + bool usestub = false; + bool keepstub = false; + addressT callsite; + struct balc_stub *stub = NULL; + + /* Assume this is a 2-byte branch. */ + callsite = fragp->fr_address + fragp->fr_fix; + + /* Find start of correct stub-group list, if in different section or + at end of current list. */ + if ((stubg_now->seg != sec) + || (stubg_now->prev != NULL + && stubg_now->prev->fragp != NULL + && callsite < stubg_now->prev->fragp->fr_address)) + stubg_now = str_hash_find (balc_stubgroup_table, sec->name); + + /* This is for ugly cases of hand-written assembly where the + order of .ent and .section directives is reversed. */ + if (stubg_now == NULL || stubg_now->fragp == NULL) + return (toofar16 ? 4 : 2); + + while (stubg_now->fragp->fr_address + stubg_now->fragp->fr_fix > 0 + && stubg_now->fragp->fr_address + stubg_now->fragp->fr_fix < callsite) + if (stubg_now->next != NULL && stubg_now->next->fragp != NULL) + stubg_now = stubg_now->next; + else + break; + + gas_assert (stubg_now->seg == sec); + + usestub = balc_find_stub_inrange (S_GET_NAME (fragp->fr_symbol), + callsite, stubg_now, &stub); + + if (usestub && stub->fragp != NULL) + keepstub = RELAX_MD_KEEPSTUB (stub->fragp->fr_subtype); + + /* We need this to happen only once per call frag, but as early as + possible in the estimation phase, before actual relaxation. */ + if (usestub && !toofar16) + { + usestub = false; + if (RELAX_MD_ONCESTUB (fragp->fr_subtype)) + { + fragp->fr_subtype + = RELAX_MD_CLEAR_ONCESTUB (fragp->fr_subtype); + if (callsite == stub->first_call->callsite) + stublist_pop_call (stub); + else + stublist_trunc_calls (stub, callsite); + } + } + /* Only track calls that cannot fit within 16-bit instruction. */ + if (usestub && toofar16 + && usestub != RELAX_MD_ONCESTUB (fragp->fr_subtype)) + { + stublist_append_call (stub, callsite); + fragp->fr_subtype = RELAX_MD_MARK_ONCESTUB (fragp->fr_subtype); + } + + if (update && usestub != RELAX_MD_USESTUB (fragp->fr_subtype)) + fragp->fr_subtype + = ((usestub && keepstub) + ? RELAX_MD_MARK_USESTUB (fragp->fr_subtype) + : RELAX_MD_CLEAR_USESTUB (fragp->fr_subtype)); + + if ((usestub && keepstub) || !toofar16) + return 2; + else + return 4; +} + +/* Compute the length of a BALC stub and adjust the RELAX_MD_KEEPSTUB + bit accordingly. If a stub is not to be instantiated, its length is 0. */ +static int +relaxed_stub_length (fragS *fragp, asection *sec, bool update) +{ + bool keepstub = false; + addressT stubsite; + struct balc_stub *stub = NULL; + + /* Assume this is a 2-byte branch. */ + stubsite = fragp->fr_address + fragp->fr_fix; + + if (stubg_now->fragp) + { + /* Section change. */ + if (stubg_now->seg != sec || (stubg_now->fragp->fr_address > stubsite)) + stubg_now = str_hash_find (balc_stubgroup_table, sec->name); + + while (stubg_now->fragp->fr_address < stubsite) + if (stubg_now->next && stubg_now->next->fragp + && stubg_now->next->fragp->fr_address <= stubsite) + stubg_now = stubg_now->next; + else + break; + } + + gas_assert (stubg_now->seg == sec); + + /* Retain this stub only if it has sufficient associated + calls and cannot be merged with another elligible stub. */ + if (balc_in_stub_group (S_GET_NAME (fragp->fr_symbol), + stubsite, stubg_now, &stub) + && stub->numcalls > 0 + && !balc_merge_stub (S_GET_NAME (fragp->fr_symbol), + stubg_now, &stub) + && stub->numcalls >= 3) + keepstub = true; + + if (keepstub != RELAX_MD_KEEPSTUB (fragp->fr_subtype)) + { + if (update) + fragp->fr_subtype + = keepstub ? RELAX_MD_MARK_KEEPSTUB (fragp->fr_subtype) + : RELAX_MD_CLEAR_KEEPSTUB (fragp->fr_subtype); + + stubg_now->next_offset += (keepstub ? 4 : -4); + } + + if (keepstub) + return 4; + else + { + /* A stub that is unused right up to the update stage + can be summarily pruned from the table. */ + if (update && stub && stub->numcalls == 0) + stubtable_delete (stubg_now->stubtable, + S_GET_NAME (fragp->fr_symbol)); + return 0; + } +} + +static bool +nanomips_gpr3_reg_p (unsigned long reg) +{ + /* Check for membership in set {16, 17, 18, 19, 4, 5, 6, 7}. */ + return ((reg >> 2 == 1 || reg >> 2 == 4)); +} + +/* Compute the length of an ADDIU instruction. */ +static int +relaxed_addiu_length (fragS *fragp, bool update) +{ + char *buf; + unsigned long insn; + offsetT sval; + unsigned long rt, rs; + bool toofar16 = true; + bool negoff = false; + + sval = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; + buf = fragp->fr_literal + fragp->fr_fix; + insn = read_compressed_insn (buf, 4); + + rt = EXTRACT_BITS (insn, NANOMIPSOP_MASK_RT, NANOMIPSOP_SH_RT); + rs = EXTRACT_BITS (insn, NANOMIPSOP_MASK_RS, NANOMIPSOP_SH_RS); + + if (rt == rs + && sval >= -8 + && sval <= 7 + && !RELAX_MD_FIXED (fragp->fr_subtype)) + { + toofar16 = false; + negoff = true; + } + else if (nanomips_gpr3_reg_p (rs) + && nanomips_gpr3_reg_p (rt) + && sval >= 0 + && sval <= 28 + && sval % 4 == 0 + && !RELAX_MD_FIXED (fragp->fr_subtype)) + toofar16 = false; + else if (nanomips_gpr3_reg_p (rt) + && rs == 0 + && (int)sval >= -1 + && (int)sval <= 126 + && !RELAX_MD_FIXED (fragp->fr_subtype)) + toofar16 = false; + else + negoff = (sval < 0); + + if (fragp && update + && toofar16 != RELAX_MD_TOOFAR16 (fragp->fr_subtype)) + fragp->fr_subtype + = (toofar16 + ? RELAX_MD_MARK_TOOFAR16 (fragp->fr_subtype) + : RELAX_MD_CLEAR_TOOFAR16 (fragp->fr_subtype)); + + if (fragp && update && negoff != RELAX_MD_NEGOFF (fragp->fr_subtype)) + fragp->fr_subtype + = negoff ? RELAX_MD_MARK_NEGOFF (fragp->fr_subtype) + : RELAX_MD_CLEAR_NEGOFF (fragp->fr_subtype); + + if (toofar16) + return 4; + else + return 2; +} + +/* Estimate the size of a frag before relaxing. We are not really relaxing + here. The estimated size is encoded in the subtype information. */ + +int +md_estimate_size_before_relax (fragS *fragp, asection *segtype) +{ + int change; + + if (RELAX_MD_P (fragp->fr_subtype)) + { + int length = 4; + + if (!nanomips_opts.no_balc_stubs + && stubg_now != NULL + && RELAX_MD_BALC_STUB_P (fragp->fr_subtype)) + length = relaxed_stub_length (fragp, segtype, false); + else if (RELAX_MD_ADDIU_P (fragp->fr_subtype)) + length = relaxed_addiu_length (fragp, false); + else if (RELAX_MD_TYPE (fragp->fr_subtype) != 0) + length = relaxed_16bit_branch_length (fragp, segtype, false); + + /* Try to relax 32-bit call through a stub. */ + if (!nanomips_opts.no_balc_stubs + && stubg_now != NULL + && RELAX_MD_TYPE (fragp->fr_subtype) == RT_BRANCH_UCND + && RELAX_MD_LINK (fragp->fr_subtype)) + length = relaxed_stub_call_length (fragp, segtype, length > 2, false); + + fragp->fr_var = length; + return length; + } + + if (nanomips_opts.pic == NO_PIC) + change = nopic_need_relax (fragp->fr_symbol, 0); + else if ((nanomips_opts.pic == SVR4_PIC) + || (nanomips_opts.pic == SVR4_LARGE_PIC)) + change = pic_need_relax (fragp->fr_symbol, segtype); + else + abort (); + + if (change) + { + fragp->fr_subtype |= RELAX_USE_SECOND; + return -RELAX_FIRST (fragp->fr_subtype); + } + else + return -RELAX_SECOND (fragp->fr_subtype); +} + +/* This is called to see whether a reloc against a defined symbol + should be converted into a reloc against a section. */ + +int +nanomips_fix_adjustable (fixS *fixp) +{ + asection *tsect; + + if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + return 0; + + if (fixp->fx_addsy == NULL) + return 1; + + /* PC relative relocations for need to be symbol rather than section + relative to allow linker relaxations to be performed later on. */ + if (pcrel_reloc_p (fixp->fx_r_type)) + return 0; + + /* Relocations to code sections need to be symbol rather than section + relative for nanoMIPS, to allow linker expansions and relaxations + without having to adjust addends. */ + tsect = S_GET_SEGMENT (fixp->fx_addsy); + if (tsect != NULL + && (tsect->flags & SEC_CODE) != 0 + && (linkrelax || symbol_used_p (fixp->fx_addsy))) + return 0; + + return 1; +} + +/* Translate internal representation of relocation info to BFD target + format. */ + +arelent ** +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) +{ + static arelent *retval[MAX_RELOC_EXPANSION + 1]; + arelent *reloc; + bfd_reloc_code_real_type code; + + memset (retval, 0, sizeof (retval)); + reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + + if (fixp->fx_pcrel && fixp->fx_r_type == BFD_RELOC_32_PCREL) + /* At this point, fx_addnumber is "symbol offset - pcrel address". + Relocations want only the symbol offset. */ + reloc->addend = fixp->fx_addnumber + reloc->address; + else + reloc->addend = fixp->fx_addnumber; + + code = fixp->fx_r_type; + + reloc->howto = bfd_reloc_type_lookup (stdoutput, code); + if (reloc->howto == NULL) + { + as_bad_where (fixp->fx_file, fixp->fx_line, + _("cannot represent %s relocation in this object file" + " format"), bfd_get_reloc_code_name (code)); + retval[0] = NULL; + } + + if (linkrelax && fixp->fx_subsy) + { + reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); + reloc->addend = 0; + retval[1] = reloc; + + reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); + reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; + reloc->howto = bfd_reloc_type_lookup (stdoutput, + BFD_RELOC_NANOMIPS_NEG); + } + else if (linkrelax_reloc_p (fixp->fx_r_type)) + { + /* For a place-holder relocation, we want any succeeding PC-relative + relocation at the same offset to be generated first, so that its + PC-relative address calculation is disassembled correctly. */ + fixS *fixp_iter = fixp; + + while (fixp_iter->fx_next != NULL) + { + /* Search ahead for PC-relative relocations at same offset. */ + fixp_iter = fixp_iter->fx_next; + if (!linkrelax_reloc_p (fixp_iter->fx_r_type) + && (fixp_iter->fx_frag->fr_address + fixp_iter->fx_where > + fixp->fx_frag->fr_address + fixp->fx_where)) + break; + + if (fixp_iter->fx_pcrel && !fixp_iter->fx_done) + { + /* Relocation found, generate it before the place-holder + reloc and mark it as done. */ + retval[1] = reloc; + reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent)); + reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); + *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp_iter->fx_addsy); + reloc->address = (fixp_iter->fx_frag->fr_address + + fixp_iter->fx_where); + reloc->addend = fixp_iter->fx_addnumber; + reloc->howto = bfd_reloc_type_lookup (stdoutput, + fixp_iter->fx_r_type); + + fixp_iter->fx_done = true; + break; + } + } + } + return retval; +} + +/* Relax a machine dependent frag. This returns the amount by which + the current size of the frag should change. */ + +int +nanomips_relax_frag (asection *sec, fragS *fragp, + long stretch ATTRIBUTE_UNUSED) +{ + if (RELAX_MD_P (fragp->fr_subtype)) + { + offsetT old_var = fragp->fr_var; + offsetT new_var = 4; + + if (!nanomips_opts.no_balc_stubs + && stubg_now != NULL + && RELAX_MD_BALC_STUB_P (fragp->fr_subtype)) + new_var = relaxed_stub_length (fragp, sec, true); + else if (RELAX_MD_ADDIU_P (fragp->fr_subtype)) + new_var = relaxed_addiu_length (fragp, true); + else if (RELAX_MD_TYPE (fragp->fr_subtype) != 0) + new_var = relaxed_16bit_branch_length (fragp, sec, true); + else + new_var = old_var; + + /* Try to relax 32-bit call through a stub. */ + if (!nanomips_opts.no_balc_stubs + && stubg_now != NULL + && RELAX_MD_TYPE (fragp->fr_subtype) == RT_BRANCH_UCND + && RELAX_MD_LINK (fragp->fr_subtype) + && RELAX_MD_TOOFAR16 (fragp->fr_subtype)) + new_var = relaxed_stub_call_length (fragp, sec, new_var > 2, true); + + fragp->fr_var = new_var; + return new_var - old_var; + } + return 0; +} + +/* Convert a machine dependent frag. */ + +void +md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) +{ + if (RELAX_MD_ADDIU_P (fragp->fr_subtype)) + { + char *buf = fragp->fr_literal + fragp->fr_fix; + unsigned long insn = read_compressed_insn (buf, 4); + offsetT sval; + unsigned rt, rs; + + rt = EXTRACT_BITS (insn, NANOMIPSOP_MASK_RT, NANOMIPSOP_SH_RT); + rs = EXTRACT_BITS (insn, NANOMIPSOP_MASK_RS, NANOMIPSOP_SH_RS); + sval = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; + + if (!RELAX_MD_TOOFAR16 (fragp->fr_subtype)) + { + if (RELAX_MD_NEGOFF (fragp->fr_subtype)) + /* ADDIU[32] -> ADDIU[RS5] */ + insn = (0x9008 + | (rt << NANOMIPSOP_SH_MP) + | (sval & 0x8) << 1 + | (sval & 0x7)); + else if (rs == 0) + /* LI[32] -> LI[16] */ + insn = (0xd000 + | (rt << NANOMIPSOP_SH_MM) + | (sval & 0x7f)); + else + /* ADDIU[32] -> ADDIU[R2] */ + insn = (0x9000 + | (rt & 0x7) << NANOMIPSOP_SH_MD + | (rs & 0x7) << NANOMIPSOP_SH_MC + | (sval & 0x1f) >> 2); + } + else if (RELAX_MD_NEGOFF (fragp->fr_subtype)) + /* ADDIU[32] -> ADDIU[NEG] */ + insn = (insn & ~0xfff) | 0x80008000 | (-sval & 0xfff); + else + insn = (insn & ~0xffff) | (sval & 0xffff); + + buf = write_compressed_insn (buf, insn, fragp->fr_var); + fragp->fr_fix += fragp->fr_var; + gas_assert (buf == fragp->fr_literal + fragp->fr_fix); + return; + } + else if (RELAX_MD_P (fragp->fr_subtype)) + { + char *buf = fragp->fr_literal + fragp->fr_fix; + int type = RELAX_MD_TYPE (fragp->fr_subtype); + unsigned long insn; + expressionS exp; + fixS *fixp; + symbolS *stubsym = NULL; + const bfd_reloc_code_real_type rtype[] + = { + BFD_RELOC_NANOMIPS_10_PCREL_S1, + BFD_RELOC_NANOMIPS_7_PCREL_S1, + BFD_RELOC_NANOMIPS_4_PCREL_S1, + BFD_RELOC_NANOMIPS_25_PCREL_S1, + BFD_RELOC_NANOMIPS_14_PCREL_S1, + BFD_RELOC_NANOMIPS_14_PCREL_S1 + }; + + if (RELAX_MD_USESTUB (fragp->fr_subtype) + && ((stubg_now->seg != (asection *) asec) + || (stubg_now->prev + && stubg_now->prev->fragp + && (fragp->fr_address + fragp->fr_fix + < stubg_now->prev->fragp->fr_address)))) + stubg_now = str_hash_find (balc_stubgroup_table, asec->name); + + exp.X_op = O_symbol; + if (RELAX_MD_USESTUB (fragp->fr_subtype) + && balc_get_stub_for_symbol (S_GET_NAME (fragp->fr_symbol), + fragp->fr_address + fragp->fr_fix, + stubg_now, &stubsym)) + { + /* Resolve call through a stub symbol. */ + exp.X_add_symbol = stubsym; + exp.X_add_number = 0; + fragp->fr_subtype + = RELAX_MD_CLEAR_TOOFAR16 (fragp->fr_subtype); + } + else + { + exp.X_add_symbol = fragp->fr_symbol; + exp.X_add_number = fragp->fr_offset; + } + + fragp->fr_fix += fragp->fr_var; + + /* We generate a fixup instead of applying it right now, + because if there is linker relaxation, we're going to + need the relocations. */ + switch (type) + { + case RT_BRANCH_UCND: + case RT_BRANCH_CNDZ: + case RT_BRANCH_CND: + fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 2, &exp, true, + rtype[type - RT_BRANCH_UCND + + (RELAX_MD_TOOFAR16 + (fragp->fr_subtype) ? 3 : 0)]); + break; + case RT_BALC_STUB: + if (!RELAX_MD_KEEPSTUB (fragp->fr_subtype)) + return; + fixp = fix_new_exp (fragp, buf - fragp->fr_literal, 4, &exp, true, + rtype[3]); + break; + default: + abort (); + } + + fixp->fx_file = fragp->fr_file; + fixp->fx_line = fragp->fr_line; + + /* These relocations can have an addend that won't fit in + 2 octets. */ + fixp->fx_no_overflow = 1; + + if (RELAX_MD_USESTUB (fragp->fr_subtype) && stubsym != NULL) + { + /* Relax 32-bit call to 16-bit call to stub. */ + buf = write_compressed_insn (buf, 0x3800, 2); + return; + } + + /* Nothing left to do for 16-bit branches that fit, + or for balc stubs */ + if (!RELAX_MD_TOOFAR16 (fragp->fr_subtype) || type == RT_BALC_STUB) + return; + + /* Relax 16-bit branches to 32-bit branches. */ + insn = read_compressed_insn (buf, 2); + + if ((insn & 0xfc00) == 0xd800) /* beqc[16]/bnec[16] */ + { + unsigned long rt = (insn & 0x0380) >> 7; + unsigned long rs = (insn & 0x0070) >> 4; + if (rt > rs) + insn = 0x88000000; /* beqc */ + else + insn = 0xa8000000; /* bnec */ + rt = nanomips_to_32_reg_d_map[rt]; + rs = nanomips_to_32_reg_d_map[rs]; + insn |= (rt << 21); + insn |= (rs << 16); + } + else if ((insn & 0xdc00) == 0x9800) /* beqzc[16]/bnezc[16] */ + { + unsigned long rt = (insn & 0x0380) >> 7; + rt = nanomips_to_32_reg_d_map[rt]; + /* beqc: 0x9800 -> 0x88000000 + bnec: 0xb800 -> 0xa8000000 */ + insn = 0x88000000 | (((insn & 0x2000) >> 13) << 29); + insn |= (rt << 21); + } + else if ((insn & 0xdc00) == 0x1800) /* bc[16]/balc[16] */ + /* bc: 0x1800 -> 0x28000000 + balc: 0x3800 -> 0x2a000000 */ + insn = 0x28000000 | (((insn & 0x2000) >> 13) << 25); + else + abort (); + + /* Nothing else to do, just write it out. */ + buf = write_compressed_insn (buf, insn, 4); + gas_assert (buf == fragp->fr_literal + fragp->fr_fix); + return; + } + { + relax_substateT subtype = fragp->fr_subtype; + bool second_longer = (subtype & RELAX_SECOND_LONGER) != 0; + bool use_second = (subtype & RELAX_USE_SECOND) != 0; + int first = RELAX_FIRST (subtype); + int second = RELAX_SECOND (subtype); + fixS *fixp = (fixS *) fragp->fr_opcode; + + /* Possibly emit a warning if we've chosen the longer option. */ + if (use_second == second_longer) + { + subtype &= ~RELAX_NOMACRO; + } + + /* Go through all the fixups for the first sequence. Disable them + (by marking them as done) if we're going to use the second + sequence instead. */ + while (fixp + && fixp->fx_frag == fragp + && fixp->fx_where < fragp->fr_fix - second) + { + if (subtype & RELAX_USE_SECOND) + fixp->fx_done = 1; + fixp = fixp->fx_next; + } + + /* Go through the fixups for the second sequence. Disable them if + we're going to use the first sequence, otherwise adjust their + addresses to account for the relaxation. */ + while (fixp && fixp->fx_frag == fragp) + { + if (subtype & RELAX_USE_SECOND) + fixp->fx_where -= first; + else + fixp->fx_done = 1; + fixp = fixp->fx_next; + } + + /* Now modify the frag contents. */ + if (subtype & RELAX_USE_SECOND) + { + char *start; + + start = fragp->fr_literal + fragp->fr_fix - first - second; + memmove (start, start + first, second); + fragp->fr_fix -= first; + } + else + fragp->fr_fix -= second; + } +} + +/* This function is called whenever a label is defined, including fake + labels instantiated off the dot special symbol. */ + +static void +nanomips_record_label (symbolS *sym) +{ + segment_info_type *si = seg_info (now_seg); + struct insn_label_list *l; + + if (free_insn_labels == NULL) + l = (struct insn_label_list *) xmalloc (sizeof *l); + else + { + l = free_insn_labels; + free_insn_labels = l->next; + } + + l->label = sym; + l->next = si->label_list; + si->label_list = l; +} + +/* This function is called as tc_frob_label() whenever a label is defined + and adds a DWARF-2 record we only want for true labels. */ + +void +nanomips_define_label (symbolS *sym) +{ + nanomips_record_label (sym); + dwarf2_emit_label (sym); +} + +/* Some special processing for a nanoMIPS ELF file. */ + +void +nanomips_elf_final_processing (void) +{ + /* Set the nanoMIPS ELF flag bits. */ + if (nanomips_opts.pic != NO_PIC) + elf_elfheader (stdoutput)->e_flags |= EF_NANOMIPS_PIC; + + if (linkrelax == true) + elf_elfheader (stdoutput)->e_flags |= EF_NANOMIPS_LINKRELAX; + + /* Set the nanoMIPS ELF ABI flags. */ + if (nanomips_abi == P32_ABI) + elf_elfheader (stdoutput)->e_flags |= E_NANOMIPS_ABI_P32; + else if (nanomips_abi == P64_ABI) + elf_elfheader (stdoutput)->e_flags |= E_NANOMIPS_ABI_P64; + + if (nanomips_32bitmode) + elf_elfheader (stdoutput)->e_flags |= EF_NANOMIPS_32BITMODE; +} + +static procS cur_proc; +static int numprocs; + +/* Fill in an rs_align_code fragment. Unlike elsewhere we want to use + 32-bit NOPs here (if applicable). */ + +void +nanomips_handle_align (fragS *fragp) +{ + char *p; + int bytes, size, excess; + valueT opcode; + + bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; + + /* tc_frag_data points to the ALIGN relocation for this frag. + Update the size of the absolute alignment symbol to match + the actual padding inserted at this alignment point. */ + if (fragp->tc_frag_data != NULL) + { + fixS *fixp = fragp->tc_frag_data; + asymbol *sym; + + while (fixp != NULL && fixp->fx_frag == fragp) + { + if (fixp->fx_r_type == BFD_RELOC_NANOMIPS_ALIGN) + { + sym = symbol_get_bfdsym (fixp->fx_addsy); + elf_symbol (sym)->internal_elf_sym.st_size = bytes; + break; + } + fixp = fixp->fx_next; + } + } + + if (fragp->fr_type != rs_align_code) + return; + + p = fragp->fr_literal + fragp->fr_fix; + opcode = nanomips_nop32_insn.insn_opcode; + size = 4; + + excess = bytes % size; + + /* Handle the leading part if we're not inserting a whole number of + instructions, and make it the end of the fixed part of the frag. + Try to fit in a short NOP if applicable and possible, + and use zeroes otherwise. */ + gas_assert (excess < 4); + fragp->fr_fix += excess; + switch (excess) + { + case 3: + *p++ = '\0'; + /* Fall through. */ + case 2: + if (!nanomips_opts.insn32) + { + p = write_compressed_insn (p, nanomips_nop16_insn.insn_opcode, 2); + break; + } + *p++ = '\0'; + /* Fall through. */ + case 1: + *p++ = '\0'; + /* Fall through. */ + case 0: + break; + } + + write_compressed_insn (p, opcode, size); + fragp->fr_var = size; +} + +static long +get_number (void) +{ + int negative = 0; + long val = 0; + + if (*input_line_pointer == '-') + { + ++input_line_pointer; + negative = 1; + } + if (!ISDIGIT (*input_line_pointer)) + as_bad (_("expected simple number")); + if (input_line_pointer[0] == '0') + { + if (input_line_pointer[1] == 'x') + { + input_line_pointer += 2; + while (ISXDIGIT (*input_line_pointer)) + { + val <<= 4; + val |= hex_value (*input_line_pointer++); + } + return negative ? -val : val; + } + else + { + ++input_line_pointer; + while (ISDIGIT (*input_line_pointer)) + { + val <<= 3; + val |= *input_line_pointer++ - '0'; + } + return negative ? -val : val; + } + } + if (!ISDIGIT (*input_line_pointer)) + { + printf (_(" *input_line_pointer == '%c' 0x%02x\n"), + *input_line_pointer, *input_line_pointer); + as_warn (_("invalid number")); + return -1; + } + while (ISDIGIT (*input_line_pointer)) + { + val *= 10; + val += *input_line_pointer++ - '0'; + } + return negative ? -val : val; +} + +/* The .file directive; just like the usual .file directive, but there + is an initial number which is the ECOFF file index. In the non-ECOFF + case .file implies DWARF-2. */ + +static void +s_nanomips_file (int x ATTRIBUTE_UNUSED) +{ + static int first_file_directive = 0; + + if (ECOFF_DEBUGGING) + { + get_number (); + s_file (0); + } + else + { + char *filename; + + filename = dwarf2_directive_filename (); + + /* Versions of GCC up to 3.1 start files with a ".file" + directive even for stabs output. Make sure that this + ".file" is handled. */ + if (filename != NULL && !first_file_directive) + { + new_logical_line (filename, -1); + s_file_string (filename); + } + first_file_directive = 1; + } +} + +/* The .loc directive, implying DWARF-2. */ + +static void +s_nanomips_loc (int x ATTRIBUTE_UNUSED) +{ + if (!ECOFF_DEBUGGING) + dwarf2_directive_loc (0); +} + +/* The .linkrelax directive. */ + +static void +s_linkrelax (int x ATTRIBUTE_UNUSED) +{ + linkrelax = true; + nanomips_linkrelax_p = true; +} + +/* The .end directive. */ + +static void +s_nanomips_end (int x ATTRIBUTE_UNUSED) +{ + symbolS *p; + + if (!is_end_of_stmt (*input_line_pointer)) + { + p = get_symbol (); + demand_empty_rest_of_line (); + } + else + p = NULL; + + if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) + as_warn (_(".end not in text section")); + + if (!cur_proc_ptr) + { + as_warn (_(".end directive without a preceding .ent directive")); + demand_empty_rest_of_line (); + return; + } + + if (p != NULL) + { + gas_assert (S_GET_NAME (p)); + if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym))) + as_warn (_(".end symbol does not match .ent symbol")); + + if (debug_type == DEBUG_STABS) + stabs_generate_asm_endfunc (S_GET_NAME (p), S_GET_NAME (p)); + } + else + as_warn (_(".end directive missing or unknown symbol")); + + /* Create an expression to calculate the size of the function. */ + if (p && cur_proc_ptr) + { + OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p); + expressionS *exp = notes_alloc (sizeof (*exp)); + + if (!nanomips_opts.no_balc_stubs && stubg_now != NULL) + stubgroup_wane (); + + obj->size = exp; + exp->X_op = O_subtract; + exp->X_add_symbol = symbol_temp_new_now (); + exp->X_op_symbol = p; + exp->X_add_number = 0; + + cur_proc_ptr->func_end_sym = exp->X_add_symbol; + } + cur_proc_ptr = NULL; +} + +/* The .aent and .ent directives. */ + +static void +s_nanomips_ent (int aent) +{ + symbolS *symbolP; + + symbolP = get_symbol (); + if (*input_line_pointer == ',') + ++input_line_pointer; + SKIP_WHITESPACE (); + if (ISDIGIT (*input_line_pointer) || *input_line_pointer == '-') + get_number (); + + if ((bfd_section_flags (now_seg) & SEC_CODE) == 0) + as_warn (_(".ent or .aent not in text section")); + + if (!aent && cur_proc_ptr) + as_warn (_("missing .end")); + + if (!aent) + { + cur_proc_ptr = &cur_proc; + memset (cur_proc_ptr, '\0', sizeof (procS)); + + cur_proc_ptr->func_sym = symbolP; + + ++numprocs; + + if (debug_type == DEBUG_STABS) + stabs_generate_asm_func (S_GET_NAME (symbolP), S_GET_NAME (symbolP)); + } + + symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION; + + if (stub_funcless_mode && !nanomips_opts.no_balc_stubs && stubg_now != NULL) + { + stub_funcless_mode = false; + stubgroup_wane (); + } + + stubgroup_new (now_seg); + demand_empty_rest_of_line (); +} + +static void +s_nanomips_frame (int ignore ATTRIBUTE_UNUSED) +{ + if (ECOFF_DEBUGGING) + s_ignore (ignore); + else + { + long val; + + if (cur_proc_ptr == NULL) + { + as_warn (_(".frame outside of .ent")); + demand_empty_rest_of_line (); + return; + } + + cur_proc_ptr->frame_reg = tc_get_register (1); + + SKIP_WHITESPACE (); + if (*input_line_pointer++ != ',' + || get_absolute_expression_and_terminator (&val) != ',') + { + as_warn (_("bad .frame directive")); + --input_line_pointer; + demand_empty_rest_of_line (); + return; + } + + cur_proc_ptr->frame_offset = val; + cur_proc_ptr->pc_reg = tc_get_register (0); + + demand_empty_rest_of_line (); + } +} + +/* The .fmask and .mask directives. */ + +static void +s_nanomips_mask (int reg_type) +{ + if (ECOFF_DEBUGGING) + s_ignore (reg_type); + else + { + long mask, off; + + if (cur_proc_ptr == NULL) + { + as_warn (_(".mask/.fmask outside of .ent")); + demand_empty_rest_of_line (); + return; + } + + if (get_absolute_expression_and_terminator (&mask) != ',') + { + as_warn (_("bad .mask/.fmask directive")); + --input_line_pointer; + demand_empty_rest_of_line (); + return; + } + + off = get_absolute_expression (); + + if (reg_type == 'F') + { + cur_proc_ptr->fpreg_mask = mask; + cur_proc_ptr->fpreg_offset = off; + } + else + { + cur_proc_ptr->reg_mask = mask; + cur_proc_ptr->reg_offset = off; + } + + demand_empty_rest_of_line (); + } +} + +/* A table describing all the processors gas knows about. Names are + matched in the order listed. + + To ease comparison, please keep this table in the same order as + gcc's nanomips_cpu_info_table[]. */ +static const struct nanomips_cpu_info nanomips_cpu_info_table[] = { + /* Entries for generic ISAs */ + { "32r6", NANOMIPS_CPU_IS_ISA, + ASE_xNMS, ISA_NANOMIPS32R6, CPU_NANOMIPS32R6 }, + { "32r6s", NANOMIPS_CPU_IS_ISA, + 0, ISA_NANOMIPS32R6, CPU_NANOMIPS32R6 }, + { "64r6", NANOMIPS_CPU_IS_ISA, + ASE_xNMS, ISA_NANOMIPS64R6, CPU_NANOMIPS64R6 }, + + /* End marker */ + { NULL, 0, 0, 0, 0 } +}; + +/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied + CPU name. */ + +static bool +nanomips_matching_cpu_name_p (const char *canonical, const char *given) +{ + while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) + given++, canonical++; + + return (*given == 0 && *canonical == 0); +} + +/* Parse an option that takes the name of a processor as its argument. + OPTION is the name of the option and CPU_STRING is the argument. + Return the corresponding processor enumeration if the CPU_STRING is + recognized, otherwise report an error and return null. + + A similar function exists in GCC. */ + +static const struct nanomips_cpu_info * +nanomips_parse_cpu (const char *option, const char *cpu_string) +{ + const struct nanomips_cpu_info *p; + + if (strcasecmp (cpu_string, "from-abi") == 0) + { + if (ABI_NEEDS_32BIT_REGS (nanomips_abi)) + return nanomips_cpu_info_from_isa (ISA_NANOMIPS32R6, false); + + if (ABI_NEEDS_64BIT_REGS (nanomips_abi)) + return nanomips_cpu_info_from_isa (ISA_NANOMIPS64R6, false); + + return nanomips_cpu_info_from_isa (NANOMIPS_DEFAULT_64BIT + ? ISA_NANOMIPS64R6 + : ISA_NANOMIPS32R6, + false); + } + + /* 'default' has traditionally been a no-op. Probably not very useful. */ + if (strcasecmp (cpu_string, "default") == 0) + return 0; + + for (p = nanomips_cpu_info_table; p->name != 0; p++) + if (nanomips_matching_cpu_name_p (p->name, cpu_string)) + return p; + + if (option != NULL) + as_bad (_("bad value (%s) for %s"), cpu_string, option); + return 0; +} + +/* Return the canonical processor information for ISA (a member of the + ISA_NANOMIPS* enumeration). */ + +static const struct nanomips_cpu_info * +nanomips_cpu_info_from_isa (int isa, bool subset) +{ + int i; + + for (i = 0; nanomips_cpu_info_table[i].name != NULL; i++) + if ((nanomips_cpu_info_table[i].flags & NANOMIPS_CPU_IS_ISA) + && isa == nanomips_cpu_info_table[i].isa) + { + if (subset && (nanomips_cpu_info_table[i].ase & ASE_xNMS) != 0) + i++; + + return (&nanomips_cpu_info_table[i]); + } + return NULL; +} + +static const struct nanomips_cpu_info * +nanomips_cpu_info_from_arch (int arch) +{ + int i; + for (i = 0; nanomips_cpu_info_table[i].name != NULL; i++) + if (arch == nanomips_cpu_info_table[i].cpu) + return (&nanomips_cpu_info_table[i]); + + return NULL; +} + +static void +show (FILE *stream, const char *string, int *col_p, int *first_p) +{ + if (*first_p) + { + fprintf (stream, "%24s", ""); + *col_p = 24; + } + else + { + fprintf (stream, ", "); + *col_p += 2; + } + + if (*col_p + strlen (string) > 72) + { + fprintf (stream, "\n%24s", ""); + *col_p = 24; + } + + fprintf (stream, "%s", string); + *col_p += strlen (string); + + *first_p = 0; +} + +void +md_show_usage (FILE *stream) +{ + int column, first; + size_t i; + + fprintf (stream, _("\ +nanoMIPS options:\n\ +-EB generate big endian output\n\ +-EL generate little endian output\n\ +-g, -g2 do not remove unneeded NOPs or swap branches\n\ +-G NUM allow referencing objects up to NUM bytes\n\ + implicitly with the gp register [default 8]\n")); + fprintf (stream, _("\ +-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); + + first = 1; + + for (i = 0; nanomips_cpu_info_table[i].name != NULL; i++) + show (stream, nanomips_cpu_info_table[i].name, &column, &first); + show (stream, "from-abi", &column, &first); + fputc ('\n', stream); + fprintf (stream, _("\ +-m32 create p32 ABI object file (default)\n\ +-m64 create p64 ABI object file\n")); + fprintf (stream, _("\ +-mcmodel=MMODEL Generate code for a specific memory model,\n\ + where MMODEL is one of: auto, medium, large\n\ +-m[no-]pic [dis]allow Position Independent Code generation\n\ +-m[no-]PIC [dis]allow large model Position Independent Code generation\n\ +-m[no-]pid [dis]allow Position Independent Data access\n\ +-m[no-]pcrel [dis]allow PC-relative address calculations\n")); + + fprintf (stream, _("\ +-minsn32 only generate 32-bit nanoMIPS instructions\n\ +-mno-insn32 generate all nanoMIPS instructions\n\ +-mhard-float allow floating-point instructions\n\ +-msoft-float do not allow floating-point instructions\n\ +-msingle-float only allow 32-bit floating-point operations\n\ +-mdouble-float allow 32-bit and 64-bit floating-point operations\n\ +--[no-]construct-floats [dis]allow floating point values to be constructed\n")); + + fprintf (stream, _("\ +-mmt generate MT instructions\n\ +-mno-mt do not generate MT instructions\n")); + fprintf (stream, _("\ +-mvirt generate Virtualization instructions\n\ +-mno-virt do not generate Virtualization instructions\n")); + fprintf (stream, _("\ +-m[no-]balc-stubs enable/disable out-of-range call optimization\n\ + through trampoline stubs\n\ +-m[no-]legacyregs [dis]allow mumerical register formats\n")); + fprintf (stream, _("\ +--linkrelax allow linker relaxations\n\ +--trap, --no-break trap exception on div by 0 and mult overflow\n\ +--break, --no-trap break exception on div by 0 and mult overflow\n")); + fputc ('\n', stream); +} + +int +nanomips_dwarf2_addr_size (void) +{ + if (HAVE_64BIT_OBJECTS) + return 8; + else + return 4; +} + +/* Standard calling conventions leave the CFA at SP on entry. */ +void +nanomips_cfi_frame_initial_instructions (void) +{ + cfi_add_CFA_def_cfa_register (SP); +} + +int +tc_nanomips_regname_to_dw2regnum (char *regname) +{ + unsigned int regnum = -1; + unsigned int reg; + + if (reg_lookup (®name, RTYPE_GP | RTYPE_NUM, ®)) + regnum = reg; + + return regnum; +} + +void +nanomips_md_finish (void) +{ + int fpabi = Val_GNU_NANOMIPS_ABI_FP_ANY; + + nanomips_flush_pending_output (); + if (cur_proc_ptr) + { + as_warn (_("missing .end at end of assembly")); + if (stubg_now != NULL) + stubgroup_wane (); + } + + if (stub_funcless_mode && !nanomips_opts.no_balc_stubs && stubg_now != NULL) + { + stub_funcless_mode = false; + stubgroup_wane (); + } + + /* Just in case no code was emitted, do the consistency check. */ + file_check_options (); +} + +/* Map a data slot size to its nanoMIPS relocation. */ +static bfd_reloc_code_real_type +nanomips_bytes_to_reloc (int nbytes, bool signed_val) +{ + bfd_reloc_code_real_type rel = BFD_RELOC_NONE; + switch (nbytes) + { + case 1: + if (signed_val) + rel = BFD_RELOC_NANOMIPS_SIGNED_8; + else + rel = BFD_RELOC_NANOMIPS_UNSIGNED_8; + break; + case 2: + if (signed_val) + rel = BFD_RELOC_NANOMIPS_SIGNED_16; + else + rel = BFD_RELOC_NANOMIPS_UNSIGNED_16; + break; + case 4: + rel = BFD_RELOC_32; + break; + case 8: + rel = BFD_RELOC_64; + break; + case 16: + break; + default: + as_bad (_("unsupported BFD relocation size %u"), nbytes); + rel = BFD_RELOC_NONE; + } + return rel; +} + +/* Check if the expression is a simple difference of local labels in + code sections. */ + +static bool +simple_diff_expr_p (expressionS *exp) +{ + return (exp->X_op == O_subtract + && exp->X_add_symbol + && exp->X_op_symbol + && exp->X_add_number == 0 + && symbol_constant_p (exp->X_add_symbol) + && symbol_constant_p (exp->X_op_symbol)); +} + +/* Parse a .byte, .word, etc. expression. + Values for the status register are specified with %st(label). + `label' will be right shifted by 2. */ + +bfd_reloc_code_real_type +nanomips_parse_cons_expression (expressionS *exp, unsigned int nbytes) +{ + bfd_reloc_code_real_type rel = BFD_RELOC_NONE; + int repeat = 1; + expression (exp); + + if (*input_line_pointer == ':') + { + expressionS count; + ++input_line_pointer; + expression (&count); + if (count.X_op != O_constant || count.X_add_number <= 0) + { + as_warn (_("unresolvable or nonpositive repeat count; using 1")); + return BFD_RELOC_NONE; + } + + /* The cons function is going to output this expression once. So we + output it count - 1 times. */ + repeat = count.X_add_number; + } + + /* Sometimes subtract expressions containing data labels are deemed + not-constant by general parse code because they fall in distinct + frags. These wouldn't be affected by linker relaxation which only + touches code, so we skip relocations for those expressions and hope + that this will not break any valid case. */ + if (linkrelax + && exp->X_op != O_constant + && (exp->X_op != O_subtract + || ((S_GET_SEGMENT (exp->X_add_symbol))->flags & SEC_CODE) != 0 + || ((S_GET_SEGMENT (exp->X_op_symbol))->flags & SEC_CODE) != 0)) + { + expressionS *iter; + bool done = false; + + /* By-pass explicit reloc generation for simple label differences to + allow the general framework to evaluate whether the difference is + fixed or link-time variable. */ + if (simple_diff_expr_p (exp)) + return rel; + + rel = nanomips_bytes_to_reloc (nbytes, sign_cons); + + /* Check if we can actually handle this expression. */ + iter = exp; + while (iter->X_add_symbol != NULL && !done) + { + switch (iter->X_op) + { + case O_subtract: + /* exp := symbol - exp */ + if (!symbol_constant_p (iter->X_add_symbol)) + { + as_bad ("Expression too complex to relocate!"); + rel = BFD_RELOC_NONE; + } + iter = symbol_get_value_expression (iter->X_op_symbol); + break; + + case O_right_shift: + /* exp := exp >> const */ + if (!symbol_constant_p (iter->X_op_symbol) + || S_GET_SEGMENT (iter->X_op_symbol) != absolute_section + || iter->X_add_number != 0) + { + as_bad ("Expression too complex to relocate!"); + rel = BFD_RELOC_NONE; + } + /* Fall through. */ + + case O_symbol: + /* exp := symbol [ + offset ] */ + iter = symbol_get_value_expression (iter->X_add_symbol); + break; + + default: + /* If the expression contains even one operator that we can't + map to relocations, then don't bother. */ + rel = BFD_RELOC_NONE; + done = true; + break; + } + } + } + while (repeat-- > 1) + emit_expr_with_reloc (exp, nbytes, rel); + + return rel; +} + +void +nanomips_cons_fix_new (fragS *frag, int where, int nbytes, expressionS *exp, + bfd_reloc_code_real_type r) +{ + if (r != BFD_RELOC_NONE) + { + /* Assuming 64 entries will be enough. */ + struct s_rentry + { + symbolS *sym; + offsetT addend; + bfd_reloc_code_real_type reloc; + } rentry[64]; + size_t numrelocs = 0; + bool comp_p; + bfd_reloc_code_real_type sym_reloc = (HAVE_64BIT_SYMBOLS + ? BFD_RELOC_64 : BFD_RELOC_32); + expressionS *iter = exp; + + /* Provisionally fill the outer-most entry. */ + rentry[numrelocs].sym = NULL; + rentry[numrelocs].addend = 0; + rentry[numrelocs].reloc = r; + + /* Dealing with composite relocation. */ + comp_p = (iter->X_op != O_symbol); + + if (iter->X_op == O_right_shift && r != sym_reloc) + /* Finalize the outer entry now. */ + numrelocs++; + else + /* Defer the outer entry for further combination. */ + sym_reloc = r; + + while (iter->X_add_symbol != NULL) + { + + if (numrelocs + 1 >= ARRAY_SIZE (rentry)) + { + as_bad ("Expression too complex to relocate!"); + break; + } + + switch (iter->X_op) + { + case O_subtract: + rentry[numrelocs].sym = iter->X_add_symbol; + rentry[numrelocs].addend = 0; + rentry[numrelocs++].reloc = sym_reloc; + rentry[numrelocs].sym = iter->X_op_symbol; + rentry[numrelocs].addend = iter->X_add_number; + sym_reloc = BFD_RELOC_NANOMIPS_NEG; + break; + + case O_right_shift: + { + int scount; + gas_assert (symbol_constant_p (iter->X_op_symbol)); + scount = S_GET_VALUE (iter->X_op_symbol); + + /* Iterate over the shift count and track the + required number of relocs. */ + while (scount-- > 0) + { + rentry[numrelocs].sym = NULL; + rentry[numrelocs].addend = 0; + rentry[numrelocs++].reloc = BFD_RELOC_NANOMIPS_ASHIFTR_1; + } + + /* We can roll the a shift step in to the expression + if it is just a simple symbol reference. This just + sets things up for the last-level block below. */ + if (S_GET_VALUE (iter->X_op_symbol) != 0 + && sym_reloc != BFD_RELOC_NANOMIPS_NEG) + { + sym_reloc = BFD_RELOC_NANOMIPS_ASHIFTR_1; + numrelocs--; + } + } + /* Fall through */ + + case O_symbol: + rentry[numrelocs].sym = iter->X_add_symbol; + if (sym_reloc == BFD_RELOC_NANOMIPS_NEG) + /* S1 - (S2 + A) => S1 + (-S2 + -A) */ + rentry[numrelocs].addend = -iter->X_add_number; + else + rentry[numrelocs].addend = iter->X_add_number; + break; + + default: + as_bad ("Expression too complex to relocate!"); + break; + } + + iter = symbol_get_value_expression (rentry[numrelocs].sym); + + /* No more levels of nesting? */ + if (iter->X_add_symbol == NULL) + rentry[numrelocs++].reloc = sym_reloc; + } + + /* Step through the list in reverse and create relocations. */ + while (numrelocs > 0) + { + fixS *fixP; + --numrelocs; + fixP = fix_new (frag, where, nbytes, rentry[numrelocs].sym, + rentry[numrelocs].addend, 0, + rentry[numrelocs].reloc); + + if (comp_p) + fixP->fx_tcbit = 1; + } + } + else + { + reloc_howto_type *reloc_howto; + int size = nbytes; + + if (r != TC_PARSE_CONS_RETURN_NONE) + { + reloc_howto = bfd_reloc_type_lookup (stdoutput, r); + size = bfd_get_reloc_size (reloc_howto); + + if (size > nbytes) + { + as_bad (_("%s relocations do not fit in %u bytes\n"), + reloc_howto->name, nbytes); + return; + } + } + else + switch (size) + { + case 1: + r = BFD_RELOC_8; + break; + case 2: + r = BFD_RELOC_16; + break; + case 3: + r = BFD_RELOC_24; + break; + case 4: + r = BFD_RELOC_32; + break; + case 8: + r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); + return; + } + + fix_new_exp (frag, where, size, exp, 0, r); + } +} + +/* Check if subtraction of 2 symbols can be fully evaluated at assembly. */ +static bool +nanomips_allow_local_subtract_symbols (symbolS *left, symbolS *right, + bool pre_relax) +{ + /* Check for intervening fixups between symbols within the same frag to + determine if relaxation could affect the difference. */ + if (symbol_get_frag (left) == symbol_get_frag (right)) + { + fixS *fixP; + fragS *fragP; + bfd_vma low, high; + struct reloc_list *rp; + + fragP = symbol_get_frag (left); + + high = S_GET_VALUE (left); + low = S_GET_VALUE (right); + + /* Swap if necessary. */ + if (high < low) + { + high = high + low; + low = high - low; + high = high - low; + } + + /* Start with the first fix-up in this frag. */ + fixP = fragP->tc_frag_data; + + /* Now look for fixups within the range. */ + while (fixP != NULL + && fixP->fx_where < low + && fixP->fx_where < high) + fixP = fixP->fx_next; + + /* Fixups within the range. */ + if (fixP != NULL && fixP->fx_where < high) + return false; + + /* Too early for checking explicit relocations, assume the worst. */ + if (pre_relax) + return false; + + rp = reloc_list; + while (rp != NULL) + { + if (rp->u.a.offset_sym) + { + if (S_GET_VALUE (rp->u.a.offset_sym) >= low + && S_GET_VALUE (rp->u.a.offset_sym) < high) + return false; + else if (S_GET_VALUE (rp->u.a.offset_sym) > high) + break; + } + rp = rp->next; + } + /* No fixup within the range. */ + return true; + } + + /* We have to assume that there may be instructions between the + two symbols and that relaxation may increase the distance between + them. */ + return false; +} + +/* md_allow_local_subtract interface + Check if a subtraction expression can be fully evaluated. */ +bool +nanomips_allow_local_subtract (expressionS *left, expressionS *right, + segT section) +{ + /* If the symbols are not in a code section then they are OK. */ + if ((section->flags & SEC_CODE) == 0) + return true; + + if ((left->X_add_symbol == right->X_add_symbol)) + return true; + + if (!linkrelax) + return true; + + /* For lable-difference relocations in .debug_info sections, we + want to force a relocation, even if the difference is link-time + invariant so that the linker has the opportunity to zero-out + AT_high_pc expressions when the corresponding sections get + garbage-collected. Spurious non-zero AT_high_pc fields of + garbage-collected sections can trip-up GDB source disassembly. */ + if (strcmp (now_seg->name, ".debug_info") == 0) + return false; + else + return nanomips_allow_local_subtract_symbols (left->X_add_symbol, + right->X_add_symbol, + true); +} + +/* Create relocations for alignment directives. */ +void +nanomips_md_do_align (int n, const char *fill, int fill_length, int max_fill) +{ + unsigned int fill_value = 0; + + if (nanomips_linkrelax_p + && (bfd_section_flags (now_seg) & SEC_CODE) != 0 + && n > 1) + { + fill_value = bfd_get_bits (fill, fill_length * 8, target_big_endian); + + if (fill == NULL && subseg_text_p (now_seg)) + frag_grow (MAX_MEM_FOR_RS_ALIGN_CODE(p2align, max)); + else if (fill_length > 1) + frag_grow (fill_length); + else + frag_grow (1); + + create_align_relocs (frag_now, n, fill_value, fill_length, max_fill); + } +} + +/* TC_VALIDATE_FIX_SUB hook. */ + +bool +nanomips_validate_fix_sub (fixS *fix) +{ + segT add_symbol_segment, sub_symbol_segment; + + /* The difference of two symbols should be resolved by the assembler when + linkrelax is not set. If the linker may relax the section containing + the symbols, then composite relocations are generated so that the + linker knows how to adjust the difference value. */ + if (!linkrelax || fix->fx_addsy == NULL) + return 0; + + /* Make sure both symbols are in the same segment, and that segment is + "normal" and relaxable. If the segment is not "normal", then the + fix is not valid. If the segment is not "relaxable", then the fix + should have been handled earlier. */ + add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); + if (!SEG_NORMAL (add_symbol_segment) + || (add_symbol_segment->flags & SEC_DEBUGGING) != 0) + return 0; + + sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); + + if (sub_symbol_segment != add_symbol_segment) + return 0; + else + { + /* For lable-difference relocations in .debug_info sections, we + want to force a relocation, even if the difference is link-time + invariant so that the linker has the opportunity to zero-out + AT_high_pc expressions when the corresponding sections get + garbage-collected. Spurious non-zero AT_high_pc fields for + garbage-collected sections can trip-up GDB source disassembly. */ + if (frag_in_section_p (fix->fx_frag, ".debug_info")) + return 1; + else + return (!nanomips_allow_local_subtract_symbols (fix->fx_addsy, + fix->fx_subsy, + false)); + } +} + +/* TC_EH_FRAME_ESTIMATE_SIZE_BEFORE_RELAX hook. + Check if the rs_cfa frag could be affected by linker relaxation and + choose a suitable size estimation heuristic. If not, fall back to + the generic estimation logic. + + The heuristic is currently hard-coded to 4 bytes. */ +int +nanomips_eh_frame_estimate_size_before_relax (fragS *frag) +{ + expressionS *exp = symbol_get_value_expression (frag->fr_symbol); + + if (linkrelax + && !nanomips_allow_local_subtract_symbols (exp->X_add_symbol, + exp->X_op_symbol, + false)) + { + int ret; + gas_assert ((frag->fr_subtype >> 3) > 0); + ret = 4; + frag->fr_subtype = (frag->fr_subtype & ~7) | ret; + + return ret; + } + else + return eh_frame_estimate_size_before_relax (frag); +} + +/* TC_EH_FRAME_RELAX_FRAG hook */ +int +nanomips_eh_frame_relax_frag (fragS *frag) +{ + int oldsize, newsize; + + oldsize = frag->fr_subtype & 7; + newsize = nanomips_eh_frame_estimate_size_before_relax (frag); + return newsize - oldsize; +} + +/* TC_EH_FRAME_CONVERT_FRAG hook + Check if the rs_cfa frag could be affected by linker relaxation and + generate relocations to fix-up the value after relaxation. + Then fall-back to the generic convert_frag. */ +void +nanomips_eh_frame_convert_frag (fragS *frag) +{ + expressionS *exp = symbol_get_value_expression (frag->fr_symbol); + + if (linkrelax && !nanomips_allow_local_subtract_symbols (exp->X_add_symbol, + exp->X_op_symbol, + false)) + { + /* Generate label-difference relocations for this frag. */ + int size = nanomips_eh_frame_estimate_size_before_relax (frag); + bfd_reloc_code_real_type r = nanomips_bytes_to_reloc (size, false); + + nanomips_cons_fix_new (frag, frag->fr_fix, size, exp, r); + } + eh_frame_convert_frag (frag); +} + +/* Hook to run before relaxation. */ + +void nanomips_pre_relax_hook (void) +{ + struct reloc_list *iter, *prev, *copy, *next; + + /* Make a private copy of the reloc_list and reverse it, + all in one iteration. */ + iter = reloc_list; + prev = copy = NULL; + + while (iter != NULL) + { + if (iter->u.a.howto->type != R_NANOMIPS_FRAME_REG) + { + reloc_list_copy = XNEW (struct reloc_list); + *reloc_list_copy = *iter; + reloc_list_copy->next = prev; + prev = reloc_list_copy; + } + iter = iter->next; + } + + /* Once reversed, reloc_list is mostly sorted, on account of how + the compiler emits explicit relocations. Optimized lookup + depends on the order of .relocs in the source matching the + order of offset symbols for those relocations. We either confirm + that the order matches or fall-back to a slower lookup. */ + iter = reloc_list_copy; + if (iter != NULL) + next = iter->next; + + while (iter != NULL && next != NULL) + { + fragS *fiter = symbol_get_frag (iter->u.a.offset_sym); + fragS *fnext = symbol_get_frag (next->u.a.offset_sym); + + if (fiter == fnext) + { + if (S_GET_VALUE (iter->u.a.offset_sym) + > S_GET_VALUE (next->u.a.offset_sym)) + { + reloc_ordered = false; + break; + } + } + else + { + while (fiter && fiter != fnext) + fiter = fiter->fr_next; + if (fiter != fnext) + { + reloc_ordered = false; + break; + } + } + iter = next; + next = iter->next; + } +} + +/* Hook to run after relaxation. */ + +void nanomips_post_relax_hook (void) +{ + reloc_list_iter = reloc_list_copy; +} diff --git a/gas/config/tc-nanomips.h b/gas/config/tc-nanomips.h new file mode 100644 index 00000000000..518bf8a8818 --- /dev/null +++ b/gas/config/tc-nanomips.h @@ -0,0 +1,187 @@ +/* tc-nanomips.h -- header file for tc-nanomips.c. + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of GAS. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef TC_NANOMIPS +#define TC_NANOMIPS + +struct frag; +struct expressionS; + +/* Default to little endian. */ +#ifndef TARGET_BYTES_BIG_ENDIAN +#define TARGET_BYTES_BIG_ENDIAN 0 +#endif + +#define TARGET_ARCH bfd_arch_nanomips + +#define WORKING_DOT_WORD 1 +#define OLD_FLOAT_READS +#define RELOC_EXPANSION_POSSIBLE +#define MAX_RELOC_EXPANSION 2 +#define LOCAL_LABELS_FB 1 + +#define TC_ADDRESS_BYTES nanomips_address_bytes +extern int nanomips_address_bytes (void); + +#define md_relax_frag(segment, fragp, stretch) \ + nanomips_relax_frag(segment, fragp, stretch) +extern int nanomips_relax_frag (asection *, struct frag *, long); + +#define md_undefined_symbol(name) (0) +#define md_operand(x) + +extern void nanomips_handle_align (struct frag *); +#define HANDLE_ALIGN(sec, fragp) nanomips_handle_align (fragp) + +#define MAX_MEM_FOR_RS_ALIGN_CODE(p2align, max) (3 + 4) + +struct insn_label_list; +#define TC_SEGMENT_INFO_TYPE struct insn_label_list * + +/* The endianness of the target format may change based on command + line arguments. */ +#define TARGET_FORMAT nanomips_target_format() +extern const char *nanomips_target_format (void); + +extern int tc_get_register (int); + +#define md_after_parse_args() nanomips_after_parse_args() +extern void nanomips_after_parse_args (void); + +#define tc_frob_label(sym) nanomips_define_label (sym) +extern void nanomips_define_label (symbolS *); + +#define tc_frob_file_before_adjust() nanomips_frob_file_before_adjust () +extern void nanomips_frob_file_before_adjust (void); + +#define tc_fix_adjustable(fixp) nanomips_fix_adjustable (fixp) +extern int nanomips_fix_adjustable (struct fix *); + +/* Values passed to md_apply_fix don't include symbol values. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + +#define TC_FORCE_RELOCATION(FIX) nanomips_force_relocation (FIX) +extern int nanomips_force_relocation (struct fix *); + +#define TC_FORCE_RELOCATION_SUB_SAME(FIX, SEG) \ + (! SEG_NORMAL (SEG) || nanomips_force_relocation (FIX)) + +#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) \ + (((SEG)->flags & SEC_CODE) != 0 && nanomips_force_relocation (FIX)) + +#define elf_tc_final_processing nanomips_elf_final_processing +extern void nanomips_elf_final_processing (void); + +extern void nanomips_md_finish (void); +#define md_finish() nanomips_md_finish() + +extern void nanomips_pop_insert (void); +#define md_pop_insert() nanomips_pop_insert() + +extern void nanomips_flush_pending_output (void); +#define md_flush_pending_output nanomips_flush_pending_output + +extern void nanomips_enable_auto_align (void); +#define md_elf_section_change_hook() nanomips_enable_auto_align() + +extern int nanomips_dwarf2_addr_size (void); +#define DWARF2_ADDR_SIZE(bfd) nanomips_dwarf2_addr_size () +#define DWARF2_FDE_RELOC_SIZE nanomips_dwarf2_addr_size () + +#define TARGET_USE_CFIPOP 1 + +#define tc_cfi_frame_initial_instructions nanomips_cfi_frame_initial_instructions +extern void nanomips_cfi_frame_initial_instructions (void); + +#define tc_regname_to_dw2regnum tc_nanomips_regname_to_dw2regnum +extern int tc_nanomips_regname_to_dw2regnum (char *regname); + +#define DWARF2_DEFAULT_RETURN_COLUMN 31 +#define DWARF2_CIE_DATA_ALIGNMENT (-4) + +/* Definitions needed to parse cons in target-specific manner. */ +#define TC_PARSE_CONS_RETURN_TYPE bfd_reloc_code_real_type +#define TC_PARSE_CONS_RETURN_NONE BFD_RELOC_NONE + +/* Parse a cons expression to determined what kind of relocations + may be needed to represent it. */ +extern bfd_reloc_code_real_type +nanomips_parse_cons_expression (struct expressionS *, unsigned); +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \ + nanomips_parse_cons_expression (EXP, NBYTES) + +/* Walk a cons expression tree and create the relocations needed + to represent the operation. */ +extern void nanomips_cons_fix_new (struct frag *, int, int, + struct expressionS *, + const bfd_reloc_code_real_type); +#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ + nanomips_cons_fix_new (FRAG, WHERE, NBYTES, EXP, RELOC) + +/* Determine what kind of difference expressions must be + evaluated by assembler. */ +extern bool nanomips_allow_local_subtract (expressionS *, + expressionS *, segT); +#define md_allow_local_subtract(lhs,rhs,sect) \ + nanomips_allow_local_subtract (lhs, rhs, sect) + +#define TC_FRAG_TYPE struct fix * + +extern void nanomips_md_do_align (int, const char *, int, int); +#define md_do_align(n,f,l,m,j) nanomips_md_do_align (n,f,l,m) + +/* If defined, this macro allows control over whether fixups for a + given section will be processed when the linkrelax variable is + set. Define it to zero and handle things in md_apply_fix instead.*/ +#define TC_LINKRELAX_FIXUP(SEG) 0 + +/* This macro is evaluated for any fixup with a fx_subsy that + fixup_segment cannot reduce to a number. If the macro returns + false an error will be reported. */ +#define TC_VALIDATE_FIX_SUB(fix, seg) nanomips_validate_fix_sub (fix) +extern bool nanomips_validate_fix_sub (struct fix *); + +#define LEX_BR LEX_NAME + +#define MD_PCREL_FROM_SECTION(FIX,SEG) 0 + +int nanomips_eh_frame_estimate_size_before_relax (fragS *); +#define TC_EH_FRAME_ESTIMATE_SIZE_BEFORE_RELAX(frag) \ + nanomips_eh_frame_estimate_size_before_relax (frag) + +int nanomips_eh_frame_relax_frag (fragS *); +#define TC_EH_FRAME_RELAX_FRAG(frag) \ + nanomips_eh_frame_relax_frag (frag) + +void nanomips_eh_frame_convert_frag (fragS *); +#define TC_EH_FRAME_CONVERT_FRAG(frag) \ + nanomips_eh_frame_convert_frag (frag) + +#define md_section_align(SEGMENT, SIZE) (SIZE) + +void nanomips_pre_relax_hook (void); +#define md_pre_relax_hook nanomips_pre_relax_hook() + +void nanomips_post_relax_hook (void); +#define md_post_relax_hook nanomips_post_relax_hook() + +#endif /* TC_NANOMIPS */ diff --git a/gas/configure b/gas/configure index 3b120d3f441..b8d25684409 100755 --- a/gas/configure +++ b/gas/configure @@ -12694,6 +12694,60 @@ _ACEOF cat >>confdefs.h <<_ACEOF #define MIPS_DEFAULT_ABI $mips_default_abi +_ACEOF + + ;; + nanomips) + # Set nanomips_cpu to the name of the default CPU. + case ${target_cpu} in + nanomips | nanomipsel | nanomipseb) + nanomips_cpu=from-abi + ;; + nanomips32*) + nanomips_cpu=32r6 + ;; + nanomips64*) + nanomips_cpu=64r6 + ;; + *) + as_fn_error "$target_cpu isn't a supported NANOMIPS CPU name" "$LINENO" 5 + ;; + esac + # Decide whether to generate 32-bit or 64-bit code by default. + # Used to resolve -march=from-abi when an embedded ABI is selected. + case ${target} in + nanomips64*-*-*) + nanomips_default_64bit=1 + ;; + *) + nanomips_default_64bit=0 + ;; + esac + # Decide which ABI to target by default. + case ${target} in + nanomips64*-*) + nanomips_default_abi=P64_ABI + ;; + nanomips*-*) + nanomips_default_abi=P32_ABI + ;; + *) + nanomips_default_abi=NO_ABI + ;; + esac + +cat >>confdefs.h <<_ACEOF +#define NANOMIPS_CPU_STRING_DEFAULT "$nanomips_cpu" +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define NANOMIPS_DEFAULT_64BIT $nanomips_default_64bit +_ACEOF + + +cat >>confdefs.h <<_ACEOF +#define NANOMIPS_DEFAULT_ABI $nanomips_default_abi _ACEOF ;; diff --git a/gas/configure.ac b/gas/configure.ac index 69547f5ffb9..03c0cb17904 100644 --- a/gas/configure.ac +++ b/gas/configure.ac @@ -423,6 +423,51 @@ changequote([,])dnl AC_DEFINE_UNQUOTED(MIPS_DEFAULT_ABI, $mips_default_abi, [Choose a default ABI for MIPS targets. ]) ;; + nanomips) + # Set nanomips_cpu to the name of the default CPU. + case ${target_cpu} in + nanomips | nanomipsel | nanomipseb) + nanomips_cpu=from-abi + ;; + nanomips32*) + nanomips_cpu=32r6 + ;; + nanomips64*) + nanomips_cpu=64r6 + ;; + *) + AC_MSG_ERROR($target_cpu isn't a supported MIPS CPU name) + ;; + esac + # Decide whether to generate 32-bit or 64-bit code by default. + # Used to resolve -march=from-abi when an embedded ABI is selected. + case ${target} in + nanomips64*-*-*) + nanomips_default_64bit=1 + ;; + *) + nanomips_default_64bit=0 + ;; + esac + # Decide which ABI to target by default. + case ${target} in + nanomips64*-*) + nanomips_default_abi=P64_ABI + ;; + nanomips*-*) + nanomips_default_abi=P32_ABI + ;; + *) + nanomips_default_abi=NO_ABI + ;; + esac + AC_DEFINE_UNQUOTED(NANOMIPS_CPU_STRING_DEFAULT, "$nanomips_cpu", + [Default CPU for nanoMIPS targets. ]) + AC_DEFINE_UNQUOTED(NANOMIPS_DEFAULT_64BIT, $nanomips_default_64bit, + [Generate 64-bit code by default on nanoMIPS targets. ]) + AC_DEFINE_UNQUOTED(NANOMIPS_DEFAULT_ABI, $nanomips_default_abi, + [Choose a default ABI for nanoMIPS targets. ]) + ;; esac # Do we need the opcodes library? diff --git a/gas/configure.tgt b/gas/configure.tgt index 7a5645fd9ae..8e1e7727603 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -85,6 +85,8 @@ case ${cpu} in mips*el) cpu_type=mips endian=little ;; mips*) cpu_type=mips endian=big ;; mt) cpu_type=mt endian=big ;; + nanomips*eb) cpu_type=nanomips endian=big ;; + nanomips*) cpu_type=nanomips endian=little ;; nds32be) cpu_type=nds32 endian=big ;; nds32le) cpu_type=nds32 endian=little ;; or1k* | or1knd*) cpu_type=or1k endian=big ;; @@ -345,6 +347,9 @@ case ${generic_target} in msp430-*-*) fmt=elf ;; + nanomips*-*-elf*) fmt=elf ;; + nanomips*-*-linux*) fmt=elf em=linux;; + nds32-*-elf*) fmt=elf ;; nds32-*-linux*) fmt=elf em=linux ;; diff --git a/gas/read.c b/gas/read.c index ae481007c32..a25828839d2 100644 --- a/gas/read.c +++ b/gas/read.c @@ -2615,7 +2615,7 @@ bss_alloc (symbolS *symbolP, addressT size, unsigned int align) subsegT current_subseg = now_subseg; segT bss_seg = bss_section; -#if defined (TC_MIPS) || defined (TC_ALPHA) +#if defined (TC_MIPS) || defined (TC_ALPHA) || defined (TC_NANOMIPS) if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour || OUTPUT_FLAVOR == bfd_target_elf_flavour) { diff --git a/ld/configure.tgt b/ld/configure.tgt index 60b62e69c08..644b6631a90 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -545,6 +545,8 @@ mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) targ_emul=elf32btsmip targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; +nanomips*-*) targ_emul=vanilla + ;; mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 targ_extra_libpath=elf32lr5900 ;; From patchwork Fri Jul 17 10:38:54 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsing X-Patchwork-Id: 139391 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1939E4BA23C6 for ; Fri, 17 Jul 2026 10:40:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1939E4BA23C6 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=GSxpSQRh X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from va-2-38.ptr.blmpb.com (va-2-38.ptr.blmpb.com [209.127.231.38]) by sourceware.org (Postfix) with ESMTPS id E10DE4BA2E0C for ; Fri, 17 Jul 2026 10:39:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E10DE4BA2E0C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org E10DE4BA2E0C Authentication-Results: sourceware.org; arc=none smtp.remote-ip=209.127.231.38 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284769; cv=none; b=CQVPseC5j57D7Isf2owOgkKqnvlEWyso+v467ybi75uu7F/HFSeSeesk1wRDdCMjd1qvcHU9f17KUVw5VDrt5YPQaD10EibBZHeBrURh4gV1f4GzhXaFNY02UUhYNAexhWcgl7Ag/a6GC2OTNC8jo1kEWX0JVaumkmfKishy02E= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284769; c=relaxed/simple; bh=cZh8mCF6P2wwQjMHpBK42VYjgXPIdfRaFZZKNzefeJE=; h=DKIM-Signature:Date:From:To:Subject:Message-Id:Mime-Version; b=Ex8BiweUamqXN6bQb4IVktSYhaOTiqolF7fZx/FtGS68iEZ78Xt5hJGDOnW1uHk0YuNq/lc2wM7DQYJ2vMBBCZvAAk4W08xGocqyWiOdpiq1h7UU92HgEnlZF3Az+MEeH1hMJCG1FWLrDPidE0jxbK5WzQQMu0U0ne0f7ocqhNI= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=GSxpSQRh DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E10DE4BA2E0C DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1784284763; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=c0vyeAsrHZqG0ZeTjy6VlCz/SkVSXygGEIww9Ce1z8I=; b=GSxpSQRhJrXqiOaZkspcExPyE2WUDptyrujhZSM6NLibjT2kbLuvVaslkVFhvlpDZiR/qM j+GUxE5uyX54zqZh/cQTLsuTe2MeeZRXicFLef/aq0j8PAXDVB/8PjEs4l3xwWVx/FtgaU 6AXt/wI+UFfqt5rFqwCMY2XLXOXS5OTe+sQ+oLYa0lXFDNwkc2/7FQn99iKzgg+6gshCLh nZcbXpDFtrBpcnZlObOtqThs7bqxIDUO+CesM8efnaaGwomcVCAZF0BAVMsSMSynJNoDRS xzLcYCcsB8IK4Kdf21+xsNo6jxnUQQHF1kFfULpQJeEX+MgOR6nFq78Zt93Lhg== Date: Fri, 17 Jul 2026 18:38:54 +0800 X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260717103858.199743-1-lei.wang@oss.cipunited.com> From: "Tsing" Received: from B1.wok.cipunited.com ([123.52.17.40]) by smtp.feishu.cn with ESMTPS; Fri, 17 Jul 2026 18:39:20 +0800 X-Original-From: Tsing To: X-Lms-Return-Path: References: <20260717103858.199743-1-lei.wang@oss.cipunited.com> Subject: [PATCH 2/6] BFD changes for nanoMIPS support. Message-Id: <20260717103858.199743-3-lei.wang@oss.cipunited.com> Mime-Version: 1.0 X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, RCVD_IN_PBL, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: tsing bfd/ * Makefile.am: Add entries for nanomips32-elf and nanomips64-elf. * Makefile.in: Regenerate. * configure: Regenerate. * configure.ac: Likewise. * config.bfd: Likewise. * archures.c: Add bfd_nanomips_arch. * reloc.c: Add nanomips relocs. * targets.c: Add naonmips_elf32_vec and nanomips_elf64_vec. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf-bfd.h: Add NANOMIPS_ELF_DATA to enum elf_target_id. * elfnn-nanomips.c: New file. * elfxx-nanomips.c: New file. * elfxx-nanomips.h: New file. include/ * elf/common.h: Add EM_NANOMIPS. * elf/nanomips.h: New file. --- bfd/Makefile.am | 17 + bfd/Makefile.in | 20 + bfd/archures.c | 5 + bfd/bfd-in2.h | 72 ++ bfd/config.bfd | 11 + bfd/configure | 4 + bfd/configure.ac | 4 + bfd/cpu-nanomips.c | 61 ++ bfd/elf-bfd.h | 1 + bfd/elfnn-nanomips.c | 1535 ++++++++++++++++++++++++++++++++++++++++ bfd/elfxx-nanomips.c | 449 ++++++++++++ bfd/elfxx-nanomips.h | 46 ++ bfd/libbfd.h | 67 ++ bfd/reloc.c | 138 ++++ bfd/targets.c | 11 + include/elf/common.h | 1 + include/elf/nanomips.h | 211 ++++++ 17 files changed, 2653 insertions(+) create mode 100644 bfd/cpu-nanomips.c create mode 100644 bfd/elfnn-nanomips.c create mode 100644 bfd/elfxx-nanomips.c create mode 100644 bfd/elfxx-nanomips.h create mode 100644 include/elf/nanomips.h diff --git a/bfd/Makefile.am b/bfd/Makefile.am index e4df05441eb..89de4afc36b 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -142,6 +142,7 @@ ALL_MACHINES = \ cpu-moxie.lo \ cpu-msp430.lo \ cpu-mt.lo \ + cpu-nanomips.lo \ cpu-nds32.lo \ cpu-nfp.lo \ cpu-ns32k.lo \ @@ -225,6 +226,7 @@ ALL_MACHINES_CFILES = \ cpu-moxie.c \ cpu-msp430.c \ cpu-mt.c \ + cpu-nanomips.c \ cpu-nds32.c \ cpu-nfp.c \ cpu-ns32k.c \ @@ -331,6 +333,7 @@ BFD32_BACKENDS = \ elf32-moxie.lo \ elf32-msp430.lo \ elf32-mt.lo \ + elf32-nanomips.lo \ elf32-nds32.lo \ elf32-or1k.lo \ elf32-pj.lo \ @@ -466,6 +469,7 @@ BFD32_BACKENDS_CFILES = \ elf32-moxie.c \ elf32-msp430.c \ elf32-mt.c \ + elf32-nanomips.c \ elf32-nds32.c \ elf32-or1k.c \ elf32-pj.c \ @@ -562,6 +566,8 @@ BFD64_BACKENDS = \ elf64-loongarch.lo \ elf64-mips.lo \ elf64-mmix.lo \ + elf64-nanomips.lo \ + elfxx-nanomips.lo \ elf64-nfp.lo \ elf64-ppc.lo \ elf64-riscv.lo \ @@ -612,6 +618,7 @@ BFD64_BACKENDS_CFILES = \ elf64-ia64-vms.c \ elf64-mips.c \ elf64-mmix.c \ + elf64-nanomips.c \ elf64-nfp.c \ elf64-ppc.c \ elf64-s390.c \ @@ -625,6 +632,7 @@ BFD64_BACKENDS_CFILES = \ elfxx-kvx.c \ elfxx-loongarch.c \ elfxx-mips.c \ + elfxx-nanomips.c \ elfxx-riscv.c \ elfxx-x86.c \ mach-o-aarch64.c \ @@ -692,6 +700,7 @@ BUILD_CFILES = \ elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ elf32-riscv.c elf64-riscv.c \ + elf32-nanomips.c elf64-nanomips.c \ peigen.c pepigen.c pex64igen.c pe-aarch64igen.c pe-loongarch64igen.c \ pe-riscv64igen.c @@ -883,6 +892,14 @@ elf64-riscv.c : elfnn-riscv.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ +elf32-nanomips.c : elfnn-nanomips.c + $(AM_V_at)echo "#line 1 \"elfnn-nanomips.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ + +elf64-nanomips.c : elfnn-nanomips.c + $(AM_V_at)echo "#line 1 \"elfnn-nanomips.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ + peigen.c : peXXigen.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/XX/pe/g < $< >> $@ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index 14512cf61fb..af5c0dd8242 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -610,6 +610,7 @@ ALL_MACHINES = \ cpu-moxie.lo \ cpu-msp430.lo \ cpu-mt.lo \ + cpu-nanomips.lo \ cpu-nds32.lo \ cpu-nfp.lo \ cpu-ns32k.lo \ @@ -693,6 +694,7 @@ ALL_MACHINES_CFILES = \ cpu-moxie.c \ cpu-msp430.c \ cpu-mt.c \ + cpu-nanomips.c \ cpu-nds32.c \ cpu-nfp.c \ cpu-ns32k.c \ @@ -800,6 +802,7 @@ BFD32_BACKENDS = \ elf32-moxie.lo \ elf32-msp430.lo \ elf32-mt.lo \ + elf32-nanomips.lo \ elf32-nds32.lo \ elf32-or1k.lo \ elf32-pj.lo \ @@ -935,6 +938,7 @@ BFD32_BACKENDS_CFILES = \ elf32-moxie.c \ elf32-msp430.c \ elf32-mt.c \ + elf32-nanomips.c \ elf32-nds32.c \ elf32-or1k.c \ elf32-pj.c \ @@ -1017,6 +1021,7 @@ BFD64_BACKENDS = \ elf32-kvx.lo \ elf32-loongarch.lo \ elf32-mips.lo \ + elf32-nanomips.lo \ elf32-riscv.lo \ elf32-score.lo \ elf32-score7.lo \ @@ -1032,6 +1037,8 @@ BFD64_BACKENDS = \ elf64-loongarch.lo \ elf64-mips.lo \ elf64-mmix.lo \ + elf64-nanomips.lo \ + elfxx-nanomips.lo \ elf64-nfp.lo \ elf64-ppc.lo \ elf64-riscv.lo \ @@ -1095,6 +1102,7 @@ BFD64_BACKENDS_CFILES = \ elfxx-kvx.c \ elfxx-loongarch.c \ elfxx-mips.c \ + elfxx-nanomips.c \ elfxx-riscv.c \ elfxx-x86.c \ mach-o-aarch64.c \ @@ -1161,6 +1169,7 @@ BUILD_CFILES = \ elf32-ia64.c elf64-ia64.c \ elf32-loongarch.c elf64-loongarch.c \ elf32-riscv.c elf64-riscv.c \ + elf32-nanomips.c elf64-nanomips.c \ peigen.c pepigen.c pex64igen.c pe-aarch64igen.c pe-loongarch64igen.c \ pe-riscv64igen.c @@ -1612,6 +1621,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-moxie.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-msp430.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-mt.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-nanomips.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-nds32.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-or1k.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-pj.Plo@am__quote@ @@ -1651,6 +1661,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-loongarch.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-nanomips.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-nfp.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ @@ -1666,6 +1677,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-kvx.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-loongarch.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-mips.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-nanomips.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-riscv.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-sparc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elfxx-tilegx.Plo@am__quote@ @@ -2394,6 +2406,14 @@ elf64-riscv.c : elfnn-riscv.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ +elf32-nanomips.c : elfnn-nanomips.c + $(AM_V_at)echo "#line 1 \"elfnn-nanomips.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/32/g < $< >> $@ + +elf64-nanomips.c : elfnn-nanomips.c + $(AM_V_at)echo "#line 1 \"elfnn-nanomips.c\"" > $@ + $(AM_V_GEN)$(SED) -e s/NN/64/g < $< >> $@ + peigen.c : peXXigen.c $(AM_V_at)echo "#line 1 \"$<\"" > $@ $(AM_V_GEN)$(SED) -e s/XX/pe/g < $< >> $@ diff --git a/bfd/archures.c b/bfd/archures.c index 0e919246673..25dff977eff 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -545,6 +545,9 @@ DESCRIPTION . bfd_arch_nfp, {* Netronome Flow Processor *} .#define bfd_mach_nfp3200 0x3200 .#define bfd_mach_nfp6000 0x6000 +. bfd_arch_nanomips, {* nanoMIPSrX *} +.#define bfd_mach_nanomipsisa32r6 32 +.#define bfd_mach_nanomipsisa64r6 64 . bfd_arch_csky, {* C-SKY. *} .#define bfd_mach_ck_unknown 0 .#define bfd_mach_ck510 1 @@ -691,6 +694,7 @@ extern const bfd_arch_info_type bfd_moxie_arch; extern const bfd_arch_info_type bfd_ft32_arch; extern const bfd_arch_info_type bfd_msp430_arch; extern const bfd_arch_info_type bfd_mt_arch; +extern const bfd_arch_info_type bfd_nanomips_arch; extern const bfd_arch_info_type bfd_nds32_arch; extern const bfd_arch_info_type bfd_nfp_arch; extern const bfd_arch_info_type bfd_ns32k_arch; @@ -779,6 +783,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_ft32_arch, &bfd_msp430_arch, &bfd_mt_arch, + &bfd_nanomips_arch, &bfd_nds32_arch, &bfd_nfp_arch, &bfd_ns32k_arch, diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index e49d67316f3..91bc8779389 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1802,6 +1802,9 @@ enum bfd_architecture bfd_arch_nfp, /* Netronome Flow Processor */ #define bfd_mach_nfp3200 0x3200 #define bfd_mach_nfp6000 0x6000 + bfd_arch_nanomips, /* nanoMIPSrX */ +#define bfd_mach_nanomipsisa32r6 32 +#define bfd_mach_nanomipsisa64r6 64 bfd_arch_csky, /* C-SKY. */ #define bfd_mach_ck_unknown 0 #define bfd_mach_ck510 1 @@ -3808,6 +3811,75 @@ enum bfd_reloc_code_real BFD_RELOC_MICROMIPS_TLS_TPREL_LO16, BFD_RELOC_MIPS_EH, + /* nanoMIPS relocations */ + BFD_RELOC_NANOMIPS_HI20, + BFD_RELOC_NANOMIPS_LO12, + BFD_RELOC_NANOMIPS_LO4_S2, + BFD_RELOC_NANOMIPS_IMM16, + BFD_RELOC_NANOMIPS_NEG12, + BFD_RELOC_NANOMIPS_GPREL7_S2, + BFD_RELOC_NANOMIPS_GPREL18, + BFD_RELOC_NANOMIPS_GPREL19_S2, + BFD_RELOC_NANOMIPS_GPREL16_S2, + BFD_RELOC_NANOMIPS_GPREL18_S3, + BFD_RELOC_NANOMIPS_4_PCREL_S1, + BFD_RELOC_NANOMIPS_7_PCREL_S1, + BFD_RELOC_NANOMIPS_10_PCREL_S1, + BFD_RELOC_NANOMIPS_11_PCREL_S1, + BFD_RELOC_NANOMIPS_14_PCREL_S1, + BFD_RELOC_NANOMIPS_21_PCREL_S1, + BFD_RELOC_NANOMIPS_25_PCREL_S1, + BFD_RELOC_NANOMIPS_PCREL_HI20, + BFD_RELOC_NANOMIPS_GOT_CALL, + BFD_RELOC_NANOMIPS_GOTPC_HI20, + BFD_RELOC_NANOMIPS_GOTPC_I32, + BFD_RELOC_NANOMIPS_GOT_LO12, + BFD_RELOC_NANOMIPS_GOT_DISP, + BFD_RELOC_NANOMIPS_GOT_PAGE, + BFD_RELOC_NANOMIPS_GOT_OFST, + BFD_RELOC_NANOMIPS_I32, + BFD_RELOC_NANOMIPS_GPREL_HI20, + BFD_RELOC_NANOMIPS_GPREL_LO12, + BFD_RELOC_NANOMIPS_TLS_GD, + BFD_RELOC_NANOMIPS_TLS_GD_I32, + BFD_RELOC_NANOMIPS_TLS_LD, + BFD_RELOC_NANOMIPS_TLS_LD_I32, + BFD_RELOC_NANOMIPS_TLS_DTPREL12, + BFD_RELOC_NANOMIPS_TLS_DTPREL16, + BFD_RELOC_NANOMIPS_TLS_DTPREL_I32, + BFD_RELOC_NANOMIPS_TLS_GOTTPREL, + BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32, + BFD_RELOC_NANOMIPS_TLS_TPREL12, + BFD_RELOC_NANOMIPS_TLS_TPREL16, + BFD_RELOC_NANOMIPS_TLS_TPREL_I32, + BFD_RELOC_NANOMIPS_TLS_DTPMOD, + BFD_RELOC_NANOMIPS_TLS_DTPREL, + BFD_RELOC_NANOMIPS_TLS_TPREL, + BFD_RELOC_NANOMIPS_PC_I32, + BFD_RELOC_NANOMIPS_GPREL_I32, + BFD_RELOC_NANOMIPS_GPREL17_S1, + BFD_RELOC_NANOMIPS_NEG, + BFD_RELOC_NANOMIPS_ASHIFTR_1, + BFD_RELOC_NANOMIPS_UNSIGNED_8, + BFD_RELOC_NANOMIPS_UNSIGNED_16, + BFD_RELOC_NANOMIPS_SIGNED_8, + BFD_RELOC_NANOMIPS_SIGNED_16, + BFD_RELOC_NANOMIPS_EH, + BFD_RELOC_NANOMIPS_JUMP_SLOT, + BFD_RELOC_NANOMIPS_ALIGN, + BFD_RELOC_NANOMIPS_FILL, + BFD_RELOC_NANOMIPS_MAX, + BFD_RELOC_NANOMIPS_INSN32, + BFD_RELOC_NANOMIPS_INSN16, + BFD_RELOC_NANOMIPS_FIXED, + BFD_RELOC_NANOMIPS_RELAX, + BFD_RELOC_NANOMIPS_NORELAX, + BFD_RELOC_NANOMIPS_SAVERESTORE, + BFD_RELOC_NANOMIPS_JALR16, + BFD_RELOC_NANOMIPS_JALR32, + BFD_RELOC_NANOMIPS_COPY, + BFD_RELOC_NANOMIPS_SIGNED_9, + /* Moxie ELF relocations. */ BFD_RELOC_MOXIE_10_PCREL, diff --git a/bfd/config.bfd b/bfd/config.bfd index 02a1a68525e..0b61fa8b9e5 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -210,6 +210,7 @@ m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch bfd_m9s12x_arch b m68*) targ_archs=bfd_m68k_arch ;; microblaze*) targ_archs=bfd_microblaze_arch ;; mips*) targ_archs=bfd_mips_arch ;; +nanomips*) targ_archs=bfd_nanomips_arch ;; nds32*) targ_archs=bfd_nds32_arch ;; or1k*|or1knd*) targ_archs=bfd_or1k_arch ;; pdp11*) targ_archs=bfd_pdp11_arch ;; @@ -961,6 +962,16 @@ case "${targ}" in targ_underscore=yes ;; + nanomips*-*-elf*) + targ_defvec=nanomips_elf32_le_vec + targ_selvecs="nanomips_elf32_be_vec nanomips_elf64_be_vec nanomips_elf64_le_vec" + ;; + + nanomips*-*-linux*) + targ_defvec=nanomips_elf32_le_vec + targ_selvecs="nanomips_elf32_be_vec nanomips_elf64_be_vec nanomips_elf64_le_vec" + ;; + or1k-*-elf | or1k-*-linux* | or1k-*-rtems*) targ_defvec=or1k_elf32_vec ;; diff --git a/bfd/configure b/bfd/configure index 89c4f92b52e..f99abe76c30 100755 --- a/bfd/configure +++ b/bfd/configure @@ -16011,6 +16011,10 @@ do msp430_elf32_vec) tb="$tb elf32-msp430.lo elf32.lo elf-attrs.lo $elf" ;; msp430_elf32_ti_vec) tb="$tb elf32-msp430.lo elf32.lo elf-attrs.lo $elf" ;; mt_elf32_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; + nanomips_elf32_be_vec) tb="$tb elf32-nanomips.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo" ;; + nanomips_elf32_le_vec) tb="$tb elf32-nanomips.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo" ;; + nanomips_elf64_be_vec) tb="$tb elf64-nanomips.lo elf64.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; + nanomips_elf64_le_vec) tb="$tb elf64-nanomips.lo elf64.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; nds32_elf32_be_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;; nds32_elf32_le_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;; nds32_elf32_linux_be_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index c30a75ba8b7..b15a5840f72 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -552,6 +552,10 @@ do msp430_elf32_vec) tb="$tb elf32-msp430.lo elf32.lo elf-attrs.lo $elf" ;; msp430_elf32_ti_vec) tb="$tb elf32-msp430.lo elf32.lo elf-attrs.lo $elf" ;; mt_elf32_vec) tb="$tb elf32-mt.lo elf32.lo $elf" ;; + nanomips_elf32_be_vec) tb="$tb elf32-nanomips.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo" ;; + nanomips_elf32_le_vec) tb="$tb elf32-nanomips.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo" ;; + nanomips_elf64_be_vec) tb="$tb elf64-nanomips.lo elf64.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; + nanomips_elf64_le_vec) tb="$tb elf64-nanomips.lo elf64.lo elfxx-nanomips.lo elf32.lo $elf ecofflink.lo"; target_size=64 ;; nds32_elf32_be_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;; nds32_elf32_le_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;; nds32_elf32_linux_be_vec) tb="$tb elf32-nds32.lo elf32.lo $elf" ;; diff --git a/bfd/cpu-nanomips.c b/bfd/cpu-nanomips.c new file mode 100644 index 00000000000..d29e52c6094 --- /dev/null +++ b/bfd/cpu-nanomips.c @@ -0,0 +1,61 @@ +/* bfd back-end for nanomips support + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \ + { \ + BITS_WORD, /* bits in a word */ \ + BITS_ADDR, /* bits in an address */ \ + 8, /* 8 bits in a byte */ \ + bfd_arch_nanomips, \ + NUMBER, \ + "nanomips", \ + PRINT, \ + 3, \ + DEFAULT, \ + bfd_default_compatible, \ + bfd_default_scan, \ + bfd_arch_default_fill, \ + NEXT, \ + 0 /* Maximum offset of a reloc from the start of an insn. */ \ + } + +enum +{ + I_nanomipsisa32r6, + I_nanomipsisa64r6, +}; + +#define NN(index) (&arch_info_struct[(index) + 1]) + +static const bfd_arch_info_type arch_info_struct[] = { + N (32, 32, bfd_mach_nanomipsisa32r6, "nanomips:isa32r6", false, + NN (I_nanomipsisa32r6)), + N (64, 64, bfd_mach_nanomipsisa64r6, "nanomips:isa64r6", false, + NULL), +}; + +const bfd_arch_info_type bfd_nanomips_arch = + N (32, 32, 0, "nanomips", true, &arch_info_struct[0]); diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h index 88d35925987..e7e3acea135 100644 --- a/bfd/elf-bfd.h +++ b/bfd/elf-bfd.h @@ -574,6 +574,7 @@ enum elf_target_id MIPS_ELF_DATA, MMIX_ELF_DATA, MN10300_ELF_DATA, + NANOMIPS_ELF_DATA, NDS32_ELF_DATA, OR1K_ELF_DATA, PPC32_ELF_DATA, diff --git a/bfd/elfnn-nanomips.c b/bfd/elfnn-nanomips.c new file mode 100644 index 00000000000..bb9b6d93a64 --- /dev/null +++ b/bfd/elfnn-nanomips.c @@ -0,0 +1,1535 @@ +/* nanoMIPS-specific support for 32-bit ELF + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file handles nanoMIPS ELF targets. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "libiberty.h" +#include "ecoff-bfd.h" +#include "elfxx-nanomips.h" +#include "elf/nanomips.h" + +#define ARCH_SIZE NN + +#if ARCH_SIZE == 32 +/* Nonzero if ABFD is using the P32 ABI. */ +#define ABI_P32_P(abfd) \ + ((elf_elfheader (abfd)->e_flags & EF_NANOMIPS_ABI) != E_NANOMIPS_ABI_P64) +#else /* ARCH_SIZE != 32 */ +/* Nonzero if ABFD is using the P64 ABI. */ +#define ABI_P64_P(abfd) \ + ((elf_elfheader (abfd)->e_flags & EF_NANOMIPS_ABI) != E_NANOMIPS_ABI_P32) +#endif /* ARCH_SIZE == 32 */ + +/* In case we're on a 32-bit machine, construct a 64-bit "-1" value + from smaller values. Start with zero, widen, *then* decrement. */ +#define MINUS_ONE (((bfd_vma)0) - 1) + +/* The relocation table used for SHT_RELA sections. */ + +static reloc_howto_type elfNN_nanomips_howto_table_rela[] = { + /* No relocation. */ + HOWTO (R_NANOMIPS_NONE, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_NONE", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* 32 bit relocation. */ + HOWTO (R_NANOMIPS_32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* 64 bit relocation. */ + HOWTO (R_NANOMIPS_64, /* type */ + 0, /* rightshift */ + 4, /* size (0 = byte, 1 = short, 2 = long) */ + 64, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_64", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + MINUS_ONE, /* dst_mask */ + false), /* pcrel_offset */ + + /* Symbol address negation, can be composed for label differences. */ + HOWTO (R_NANOMIPS_NEG, /* type */ + 0, /* rightshift */ + 4, /* size (0 = byte, 1 = short, 2 = long) */ + 64, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_negative_reloc, /* special_function */ + "R_NANOMIPS_NEG", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* A 5 bit shift field. */ + HOWTO (R_NANOMIPS_ASHIFTR_1, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_ASHIFTR_1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_UNSIGNED_8, /* type */ + 0, /* rightshift */ + 1, /* size */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_UNSIGNED_8", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_SIGNED_8, /* type */ + 0, /* rightshift */ + 1, /* size */ + 8, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_SIGNED_8", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_UNSIGNED_16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_UNSIGNED_16", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_SIGNED_16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_SIGNED_16", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffff, /* dst_mask */ + false), /* pcrel_offset */ + + EMPTY_HOWTO (R_NANOMIPS_RELATIVE), + EMPTY_HOWTO (R_NANOMIPS_GLOBAL), + + /* Lazy resolver jump slot. */ + HOWTO (R_NANOMIPS_JUMP_SLOT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_JUMP_SLOT", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Reserved for IFUNC support. */ + EMPTY_HOWTO (R_NANOMIPS_IRELATIVE), + + HOWTO (R_NANOMIPS_PC25_S1, /* type */ + 1, /* rightshift */ + 4, /* size */ + 25, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC25_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x01ffffff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_PC21_S1, /* type */ + 1, /* rightshift */ + 4, /* size */ + 21, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC21_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0001ffff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_PC14_S1, /* type */ + 1, /* rightshift */ + 4, /* size */ + 14, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC14_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x00003fff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_PC11_S1, /* type */ + 1, /* rightshift */ + 4, /* size */ + 11, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC11_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x000007ff, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_PC10_S1, /* type */ + 1, /* rightshift */ + 2, /* size */ + 10, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC10_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x000003ff, /* dst_mask */ + true), /* pcrel_offset */ + + /* This is for nanoMIPS branches. */ + HOWTO (R_NANOMIPS_PC7_S1, /* type */ + 1, /* rightshift */ + 2, /* size */ + 7, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC7_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0000007f, /* dst_mask */ + true), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_PC4_S1, /* type */ + 1, /* rightshift */ + 2, /* size */ + 4, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC4_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0000000f, /* dst_mask */ + true), /* pcrel_offset */ + + /* GP relative reference. */ + HOWTO (R_NANOMIPS_GPREL19_S2, /* type */ + 2, /* rightshift */ + 4, /* size */ + 19, /* bitsize */ + false, /* pc_relative */ + 2, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL19_S2", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffffc, /* dst_mask */ + false), /* pcrel_offset */ + + /* GP relative reference. */ + HOWTO (R_NANOMIPS_GPREL18_S3, /* type */ + 3, /* rightshift */ + 4, /* size */ + 18, /* bitsize */ + false, /* pc_relative */ + 3, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL18_S3", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffff8, /* dst_mask */ + false), /* pcrel_offset */ + + /* GP relative reference. */ + HOWTO (R_NANOMIPS_GPREL18, /* type */ + 0, /* rightshift */ + 4, /* size */ + 18, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL18", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0003ffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* GP relative reference. */ + HOWTO (R_NANOMIPS_GPREL17_S1, /* type */ + 1, /* rightshift */ + 4, /* size */ + 17, /* bitsize */ + false, /* pc_relative */ + 1, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL17_S1", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0001fffe, /* dst_mask */ + false), /* pcrel_offset */ + + /* GP relative reference. */ + HOWTO (R_NANOMIPS_GPREL16_S2, /* type */ + 2, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 2, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL16_S2", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0003fffc, /* dst_mask */ + false), /* pcrel_offset */ + + /* GP- and PC-relative relocations. */ + HOWTO (R_NANOMIPS_GPREL7_S2, /* type */ + 2, /* rightshift */ + 2, /* size */ + 7, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL7_S2", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0000007f, /* dst_mask */ + false), /* pcrel_offset */ + + /* High 20 bits of GP relative reference. */ + HOWTO (R_NANOMIPS_GPREL_HI20, /* type */ + 0, /* rightshift */ + 4, /* size */ + 20, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL_HI20", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffffd, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_PCHI20, /* type */ + 12, /* rightshift */ + 4, /* size */ + 20, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PCHI20", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffffd, /* dst_mask */ + true), /* pcrel_offset */ + + /* High 20 bits of symbol value. */ + HOWTO (R_NANOMIPS_HI20, /* type */ + 12, /* rightshift */ + 4, /* size */ + 20, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_HI20", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffffd, /* dst_mask */ + false), /* pcrel_offset */ + + /* Low 12 bits of symbol value. */ + HOWTO (R_NANOMIPS_LO12, /* type */ + 0, /* rightshift */ + 4, /* size */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_LO12", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x00000fff, /* dst_mask */ + false), /* pcrel_offset */ + + /* High 32 bits of 64-bit address. */ + HOWTO (R_NANOMIPS_GPREL_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* High 32 bits of 64-bit address. */ + HOWTO (R_NANOMIPS_PC_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* Refers to low 32-bits of 48-bit instruction. The 32-bit value + is encoded as nanoMIPS instruction stream - so it will be + half-word swapped on little endian targets. */ + HOWTO (R_NANOMIPS_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_I32", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* Displacement in the global offset table. */ + HOWTO (R_NANOMIPS_GOT_DISP, /* type */ + 2, /* rightshift */ + 4, /* size */ + 19, /* bitsize */ + false, /* pc_relative */ + 2, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GOT_DISP", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x001ffffc, /* dst_mask */ + false), /* pcrel_offset */ + /* High 32 bits of 64-bit address. */ + HOWTO (R_NANOMIPS_GOTPC_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GOTPC_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* High 20 bits of PC-relative GOT offset. */ + HOWTO (R_NANOMIPS_GOTPC_HI20, /* type */ + 12, /* rightshift */ + 4, /* size */ + 20, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GOTPC_HI20", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x001ffffd, /* dst_mask */ + true), /* pcrel_offset */ + + /* Low 12 bits of displacement in global offset table. */ + HOWTO (R_NANOMIPS_GOT_LO12, /* type */ + 0, /* rightshift */ + 4, /* size */ + 12, /* bitsize */ + false, /* pc_relative */ + 2, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GOT_LO12", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x00000fff, /* dst_mask */ + true), /* pcrel_offset */ + + /* 19 bit call through global offset table. */ + HOWTO (R_NANOMIPS_GOT_CALL, /* type */ + 2, /* rightshift */ + 4, /* size */ + 19, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GOT_CALL", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x001ffffc, /* dst_mask */ + false), /* pcrel_offset */ + + /* Displacement to page pointer in the global offset table. */ + HOWTO (R_NANOMIPS_GOT_PAGE, /* type */ + 2, /* rightshift */ + 4, /* size */ + 19, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GOT_PAGE", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x001ffffc, /* dst_mask */ + false), /* pcrel_offset */ + + /* Offset from page pointer in the global offset table. */ + HOWTO (R_NANOMIPS_GOT_OFST, /* type */ + 0, /* rightshift */ + 4, /* size */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GOT_OFST", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x00000fff, /* dst_mask */ + false), /* pcrel_offset */ + + /* Low 4 bits of symbol value. */ + HOWTO (R_NANOMIPS_LO4_S2, /* type */ + 2, /* rightshift */ + 2, /* size */ + 4, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_LO4_S2", /* name */ + false, /* partial_inplace */ + 0x0000000f, /* src_mask */ + 0x0000000f, /* dst_mask */ + false), /* pcrel_offset */ + + /* Reserved for 64-bit ABI, HI32 relocation. */ + EMPTY_HOWTO (R_NANOMIPS_RESERVED1), + + /* Low 12 bits of GP-relative displacement. */ + HOWTO (R_NANOMIPS_GPREL_LO12, /* type */ + 0, /* rightshift */ + 4, /* size */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_GPREL_LO12", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x00000fff, /* dst_mask */ + false), /* pcrel_offset */ + + /* Section displacement. */ + HOWTO (R_NANOMIPS_SCN_DISP, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_SCN_DISP", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* Copy relocation. */ + HOWTO (R_NANOMIPS_COPY, /* type */ + 0, /* rightshift */ + 0, /* this one is variable size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_COPY", /* name */ + false, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + false), /* pcrel_offset */ + + EMPTY_HOWTO (45), + EMPTY_HOWTO (46), + EMPTY_HOWTO (47), + EMPTY_HOWTO (48), + EMPTY_HOWTO (49), + EMPTY_HOWTO (50), + EMPTY_HOWTO (51), + EMPTY_HOWTO (52), + EMPTY_HOWTO (53), + EMPTY_HOWTO (54), + EMPTY_HOWTO (55), + EMPTY_HOWTO (56), + EMPTY_HOWTO (57), + EMPTY_HOWTO (58), + EMPTY_HOWTO (59), + EMPTY_HOWTO (60), + EMPTY_HOWTO (61), + EMPTY_HOWTO (62), + EMPTY_HOWTO (63), + + /* Place-holder for code alignment. */ + HOWTO (R_NANOMIPS_ALIGN, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_ALIGN", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Fill value for code alignment. */ + HOWTO (R_NANOMIPS_FILL, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_FILL", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Maximum padding bytes for code alignment. */ + HOWTO (R_NANOMIPS_MAX, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_MAX", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Place-holder to enforce 32-bit instruction encoding. */ + HOWTO (R_NANOMIPS_INSN32, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_INSN32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Place-holder to inhibit relaxation on one instruction. */ + HOWTO (R_NANOMIPS_FIXED, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_FIXED", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Marker to inhibit linker relaxation. */ + HOWTO (R_NANOMIPS_NORELAX, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_NORELAX", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Marker to enable linker relaxation. */ + HOWTO (R_NANOMIPS_RELAX, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_RELAX", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Place-holder for relaxation of save/restore instructions. */ + HOWTO (R_NANOMIPS_SAVERESTORE, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_SAVERESTORE", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Place-holder to enforce 16-bit instruction encoding. */ + HOWTO (R_NANOMIPS_INSN16, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_INSN16", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Place-holder to enforce 32-bit JALR encoding. */ + HOWTO (R_NANOMIPS_JALR32, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_JALR32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + /* Place-holder to enforce 16-bit JALR encoding. */ + HOWTO (R_NANOMIPS_JALR16, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler. */ + "R_NANOMIPS_JALR16", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + EMPTY_HOWTO (75), + + /* Place-holder for relaxing frame-register information. */ + HOWTO (R_NANOMIPS_FRAME_REG, /* type */ + 0, /* rightshift */ + 1, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special handler */ + "R_NANOMIPS_FRAME_REG", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false), /* pcrel_offset */ + + + EMPTY_HOWTO (77), + EMPTY_HOWTO (78), + EMPTY_HOWTO (79), + + /* TLS GD/LD dynamic relocations. */ + HOWTO (R_NANOMIPS_TLS_DTPMOD, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_DTPMOD", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_TLS_DTPREL, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_DTPREL", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS IE dynamic relocations. */ + HOWTO (R_NANOMIPS_TLS_TPREL, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_TPREL", /* name */ + false, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS general dynamic variable reference. */ + HOWTO (R_NANOMIPS_TLS_GD, /* type */ + 2, /* rightshift */ + 4, /* size */ + 19, /* bitsize */ + false, /* pc_relative */ + 2, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_GD", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffffc, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_TLS_GD_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_GD_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS local dynamic variable reference. */ + HOWTO (R_NANOMIPS_TLS_LD, /* type */ + 2, /* rightshift */ + 4, /* size */ + 19, /* bitsize */ + false, /* pc_relative */ + 2, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_LD", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffffc, /* dst_mask */ + false), /* pcrel_offset */ + + HOWTO (R_NANOMIPS_TLS_LD_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_LD_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS local dynamic 12-bit offset. */ + HOWTO (R_NANOMIPS_TLS_DTPREL12, /* type */ + 0, /* rightshift */ + 4, /* size */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_DTPREL12", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x00000fff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS local dynamic 16-bit offset. */ + HOWTO (R_NANOMIPS_TLS_DTPREL16, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_DTPREL16", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0000ffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS local dynamic 32-bit offset. */ + HOWTO (R_NANOMIPS_TLS_DTPREL_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_DTPREL_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS thread pointer 21-bit GOT offset. */ + HOWTO (R_NANOMIPS_TLS_GOTTPREL, /* type */ + 2, /* rightshift */ + 4, /* size */ + 19, /* bitsize */ + false, /* pc_relative */ + 2, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_GOTTPREL", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x001ffffc, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS thread pointer 32-bit GOT offset. */ + HOWTO (R_NANOMIPS_TLS_GOTTPREL_PC_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_GOTTPREL_PC_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + true), /* pcrel_offset */ + + /* TLS thread pointer 12-bit offset. */ + HOWTO (R_NANOMIPS_TLS_TPREL12, /* type */ + 0, /* rightshift */ + 4, /* size */ + 12, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_TPREL12", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x00000fff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS thread pointer 16-bit offset. */ + HOWTO (R_NANOMIPS_TLS_TPREL16, /* type */ + 0, /* rightshift */ + 4, /* size */ + 16, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_TPREL16", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0x0000ffff, /* dst_mask */ + false), /* pcrel_offset */ + + /* TLS thread pointer 32-bit offset. */ + HOWTO (R_NANOMIPS_TLS_TPREL_I32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_TLS_TPREL_I32", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + false), /* pcrel_offset */ +}; + +/* GNU extension to record C++ vtable hierarchy */ +static reloc_howto_type elf_nanomips_gnu_vtinherit_howto = + HOWTO (R_NANOMIPS_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 4, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_NANOMIPS_GNU_VTINHERIT", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false); /* pcrel_offset */ + +/* GNU extension to record C++ vtable member usage */ +static reloc_howto_type elf_nanomips_gnu_vtentry_howto = + HOWTO (R_NANOMIPS_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 4, /* size */ + 0, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_NANOMIPS_GNU_VTENTRY", /* name */ + false, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + false); /* pcrel_offset */ + +/* 32 bit pc-relative. */ +static reloc_howto_type elf_nanomips_gnu_pcrel32 = + HOWTO (R_NANOMIPS_PC32, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + true, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_PC32", /* name */ + true, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + true); /* pcrel_offset */ + +/* Used in EH tables. */ +static reloc_howto_type elf_nanomips_eh_howto = + HOWTO (R_NANOMIPS_EH, /* type */ + 0, /* rightshift */ + 4, /* size */ + 32, /* bitsize */ + false, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + _bfd_nanomips_elf_generic_reloc, /* special_function */ + "R_NANOMIPS_EH", /* name */ + true, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + false); /* pcrel_offset */ + +/* A mapping from BFD reloc types to nanoMIPS ELF reloc types. */ + +struct elf_reloc_map +{ + bfd_reloc_code_real_type bfd_val; + enum elf_nanomips_reloc_type elf_val; +}; + +static const struct elf_reloc_map nanomips_reloc_map[] = { + { BFD_RELOC_NONE, R_NANOMIPS_NONE }, + { BFD_RELOC_32, R_NANOMIPS_32 }, + { BFD_RELOC_64, R_NANOMIPS_64 }, + { BFD_RELOC_NANOMIPS_NEG, R_NANOMIPS_NEG }, + { BFD_RELOC_NANOMIPS_ASHIFTR_1, R_NANOMIPS_ASHIFTR_1 }, + { BFD_RELOC_NANOMIPS_UNSIGNED_8, R_NANOMIPS_UNSIGNED_8 }, + { BFD_RELOC_NANOMIPS_SIGNED_8, R_NANOMIPS_SIGNED_8 }, + { BFD_RELOC_NANOMIPS_UNSIGNED_16, R_NANOMIPS_UNSIGNED_16 }, + { BFD_RELOC_16, R_NANOMIPS_UNSIGNED_16 }, + { BFD_RELOC_NANOMIPS_SIGNED_16, R_NANOMIPS_SIGNED_16 }, + { BFD_RELOC_NANOMIPS_HI20, R_NANOMIPS_HI20 }, + { BFD_RELOC_NANOMIPS_LO12, R_NANOMIPS_LO12 }, + { BFD_RELOC_NANOMIPS_IMM16, R_NANOMIPS_LO12 }, + { BFD_RELOC_NANOMIPS_25_PCREL_S1, R_NANOMIPS_PC25_S1 }, + { BFD_RELOC_NANOMIPS_21_PCREL_S1, R_NANOMIPS_PC21_S1 }, + { BFD_RELOC_NANOMIPS_14_PCREL_S1, R_NANOMIPS_PC14_S1 }, + { BFD_RELOC_NANOMIPS_11_PCREL_S1, R_NANOMIPS_PC11_S1 }, + { BFD_RELOC_NANOMIPS_10_PCREL_S1, R_NANOMIPS_PC10_S1 }, + { BFD_RELOC_NANOMIPS_7_PCREL_S1, R_NANOMIPS_PC7_S1 }, + { BFD_RELOC_NANOMIPS_GPREL7_S2, R_NANOMIPS_GPREL7_S2 }, + { BFD_RELOC_NANOMIPS_GPREL18, R_NANOMIPS_GPREL18 }, + { BFD_RELOC_NANOMIPS_GPREL19_S2, R_NANOMIPS_GPREL19_S2 }, + { BFD_RELOC_NANOMIPS_4_PCREL_S1,R_NANOMIPS_PC4_S1 }, + { BFD_RELOC_NANOMIPS_PCREL_HI20, R_NANOMIPS_PCHI20 }, + { BFD_RELOC_NANOMIPS_GPREL16_S2, R_NANOMIPS_GPREL16_S2 }, + { BFD_RELOC_NANOMIPS_GPREL18_S3, R_NANOMIPS_GPREL18_S3 }, + { BFD_RELOC_NANOMIPS_GOT_CALL, R_NANOMIPS_GOT_CALL }, + { BFD_RELOC_NANOMIPS_GOT_DISP, R_NANOMIPS_GOT_DISP }, + { BFD_RELOC_NANOMIPS_GOT_PAGE, R_NANOMIPS_GOT_PAGE }, + { BFD_RELOC_NANOMIPS_GOT_OFST, R_NANOMIPS_GOT_OFST }, + { BFD_RELOC_NANOMIPS_GOTPC_HI20, R_NANOMIPS_GOTPC_HI20 }, + { BFD_RELOC_NANOMIPS_GOT_LO12, R_NANOMIPS_GOT_LO12 }, + { BFD_RELOC_NANOMIPS_GOTPC_I32, R_NANOMIPS_GOTPC_I32 }, + { BFD_RELOC_NANOMIPS_I32, R_NANOMIPS_I32 }, + { BFD_RELOC_NANOMIPS_GPREL_HI20, R_NANOMIPS_GPREL_HI20 }, + { BFD_RELOC_NANOMIPS_PC_I32, R_NANOMIPS_PC_I32 }, + { BFD_RELOC_NANOMIPS_GPREL_I32, R_NANOMIPS_GPREL_I32 }, + { BFD_RELOC_NANOMIPS_GPREL17_S1, R_NANOMIPS_GPREL17_S1 }, + { BFD_RELOC_NANOMIPS_GPREL_LO12, R_NANOMIPS_GPREL_LO12 }, + { BFD_RELOC_NANOMIPS_LO4_S2, R_NANOMIPS_LO4_S2 }, + { BFD_RELOC_NANOMIPS_COPY, R_NANOMIPS_COPY }, + + { BFD_RELOC_NANOMIPS_ALIGN, R_NANOMIPS_ALIGN }, + { BFD_RELOC_NANOMIPS_FILL, R_NANOMIPS_FILL }, + { BFD_RELOC_NANOMIPS_MAX, R_NANOMIPS_MAX }, + { BFD_RELOC_NANOMIPS_INSN32, R_NANOMIPS_INSN32 }, + { BFD_RELOC_NANOMIPS_INSN16, R_NANOMIPS_INSN16 }, + { BFD_RELOC_NANOMIPS_FIXED, R_NANOMIPS_FIXED }, + { BFD_RELOC_NANOMIPS_RELAX, R_NANOMIPS_RELAX }, + { BFD_RELOC_NANOMIPS_NORELAX, R_NANOMIPS_NORELAX }, + { BFD_RELOC_NANOMIPS_SAVERESTORE, R_NANOMIPS_SAVERESTORE }, + { BFD_RELOC_NANOMIPS_JALR32, R_NANOMIPS_JALR32 }, + { BFD_RELOC_NANOMIPS_JALR16, R_NANOMIPS_JALR16 }, + + { BFD_RELOC_NANOMIPS_TLS_GD, R_NANOMIPS_TLS_GD }, + { BFD_RELOC_NANOMIPS_TLS_GD_I32, R_NANOMIPS_TLS_GD_I32 }, + { BFD_RELOC_NANOMIPS_TLS_LD, R_NANOMIPS_TLS_LD }, + { BFD_RELOC_NANOMIPS_TLS_LD_I32, R_NANOMIPS_TLS_LD_I32 }, + { BFD_RELOC_NANOMIPS_TLS_DTPREL12, R_NANOMIPS_TLS_DTPREL12 }, + { BFD_RELOC_NANOMIPS_TLS_DTPREL16, R_NANOMIPS_TLS_DTPREL16 }, + { BFD_RELOC_NANOMIPS_TLS_DTPREL_I32, R_NANOMIPS_TLS_DTPREL_I32 }, + { BFD_RELOC_NANOMIPS_TLS_GOTTPREL, R_NANOMIPS_TLS_GOTTPREL }, + { BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32, R_NANOMIPS_TLS_GOTTPREL_PC_I32 }, + { BFD_RELOC_NANOMIPS_TLS_TPREL12, R_NANOMIPS_TLS_TPREL12 }, + { BFD_RELOC_NANOMIPS_TLS_TPREL16, R_NANOMIPS_TLS_TPREL16 }, + { BFD_RELOC_NANOMIPS_TLS_TPREL_I32, R_NANOMIPS_TLS_TPREL_I32 }, + { BFD_RELOC_NANOMIPS_TLS_DTPMOD, R_NANOMIPS_TLS_DTPMOD }, + { BFD_RELOC_NANOMIPS_TLS_DTPREL, R_NANOMIPS_TLS_DTPREL }, + { BFD_RELOC_NANOMIPS_TLS_TPREL, R_NANOMIPS_TLS_TPREL }, +}; + +/* Given a BFD reloc type, return a howto structure. */ + +static reloc_howto_type * +bfd_elfNN_bfd_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + unsigned int i; + reloc_howto_type *howto_nanomips_table; + + howto_nanomips_table = elfNN_nanomips_howto_table_rela; + + for (i = 0; i < sizeof (nanomips_reloc_map) / sizeof (struct elf_reloc_map); + i++) + { + if (nanomips_reloc_map[i].bfd_val == code) + return &howto_nanomips_table[(int) nanomips_reloc_map[i].elf_val]; + } + + switch (code) + { + default: + bfd_set_error (bfd_error_bad_value); + return NULL; + + case BFD_RELOC_CTOR: + return &howto_nanomips_table[(int) R_NANOMIPS_32]; + + case BFD_RELOC_VTABLE_INHERIT: + return &elf_nanomips_gnu_vtinherit_howto; + case BFD_RELOC_VTABLE_ENTRY: + return &elf_nanomips_gnu_vtentry_howto; + case BFD_RELOC_NANOMIPS_EH: + return &elf_nanomips_eh_howto; + case BFD_RELOC_32_PCREL: + return &elf_nanomips_gnu_pcrel32; + } +} + +/* Map a BFD relocation to its display name. */ + +static reloc_howto_type * +bfd_elfNN_bfd_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, + const char *r_name) +{ + unsigned int i; + + for (i = 0; + i < (sizeof (elfNN_nanomips_howto_table_rela) + / sizeof (elfNN_nanomips_howto_table_rela[0])); i++) + if (elfNN_nanomips_howto_table_rela[i].name != NULL + && strcasecmp (elfNN_nanomips_howto_table_rela[i].name, r_name) == 0) + return &elfNN_nanomips_howto_table_rela[i]; + + if (strcasecmp (elf_nanomips_gnu_vtinherit_howto.name, r_name) == 0) + return &elf_nanomips_gnu_vtinherit_howto; + if (strcasecmp (elf_nanomips_gnu_vtentry_howto.name, r_name) == 0) + return &elf_nanomips_gnu_vtentry_howto; + if (strcasecmp (elf_nanomips_eh_howto.name, r_name) == 0) + return &elf_nanomips_eh_howto; + + return NULL; +} + +/* Given a nanoMIPS Elf_Internal_Rel, fill in an arelent structure. */ + +static reloc_howto_type * +nanomips_elfNN_rtype_to_howto (bfd *abfd, unsigned int r_type) +{ + switch (r_type) + { + case R_NANOMIPS_GNU_VTINHERIT: + return &elf_nanomips_gnu_vtinherit_howto; + case R_NANOMIPS_GNU_VTENTRY: + return &elf_nanomips_gnu_vtentry_howto; + case R_NANOMIPS_EH: + return &elf_nanomips_eh_howto; + case R_NANOMIPS_PC32: + return &elf_nanomips_gnu_pcrel32; + default: + if (r_type >= ARRAY_SIZE (elfNN_nanomips_howto_table_rela)) + { + (*_bfd_error_handler) (_("%pB: unsupported relocation type %#x"), + abfd, r_type); + bfd_set_error (bfd_error_bad_value); + return NULL; + } + return &elfNN_nanomips_howto_table_rela[r_type]; + } +} + +/* Given a nanoMIPS Elf_Internal_Rela, fill in an arelent structure. */ + +static bool +nanomips_info_to_howto_rela (bfd *abfd, arelent *cache_ptr, Elf_Internal_Rela *dst) +{ + cache_ptr->howto = nanomips_elfNN_rtype_to_howto (abfd, ELFNN_R_TYPE (dst->r_info)); + cache_ptr->addend = dst->r_addend; + return cache_ptr->howto != NULL; +} + +/* nanoMIPS ELF local labels start with '$'. */ + +static bool +nanomips_elf_is_local_label_name (bfd *abfd, const char *name) +{ + if (name[0] == '$') + return true; + + /* Fall back to the generic ELF local label syntax. */ + return _bfd_elf_is_local_label_name (abfd, name); +} + +/* Set the right machine number for a nanoMIPS ELF file. */ + +static bool +nanomips_elfNN_object_p (bfd *abfd) +{ + unsigned long mach; + + if (!ABI_PNN_P (abfd)) + return false; + + mach = _bfd_elf_nanomips_mach (elf_elfheader (abfd)->e_flags); + bfd_default_set_arch_mach (abfd, bfd_arch_nanomips, mach); + return true; +} + +#if ARCH_SIZE == 32 +# define PRSTATUS_SIZE 256 +# define PRSTATUS_OFFSET_PR_CURSIG 12 +# define PRSTATUS_OFFSET_PR_PID 24 +# define PRSTATUS_OFFSET_PR_REG 72 +# define ELF_GREGSET_T_SIZE 180 +# define PRPSINFO_SIZE 128 +# define PRPSINFO_OFFSET_PR_PID 16 +# define PRPSINFO_OFFSET_PR_FNAME 32 +# define PRPSINFO_OFFSET_PR_PSARGS 48 +#else +# define PRSTATUS_SIZE 480 +# define PRSTATUS_OFFSET_PR_CURSIG 12 +# define PRSTATUS_OFFSET_PR_PID 32 +# define PRSTATUS_OFFSET_PR_REG 112 +# define ELF_GREGSET_T_SIZE 360 +# define PRPSINFO_SIZE 136 +# define PRPSINFO_OFFSET_PR_PID 24 +# define PRPSINFO_OFFSET_PR_FNAME 40 +# define PRPSINFO_OFFSET_PR_PSARGS 56 +#endif + +static bool +nanomips_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) +{ + size_t size; + int offset; + + switch (note->descsz) + { + default: + return false; + + case PRSTATUS_SIZE: /* sizeof(struct elf_prstatus) on Linux/nanoMIPS. */ + /* pr_cursig */ + elf_tdata (abfd)->core->signal + = bfd_get_16 (abfd, note->descdata + PRSTATUS_OFFSET_PR_CURSIG); + + /* pr_pid */ + elf_tdata (abfd)->core->lwpid + = bfd_get_32 (abfd, note->descdata + PRSTATUS_OFFSET_PR_PID); + + /* pr_reg */ + offset = PRSTATUS_OFFSET_PR_REG; + size = ELF_GREGSET_T_SIZE; + break; + } + /* Make a ".reg/999" section. */ + return _bfd_elfcore_make_pseudosection (abfd, ".reg", size, + note->descpos + offset); +} + +static bool +nanomips_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) +{ + switch (note->descsz) + { + default: + return false; + + case PRPSINFO_SIZE: /* sizeof(struct elf_prpsinfo) on Linux/nanoMIPS. */ + /* pr_pid */ + elf_tdata (abfd)->core->pid + = bfd_get_32 (abfd, note->descdata + PRPSINFO_OFFSET_PR_PID); + + /* pr_fname */ + elf_tdata (abfd)->core->program = _bfd_elfcore_strndup + (abfd, note->descdata + PRPSINFO_OFFSET_PR_FNAME, 16); + + /* pr_psargs */ + elf_tdata (abfd)->core->command = _bfd_elfcore_strndup + (abfd, note->descdata + PRPSINFO_OFFSET_PR_PSARGS, 80); + break; + } + /* Note that for some reason, a spurious space is tacked + onto the end of the args in some (at least one anyway) + implementations, so strip it off if it exists. */ + { + char *command = elf_tdata (abfd)->core->command; + int n = strlen (command); + + if (0 < n && command[n - 1] == ' ') + command[n - 1] = '\0'; + } + return true; +} + +/* Write Linux core PRSTATUS note into core file. */ + +static char * +nanomips_elf_write_core_note (bfd *abfd, char *buf, int *bufsiz, int note_type, + ...) +{ + switch (note_type) + { + default: + return NULL; + + case NT_PRPSINFO: + BFD_FAIL (); + return NULL; + + case NT_PRSTATUS: + { + char data[PRSTATUS_SIZE]; + va_list ap; + long pid; + int cursig; + const void *greg; + + va_start (ap, note_type); + memset (data, 0, PRSTATUS_OFFSET_PR_REG); + pid = va_arg (ap, long); + bfd_put_32 (abfd, pid, data + PRSTATUS_OFFSET_PR_PID); + cursig = va_arg (ap, int); + bfd_put_16 (abfd, cursig, data + PRSTATUS_OFFSET_PR_CURSIG); + greg = va_arg (ap, const void *); + memcpy (data + PRSTATUS_OFFSET_PR_REG, greg, ELF_GREGSET_T_SIZE); + memset (data + PRSTATUS_OFFSET_PR_REG + ELF_GREGSET_T_SIZE, 0, + PRSTATUS_SIZE - (PRSTATUS_OFFSET_PR_REG + ELF_GREGSET_T_SIZE)); + va_end (ap); + return elfcore_write_note (abfd, buf, bufsiz, + "CORE", note_type, data, sizeof (data)); + } + } +} + +#define ELF_ARCH bfd_arch_nanomips +#define ELF_TARGET_ID NANOMIPS_ELF_DATA +#define ELF_MACHINE_CODE EM_NANOMIPS + +#define elf_backend_collect true +#define elf_backend_type_change_ok true +#define elf_info_to_howto nanomips_info_to_howto_rela +#define elf_backend_object_p nanomips_elfNN_object_p +#define elf_backend_section_processing _bfd_nanomips_elf_section_processing +#define elf_backend_section_from_shdr _bfd_nanomips_elf_section_from_shdr +#define elf_backend_final_write_processing \ + _bfd_nanomips_elf_final_write_processing +#define elf_backend_grok_prstatus nanomips_elf_grok_prstatus +#define elf_backend_grok_psinfo nanomips_elf_grok_psinfo +#define elf_backend_write_core_note nanomips_elf_write_core_note + +#define elf_backend_may_use_rela_p 1 +#define elf_backend_default_use_rela_p 1 +#define elf_backend_sign_extend_vma true +#define elf_backend_plt_readonly 1 + +#define bfd_elfNN_bfd_print_private_bfd_data \ + _bfd_nanomips_elf_print_private_bfd_data +#define bfd_elfNN_mkobject _bfd_nanomips_elf_mkobject +#define bfd_elfNN_bfd_is_local_label_name \ + nanomips_elf_is_local_label_name + +#define ELF_MAXPAGESIZE 0x1000 +#define ELF_COMMONPAGESIZE 0x1000 + +/* Support for nanomipsNN target. */ + +#define TARGET_LITTLE_SYM nanomips_elfNN_le_vec +#define TARGET_LITTLE_NAME "elfNN-littlenanomips" +#define TARGET_BIG_SYM nanomips_elfNN_be_vec +#define TARGET_BIG_NAME "elfNN-bignanomips" + +#define elfNN_bed elfNN_nanomips_bed + +/* Include the target file for this target. */ +#include "elfNN-target.h" diff --git a/bfd/elfxx-nanomips.c b/bfd/elfxx-nanomips.c new file mode 100644 index 00000000000..7f4a441d789 --- /dev/null +++ b/bfd/elfxx-nanomips.c @@ -0,0 +1,449 @@ +/* nanoMIPS-specific support for ELF + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file handles functionality common to nanoMIPS ABIs. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "ecoff-bfd.h" +#include "elfxx-nanomips.h" +#include "elf/nanomips.h" + +/* nanoMIPS ELF private object data. */ + +struct nanomips_elf_obj_tdata +{ + /* Generic ELF private object data. */ + struct elf_obj_tdata root; + + /* Input BFD providing Tag_GNU_NANOMIPS_ABI_FP attribute for output. */ + bfd *abi_fp_bfd; + + bfd_signed_vma sdata_section[1000]; +}; + +/* Get nanoMIPS ELF private object data from BFD's tdata. */ + +#define nanomips_elf_tdata(bfd) \ + ((struct nanomips_elf_obj_tdata *) (bfd)->tdata.any) + +/* Allocate nanoMIPS ELF private object data. */ + +bool +_bfd_nanomips_elf_mkobject (bfd *abfd) +{ + return bfd_elf_allocate_object (abfd, sizeof (struct nanomips_elf_obj_tdata)); +} + +/* A generic howto special_function. This calculates and installs the + relocation itself, thus avoiding the oft-discussed problems in + bfd_perform_relocation and bfd_install_relocation. */ + +bfd_reloc_status_type +_bfd_nanomips_elf_generic_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, asymbol *symbol, + void *data ATTRIBUTE_UNUSED, + asection *input_section, bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_signed_vma val; + bfd_reloc_status_type status; + bool relocatable; + + relocatable = (output_bfd != NULL); + + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + /* Build up the field adjustment in VAL. */ + val = 0; + if (!relocatable || (symbol->flags & BSF_SECTION_SYM) != 0) + { + /* Either we're calculating the final field value or we have a + relocation against a section symbol. Add in the section's + offset or address. */ + val += symbol->section->output_section->vma; + val += symbol->section->output_offset; + } + + if (!relocatable) + { + /* We're calculating the final field value. Add in the symbol's value + and, if pc-relative, subtract the address of the field itself. */ + val += symbol->value; + if (reloc_entry->howto->pc_relative) + { + val -= input_section->output_section->vma; + val -= input_section->output_offset; + val -= reloc_entry->address; + } + } + /* VAL is now the final adjustment. If we're keeping this relocation + in the output file, and if the relocation uses a separate addend, + we just need to add VAL to that addend. Otherwise we need to add + VAL to the relocation field itself. */ + if (relocatable && !reloc_entry->howto->partial_inplace) + reloc_entry->addend += val; + else + { + bfd_byte *location = (bfd_byte *) data + reloc_entry->address; + + /* Add in the separate addend, if any. */ + val += reloc_entry->addend; + + /* Add VAL to the relocation field. */ + status = _bfd_relocate_contents (reloc_entry->howto, abfd, val, + location); + if (status != bfd_reloc_ok) + return status; + } + + if (relocatable) + reloc_entry->address += input_section->output_offset; + + return bfd_reloc_ok; +} + +/* A negation howto special_function. */ + +bfd_reloc_status_type +_bfd_nanomips_elf_negative_reloc (bfd *abfd ATTRIBUTE_UNUSED, + arelent *reloc_entry, asymbol *symbol, + void *data ATTRIBUTE_UNUSED, + asection *input_section, bfd *output_bfd, + char **error_message ATTRIBUTE_UNUSED) +{ + bfd_signed_vma val; + bool relocatable; + + relocatable = (output_bfd != NULL); + + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) + return bfd_reloc_outofrange; + + /* Calculate the value of the symbol S. */ + val = 0; + val += symbol->section->output_section->vma; + val += symbol->section->output_offset; + val += symbol->value; + + /* Transmit the negated value (-S + A) for composition. */ + if (!relocatable && reloc_entry[1].address == reloc_entry->address) + reloc_entry[1].addend = - val + reloc_entry->addend; + + if (relocatable) + reloc_entry->address += input_section->output_offset; + + return bfd_reloc_ok; +} + +/* Map flag bits to BFD architecture. */ + +unsigned long +_bfd_elf_nanomips_mach (flagword flags) +{ + switch (flags & EF_NANOMIPS_ARCH) + { + default: + case E_NANOMIPS_ARCH_32R6: + return bfd_mach_nanomipsisa32r6; + case E_NANOMIPS_ARCH_64R6: + return bfd_mach_nanomipsisa64r6; + } + return 0; +} + +/* Return printable name for ABI. */ + +static inline char * +elf_nanomips_abi_name (bfd *abfd) +{ + flagword flags; + + flags = elf_elfheader (abfd)->e_flags; + switch (flags & EF_NANOMIPS_ABI) + { + case 0: + return "none"; + case E_NANOMIPS_ABI_P32: + return "P32"; + case E_NANOMIPS_ABI_P64: + return "P64"; + default: + return "unknown abi"; + } +} + +/* Work over a section just before writing it out. This routine is + used by both the 32-bit and the 64-bit ABI. */ + +bool +_bfd_nanomips_elf_section_processing (bfd *abfd, Elf_Internal_Shdr *hdr) +{ + if (hdr->bfd_section != NULL) + { + const char *name = bfd_section_name (hdr->bfd_section); + + /* .sbss is not handled specially here because the GNU/Linux + prelinker can convert .sbss from NOBITS to PROGBITS and + changing it back to NOBITS breaks the binary. The entry in + _bfd_nanomips_elf_special_sections will ensure the correct flags + are set on .sbss if BFD creates it without reading it from an + input file, and without special handling here the flags set + on it in an input file will be followed. */ + if (strcmp (name, ".sdata") == 0 + || strcmp (name, ".lit8") == 0 + || strcmp (name, ".lit4") == 0 + || strncmp (name, ".sdata_", 7) == 0) + { + hdr->sh_flags |= SHF_ALLOC | SHF_WRITE; + hdr->sh_type = SHT_PROGBITS; + } + else if (strcmp (name, ".srdata") == 0) + { + hdr->sh_flags |= SHF_ALLOC; + hdr->sh_type = SHT_PROGBITS; + } + else if (strcmp (name, ".compact_rel") == 0) + { + hdr->sh_flags = 0; + hdr->sh_type = SHT_PROGBITS; + } + else if (strcmp (name, ".rtproc") == 0) + { + if (hdr->sh_addralign != 0 && hdr->sh_entsize == 0) + { + unsigned int adjust; + + adjust = hdr->sh_size % hdr->sh_addralign; + if (adjust != 0) + hdr->sh_size += hdr->sh_addralign - adjust; + } + } + } + return true; +} + +/* Handle a nanoMIPS specific section when reading an object file. + This is called when elfcode.h finds a section with an unknown type. + This routine supports both the 32-bit and 64-bit ELF ABI. */ + +bool +_bfd_nanomips_elf_section_from_shdr (bfd *abfd, Elf_Internal_Shdr *hdr, + const char *name, int shindex) +{ + flagword flags = 0; + + if (!_bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex)) + return false; + + if (flags) + { + if (!bfd_set_section_flags (hdr->bfd_section, + (bfd_section_flags (hdr->bfd_section) + | flags))) + return false; + } + + return true; +} + +/* Functions for the dynamic linker. */ + +/* Set ABFD's EF_NANOMIPS_ARCH and EF_NANOMIPS_MACH flags. */ + +static void +nanomips_set_isa_flags (bfd *abfd) +{ + flagword val = 0; + + elf_elfheader (abfd)->e_flags &= ~(EF_NANOMIPS_ARCH | EF_NANOMIPS_MACH); + elf_elfheader (abfd)->e_flags |= val; +} + +/* The final processing done just before writing out a nanoMIPS ELF + object file. This gets the nanoMIPS architecture right based on the + machine number. This is used by both the 32-bit and the 64-bit ABI. */ + +void +_bfd_nanomips_final_write_processing (bfd *abfd) +{ + nanomips_set_isa_flags (abfd); +} + +bool +_bfd_nanomips_elf_final_write_processing (bfd *abfd) +{ + _bfd_nanomips_final_write_processing (abfd); + return _bfd_elf_final_write_processing (abfd); +} + +/* Return the meaning of Tag_GNU_NANOMIPS_ABI_FP value FP, or null if + not known. */ + +const char * +_bfd_nanomips_fp_abi_string (int fp) +{ + switch (fp) + { + /* These strings aren't translated because they're simply + option lists. */ + case Val_GNU_NANOMIPS_ABI_FP_DOUBLE: + return "-mdouble-float"; + case Val_GNU_NANOMIPS_ABI_FP_SINGLE: + return "-msingle-float"; + case Val_GNU_NANOMIPS_ABI_FP_SOFT: + return "-msoft-float"; + default: + return 0; + } +} + +/* Print the name of an ASE. */ + +static void +print_nanomips_ases (FILE *file, unsigned int mask) +{ + if (mask & NANOMIPS_ASE_MT) + fputs ("\n\tMT ASE", file); + if (mask & NANOMIPS_ASE_VIRT) + fputs ("\n\tVZ ASE", file); + if ((mask & NANOMIPS_ASE_xNMS) == 0) + fputs ("\n\tnanoMIPS subset", file); + else if (mask == 0) + fprintf (file, "\n\t%s", _("None")); + else if ((mask & ~NANOMIPS_ASE_MASK) != 0) + fprintf (stdout, "\n\t%s (%x)", _("Unknown"), mask & ~NANOMIPS_ASE_MASK); +} + +/* Print the name of an ISA extension. None yet for nanoMIPS. */ + +static void +print_nanomips_isa_ext (FILE *file, unsigned int isa_ext) +{ + switch (isa_ext) + { + case 0: + fputs (_("None"), file); + break; + default: + fprintf (file, "%s (%d)", _("Unknown"), isa_ext); + break; + } +} + +/* Decode and print the FP ABI mode. */ + +static void +print_nanomips_fp_abi_value (FILE *file, int val) +{ + switch (val) + { + case Val_GNU_NANOMIPS_ABI_FP_ANY: + fprintf (file, _("Hard or soft float\n")); + break; + case Val_GNU_NANOMIPS_ABI_FP_DOUBLE: + fprintf (file, _("Hard float (double precision)\n")); + break; + case Val_GNU_NANOMIPS_ABI_FP_SINGLE: + fprintf (file, _("Hard float (single precision)\n")); + break; + case Val_GNU_NANOMIPS_ABI_FP_SOFT: + fprintf (file, _("Soft float\n")); + break; + default: + fprintf (file, "??? (%d)\n", val); + break; + } +} + +/* Print nanoMIPS-specific ELF data. */ + +bool +_bfd_nanomips_elf_print_private_bfd_data (bfd *abfd, void *ptr) +{ + FILE *file = ptr; + + BFD_ASSERT (abfd != NULL && ptr != NULL); + + /* Print normal ELF private data. */ + _bfd_elf_print_private_bfd_data (abfd, ptr); + + /* xgettext:c-format */ + fprintf (file, _("private flags = %08lx:"), elf_elfheader (abfd)->e_flags); + + if ((elf_elfheader (abfd)->e_flags & EF_NANOMIPS_ABI) == E_NANOMIPS_ABI_P32) + fprintf (file, _(" [abi=P32]")); + else if ((elf_elfheader (abfd)->e_flags & EF_NANOMIPS_ABI) == + E_NANOMIPS_ABI_P64) + fprintf (file, _(" [abi=P64]")); + else + fprintf (file, _(" [no abi set]")); + + if ((elf_elfheader (abfd)->e_flags & EF_NANOMIPS_ARCH) == E_NANOMIPS_ARCH_32R6) + fprintf (file, " [nanomips32r6]"); + else if ((elf_elfheader (abfd)->e_flags & EF_NANOMIPS_ARCH) == E_NANOMIPS_ARCH_64R6) + fprintf (file, " [nanomips64r6]"); + else + fprintf (file, _(" [unknown ISA]")); + + if (elf_elfheader (abfd)->e_flags & EF_NANOMIPS_32BITMODE) + fprintf (file, " [32bitmode]"); + else + fprintf (file, _(" [not 32bitmode]")); + + if (elf_elfheader (abfd)->e_flags & EF_NANOMIPS_PIC) + fprintf (file, " [PIC]"); + + fputc ('\n', file); + + return true; +} + +const struct bfd_elf_special_section _bfd_nanomips_elf_special_sections[] = { + { STRING_COMMA_LEN (".lit4"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE}, + { STRING_COMMA_LEN (".lit8"), 0, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE}, + { STRING_COMMA_LEN (".sbss"), -2, SHT_NOBITS, SHF_ALLOC + SHF_WRITE}, + { STRING_COMMA_LEN (".sdata"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE}, + { NULL, 0, 0, 0, 0 } +}; + +/* Merge non visibility st_other attributes. Ensure that the + STO_OPTIONAL flag is copied into h->other, even if this is not a + definiton of the symbol. */ + +void +_bfd_nanomips_elf_merge_symbol_attribute (struct elf_link_hash_entry *h, + unsigned int st_other, + bool definition, + bool dynamic ATTRIBUTE_UNUSED) +{ + if ((st_other & ~ELF_ST_VISIBILITY (-1)) != 0) + { + unsigned char other; + other = (definition ? st_other : h->other); + other &= ~ELF_ST_VISIBILITY (-1); + h->other = other | ELF_ST_VISIBILITY (h->other); + } +} diff --git a/bfd/elfxx-nanomips.h b/bfd/elfxx-nanomips.h new file mode 100644 index 00000000000..c5ed51c7538 --- /dev/null +++ b/bfd/elfxx-nanomips.h @@ -0,0 +1,46 @@ +/* nanoMIPS ELF specific backend routines. + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "elf/nanomips.h" + +extern bool _bfd_nanomips_elf_mkobject (bfd *); +extern bool _bfd_nanomips_elf_section_processing + (bfd *, Elf_Internal_Shdr *); +extern bool _bfd_nanomips_elf_section_from_shdr + (bfd *, Elf_Internal_Shdr *, const char *, int); +extern void _bfd_nanomips_final_write_processing + (bfd *); +extern bool _bfd_nanomips_elf_final_write_processing + (bfd *); +extern const char *_bfd_nanomips_fp_abi_string (int); +extern bool _bfd_nanomips_elf_print_private_bfd_data (bfd *, void *); + +extern bfd_reloc_status_type _bfd_nanomips_elf_generic_reloc + (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); +extern bfd_reloc_status_type _bfd_nanomips_elf_negative_reloc + (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **); + +extern unsigned long _bfd_elf_nanomips_mach (flagword); +extern void _bfd_nanomips_elf_merge_symbol_attribute + (struct elf_link_hash_entry *, unsigned int, bool, bool); + +extern const struct bfd_elf_special_section _bfd_nanomips_elf_special_sections[]; diff --git a/bfd/libbfd.h b/bfd/libbfd.h index 27bc0875cf6..2b2789ab381 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1278,6 +1278,73 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_MICROMIPS_JMP", "BFD_RELOC_MIPS16_JMP", "BFD_RELOC_MIPS16_GPREL", + "BFD_RELOC_NANOMIPS_HI20", + "BFD_RELOC_NANOMIPS_LO12", + "BFD_RELOC_NANOMIPS_LO4_S2", + "BFD_RELOC_NANOMIPS_IMM16", + "BFD_RELOC_NANOMIPS_NEG12", + "BFD_RELOC_NANOMIPS_GPREL7_S2", + "BFD_RELOC_NANOMIPS_GPREL18", + "BFD_RELOC_NANOMIPS_GPREL19_S2", + "BFD_RELOC_NANOMIPS_GPREL16_S2", + "BFD_RELOC_NANOMIPS_GPREL18_S3", + "BFD_RELOC_NANOMIPS_4_PCREL_S1", + "BFD_RELOC_NANOMIPS_7_PCREL_S1", + "BFD_RELOC_NANOMIPS_10_PCREL_S1", + "BFD_RELOC_NANOMIPS_11_PCREL_S1", + "BFD_RELOC_NANOMIPS_14_PCREL_S1", + "BFD_RELOC_NANOMIPS_21_PCREL_S1", + "BFD_RELOC_NANOMIPS_25_PCREL_S1", + "BFD_RELOC_NANOMIPS_PCREL_HI20", + "BFD_RELOC_NANOMIPS_GOT_CALL", + "BFD_RELOC_NANOMIPS_GOTPC_HI20", + "BFD_RELOC_NANOMIPS_GOTPC_I32", + "BFD_RELOC_NANOMIPS_GOT_LO12", + "BFD_RELOC_NANOMIPS_GOT_DISP", + "BFD_RELOC_NANOMIPS_GOT_PAGE", + "BFD_RELOC_NANOMIPS_GOT_OFST", + "BFD_RELOC_NANOMIPS_I32", + "BFD_RELOC_NANOMIPS_GPREL_HI20", + "BFD_RELOC_NANOMIPS_GPREL_LO12", + "BFD_RELOC_NANOMIPS_TLS_GD", + "BFD_RELOC_NANOMIPS_TLS_GD_I32", + "BFD_RELOC_NANOMIPS_TLS_LD", + "BFD_RELOC_NANOMIPS_TLS_LD_I32", + "BFD_RELOC_NANOMIPS_TLS_DTPREL12", + "BFD_RELOC_NANOMIPS_TLS_DTPREL16", + "BFD_RELOC_NANOMIPS_TLS_DTPREL_I32", + "BFD_RELOC_NANOMIPS_TLS_GOTTPREL", + "BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32", + "BFD_RELOC_NANOMIPS_TLS_TPREL12", + "BFD_RELOC_NANOMIPS_TLS_TPREL16", + "BFD_RELOC_NANOMIPS_TLS_TPREL_I32", + "BFD_RELOC_NANOMIPS_TLS_DTPMOD", + "BFD_RELOC_NANOMIPS_TLS_DTPREL", + "BFD_RELOC_NANOMIPS_TLS_TPREL", + "BFD_RELOC_NANOMIPS_PC_I32", + "BFD_RELOC_NANOMIPS_GPREL_I32", + "BFD_RELOC_NANOMIPS_GPREL17_S1", + "BFD_RELOC_NANOMIPS_NEG", + "BFD_RELOC_NANOMIPS_ASHIFTR_1", + "BFD_RELOC_NANOMIPS_UNSIGNED_8", + "BFD_RELOC_NANOMIPS_UNSIGNED_16", + "BFD_RELOC_NANOMIPS_SIGNED_8", + "BFD_RELOC_NANOMIPS_SIGNED_16", + "BFD_RELOC_NANOMIPS_EH", + "BFD_RELOC_NANOMIPS_JUMP_SLOT", + "BFD_RELOC_NANOMIPS_ALIGN", + "BFD_RELOC_NANOMIPS_FILL", + "BFD_RELOC_NANOMIPS_MAX", + "BFD_RELOC_NANOMIPS_INSN32", + "BFD_RELOC_NANOMIPS_INSN16", + "BFD_RELOC_NANOMIPS_FIXED", + "BFD_RELOC_NANOMIPS_RELAX", + "BFD_RELOC_NANOMIPS_NORELAX", + "BFD_RELOC_NANOMIPS_SAVERESTORE", + "BFD_RELOC_NANOMIPS_JALR16", + "BFD_RELOC_NANOMIPS_JALR32", + "BFD_RELOC_NANOMIPS_COPY", + "BFD_RELOC_NANOMIPS_SIGNED_9", "BFD_RELOC_HI16", "BFD_RELOC_HI16_S", "BFD_RELOC_LO16", diff --git a/bfd/reloc.c b/bfd/reloc.c index 6b9e00da5d6..9a9e719b0ac 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -2264,6 +2264,144 @@ ENUMX ENUMDOC Fujitsu Frv Relocations. +ENUM + BFD_RELOC_NANOMIPS_HI20 +ENUMX + BFD_RELOC_NANOMIPS_LO12 +ENUMX + BFD_RELOC_NANOMIPS_LO4_S2 +ENUMX + BFD_RELOC_NANOMIPS_IMM16 +ENUMX + BFD_RELOC_NANOMIPS_NEG12 +ENUMX + BFD_RELOC_NANOMIPS_GPREL7_S2 +ENUMX + BFD_RELOC_NANOMIPS_GPREL18 +ENUMX + BFD_RELOC_NANOMIPS_GPREL19_S2 +ENUMX + BFD_RELOC_NANOMIPS_GPREL16_S2 +ENUMX + BFD_RELOC_NANOMIPS_GPREL18_S3 +ENUMX + BFD_RELOC_NANOMIPS_4_PCREL_S1 +ENUMX + BFD_RELOC_NANOMIPS_7_PCREL_S1 +ENUMX + BFD_RELOC_NANOMIPS_10_PCREL_S1 +ENUMX + BFD_RELOC_NANOMIPS_11_PCREL_S1 +ENUMX + BFD_RELOC_NANOMIPS_14_PCREL_S1 +ENUMX + BFD_RELOC_NANOMIPS_21_PCREL_S1 +ENUMX + BFD_RELOC_NANOMIPS_25_PCREL_S1 +ENUMX + BFD_RELOC_NANOMIPS_PCREL_HI20 +ENUMX + BFD_RELOC_NANOMIPS_GOT_CALL +ENUMX + BFD_RELOC_NANOMIPS_GOTPC_HI20 +ENUMX + BFD_RELOC_NANOMIPS_GOTPC_I32 +ENUMX + BFD_RELOC_NANOMIPS_GOT_LO12 +ENUMX + BFD_RELOC_NANOMIPS_GOT_DISP +ENUMX + BFD_RELOC_NANOMIPS_GOT_PAGE +ENUMX + BFD_RELOC_NANOMIPS_GOT_OFST +ENUMX + BFD_RELOC_NANOMIPS_I32 +ENUMX + BFD_RELOC_NANOMIPS_GPREL_HI20 +ENUMX + BFD_RELOC_NANOMIPS_GPREL_LO12 +ENUMX + BFD_RELOC_NANOMIPS_TLS_GD +ENUMX + BFD_RELOC_NANOMIPS_TLS_GD_I32 +ENUMX + BFD_RELOC_NANOMIPS_TLS_LD +ENUMX + BFD_RELOC_NANOMIPS_TLS_LD_I32 +ENUMX + BFD_RELOC_NANOMIPS_TLS_DTPREL12 +ENUMX + BFD_RELOC_NANOMIPS_TLS_DTPREL16 +ENUMX + BFD_RELOC_NANOMIPS_TLS_DTPREL_I32 +ENUMX + BFD_RELOC_NANOMIPS_TLS_GOTTPREL +ENUMX + BFD_RELOC_NANOMIPS_TLS_GOTTPREL_PC_I32 +ENUMX + BFD_RELOC_NANOMIPS_TLS_TPREL12 +ENUMX + BFD_RELOC_NANOMIPS_TLS_TPREL16 +ENUMX + BFD_RELOC_NANOMIPS_TLS_TPREL_I32 +ENUMX + BFD_RELOC_NANOMIPS_TLS_DTPMOD +ENUMX + BFD_RELOC_NANOMIPS_TLS_DTPREL +ENUMX + BFD_RELOC_NANOMIPS_TLS_TPREL +ENUMX + BFD_RELOC_NANOMIPS_PC_I32 +ENUMX + BFD_RELOC_NANOMIPS_GPREL_I32 +ENUMX + BFD_RELOC_NANOMIPS_GPREL17_S1 +ENUMX + BFD_RELOC_NANOMIPS_NEG +ENUMX + BFD_RELOC_NANOMIPS_ASHIFTR_1 +ENUMX + BFD_RELOC_NANOMIPS_UNSIGNED_8 +ENUMX + BFD_RELOC_NANOMIPS_UNSIGNED_16 +ENUMX + BFD_RELOC_NANOMIPS_SIGNED_8 +ENUMX + BFD_RELOC_NANOMIPS_SIGNED_16 +ENUMX + BFD_RELOC_NANOMIPS_EH +ENUMX + BFD_RELOC_NANOMIPS_JUMP_SLOT +ENUMX + BFD_RELOC_NANOMIPS_ALIGN +ENUMX + BFD_RELOC_NANOMIPS_FILL +ENUMX + BFD_RELOC_NANOMIPS_MAX +ENUMX + BFD_RELOC_NANOMIPS_INSN32 +ENUMX + BFD_RELOC_NANOMIPS_INSN16 +ENUMX + BFD_RELOC_NANOMIPS_FIXED +ENUMX + BFD_RELOC_NANOMIPS_RELAX +ENUMX + BFD_RELOC_NANOMIPS_NORELAX +ENUMX + BFD_RELOC_NANOMIPS_SAVERESTORE +ENUMX + BFD_RELOC_NANOMIPS_JALR16 +ENUMX + BFD_RELOC_NANOMIPS_JALR32 +ENUMX + BFD_RELOC_NANOMIPS_COPY +ENUMX + BFD_RELOC_NANOMIPS_SIGNED_9 +ENUMDOC + nanoMIPS relocations +COMMENT + ENUM BFD_RELOC_MN10300_GOTOFF24 ENUMDOC diff --git a/bfd/targets.c b/bfd/targets.c index fcf650410dc..4d029e536e1 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -830,6 +830,10 @@ extern const bfd_target moxie_elf32_le_vec; extern const bfd_target msp430_elf32_vec; extern const bfd_target msp430_elf32_ti_vec; extern const bfd_target mt_elf32_vec; +extern const bfd_target nanomips_elf32_be_vec; +extern const bfd_target nanomips_elf32_le_vec; +extern const bfd_target nanomips_elf64_le_vec; +extern const bfd_target nanomips_elf64_be_vec; extern const bfd_target nds32_elf32_be_vec; extern const bfd_target nds32_elf32_le_vec; extern const bfd_target nds32_elf32_linux_be_vec; @@ -1206,6 +1210,13 @@ static const bfd_target * const _bfd_target_vector[] = &mt_elf32_vec, + &nanomips_elf32_be_vec, + &nanomips_elf32_le_vec, +#ifdef BFD64 + &nanomips_elf64_be_vec, + &nanomips_elf64_le_vec, +#endif + &nds32_elf32_be_vec, &nds32_elf32_le_vec, &nds32_elf32_linux_be_vec, diff --git a/include/elf/common.h b/include/elf/common.h index f811b8daeb5..eb1c422ec62 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -360,6 +360,7 @@ #define EM_U16_U8CORE 260 /* LAPIS nX-U16/U8 */ #define EM_TACHYUM 261 /* Tachyum */ #define EM_56800EF 262 /* NXP 56800EF Digital Signal Controller (DSC) */ +#define EM_NANOMIPS 263 /* MIPS Tech nanoMIPS architecture. */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision diff --git a/include/elf/nanomips.h b/include/elf/nanomips.h new file mode 100644 index 00000000000..25ca243e6b7 --- /dev/null +++ b/include/elf/nanomips.h @@ -0,0 +1,211 @@ +/* nanoMIPS ELF support for BFD. + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file holds definitions specific to the nanoMIPS ELF ABI. */ + +#ifndef _ELF_NANOMIPS_H +#define _ELF_NANOMIPS_H + +#include "elf/reloc-macros.h" + +#ifdef __cplusplus +extern "C" { +#endif + +START_RELOC_NUMBERS (elf_nanomips_reloc_type) + RELOC_NUMBER (R_NANOMIPS_NONE, 0) + RELOC_NUMBER (R_NANOMIPS_32, 1) + RELOC_NUMBER (R_NANOMIPS_64, 2) + RELOC_NUMBER (R_NANOMIPS_NEG, 3) + RELOC_NUMBER (R_NANOMIPS_ASHIFTR_1, 4) + RELOC_NUMBER (R_NANOMIPS_UNSIGNED_8, 5) + RELOC_NUMBER (R_NANOMIPS_SIGNED_8, 6) + RELOC_NUMBER (R_NANOMIPS_UNSIGNED_16, 7) + RELOC_NUMBER (R_NANOMIPS_SIGNED_16, 8) + RELOC_NUMBER (R_NANOMIPS_RELATIVE, 9) + RELOC_NUMBER (R_NANOMIPS_GLOBAL, 10) + RELOC_NUMBER (R_NANOMIPS_JUMP_SLOT, 11) + RELOC_NUMBER (R_NANOMIPS_IRELATIVE, 12) + + RELOC_NUMBER (R_NANOMIPS_PC25_S1, 13) + RELOC_NUMBER (R_NANOMIPS_PC21_S1, 14) + RELOC_NUMBER (R_NANOMIPS_PC14_S1, 15) + RELOC_NUMBER (R_NANOMIPS_PC11_S1, 16) + RELOC_NUMBER (R_NANOMIPS_PC10_S1, 17) + RELOC_NUMBER (R_NANOMIPS_PC7_S1, 18) + RELOC_NUMBER (R_NANOMIPS_PC4_S1, 19) + + RELOC_NUMBER (R_NANOMIPS_GPREL19_S2, 20) + RELOC_NUMBER (R_NANOMIPS_GPREL18_S3, 21) + RELOC_NUMBER (R_NANOMIPS_GPREL18, 22) + RELOC_NUMBER (R_NANOMIPS_GPREL17_S1, 23) + RELOC_NUMBER (R_NANOMIPS_GPREL16_S2, 24) + RELOC_NUMBER (R_NANOMIPS_GPREL7_S2, 25) + RELOC_NUMBER (R_NANOMIPS_GPREL_HI20, 26) + RELOC_NUMBER (R_NANOMIPS_PCHI20, 27) + + RELOC_NUMBER (R_NANOMIPS_HI20, 28) + RELOC_NUMBER (R_NANOMIPS_LO12, 29) + RELOC_NUMBER (R_NANOMIPS_GPREL_I32, 30) + RELOC_NUMBER (R_NANOMIPS_PC_I32, 31) + RELOC_NUMBER (R_NANOMIPS_I32, 32) + RELOC_NUMBER (R_NANOMIPS_GOT_DISP, 33) + RELOC_NUMBER (R_NANOMIPS_GOTPC_I32, 34) + RELOC_NUMBER (R_NANOMIPS_GOTPC_HI20, 35) + RELOC_NUMBER (R_NANOMIPS_GOT_LO12, 36) + RELOC_NUMBER (R_NANOMIPS_GOT_CALL, 37) + RELOC_NUMBER (R_NANOMIPS_GOT_PAGE, 38) + RELOC_NUMBER (R_NANOMIPS_GOT_OFST, 39) + RELOC_NUMBER (R_NANOMIPS_LO4_S2, 40) + /* Reserved for 64-bit ABI. */ + RELOC_NUMBER (R_NANOMIPS_RESERVED1, 41) + RELOC_NUMBER (R_NANOMIPS_GPREL_LO12, 42) + RELOC_NUMBER (R_NANOMIPS_SCN_DISP, 43) + RELOC_NUMBER (R_NANOMIPS_COPY, 44) + + RELOC_NUMBER (R_NANOMIPS_ALIGN, 64) + RELOC_NUMBER (R_NANOMIPS_FILL, 65) + RELOC_NUMBER (R_NANOMIPS_MAX, 66) + RELOC_NUMBER (R_NANOMIPS_INSN32, 67) + RELOC_NUMBER (R_NANOMIPS_FIXED, 68) + RELOC_NUMBER (R_NANOMIPS_NORELAX, 69) + RELOC_NUMBER (R_NANOMIPS_RELAX, 70) + RELOC_NUMBER (R_NANOMIPS_SAVERESTORE, 71) + RELOC_NUMBER (R_NANOMIPS_INSN16, 72) + RELOC_NUMBER (R_NANOMIPS_JALR32, 73) + RELOC_NUMBER (R_NANOMIPS_JALR16, 74) + RELOC_NUMBER (R_NANOMIPS_FRAME_REG, 76) + + /* TLS relocations. */ + RELOC_NUMBER (R_NANOMIPS_TLS_DTPMOD, 80) + RELOC_NUMBER (R_NANOMIPS_TLS_DTPREL, 81) + RELOC_NUMBER (R_NANOMIPS_TLS_TPREL, 82) + RELOC_NUMBER (R_NANOMIPS_TLS_GD, 83) + RELOC_NUMBER (R_NANOMIPS_TLS_GD_I32, 84) + RELOC_NUMBER (R_NANOMIPS_TLS_LD, 85) + RELOC_NUMBER (R_NANOMIPS_TLS_LD_I32, 86) + RELOC_NUMBER (R_NANOMIPS_TLS_DTPREL12, 87) + RELOC_NUMBER (R_NANOMIPS_TLS_DTPREL16, 88) + RELOC_NUMBER (R_NANOMIPS_TLS_DTPREL_I32, 89) + RELOC_NUMBER (R_NANOMIPS_TLS_GOTTPREL, 90) + RELOC_NUMBER (R_NANOMIPS_TLS_GOTTPREL_PC_I32, 91) + RELOC_NUMBER (R_NANOMIPS_TLS_TPREL12, 92) + RELOC_NUMBER (R_NANOMIPS_TLS_TPREL16, 93) + RELOC_NUMBER (R_NANOMIPS_TLS_TPREL_I32, 94) + + FAKE_RELOC (R_NANOMIPS_max, 94) + /* May be used for compact unwind tables in the future. */ + RELOC_NUMBER (R_NANOMIPS_PC32, 248) + RELOC_NUMBER (R_NANOMIPS_EH, 249) + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_NANOMIPS_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_NANOMIPS_GNU_VTENTRY, 254) +END_RELOC_NUMBERS (R_NANOMIPS_maxext) + +/* Processor specific flags for the ELF header e_flags field. */ + +/* File may be relaxed by the linker. */ +#define EF_NANOMIPS_LINKRELAX 0x00000001 + +/* File contains position independent code. */ +#define EF_NANOMIPS_PIC 0x00000002 + +/* Indicates code compiled for a 64-bit machine in 32-bit mode + (regs are 32-bits wide). */ +#define EF_NANOMIPS_32BITMODE 0x00000004 + +/* Four bit nanoMIPS architecture field. */ +#define EF_NANOMIPS_ARCH 0xf0000000 + +/* -march=32r6[s] code. */ +#define E_NANOMIPS_ARCH_32R6 0x00000000 + +/* -march=64r6 code. */ +#define E_NANOMIPS_ARCH_64R6 0x10000000 + +/* The ABI of the file. */ +#define EF_NANOMIPS_ABI 0x0000F000 + +/* nanoMIPS ABI in 32 bit mode. */ +#define E_NANOMIPS_ABI_P32 0x00001000 + +/* nanoMIPS ABI in 64 bit mode. */ +#define E_NANOMIPS_ABI_P64 0x00002000 + +/* Machine variant if we know it. This field was invented at Cygnus + for MIPS. It may be used similarly for nanoMIPS. */ + +#define EF_NANOMIPS_MACH 0x00FF0000 + +/* Object attribute tags. */ +enum +{ + /* 0-3 are generic. */ + + /* Floating-point ABI used by this object file. */ + Tag_GNU_NANOMIPS_ABI_FP = 4, +}; + +/* Object attribute values. */ +enum +{ + /* Values defined for Tag_GNU_NANOMIPS_ABI_FP. */ + + /* Not tagged or not using any ABIs affected by the differences. */ + Val_GNU_NANOMIPS_ABI_FP_ANY = 0, + + /* Using hard-float -mdouble-float. */ + Val_GNU_NANOMIPS_ABI_FP_DOUBLE = 1, + + /* Using hard-float -msingle-float. */ + Val_GNU_NANOMIPS_ABI_FP_SINGLE = 2, + + /* Using soft-float. */ + Val_GNU_NANOMIPS_ABI_FP_SOFT = 3, +}; + +/* Masks for the ases word of an ABI flags structure. + + Unfortunate decisions in early development transitioning from MIPS + to nanoMIPS, left this horifically fragmented. Bits marked as + UNUSED may be cannibalized for future ASEs; bits marked as RESERVED + are intended to remain blocked. If MIPS history is anything to go + by, nanoMIPS will eventually spawn enough ASEs to fill up the gaps! */ + +#define NANOMIPS_ASE_UNUSED1 0x00000002 /* was DSP R2 ASE. */ +#define NANOMIPS_ASE_UNUSED2 0x00000010 /* was MDMX ASE. */ +#define NANOMIPS_ASE_UNUSED3 0x00000020 /* was MIPS-3D ASE. */ +#define NANOMIPS_ASE_MT 0x00000040 /* MT ASE. */ +#define NANOMIPS_ASE_UNUSED4 0x00000080 /* was SmartMIPS ASE. */ +#define NANOMIPS_ASE_VIRT 0x00000100 /* VZ ASE. */ +#define NANOMIPS_ASE_RESERVED1 0x00000400 /* was MIPS16 ASE. */ +#define NANOMIPS_ASE_RESERVED2 0x00000800 /* was MICROMIPS ASE. */ +#define NANOMIPS_ASE_UNUSED5 0x00004000 /* was MIPS16 E2 Extension. */ +#define NANOMIPS_ASE_CRYPTO 0x00010000 /* Cryptography extension. */ +#define NANOMIPS_ASE_xNMS 0x00040000 /* not nanoMIPS Subset. */ +#define NANOMIPS_ASE_MASK 0x0007af4d /* All valid ASEs. */ + +#ifdef __cplusplus +} +#endif + +#endif /* _ELF_NANOMIPS_H */ From patchwork Fri Jul 17 10:38:55 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsing X-Patchwork-Id: 139392 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B2F34BA2E0A for ; Fri, 17 Jul 2026 10:40:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8B2F34BA2E0A Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=k8G1G2ZB X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from va-2-30.ptr.blmpb.com (va-2-30.ptr.blmpb.com [209.127.231.30]) by sourceware.org (Postfix) with ESMTPS id DDA684BA2E11 for ; Fri, 17 Jul 2026 10:39:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DDA684BA2E11 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DDA684BA2E11 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=209.127.231.30 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284771; cv=none; b=ibXCKP8NXUyBjpB5ehDO78Hk323duN3lwFZxVVXc4roi/nohrkAjEDS3Xz9ORTqmAKrX3Qg9ayPBqf8dJZKfhxd/iZpvjZBIe1ce1N8L4kKLNlMdAg7e1mohaSaEh6YBrrSMUFQ24uhAG8EBuW+f5DBrt8VGjCoBXbaVI93kd6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284771; c=relaxed/simple; bh=OLvNwXP9k6zfiRyUHUHdxdEhpKLTnl3k3qLANR0DGf0=; h=DKIM-Signature:Subject:Message-Id:Date:To:Mime-Version:From; b=MU1X4awJ+dhtOCll35Yc7hPHdB8gJ9JSPVA/QS5uDVKyKO9ePDmpByeHueGTJ5hQrJXdZ6o8s9E5DKYIoTpUXh6PNRb1/47snDCMAVnoKQHKIGcZEpyyPuwsYkcm3Z25MfFmg0844CkyUtCZSbsW/kC3kVr22G3VAmy+JE5Ezz4= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=k8G1G2ZB DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DDA684BA2E11 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1784284764; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=xiz4XjLm70JsN19CnolRs0wDrzAEWcfhhKSEsy61gmc=; b=k8G1G2ZBACTS7Mo1WOgM34oU7pxSmu25aEjhyJxcsXDW+m0g7fzrAj7VteVl3J7tuYfhvL wDbSpGIOVBC6ALczRYuxCjX/gINZ94QyITObHgN88OKPJJMUcKbfybVt9feag4BDtNNSlK YqgAQIx8pP3G6Z3N7vFe5iylvrPCXeHMBeCz31WBiuQT1bA9NgGzDmO2341NLkQqE7WhDM z8cRwwMmA/UE4DVvJHaJTnR63vcXdjHzqsOBqv0Z6BuHVSoGVe11id7X6q36HA/g8/7gPY iex+O/fxNhDUANVbwgAY4dtIa8XwxgJOuYtiGREEmZQB4/amZ2res8hRn23qMw== Subject: [PATCH 3/6] Opcodes changes for nanoMIPS support. Message-Id: <20260717103858.199743-4-lei.wang@oss.cipunited.com> References: <20260717103858.199743-1-lei.wang@oss.cipunited.com> In-Reply-To: <20260717103858.199743-1-lei.wang@oss.cipunited.com> Date: Fri, 17 Jul 2026 18:38:55 +0800 X-Lms-Return-Path: To: Mime-Version: 1.0 X-Original-From: Tsing X-Mailer: git-send-email 2.39.5 From: "Tsing" Received: from B1.wok.cipunited.com ([123.52.17.40]) by smtp.feishu.cn with ESMTPS; Fri, 17 Jul 2026 18:39:22 +0800 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_PBL, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: tsing include/ * dis-asm.h: Add prototypes for print_insn_nanomips and print_nanomips_disassembler_options. * opcode/nanomips.h: New file. opcodes/ * Makefile.am: Add nanoMIPS target. * Makefile.in: Regenerate. * configure: Add entry for bfd_nanomips_arch. * configure.ac: Regenerate. * disassemble.c (disassembler): Add support for naonmips. (disassembler_usage): Likewise. * nanomips-dis.c: New file. * nanomips-formats.h: New file. * nanomips-opc.c: New file. --- include/dis-asm.h | 1 + include/opcode/nanomips.h | 1238 ++++++++++++++++++++++++++++++++ opcodes/Makefile.am | 2 + opcodes/Makefile.in | 4 + opcodes/configure | 1 + opcodes/configure.ac | 1 + opcodes/disassemble.c | 14 + opcodes/disassemble.h | 1 + opcodes/nanomips-dis.c | 1394 ++++++++++++++++++++++++++++++++++++ opcodes/nanomips-formats.h | 265 +++++++ opcodes/nanomips-opc.c | 807 +++++++++++++++++++++ 11 files changed, 3728 insertions(+) create mode 100644 include/opcode/nanomips.h create mode 100644 opcodes/nanomips-dis.c create mode 100644 opcodes/nanomips-formats.h create mode 100644 opcodes/nanomips-opc.c diff --git a/include/dis-asm.h b/include/dis-asm.h index c3d5d8c5438..4dcddefe420 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -386,6 +386,7 @@ extern disassembler_ftype cris_get_disassembler (bfd *); extern void print_aarch64_disassembler_options (FILE *); extern void print_i386_disassembler_options (FILE *); extern void print_mips_disassembler_options (FILE *); +extern void print_nanomips_disassembler_options (FILE *); extern void print_nfp_disassembler_options (FILE *); extern void print_ppc_disassembler_options (FILE *); extern void print_riscv_disassembler_options (FILE *); diff --git a/include/opcode/nanomips.h b/include/opcode/nanomips.h new file mode 100644 index 00000000000..fb9d7b0ee9b --- /dev/null +++ b/include/opcode/nanomips.h @@ -0,0 +1,1238 @@ +/* nanomips.h. nanoMIPS opcode list for GDB, the GNU debugger. + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING3. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef _NANOMIPS_H_ +#define _NANOMIPS_H_ + +#include "bfd.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Enumerates the various types of nanoMIPS operand. */ +enum nanomips_operand_type { + /* Described by nanomips_int_operand. */ + OP_INT, + + /* Described by nanomips_mapped_int_operand. */ + OP_MAPPED_INT, + + /* Described by nanomips_msb_operand. */ + OP_MSB, + + /* Described by nanomips_reg_operand. */ + OP_REG, + + /* Like OP_REG, but can be omitted if the register is the same as the + previous operand. */ + OP_OPTIONAL_REG, + + /* Described by nanomips_reg_pair_operand. */ + OP_REG_PAIR, + + /* Described by nanomips_pcrel_operand. */ + OP_PCREL, + + /* The register list and frame size for a MIPS16 SAVE or RESTORE + instruction. */ + OP_SAVE_RESTORE_LIST, + + /* A register operand that must match the destination register. */ + OP_REPEAT_DEST_REG, + + /* A register operand that must match the previous register. */ + OP_REPEAT_PREV_REG, + + /* Described by nanomips_prev_operand. */ + OP_CHECK_PREV, + + /* A register operand that must not be zero. */ + OP_NON_ZERO_REG, + + /* The floating-point register list for a nanoMIPS SAVE or RESTORE + instruction. */ + OP_SAVE_RESTORE_FP_LIST, + + /* Fractured upper immediate PC-offset for nanoMIPS */ + OP_HI20_PCREL, + + /* Fractured upper immediate 20-bit signed integer for nanoMIPS */ + OP_HI20_INT, + + /* Fractured upper immediate 20-bit scaled integer for nanoMIPS */ + OP_HI20_SCALE, + + /* A non-zero PC-relative offset. */ + OP_NON_ZERO_PCREL_S1, + + /* To check a mapped register against a previous operand. */ + OP_MAPPED_CHECK_PREV, + + /* Unsigned word operand. */ + OP_UINT_WORD, + + /* Signed word operand. */ + OP_INT_WORD, + + /* Immediate PC-relative word operand. */ + OP_PC_WORD, + + /* Immediate GP-relative word operand. */ + OP_GPREL_WORD, + + /* Don't care bits. */ + OP_DONT_CARE, + + /* Immediate unsigned word operand, to be negated. */ + OP_NEG_INT, + + /* Immediate (non-relocatable) integer operand. */ + OP_IMM_INT, + + /* Immediate (non-relocatable) word operand. */ + OP_IMM_WORD, + + /* Base register for limited types of offsets. */ + OP_BASE_CHECK_OFFSET, + + /* Copy over bits from another part of instruction. */ + OP_COPY_BITS, + + /* Select bits for a COP0 register. */ + OP_CP0SEL, +}; + +/* Enumerates the types of nanoMIPS register. */ +enum nanomips_reg_operand_type { + /* General registers $0-$31. Software names like $at can also be used. */ + OP_REG_GP, + + /* Floating-point registers $f0-$f31. */ + OP_REG_FP, + + /* DSP accumulator registers $ac0-$ac3. */ + OP_REG_ACC, + + /* Coprocessor registers in numeric format, $0-$31. */ + OP_REG_COPRO, + + /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can + also be used in some contexts. */ + OP_REG_HW, + + /* Co-processor 0 named registers. */ + OP_REG_CP0, + + /* Co-processor 0 named registers with select. */ + OP_REG_CP0SEL +}; + +/* Base class for all operands. */ +struct nanomips_operand +{ + /* The type of the operand. */ + enum nanomips_operand_type type; + + /* The operand occupies SIZE bits of the instruction, starting at LSB. */ + unsigned short size; + unsigned short lsb; + + /* These are used to split a value across two different + parts of the instruction encoding. */ + unsigned int size_top; + unsigned int lsb_top; +}; + +/* Describes an integer operand with a regular encoding pattern. */ +struct nanomips_int_operand +{ + struct nanomips_operand root; + + /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. + The cyclically previous field value encodes 1 << SHIFT less than that, + and so on. E.g. + + - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, + but 15 encodes -1. + + - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is + shifted left two places. + + - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except + that 0 encodes 8. + + - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ + unsigned int max_val; + int bias; + unsigned int shift; + + /* True if the operand should be printed as hex rather than decimal. */ + bool print_hex; +}; + +/* Uses a lookup table to describe a small integer operand. */ +struct nanomips_mapped_int_operand +{ + struct nanomips_operand root; + + /* Maps each encoding value to the integer that it represents. */ + const int *int_map; + + /* True if the operand should be printed as hex rather than decimal. */ + bool print_hex; +}; + +/* An operand that encodes the most significant bit position of a bitfield. + Given a bitfield that spans bits [MSB, LSB], some operands of this type + encode MSB directly while others encode MSB - LSB. Each operand of this + type is preceded by an integer operand that specifies LSB. + + The assembly form varies between instructions. For some instructions, + such as EXT, the operand is written as the bitfield size. For others, + such as EXTS, it is written in raw MSB - LSB form. */ +struct nanomips_msb_operand +{ + struct nanomips_operand root; + + /* The assembly-level operand encoded by a field value of 0. */ + int bias; + + /* True if the operand encodes MSB directly, false if it encodes + MSB - LSB. */ + bool add_lsb; + + /* The maximum value of MSB + 1. */ + unsigned int opsize; +}; + +/* Describes a single register operand. */ +struct nanomips_reg_operand +{ + struct nanomips_operand root; + + /* The type of register. */ + enum nanomips_reg_operand_type reg_type; + + /* If nonnull, REG_MAP[N] gives the register associated with encoding N, + otherwise the encoding is the same as the register number. */ + const unsigned char *reg_map; +}; + +/* Describes an operand that which must match a condition based on the + previous operand. */ +struct nanomips_check_prev_operand +{ + struct nanomips_operand root; + + bool greater_than_ok; + bool less_than_ok; + bool equal_ok; + bool zero_ok; +}; + +/* Describes an operand that encodes a pair of registers. */ +struct nanomips_reg_pair_operand +{ + struct nanomips_operand root; + + /* The type of register. */ + enum nanomips_reg_operand_type reg_type; + + /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ + unsigned char *reg1_map; + unsigned char *reg2_map; +}; + +/* Describes an operand that is calculated relative to a base PC. + The base PC is usually the address of the following instruction, + but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ +struct nanomips_pcrel_operand +{ + /* Encodes the offset. */ + struct nanomips_int_operand root; + + /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', + which is then added to the offset encoded by ROOT. */ + unsigned int align_log2 : 8; + + /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then + reinstated. This is true for jumps and branches and false for + PC-relative data instructions. */ + unsigned int include_isa_bit : 1; + + /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. + This is true for JALX and false otherwise. */ + unsigned int flip_isa_bit : 1; +}; + +/* This structure holds information for a particular instruction. */ + +struct nanomips_opcode +{ + /* The name of the instruction. */ + const char *name; + /* An optional suffix. */ + const char *suffix; + /* A string describing the arguments for this instruction. */ + const char *args; + /* The basic opcode for the instruction. When assembling, this + opcode is modified by the arguments to produce the actual opcode + that is used. If pinfo is INSN_MACRO, then this is 0. */ + unsigned long match; + /* If pinfo is not INSN_MACRO, then this is a bit mask for the + relevant portions of the opcode when disassembling. If the + actual opcode anded with the match field equals the opcode field, + then we have found the correct instruction. If pinfo is + INSN_MACRO, then this field is the macro identifier. */ + unsigned long mask; + /* For a macro, this is INSN_MACRO. Otherwise, it is a collection + of bits describing the instruction, notably any relevant hazard + information. */ + unsigned long pinfo; + /* A collection of additional bits describing the instruction. */ + unsigned long pinfo2; + /* A collection of bits describing the instruction sets of which this + instruction or macro is a member. */ + unsigned long membership; + /* A collection of bits describing the ASE of which this instruction + or macro is a member. */ + unsigned long ase; +}; + +/* Return true if the assembly syntax allows OPERAND to be omitted. */ + +static inline bool +nanomips_optional_operand_p (const struct nanomips_operand *operand) +{ + return (operand->type == OP_OPTIONAL_REG + || operand->type == OP_REPEAT_PREV_REG + || (operand->type != OP_INT + && operand->size == 0 + && operand->lsb == 0)); +} + +/* Return a version of INSN in which the field specified by OPERAND + has value UVAL. */ + +static inline unsigned int +nanomips_insert_operand (const struct nanomips_operand *operand, + unsigned int insn, unsigned int uval) +{ + unsigned int mask; + unsigned int size_bottom = operand->size - operand->size_top; + + mask = (1 << size_bottom) - 1; + insn &= ~(mask << operand->lsb); + insn |= (uval & mask) << operand->lsb; + + mask = (1 << operand->size_top) - 1; + insn &= ~(mask << operand->lsb_top); + insn |= ((uval & (mask << size_bottom)) >> size_bottom) << operand->lsb_top; + return insn; +} + +/* Extract OPERAND from instruction INSN. */ + +static inline unsigned int +nanomips_extract_operand (const struct nanomips_operand *operand, + unsigned int insn) +{ + unsigned int uval; + unsigned int size_bottom = operand->size - operand->size_top; + + uval = (insn >> operand->lsb_top) & ((1 << operand->size_top) - 1); + uval <<= size_bottom; + uval |= (insn >> operand->lsb) & ((1 << size_bottom) - 1); + return uval; +} + +/* UVAL is the value encoded by OPERAND. Return it in signed form. */ + +static inline int +nanomips_signed_operand (const struct nanomips_operand *operand, + unsigned int uval) +{ + unsigned int sign_bit, mask; + + mask = (1 << operand->size) - 1; + sign_bit = 1 << (operand->size - 1); + return ((uval + sign_bit) & mask) - sign_bit; +} + +/* Return the integer that OPERAND encodes as UVAL. */ + +static inline int +nanomips_decode_int_operand (const struct nanomips_int_operand *operand, + unsigned int uval) +{ + uval |= (operand->max_val - uval) & -(1 << operand->root.size); + uval += operand->bias; + uval <<= operand->shift; + return uval; +} + +/* Return the maximum value that can be encoded by OPERAND. */ + +static inline int +nanomips_int_operand_max (const struct nanomips_int_operand *operand) +{ + return (operand->max_val + operand->bias) << operand->shift; +} + +/* Return the minimum value that can be encoded by OPERAND. */ + +static inline int +nanomips_int_operand_min (const struct nanomips_int_operand *operand) +{ + unsigned int mask; + + mask = (1 << operand->root.size) - 1; + return nanomips_int_operand_max (operand) - (mask << operand->shift); +} + +/* Return the register that OPERAND encodes as UVAL. */ + +static inline int +nanomips_decode_reg_operand (const struct nanomips_reg_operand *operand, + unsigned int uval) +{ + if (operand->reg_map) + uval = operand->reg_map[uval]; + return uval; +} + +/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. + Return the address that it encodes. */ + +static inline bfd_vma +nanomips_decode_pcrel_operand (const struct nanomips_pcrel_operand *operand, + bfd_vma base_pc, unsigned int uval) +{ + bfd_vma addr; + + addr = base_pc & -(1 << operand->align_log2); + addr += nanomips_decode_int_operand (&operand->root, uval); + if (operand->include_isa_bit) + addr |= base_pc & 1; + if (operand->flip_isa_bit) + addr ^= 1; + return addr; +} + +/* Describes an operand that encapsulates a mapped register with + a check against the previous operand. */ +struct nanomips_mapped_check_prev_operand +{ + struct nanomips_operand root; + + enum nanomips_reg_operand_type reg_type; + const unsigned char *reg_map; + + bool greater_than_ok; + bool less_than_ok; + bool equal_ok; + bool zero_ok; +}; + +/* Describes an operand that encapsulates a base register with + a check against the type of offset. */ +struct nanomips_base_check_offset_operand +{ + struct nanomips_operand root; + + enum nanomips_reg_operand_type reg_type; + + bool const_ok; + bool expr_ok; +}; + +/* Return true if MO is an instruction that requires 32-bit encoding. */ + +static inline bool +nanomips_opcode_32bit_p (const struct nanomips_opcode *mo) +{ + return mo->mask >> 16 != 0; +} + +static inline int +nanomips_operand_mask (const struct nanomips_operand *operand) +{ + unsigned int mask; + + mask = ((1 << operand->size_top) - 1) << operand->lsb_top; + mask |= ((1 << (operand->size - operand->size_top)) - 1) << operand->lsb; + return mask; +} + +/* Return the UVAL encoding of REGNO as OPERAND. */ + +static inline unsigned int +nanomips_encode_reg_operand (const struct nanomips_operand *operand, + int regno) +{ + unsigned int uval; + const unsigned int num_vals = 1 << operand->size; + const struct nanomips_reg_operand *reg_op + = (const struct nanomips_reg_operand *) operand; + + for (uval = 0; uval < num_vals; uval++) + if (reg_op->reg_map[uval] == regno) + break; + return uval; +} + +/* Re-organize HI20 bits of OPERAND encoded as UVAL. */ + +#define SIGNEX_VALUE(OP) {OP_INT, OP->size - 1, 0, 0, 0} + +static inline int +nanomips_decode_hi20_operand (const struct nanomips_operand *operand, + unsigned int uval) +{ + const struct nanomips_operand op_ext = SIGNEX_VALUE (operand); + const struct nanomips_operand op_shuffle = {OP_INT, 19, 10, 10, 0}; + unsigned int low19 = nanomips_extract_operand (&op_shuffle, uval); + return nanomips_insert_operand (&op_ext, uval, low19); +} + +/* Decode HI20 signed integer. */ + +#define SIGNED_VALUE(OP) {OP_INT, OP->size, 0, 0, 0} + +static inline int +nanomips_decode_hi20_int_operand (const struct nanomips_operand *operand, + unsigned int uval) +{ + const struct nanomips_operand op_enc = SIGNED_VALUE (operand); + uval = nanomips_decode_hi20_operand (operand, uval); + return (nanomips_signed_operand (&op_enc, uval)); +} + +/* Decode HI20 PCREL */ + +#define PCREL_VALUE(OP) { { { OP_PCREL, OP->size, 0, 0, 0}, \ + (1 << (OP->size - 1)) - 1, 0, 0, false}, 12, 0, 0} + +static inline bfd_vma +nanomips_decode_hi20_pcrel_operand (const struct nanomips_operand *operand, + bfd_vma base_pc, unsigned int uval) +{ + const struct nanomips_pcrel_operand pcrel_op = PCREL_VALUE (operand); + uval = nanomips_decode_hi20_operand (operand, uval); + return nanomips_decode_pcrel_operand (&pcrel_op, base_pc, uval << 12); +} + +/* Return true if MO is an instruction that requires 48-bit encoding. */ + +static inline bool +opcode_48bit_p (const struct nanomips_opcode *mo) +{ + return ((mo->mask >> 16 == 0) + && ((mo->match >> 10) == 0x18)); +} + +/* These are the bits which may be set in the pinfo field of an + instructions, if it is not equal to INSN_MACRO. */ + +/* Writes to operand number N. */ +#define INSN_WRITE_SHIFT 0 +#define INSN_WRITE_1 0x00000001 +#define INSN_WRITE_2 0x00000002 +#define INSN_WRITE_ALL 0x00000003 +/* Reads from operand number N. */ +#define INSN_READ_SHIFT 2 +#define INSN_READ_1 0x00000004 +#define INSN_READ_2 0x00000008 +#define INSN_READ_3 0x00000010 +#define INSN_READ_ALL 0x0000001c +/* Modifies general purpose register 31. */ +#define INSN_WRITE_GPR_31 0x00000020 +/* Reads coprocessor register other than floating point register. */ +#define INSN_COP 0x00000040 +/* Instruction loads value from memory. */ +#define INSN_LOAD_MEMORY 0x00000080 +/* Reads the accumulator register. */ +#define INSN_READ_ACC 0x00000100 +/* Modifies the HI register. */ +#define INSN_WRITE_ACC 0x00000200 +/* Instruction stores value into memory. */ +#define INSN_STORE_MEMORY 0x00000400 +/* Instruction uses single precision floating point. */ +#define INSN_FP_S 0x00000800 +/* Instruction uses double precision floating point. */ +#define INSN_FP_D 0x00001000 +/* A user-defined instruction. */ +#define INSN_UDI 0x00002000 +/* Instruction is actually a macro. It should be ignored by the + disassembler, and requires special treatment by the assembler. */ +#define INSN_MACRO 0xffffffff + +/* These are the bits which may be set in the pinfo2 field of an + instruction. */ + +/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ +#define INSN2_ALIAS 0x00000001 +/* Macro uses single-precision floating-point instructions. This should + only be set for macros. For instructions, FP_S in pinfo carries the + same information. */ +#define INSN2_M_FP_S 0x00000002 +/* Macro uses double-precision floating-point instructions. This should + only be set for macros. For instructions, FP_D in pinfo carries the + same information. */ +#define INSN2_M_FP_D 0x00000004 +/* Is an unconditional branch insn. */ +#define INSN2_UNCOND_BRANCH 0x00000008 +/* Is a conditional branch insn. */ +#define INSN2_COND_BRANCH 0x00000010 +/* This indicates delayed branch converted to compact branch. */ +#define INSN2_CONVERTED_TO_COMPACT 0x00000020 +/* Marks the LI macro expansion as special, temporary. */ +#define INSN2_MACRO 0x00000040 + +/* Masks used to mark instructions to indicate which MIPS ISA level + they were introduced in. INSN_ISA_MASK masks an enumeration that + specifies the base ISA level(s). The remainder of a 32-bit + word constructed using these macros is a bitmask of the remaining + INSN_* values below. */ + +#define INSN_ISA_MASK 0x00000003ul + +/* We cannot start at zero due to ISA_UNKNOWN below. */ +#define INSN_ISAN32R6 1 +#define INSN_ISAN64R6 2 + +#define ISA_UNKNOWN 0 /* Gas internal use. */ + +#define ISA_NANOMIPS32R6 INSN_ISAN32R6 +#define ISA_NANOMIPS64R6 INSN_ISAN64R6 + +/* CPU defines, use instead of hardcoding processor number. Keep this + in sync with bfd/archures.c in order for machine selection to work. */ +#define CPU_UNKNOWN 0 /* Gas internal use. */ + +#define CPU_NANOMIPS32R6 32 +#define CPU_NANOMIPS64R6 64 + +#define ISAF(X) (1 << (INSN_ISA##X - 1)) + +/* The same information in table form: bit INSN_ISA - 1 of index + INSN_UPTO - 1 is set if ISA Y includes ISA X. */ +static const unsigned int nanomips_isa_table[] = { + ISAF(N32R6), + ISAF(N32R6) | ISAF(N64R6) +}; +#undef ISAF + +/* MT ASE */ +#define ASE_MT 0x00000010 +/* Virtualization ASE */ +#define ASE_VIRT 0x00000020 +#define ASE_VIRT64 0x00000040 +/* Excluded for low power instruction subset for nanoMIPS. */ +#define ASE_xNMS 0x00002000 + +static inline bool +nanomips_cpu_is_member (int cpu, unsigned int mask) +{ + switch (cpu) + { + case CPU_NANOMIPS32R6: + return (mask & INSN_ISA_MASK) == INSN_ISAN32R6; + + case CPU_NANOMIPS64R6: + return ((mask & INSN_ISA_MASK) == INSN_ISAN32R6) + || ((mask & INSN_ISA_MASK) == INSN_ISAN64R6); + + default: + return false; + } +} + +/* Test for membership in an ISA including chip specific ISAs. INSN + is pointer to an element of the opcode table; ISA is the specified + ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to + test, or zero if no CPU specific ISA test is desired. Return true + if instruction INSN is available to the given ISA and CPU. */ +static inline bool +nanomips_opcode_is_member (const struct nanomips_opcode *insn, + int isa, int ase, int cpu) +{ + /* Test for ISA level compatibility. */ + if ((isa & INSN_ISA_MASK) != 0 + && (insn->membership & INSN_ISA_MASK) != 0 + && ((nanomips_isa_table[(isa & INSN_ISA_MASK) - 1] + >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) + return true; + + /* Test for ASE compatibility. */ + if (insn->ase != 0 && (ase & insn->ase) == insn->ase) + return true; + + /* Test for processor-specific extensions. */ + if (nanomips_cpu_is_member (cpu, insn->membership)) + return true; + + return false; +} + +/* This is a list of macro expanded instructions. + + _I appended means immediate + _A appended means target address of a jump + _AB appended means address with (possibly zero) base register + _AC appended means either symbolic address with no base register + or constant offset with base register. + _D appended means 64 bit floating point constant + _S appended means 32 bit floating point constant. */ + +enum +{ + M_ABS, + M_ACLR_AC, + M_ADD_I, + M_ADDU_I, + M_AND_I, + M_ASET_AC, + M_BEQ, + M_BEQ_I, + M_BGE, + M_BGE_I, + M_BGEU, + M_BGEU_I, + M_BGEZ, + M_BGT, + M_BGT_I, + M_BGTU, + M_BGTU_I, + M_BGTZ, + M_BLE, + M_BLE_I, + M_BLEU, + M_BLEU_I, + M_BLEZ, + M_BLT, + M_BLT_I, + M_BLTU, + M_BLTU_I, + M_BLTZ, + M_BNE, + M_BNE_I, + M_CACHE_AC, + M_CACHEE_AC, + M_DABS, + M_DADD_I, + M_DADDU_I, + M_DLA_AB, + M_DLI, + M_DMUL, + M_DMUL_I, + M_DSUB_I, + M_DSUBU_I, + M_J_A, + M_JAL_A, + M_JRADDIUSP, + M_LA_AB, + M_LB_AC, + M_LBE_AC, + M_LBU_AC, + M_LBUE_AC, + M_LD_AC, + M_LDC1_AC, + M_LDC2_AC, + M_LDM_AC, + M_LH_AC, + M_LHE_AC, + M_LHU_AC, + M_LHUE_AC, + M_LI, + M_LI_D, + M_LI_DD, + M_LI_S, + M_LI_SS, + M_LL_AC, + M_LLD_AC, + M_LLE_AC, + M_LW_AC, + M_LWC1_AC, + M_LWC2_AC, + M_LWE_AC, + M_LWM_AC, + M_LWU_AC, + M_MUL, + M_MUL_I, + M_NOR_I, + M_OR_I, + M_PREF_AC, + M_PREFE_AC, + M_REM_3I, + M_DROL, + M_ROL, + M_DROL_I, + M_ROL_I, + M_ROR_I, + M_SC_AC, + M_SCD_AC, + M_SCE_AC, + M_SD_AC, + M_SDC1_AC, + M_SDC2_AC, + M_SDM_AC, + M_SEQ, + M_SEQ_I, + M_SGE, + M_SGE_I, + M_SGEU, + M_SGEU_I, + M_SGT, + M_SGT_I, + M_SGTU, + M_SGTU_I, + M_SLE, + M_SLE_I, + M_SLEU, + M_SLEU_I, + M_SLT_I, + M_SLTU_I, + M_SNE, + M_SNE_I, + M_SB_AC, + M_SBE_AC, + M_SH_AC, + M_SHE_AC, + M_SW_AC, + M_SWE_AC, + M_SWC1_AC, + M_SWC2_AC, + M_SWM_AC, + M_SUB_I, + M_SUBU_I, + M_TEQ_I, + M_TNE_I, + M_ULD_AC, + M_ULH_AC, + M_ULW_AC, + M_USH_AC, + M_USW_AC, + M_USD_AC, + M_XOR_I, + M_BGEZAL, + M_BLTZAL, + M_EXT, + M_INS, + M_MOD_I, + M_MODU_I, + M_DMOD_I, + M_DMODU_I, + M_DIV_I, + M_DIVU_I, + M_DDIV_I, + M_DDIVU_I, + M_NANOMIPS_NUM_MACROS +}; + +/* These are the bit masks and shift counts used for the different fields + in the nanoMIPS instruction formats. No masks are provided for the + fixed portions of an instruction, since they are not needed. */ + +#define NANOMIPSOP_MASK_RS 0x1f +#define NANOMIPSOP_SH_RS 16 +#define NANOMIPSOP_MASK_RT 0x1f +#define NANOMIPSOP_SH_RT 21 +#define NANOMIPSOP_SH_MC 4 +#define NANOMIPSOP_SH_MD 7 +#define NANOMIPSOP_SH_MP 5 +#define NANOMIPSOP_SH_MM 7 + +#define NANOMIPSOP_SH_CP0SEL 5 +#define NANOMIPSOP_MASK_CP0SEL 0x1f + +/* Describes a COP0 named register with a fixed select. */ +struct nanomips_cp0_name +{ + const char *name; + unsigned int num; + unsigned int sel; +}; + +/* The reference list of COP0 named register with fixed selects. */ +static const struct nanomips_cp0_name nanomips_cp0_3264r6[] = { + {"$index", 0, 0}, + {"$mvpcontrol", 0, 1}, + {"$mvpconf0", 0, 2}, + {"$mvpconf1", 0, 3}, + {"$vpcontrol", 0, 4}, + {"$random", 1, 0}, + {"$vpecontrol", 1, 1}, + {"$vpeconf0", 1, 2}, + {"$vpeconf1", 1, 3}, + {"$yqmask", 1, 4}, + {"$vpeschedule", 1, 5}, + {"$vpeschefback", 1, 6}, + {"$vpeopt", 1, 7}, + {"$entrylo0", 2, 0}, + {"$tcstatus", 2, 1}, + {"$tcbind", 2, 2}, + {"$tcrestart", 2, 3}, + {"$tchalt", 2, 4}, + {"$tccontext", 2, 5}, + {"$tcschedule", 2, 6}, + {"$tcschefback", 2, 7}, + {"$entrylo1", 3, 0}, + {"$tcopt", 3, 7}, + {"$context", 4, 0}, + {"$contextconfig", 4, 1}, + {"$userlocal", 4, 2}, + {"$xcontextconfig", 4, 3}, + {"$pagemask", 5, 0}, + {"$pagegrain", 5, 1}, + {"$segctl0", 5, 2}, + {"$segctl1", 5, 3}, + {"$segctl2", 5, 4}, + {"$pwbase", 5, 5}, + {"$pwfield", 5, 6}, + {"$pwsize", 5, 7}, + {"$wired", 6, 0}, + {"$srsconf0", 6, 1}, + {"$srsconf1", 6, 2}, + {"$srsconf2", 6, 3}, + {"$srsconf3", 6, 4}, + {"$srsconf4", 6, 5}, + {"$pwctl", 6, 6}, + {"$hwrena", 7, 0}, + {"$badvaddr", 8, 0}, + {"$badinst", 8, 1}, + {"$badinstrp", 8, 2}, + {"$count", 9, 0}, + {"$entryhi", 10, 0}, + {"$guestctl1", 10, 4}, + {"$guestctl2", 10, 5}, + {"$guestctl3", 10, 6}, + {"$compare", 11, 0}, + {"$guestctl0ext", 11, 4}, + {"$status", 12, 0}, + {"$intctl", 12, 1}, + {"$srsctl", 12, 2}, + {"$srsmap", 12, 3}, + {"$view_ipl", 12, 4}, + {"$srsmap2", 12, 5}, + {"$guestctl0", 12, 6}, + {"$gtoffset", 12, 7}, + {"$cause", 13, 0}, + {"$view_ripl", 13, 4}, + {"$nestedexc", 13, 5}, + {"$epc", 14, 0}, + {"$nestedepc", 14, 2}, + {"$prid", 15, 0}, + {"$ebase", 15, 1}, + {"$cdmmbase", 15, 2}, + {"$cmgcrbase", 15, 3}, + {"$config", 16, 0}, + {"$config1", 16, 1}, + {"$config2", 16, 2}, + {"$config3", 16, 3}, + {"$config4", 16, 4}, + {"$config5", 16, 5}, + {"$lladdr", 17, 0}, + {"$xcontext", 20, 0}, + {"$debug", 23, 0}, + {"$tracecontrol", 23, 1}, + {"$tracecontrol2", 23, 2}, + {"$usertracedata1", 23, 3}, + {"$traceibpc", 23, 4}, + {"$tracedbpc", 23, 5}, + {"$debug2", 23, 6}, + {"$depc", 24, 0}, + {"$tracecontrol3", 24, 2}, + {"$usertracedata2", 24, 3}, + {"$errctl", 26, 0}, + {"$cacheerr", 27, 0}, + {"$errorepc", 30, 0}, + {"$desave", 31, 0}, + {"$kscratch1", 31, 2}, + {"$kscratch2", 31, 3}, + {"$kscratch3", 31, 4}, + {"$kscratch4", 31, 5}, + {"$kscratch5", 31, 6}, + {"$kscratch6", 31, 7}, + {NULL, 0, 0} +}; + +/* Describes a CP0 named register which permits various select values. */ + struct nanomips_cp0_select +{ + const char *name; + unsigned int num; + unsigned int selmask; +}; + +/* Currently recognized CP0 select patterns. */ + +#define NANOMIPS_CP0SEL_MASK_EVEN 0x55555555 +#define NANOMIPS_CP0SEL_MASK_ODD 0xaaaaaaaa +#define NANOMIPS_CP0SEL_MASK_ANY 0xffffffff + +/* The reference list of CP0 named register with variable selects. */ +static const struct nanomips_cp0_select nanomips_cp0sel_3264r6[] = { + {"$watchlo", 18, NANOMIPS_CP0SEL_MASK_ANY}, + {"$watchhi", 19, NANOMIPS_CP0SEL_MASK_ANY}, + {"$perfctl", 25, NANOMIPS_CP0SEL_MASK_EVEN}, + {"$perfcnt", 25, NANOMIPS_CP0SEL_MASK_ANY}, + {"$taglo", 28, NANOMIPS_CP0SEL_MASK_EVEN}, + {"$datalo", 28, NANOMIPS_CP0SEL_MASK_ODD}, + {"$taghi", 29, NANOMIPS_CP0SEL_MASK_EVEN}, + {"$datahi", 29, NANOMIPS_CP0SEL_MASK_ODD}, + {NULL, 0, 0} +}; + +/* These are the characters which may appears in the args field of a nanoMIPS + instruction. They appear in the order in which the fields appear when the + instruction is used. Commas and parentheses in the args string are ignored + when assembling, and written into the output when disassembling. + + Operands for 16-bit nanoMIPS instructions. + + "ma" must be $28 + "mb" 5-bit non-zero GP register at bit 5 + "mc" 3-bit nanoMIPS registers 4-7, 16-19 bit 4 + The same register used as both source and target. + "md" 3-bit nanoMIPS registers 4-7, 16-19 at bit 7 + "me" 3-bit nanoMIPS registers 4-7, 16-19 at bit 1 + "mf" 3-bit nanoMIPS register 4-7, 16-19 at bit 7. + Must be larger than the last seen register. + "mg" 3-bit nanoMIPS register 4-7, 16-19 at bit 4. + Must be smaller than the last seen register. + "mh" 3-bit nanoMIPS register 4-7, 16-19 at bit 7. + Must be at least as large as the last seen register. + "mi" 3-bit nanoMIPS register 4-7, 16-19 at bit 4. + May be at most as large as the last seen register. + + "mj" 5-bit nanoMIPS registers at bit 0 + "mk" must be the same as the destination register + "ml" 3-bit nanoMIPS registers 4-7, 16-19 at bit 4 + "mm" 3-bit nanoMIPS registers 0, 4-7, 17-19 at bit 7 + "mn" 5-bit encoding of a save/restore register list + "mp" 5-bit nanoMIPS registers at bit 5 + "mq" 2-bit pair at bits [8,3] maps to ($a0,$a1), ($a1,$a2), ($a2,$a3) + or ($a3,$a4) + "mr" 2-bit pair at bits [8,3] maps to ($a1,$a0), ($a2,$a1), ($a3,$a2) + or ($a4,$a3) + "ms" must be $29 + "mt" must be the same as the previous register + "mu" 4-bit encoding of nanoMIPS destination register at bit 5 + "mv" 4-bit encoding of nanoMIPS destination register at bit 0 + "mw" 4-bit encoding of nanoMIPS source register at bit 5 + "mx" 4-bit encoding of nanoMIPS source register at bit 0 + "my" must be $31 + "mz" must be literal 0 + + "mA" 7-bit relocatable GP offset (0 .. 127) << 2 + "mB" 3-bit immediate at bit 0 (0, 4, 8, 12, 16, 20, 24, 28) + "mC" 4-bit immediate at bit 0 (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 65535, 14, 15) + "mD" 10-bit signed branch address, split & scaled at bit 0 [S9:1,S10] + "mE" 7-bit signed branch address, split & scaled at bit 0 [S6:1,S7] + "mF" 4-bit unsigned branch address, scaled at bit 0 [U4:U1] + "mG" 4-bit scaled immediate at bit 4, (0 .. 15) << 4 + "mH" 2-bit scaled immediate at bit 1, (0 .. 3) << 1 + "mI" 7-bit immediate at bit 0, (-1 .. 126) + "mJ" 4-bit scaled immediate at bit 0, (0 .. 15) << 2 + "mK" 3-bit BREAK/SDBBP code at bit 0 + "mL" 2-bit immediate at bit 0, (0 .. 3) + "mM" 3-bit immediate at bit 0, (1 .. 8) + "mN" 2-bit split scaled immediate at bits 8 & 3 (0 .. 3) << 2 + "mO" 7-bit immediate GP offset at bit 0, (0 .. 127) << 2 + "mP" 2-bit SYSCALL/HYPCALL code at bit 0 + "mQ" 4-bit immediate signed offset, (s3,s2:s0) + "mR" 5-bit immediate at bit 0, (0 .. 31) << 2 + "mS" 6-bit immediate at bit 0, (0 .. 63) << 2 + "mZ" must be zero + + Operands for 32-bit nanoMIPS instructions. + + "+1" 18-bit unsigned GP-relative offset, (u17:u0) + "+2" 18-bit scaled GP-relative offset, (u18:u2) << 2 + "+3" 21-bit scaled GP-relative offset, (u18:u1) << 1 + "+4" 18-bit GP-relative offset, (0 .. 2^18-1) << 3 + "+5" 4-bit encoding of nanoMIPS source register at bit 21 + "+6" 5-bit mask encoding, corresponding to (1 << X) - 1 + "+7" 1-bit register at bit 24, (0,1) => ($a0,$a1) + "+8" 23-bit un-spec'ed value at bit 3 for UDIs. + "+9" 7-bit immediate at bit 11, (0 .. 127) + + "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes + LSB. + "+B" 5-bit INS/DINS size, which becomes MSB + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + "+C" 5-bit EXT/DEXT size, which becomes MSBD. + Requires that "+A" or "+E" occur first to set position. + Enforces: 0 < (pos+size) <= 32. + "+D" 4-bit encoding of a floating point save/restore register list + "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32. + "+F" 5-bit DINSM/DINSU size, which becomes MSB-32. + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5-bit DEXTM size, which becomes MSBD-32. + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5-bit DEXTU size, which becomes MSBD. + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+I" 5-bit EXTW/EXTD/PREPEND position, which becomes LSB. + "+J" 19-bit BREAK/SDBBP function code at bit 0 + "+K" Tri-part upper 20-bits of immediate value. + "+L" 10-bit WAIT code at bit 16 + "+M" 18-bit SYSCALL/HYPCALL code at bit 0 + "+N" 9-bit immediate at bit 3, (0 .. 511) << 3 + + "+i" 5-bit SYNC code type at bit 16, (0..31) + "+j" 9-bit signed offset (s7:s0,s8), (-256 .. 255) + "+k" 5-bit nanoMIPS registers at bit 3 + "+p" 9-bit scaled signed offset, (s7:s2) << 2 for LL/SC* + "+q" 9-bit scaled signed offset, (s7:s3) << 3 for LLD/SCD* + "+r" 21-bit PC-relative branch offset (s19:s1,s20) << 1 + "+s" 21-bit immediate offset for PC-relative operation ((s19:s1,s20) + 2) << 1 + "+t" 5-bit non-zero GP register at bit 21 + "+u" 25-bit PC-relative branch offset (s24:s1,s25) << 1 + "+v" 5-bit mapping of R6 ALIGN byte-wise shift to EXTW bit-wise shift. + "+w" 2-bit shift for scaled address calculation at bit 9, (0..3) + "+*" 4-bit ROTX shift at bit 7, (0 .. 15) << 1 + "+|" 1-bit ROTX stripe at bit 6, (0 .. 1) + + "." 21-bit scaled GP-relative offset, (u21:u2) << 2 + "<" 5-bit immediate shift value for bit operations, (0..31) + "|" 3-bit Element count for load/store multiple, (1..8) + "~" 11-bit branch offset, (s9:s1,s10) << 1 + "^" 5-bit trap code at bit 11, (0..31) + "b" 5-bit base register at bit 16 for label or symbolic offsets + "c" 5-bit base register at bit 16, either used with immediate offset + or skipped with symbolic offset. + "d" 5-bit destination register specifier at bit 11 + "g" 12-bit unsigned immediate at bit 0, (0..4095) + "h" 12-bit negative immediate at bit 0, (-4095..0) + "i" 12-bit unsigned immediate at bit 0, (0..4095) + "j" 16-bit unsigned immediate at bit 0, (0..65535) + "k" 5-bit cache operation code at bit 21, (0..31) + "n" 11-bit encoding of save/restore register list + "o" 12-bit offset at bit 0, (0..4095) + "p" 14-bit PC-relative branch offset (s13:s1,s14) << 1 + "r" 5-bit same register at bit 16, used as both source and target + "s" 5-bit source register specifier at bit 16 + "t" 5-bit target register specifier at bit 21 + "u" Tri-part upper 20 bits of address + "x" Tri-part upper 20 bits of address, scaled by 12 bits + "v" 5-bit same register used as both source and destination at bit 15 + "w" 5-bit same register used as both target and destination at bit 21 + "z" must be zero register + + Used in special matching contexts: + "-a" 5-bit don't care at bit 16 + "-b" 8-bit split don't care, 5@16 and 4@9 + "-i" Ignored register operand, internally used for macro expansions. + "-m" Place-holder to copy 5 bits from bit 11 to bit 21 + "-n" Place-holder to copy 5 bits from bit 11 to bit 16 + + Exclusively for 48-bit nanoMIPS instructions: + + "+O" Signed GP-relative 32-bit offset in instruction byte order + "+P" Immediate signed 32-bit value in instruction byte order + "+Q" Unsigned 32-bit value or address in instruction byte order + "+R" Signed 32-bit value in instruction byte order + "+S" Signed PC-relative 32-bit offset in instruction byte order + + Coprocessor instructions: + "E" 5-bit target register + "G" 5-bit source register + "H" 5-bit sel field for (D)MTC* and (D)MFC* + "J" 5-bit select code at bit 11 for named COP1 registers, (0..31) + "K" 10-bit register+select encoding at bit 11 for named h/w register + "O" 10-bit register+select encoding at bit 11 for named COP1 register + "P" 5-bit named COP1 register at bit 16 + "Q" 5-bit select code at bit 11 + "U" 5-bit named HW register at bit 16 + + MT instructions: + "!" 1-bit u-mode for move to/from thread registers at bit 10, (0,1) + "$" 1-bit high-mode for move to/from thread registers at bit 3, (0,1) + "*" 2-bit accumulator register at bit 18, (0..3) + + Floating point instructions: + "D" 5-bit destination register + "R" 5-bit fr destination register + "S" 5-bit fs source 1 register + "T" 5-bit ft source 2 register + "V" 5-bit same register used as floating source and destination or target + + Macro instructions: + "A" general 32 bit expression + "I" 32-bit immediate (value placed in imm_expr). + "F" 64-bit floating point constant in memory + "L" 64-bit floating point constant in memory + "f" 32-bit floating point constant in memory + "l" 32-bit floating point constant in memory + + CP2 instructions: + "C" 23-bit coprocessor function code at bit 3 + + Other: + "()" parens surrounding optional value + "," separates operands + "+" start of extension sequence + + Characters used so far, for quick reference when adding more: + "12345 78 0" + ".<\|~@^!$*" + "A CDEFGHIJKL OP RSTUV " + " bcde ghijk nop rstuvwx z" + + Extension character sequences used so far ("+" followed by the + following), for quick reference when adding more: + "123456789 + "*|;" + "ABCDEFGHIJKLMNOPQRS " + " ij pqrstuvw " + + Extension character sequences used so far ("m" followed by the + following), for quick reference when adding more: + "" + "" + "ABCDEFGHIJKLMNOPQRS Z" + "abcdefghijklmn pqrstuvwxyz" + + Extension character sequences used so far ("-" followed by the + following), for quick reference when adding more: + "" + "" + " " + "ab i mn " +*/ + +extern const struct nanomips_operand *decode_nanomips_operand (const char *); +extern const struct nanomips_opcode nanomips_opcodes[]; +extern const int bfd_nanomips_num_opcodes; + +#ifdef __cplusplus +} +#endif + +#endif /* _NANOMIPS_H_ */ diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index a0fcf4d5ec7..0aa9836ece0 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -212,6 +212,8 @@ TARGET32_LIBOPCODES_CFILES = \ mt-dis.c \ mt-ibld.c \ mt-opc.c \ + nanomips-dis.c \ + nanomips-opc.c \ nds32-asm.c \ nds32-dis.c \ ns32k-dis.c \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index c5449bebf54..1f81ba70efc 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -618,6 +618,8 @@ TARGET32_LIBOPCODES_CFILES = \ mt-dis.c \ mt-ibld.c \ mt-opc.c \ + nanomips-dis.c \ + nanomips-opc.c \ nds32-asm.c \ nds32-dis.c \ ns32k-dis.c \ @@ -998,6 +1000,8 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mt-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mt-ibld.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mt-opc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nanomips-dis.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nanomips-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nds32-asm.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nds32-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nfp-dis.Plo@am__quote@ diff --git a/opcodes/configure b/opcodes/configure index 3e0962b9408..c544b7a569d 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -14369,6 +14369,7 @@ if test x${all_targets} = xfalse ; then bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; bfd_msp430_arch) ta="$ta msp430-dis.lo msp430-decode.lo" ;; + bfd_nanomips_arch) ta="$ta nanomips-dis.lo nanomips-opc.lo" ;; bfd_nds32_arch) ta="$ta nds32-asm.lo nds32-dis.lo" ;; bfd_nfp_arch) ta="$ta nfp-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index 2c2556598c9..a54c26ee880 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -308,6 +308,7 @@ if test x${all_targets} = xfalse ; then bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; bfd_mt_arch) ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;; bfd_msp430_arch) ta="$ta msp430-dis.lo msp430-decode.lo" ;; + bfd_nanomips_arch) ta="$ta nanomips-dis.lo nanomips-opc.lo" ;; bfd_nds32_arch) ta="$ta nds32-asm.lo nds32-dis.lo" ;; bfd_nfp_arch) ta="$ta nfp-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 77d44bb08db..8760b28d107 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -102,6 +102,7 @@ #define ARCH_xtensa #define ARCH_z80 #define ARCH_z8k +#define ARCH_nanomips #endif #ifdef ARCH_m32c @@ -294,6 +295,11 @@ disassembler (enum bfd_architecture a, disassemble = print_insn_msp430; break; #endif +#ifdef ARCH_nanomips + case bfd_arch_nanomips: + disassemble = print_insn_nanomips; + break; +#endif #ifdef ARCH_nds32 case bfd_arch_nds32: disassemble = print_insn_nds32; @@ -556,6 +562,9 @@ disassembler_usage (FILE *stream ATTRIBUTE_UNUSED) #ifdef ARCH_nfp print_nfp_disassembler_options (stream); #endif +#ifdef ARCH_nanomips + print_nanomips_disassembler_options (stream); +#endif #ifdef ARCH_powerpc print_ppc_disassembler_options (stream); #endif @@ -683,6 +692,11 @@ disassemble_init_for_target (struct disassemble_info * info) info->created_styled_output = true; break; #endif +#ifdef ARCH_nanomips + case bfd_arch_nanomips: + info->disassembler_needs_relocs = true; + break; +#endif #ifdef ARCH_pru case bfd_arch_pru: info->disassembler_needs_relocs = true; diff --git a/opcodes/disassemble.h b/opcodes/disassemble.h index 2157790c947..901df877a0b 100644 --- a/opcodes/disassemble.h +++ b/opcodes/disassemble.h @@ -73,6 +73,7 @@ extern int print_insn_mn10300 (bfd_vma, disassemble_info *); extern int print_insn_moxie (bfd_vma, disassemble_info *); extern int print_insn_msp430 (bfd_vma, disassemble_info *); extern int print_insn_mt (bfd_vma, disassemble_info *); +extern int print_insn_nanomips (bfd_vma, disassemble_info *); extern int print_insn_nds32 (bfd_vma, disassemble_info *); extern int print_insn_nfp (bfd_vma, disassemble_info *); extern int print_insn_ns32k (bfd_vma, disassemble_info *); diff --git a/opcodes/nanomips-dis.c b/opcodes/nanomips-dis.c new file mode 100644 index 00000000000..195d2408d94 --- /dev/null +++ b/opcodes/nanomips-dis.c @@ -0,0 +1,1394 @@ +/* Print nanoMIPS instructions for GDB, the GNU debugger, or for objdump. + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "libiberty.h" +#include "opcode/nanomips.h" +#include "opintl.h" +#include "disassemble.h" + +#if !defined(EMBEDDED_ENV) +#include "elf-bfd.h" +#include "elf/nanomips.h" +#include "elfxx-nanomips.h" +#endif + +/* FIXME: These should be shared with gdb somehow. */ + +static const char * const nanomips_gpr_names_numeric[32] = { + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const nanomips_gpr_names_symbolic[32] = { + "zero", "at", "t4", "t5", "a0", "a1", "a2", "a3", + "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" +}; + +static const char * const nanomips_fpr_names_numeric[32] = { + "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", + "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", + "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", + "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" +}; + +static const char * const nanomips_fpr_names_64[32] = { + "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", + "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", + "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", + "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" +}; + +static const char * const nanomips_cp0_names_numeric[32] = +{ + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const nanomips_hwr_names_numeric[32] = { + "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" +}; + +static const char * const nanomips_hwr_names_3264r6[32] = { + "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres", + "hwr_perfcnt", "hwr_xnp", "$6", "$7", + "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", + "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", "$28", "hwr_userlocal", + "$30", "$31" +}; + +/* The empty-list of CP0 registers serves as an indicator to fall-back to + numeric register names. */ +static const struct nanomips_cp0_name nanomips_cp0_numeric[] = { + {NULL, 0, 0} +}; +static const struct nanomips_cp0_select nanomips_cp0sel_numeric[] = { + {NULL, 0, 0} +}; + +struct nanomips_abi_choice +{ + const char *name; + const char *const *gpr_names; + const char *const *fpr_names; +}; + +struct nanomips_abi_choice nanomips_abi_choices[] = { + {"numeric", nanomips_gpr_names_numeric, nanomips_fpr_names_numeric}, + {"p32", nanomips_gpr_names_symbolic, nanomips_fpr_names_64}, + {"p64", nanomips_gpr_names_symbolic, nanomips_fpr_names_64}, +}; + +struct nanomips_arch_choice +{ + const char *name; + int bfd_mach_valid; + unsigned long bfd_mach; + int processor; + int isa; + int ase; + const struct nanomips_cp0_name *cp0_names; + const struct nanomips_cp0_select *cp0sel_names; + const char *const *hwr_names; +}; + +const struct nanomips_arch_choice nanomips_arch_choices[] = { + {"numeric", 0, 0, 0, 0, 0, + nanomips_cp0_numeric, nanomips_cp0sel_numeric, nanomips_hwr_names_numeric}, + + {"32r6", 1, bfd_mach_nanomipsisa32r6, CPU_NANOMIPS32R6, ISA_NANOMIPS32R6, + (ASE_VIRT | ASE_MT | ASE_xNMS), + nanomips_cp0_3264r6, nanomips_cp0sel_3264r6, nanomips_hwr_names_3264r6}, + + {"32r6s", 1, bfd_mach_nanomipsisa32r6, CPU_NANOMIPS32R6, ISA_NANOMIPS32R6, + (ASE_VIRT | ASE_MT), + nanomips_cp0_3264r6, nanomips_cp0sel_3264r6, nanomips_hwr_names_3264r6}, + + {"64r6", 1, bfd_mach_nanomipsisa64r6, CPU_NANOMIPS64R6, ISA_NANOMIPS64R6, + (ASE_VIRT | ASE_MT | ASE_xNMS), + nanomips_cp0_3264r6, nanomips_cp0sel_3264r6, nanomips_hwr_names_3264r6}, +}; + +/* ISA and processor type to disassemble for, and register names to use. + set_default_nanomips_dis_options and parse_nanomips_dis_options fill in + these values. */ + +static int nanomips_processor; +static int nanomips_ase; +static int nanomips_isa; +static const char *const *nanomips_gpr_names; +static const char *const *nanomips_fpr_names; +static const struct nanomips_cp0_name *nanomips_cp0_names; +static const struct nanomips_cp0_select *nanomips_cp0sel_names; +static const char *const *nanomips_hwr_names; + +/* Other options */ +static int no_aliases; /* If set, disassemble as most general inst. */ +static bool show_arch_insn; /* Mnemonics with suffix. */ + +/* Map ABI name to nanomips_abi_choice descriptor. */ + +static const struct nanomips_abi_choice * +choose_abi_by_name (const char *name, unsigned int namelen) +{ + const struct nanomips_abi_choice *c; + unsigned int i; + + for (i = 0, c = NULL; i < ARRAY_SIZE (nanomips_abi_choices) && c == NULL; + i++) + if (strncmp (nanomips_abi_choices[i].name, name, namelen) == 0 + && strlen (nanomips_abi_choices[i].name) == namelen) + c = &nanomips_abi_choices[i]; + + return c; +} + +/* Map architecture name to nanomips_arch_choice descriptor. */ + +static const struct nanomips_arch_choice * +choose_arch_by_name (const char *name, unsigned int namelen) +{ + const struct nanomips_arch_choice *c = NULL; + unsigned int i; + + for (i = 0, c = NULL; i < ARRAY_SIZE (nanomips_arch_choices) && c == NULL; + i++) + if (strncmp (nanomips_arch_choices[i].name, name, namelen) == 0 + && strlen (nanomips_arch_choices[i].name) == namelen) + c = &nanomips_arch_choices[i]; + + return c; +} + +/* Map BFD architecture to nanomips_arch_choice descriptor. */ + +static const struct nanomips_arch_choice * +choose_arch_by_number (unsigned long mach) +{ + static unsigned long hint_bfd_mach; + static const struct nanomips_arch_choice *hint_arch_choice; + const struct nanomips_arch_choice *c; + unsigned int i; + + /* We optimize this because even if the user specifies no + flags, this will be done for every instruction! */ + if (hint_bfd_mach == mach + && hint_arch_choice != NULL + && hint_arch_choice->bfd_mach == hint_bfd_mach) + return hint_arch_choice; + + for (i = 0, c = NULL; i < ARRAY_SIZE (nanomips_arch_choices) && c == NULL; + i++) + { + if (nanomips_arch_choices[i].bfd_mach_valid + && nanomips_arch_choices[i].bfd_mach == mach) + { + c = &nanomips_arch_choices[i]; + hint_bfd_mach = mach; + hint_arch_choice = c; + } + } + return c; +} + +/* Select default descriptors and initial mode for the default + architecture. */ + +static void +set_default_nanomips_dis_options (struct disassemble_info *info) +{ + const struct nanomips_arch_choice *chosen_arch; + + nanomips_isa = ISA_NANOMIPS32R6; + nanomips_processor = CPU_NANOMIPS32R6; + nanomips_isa = true; + nanomips_ase = 0; + nanomips_fpr_names = nanomips_fpr_names_numeric; + nanomips_cp0_names = nanomips_cp0_numeric; + nanomips_cp0sel_names = nanomips_cp0sel_numeric; + nanomips_hwr_names = nanomips_hwr_names_numeric; + no_aliases = 0; + show_arch_insn = false; + + nanomips_gpr_names = nanomips_gpr_names_symbolic; + + /* Set ISA, architecture, and cp0 register names as best we can. */ + chosen_arch = choose_arch_by_number (info->mach); + if (chosen_arch != NULL) + { + nanomips_processor = chosen_arch->processor; + nanomips_isa = chosen_arch->isa; + nanomips_ase = chosen_arch->ase; + nanomips_cp0_names = chosen_arch->cp0_names; + nanomips_cp0sel_names = chosen_arch->cp0sel_names; + nanomips_hwr_names = chosen_arch->hwr_names; + } +} + +/* Parse and translate a command-line options to internal state. */ + +static void +parse_nanomips_dis_option (const char *option, unsigned int len) +{ + unsigned int i, optionlen, vallen; + const char *val; + const struct nanomips_abi_choice *chosen_abi; + const struct nanomips_arch_choice *chosen_arch; + + /* Try to match options that are simple flags */ + if (startswith (option, "show-arch-insn")) + { + show_arch_insn = true; + return; + } + + if (startswith (option, "no-aliases")) + { + no_aliases = 1; + return; + } + + if (startswith (option, "virt")) + { + nanomips_ase |= ASE_VIRT; + + if (nanomips_isa & ISA_NANOMIPS64R6) + nanomips_ase |= ASE_VIRT64; + } + + /* Look for the = that delimits the end of the option name. */ + for (i = 0; i < len; i++) + if (option[i] == '=') + break; + + if (i == 0) /* Invalid option: no name before '='. */ + return; + if (i == len) /* Invalid option: no '='. */ + return; + if (i == (len - 1)) /* Invalid option: no value after '='. */ + return; + + optionlen = i; + val = option + (optionlen + 1); + vallen = len - (optionlen + 1); + + if (strncmp ("gpr-names", option, optionlen) == 0 + && strlen ("gpr-names") == optionlen) + { + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + nanomips_gpr_names = chosen_abi->gpr_names; + return; + } + + if (strncmp ("fpr-names", option, optionlen) == 0 + && strlen ("fpr-names") == optionlen) + { + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + nanomips_fpr_names = chosen_abi->fpr_names; + return; + } + + if (strncmp ("cp0-names", option, optionlen) == 0 + && strlen ("cp0-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + { + nanomips_cp0_names = chosen_arch->cp0_names; + nanomips_cp0sel_names = chosen_arch->cp0sel_names; + } + return; + } + + if (strncmp ("hwr-names", option, optionlen) == 0 + && strlen ("hwr-names") == optionlen) + { + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + nanomips_hwr_names = chosen_arch->hwr_names; + return; + } + + if (strncmp ("reg-names", option, optionlen) == 0 + && strlen ("reg-names") == optionlen) + { + /* We check both ABI and ARCH here unconditionally, so + that "numeric" will do the desirable thing: select + numeric register names for all registers. Other than + that, a given name probably won't match both. */ + chosen_abi = choose_abi_by_name (val, vallen); + if (chosen_abi != NULL) + { + nanomips_gpr_names = chosen_abi->gpr_names; + nanomips_fpr_names = chosen_abi->fpr_names; + } + chosen_arch = choose_arch_by_name (val, vallen); + if (chosen_arch != NULL) + { + nanomips_cp0_names = chosen_arch->cp0_names; + nanomips_cp0sel_names = chosen_arch->cp0sel_names; + nanomips_hwr_names = chosen_arch->hwr_names; + } + return; + } +} + +/* Loop to parse nanoMIPS-specific command-line options. */ + +static void +parse_nanomips_dis_options (const char *options) +{ + const char *option_end; + + if (options == NULL) + return; + + while (*options != '\0') + { + /* Skip empty options. */ + if (*options == ',') + { + options++; + continue; + } + /* We know that *options is neither NUL or a comma. */ + option_end = options + 1; + while (*option_end != ',' && *option_end != '\0') + option_end++; + + parse_nanomips_dis_option (options, option_end - options); + + /* Go on to the next one. If option_end points to a comma, it + will be skipped above. */ + options = option_end; + } +} + +/* Look-up and print the symbolic name of a named CP0 register with + a fixed select value. Fall-back to numeric format if no match is + found. */ + +static void +print_cp0_reg (struct disassemble_info *info, int regno) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + + int i; + unsigned int selnum = regno & NANOMIPSOP_MASK_CP0SEL; + unsigned int cp0_regno = regno >> NANOMIPSOP_SH_CP0SEL; + + if (nanomips_cp0_names != nanomips_cp0_numeric) + for (i = cp0_regno; nanomips_cp0_names[i].name; i++) + { + if (nanomips_cp0_names[i].num == cp0_regno + && nanomips_cp0_names[i].sel == selnum) + { + infprintf (info->stream, dis_style_register, "%s", + nanomips_cp0_names[i].name + 1); + return; + } + } + + /* A select value of 0 is deemed optional. */ + if (selnum == 0) + infprintf (info->stream, dis_style_register, "$%d", cp0_regno); + else + infprintf (info->stream, dis_style_register, "$%d,%d", cp0_regno, selnum); +} + +/* Look-up and print the symbolic name of a named CP0 register with + a variable select value. Fall-back to numeric format if no match is + found. */ + +static void +print_cp0sel_reg (struct disassemble_info *info, unsigned int regno, + unsigned int selnum) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + int i; + + for (i = 0; nanomips_cp0sel_names[i].name; i++) + { + if (nanomips_cp0sel_names[i].num == regno + && ((1 << selnum) & nanomips_cp0sel_names[i].selmask) != 0) + { + infprintf (info->stream, dis_style_register, "%s,%d", + nanomips_cp0sel_names[i].name + 1, selnum); + return; + } + } + + /* A select value of 0 is deemed optional. */ + if (selnum == 0) + infprintf (info->stream, dis_style_register, "$%d", regno); + else + infprintf (info->stream, dis_style_register, "$%d,%d", regno, selnum); +} + +/* Print register REGNO, of type TYPE, for instruction OPCODE. */ + +static void +print_reg (struct disassemble_info *info, + const struct nanomips_opcode *opcode, + enum nanomips_reg_operand_type type, int regno) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + + switch (type) + { + case OP_REG_GP: + infprintf (info->stream, dis_style_register, "%s", nanomips_gpr_names[regno]); + break; + + case OP_REG_FP: + infprintf (info->stream, dis_style_register, "%s", nanomips_fpr_names[regno]); + break; + + case OP_REG_ACC: + infprintf (info->stream, dis_style_register, "$ac%d", regno); + break; + + case OP_REG_COPRO: + if (opcode->name[strlen (opcode->name) - 1] == '1') + infprintf (info->stream, dis_style_register, "%s", nanomips_cp0_names[regno]); + else + infprintf (info->stream, dis_style_register, "$%d", regno); + break; + + case OP_REG_HW: + info->fprintf_func (info->stream, "%s", nanomips_hwr_names[regno]); + break; + + case OP_REG_CP0: + print_cp0_reg (info, regno); + break; + + case OP_REG_CP0SEL: + /* Need to check select bits againt mask, defer output to next operand. */ + break; + } +} + +/* Used to track the state carried over from previous operands in + an instruction. */ + +struct nanomips_print_arg_state +{ + /* The value of the last OP_INT seen. We only use this for OP_MSB, + where the value is known to be unsigned and small. */ + unsigned int last_int; + + /* The type and number of the last OP_REG seen. We only use this for + OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ + enum nanomips_reg_operand_type last_reg_type; + unsigned int last_regno; + unsigned int dest_regno; + unsigned int seen_dest; +}; + +/* Initialize STATE for the start of an instruction. */ + +static inline void +init_print_arg_state (struct nanomips_print_arg_state *state) +{ + memset (state, 0, sizeof (*state)); +} + +/* Record information about a register operand. */ + +static void +nanomips_seen_register (struct nanomips_print_arg_state *state, + unsigned int regno, + enum nanomips_reg_operand_type reg_type) +{ + state->last_reg_type = reg_type; + state->last_regno = regno; + + if (!state->seen_dest) + { + state->seen_dest = 1; + state->dest_regno = regno; + } +} + +/* Pretty-print a save/restore register list. */ + +static void +nanomips_print_save_restore (struct disassemble_info *info, + unsigned int uval, bool mode16) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + void *is = info->stream; + char *comma = ","; + unsigned int pending = 0; + unsigned int freg, fp, count, gp, ra; + fp = gp = ra = 0; + + if (mode16) + { + freg = 30 | (uval >> 4); + count = uval & 0xf; + } + else + { + freg = (uval >> 6) & 0x1f; + count = (uval >> 1) & 0xf; + if (count > 0) + gp = uval & 1; + } + + if (freg == 30 && count > 0) + fp = 1; + if ((freg == 31 && count > 0) || (freg == 30 && count > 1)) + ra = 1; + + if (freg + count == 45) + gp = 1; + + count = count - gp; + if (fp && count > 0) + { + freg = (freg & 0x10) | ((freg + 1) % 32); + count--; + } + + if (ra && count > 0) + { + freg = (freg & 0x10) | ((freg + 1) % 32); + count--; + } + + if (fp) + { + infprintf (is, dis_style_register, "%s", nanomips_gpr_names[30]); + pending = 1; + } + + if (ra) + { + infprintf (is, dis_style_register, "%s%s", (pending ? comma : ""), nanomips_gpr_names[31]); + pending = 1; + } + + if (count > 0) + { + if (count > 1) + infprintf (is, dis_style_register, "%s%s-%s", (pending ? comma : ""), + nanomips_gpr_names[freg], + nanomips_gpr_names[freg + count - 1]); + else + infprintf (is, dis_style_register, "%s%s", (pending ? comma : ""), + nanomips_gpr_names[freg]); + pending = 1; + } + + if (gp) + infprintf (is, dis_style_register, "%s%s", (pending ? comma : ""), nanomips_gpr_names[28]); +} + +/* Pretty-print save/restore floating-point register list. */ + +static void +nanomips_print_save_restore_fp (struct disassemble_info *info, + unsigned int count) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + void *is = info->stream; + + if (count == 1) + infprintf (is, dis_style_register, "%s", nanomips_fpr_names[0]); + else + infprintf (is, dis_style_register, "%s-%s", nanomips_fpr_names[0], + nanomips_fpr_names[count - 1]); +} + +/* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. + UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is + the base address for OP_PCREL operands. */ + +static void +print_insn_arg (struct disassemble_info *info, + struct nanomips_print_arg_state *state, + const struct nanomips_opcode *opcode, + const struct nanomips_operand *operand, + bfd_vma base_pc, unsigned int uval) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + void *is = info->stream; + + switch (operand->type) + { + case OP_INT: + case OP_IMM_INT: + { + const struct nanomips_int_operand *int_op; + + int_op = (const struct nanomips_int_operand *) operand; + uval = nanomips_decode_int_operand (int_op, uval); + state->last_int = uval; + if (int_op->print_hex) + infprintf (is, dis_style_immediate, "0x%x", uval); + else + infprintf (is, dis_style_immediate, "%d", uval); + } + break; + + case OP_MAPPED_INT: + { + const struct nanomips_mapped_int_operand *mint_op; + + mint_op = (const struct nanomips_mapped_int_operand *) operand; + uval = mint_op->int_map[uval]; + state->last_int = uval; + if (mint_op->print_hex) + infprintf (is, dis_style_immediate, "0x%x", uval); + else + infprintf (is, dis_style_immediate, "%d", uval); + } + break; + + case OP_MSB: + { + const struct nanomips_msb_operand *msb_op; + + msb_op = (const struct nanomips_msb_operand *) operand; + uval += msb_op->bias; + if (msb_op->add_lsb) + uval -= state->last_int; + infprintf (is, dis_style_immediate, "%d", uval); + } + break; + + case OP_REG: + case OP_OPTIONAL_REG: + case OP_MAPPED_CHECK_PREV: + case OP_BASE_CHECK_OFFSET: + { + const struct nanomips_reg_operand *reg_op; + + reg_op = (const struct nanomips_reg_operand *) operand; + uval = nanomips_decode_reg_operand (reg_op, uval); + print_reg (info, opcode, reg_op->reg_type, uval); + + nanomips_seen_register (state, uval, reg_op->reg_type); + } + break; + + case OP_REG_PAIR: + { + const struct nanomips_reg_pair_operand *pair_op; + + pair_op = (const struct nanomips_reg_pair_operand *) operand; + print_reg (info, opcode, pair_op->reg_type, pair_op->reg1_map[uval]); + infprintf (is, dis_style_text, ","); + print_reg (info, opcode, pair_op->reg_type, pair_op->reg2_map[uval]); + } + break; + + case OP_PCREL: + { + const struct nanomips_pcrel_operand *pcrel_op; + + pcrel_op = (const struct nanomips_pcrel_operand *) operand; + info->target = nanomips_decode_pcrel_operand (pcrel_op, base_pc, uval); + + /* Preserve the ISA bit for the GDB disassembler, + otherwise clear it. */ + if (info->flavour != bfd_target_unknown_flavour) + info->target &= -2; + + (*info->print_address_func) (info->target, info); + } + break; + + case OP_NON_ZERO_PCREL_S1: + { + const struct nanomips_pcrel_operand pcrel_op = { + {{OP_PCREL, operand->size, operand->lsb, 0, 0}, + (1 << operand->size) - 1, 0, 1, true}, 0, 0, 0 + }; + + if ((info->flags & INSN_HAS_RELOC) == 0) + info->target = nanomips_decode_pcrel_operand (&pcrel_op, base_pc, + uval); + else + info->target = 0; + (*info->print_address_func) (info->target, info); + } + break; + + case OP_CHECK_PREV: + case OP_NON_ZERO_REG: + { + print_reg (info, opcode, OP_REG_GP, uval & 31); + nanomips_seen_register (state, uval, OP_REG_GP); + } + break; + + case OP_SAVE_RESTORE_LIST: + nanomips_print_save_restore (info, uval, opcode->mask >> 16 == 0); + break; + + case OP_SAVE_RESTORE_FP_LIST: + nanomips_print_save_restore_fp (info, uval + 1); + break; + + case OP_REPEAT_PREV_REG: + print_reg (info, opcode, state->last_reg_type, state->last_regno); + break; + + case OP_REPEAT_DEST_REG: + print_reg (info, opcode, state->last_reg_type, state->dest_regno); + break; + + case OP_HI20_PCREL: + { + if ((info->flags & INSN_HAS_RELOC) == 0) + { + uval = nanomips_decode_hi20_int_operand (operand, uval); + infprintf (is, dis_style_immediate, "0x%x", uval & 0xfffff); + } + else + { + info->target = nanomips_decode_hi20_pcrel_operand (operand, base_pc, + uval); + infprintf (is, dis_style_text, "%%pcrel_hi("); + (*info->print_address_func) (info->target, info); + infprintf (is, dis_style_text, ")"); + } + } + break; + + case OP_HI20_SCALE: + { + uval = nanomips_decode_hi20_int_operand (operand, uval); + state->last_int = uval; + infprintf (is, dis_style_immediate, "0x%x", uval & 0xfffff); + } + break; + + case OP_HI20_INT: + { + uval = nanomips_decode_hi20_int_operand (operand, uval); + state->last_int = uval; + if ((info->flags & INSN_HAS_RELOC) != 0 || uval == 0) + infprintf (is, dis_style_immediate, "0x%x", uval & 0xfffff); + else + infprintf (is, dis_style_immediate, "%%hi(0x%x)", (uval & 0xfffff) << 12); + } + break; + + case OP_IMM_WORD: + { + const struct nanomips_int_operand *int_op; + int_op = (const struct nanomips_int_operand *) operand; + state->last_int = ((uval >> 16) & 0xffff) | (uval << 16); + state->last_int += int_op->bias; + infprintf (is, dis_style_immediate, "%d", state->last_int); + } + break; + + case OP_INT_WORD: + case OP_GPREL_WORD: + { + state->last_int = ((uval >> 16) & 0xffff) | (uval << 16); + infprintf (is, dis_style_immediate, "%d", state->last_int); + } + break; + + case OP_UINT_WORD: + { + state->last_int = ((uval >> 16) & 0xffff) | (uval << 16); + infprintf (is, dis_style_immediate, "0x%x", state->last_int); + } + break; + + case OP_PC_WORD: + { + info->target = base_pc + (((uval >> 16) & 0xffff) | (uval << 16)); + (*info->print_address_func) (info->target, info); + } + break; + + case OP_NEG_INT: + infprintf (is, dis_style_immediate, "-%d", uval); + break; + + case OP_CP0SEL: + print_cp0sel_reg (info, state->last_regno, uval); + break; + + case OP_DONT_CARE: + case OP_COPY_BITS: + default: + break; + } +} + +/* Check if register+select map to a valid CP0 select sequence. */ + +static bool +validate_cp0_reg_operand (unsigned int uval) +{ + int i; + unsigned int regno, selnum; + regno = uval >> NANOMIPSOP_SH_CP0SEL; + selnum = uval & NANOMIPSOP_MASK_CP0SEL; + + for (i = 0; nanomips_cp0_3264r6[i].name; i++) + if (regno == nanomips_cp0_3264r6[i].num + && selnum == nanomips_cp0_3264r6[i].sel) + break; + else if (regno < nanomips_cp0_3264r6[i].num) + return false; + + if (nanomips_cp0_3264r6[i].name == NULL) + return false; + + return true; +} + +/* Validate the arguments for INSN, which is described by OPCODE. + Use DECODE_OPERAND to get the encoding of each operand. */ + +static bool +validate_insn_args (const struct nanomips_opcode *opcode, + const struct nanomips_operand *(*decode_operand) (const char *), + unsigned int insn, struct disassemble_info *info) +{ + struct nanomips_print_arg_state state; + const struct nanomips_operand *operand; + const char *s; + unsigned int uval; + + init_print_arg_state (&state); + for (s = opcode->args; *s; ++s) + { + switch (*s) + { + case ',': + case '(': + case ')': + break; + + case '#': + ++s; + break; + + default: + operand = decode_operand (s); + + if (!operand) + continue; + + uval = nanomips_extract_operand (operand, insn); + switch (operand->type) + { + case OP_REG: + case OP_OPTIONAL_REG: + case OP_BASE_CHECK_OFFSET: + { + const struct nanomips_reg_operand *reg_op; + + reg_op = (const struct nanomips_reg_operand *) operand; + + if (operand->type == OP_REG + && reg_op->reg_type == OP_REG_CP0 + && !validate_cp0_reg_operand (uval)) + return false; + + uval = nanomips_decode_reg_operand (reg_op, uval); + nanomips_seen_register (&state, uval, reg_op->reg_type); + } + break; + + case OP_CHECK_PREV: + { + const struct nanomips_check_prev_operand *prev_op + = (const struct nanomips_check_prev_operand *) operand; + + if (!prev_op->zero_ok && uval == 0) + return false; + + if (((prev_op->less_than_ok && uval < state.last_regno) + || (prev_op->greater_than_ok && uval > state.last_regno) + || (prev_op->equal_ok && uval == state.last_regno))) + break; + + return false; + } + + case OP_MAPPED_CHECK_PREV: + { + const struct nanomips_mapped_check_prev_operand *prev_op = + (const struct nanomips_mapped_check_prev_operand *) operand; + unsigned int last_uval = + nanomips_encode_reg_operand (operand, state.last_regno); + + if (((prev_op->less_than_ok && uval < last_uval) + || (prev_op->greater_than_ok && uval > last_uval) + || (prev_op->equal_ok && uval == last_uval))) + break; + + return false; + } + + case OP_NON_ZERO_REG: + if (uval == 0) + return false; + break; + + case OP_NON_ZERO_PCREL_S1: + if (uval == 0 && (info->flags & INSN_HAS_RELOC) == 0) + return false; + break; + + case OP_SAVE_RESTORE_LIST: + { + /* The operand for SAVE/RESTORE is split into 3 pieces + rather than just 2 but we only support a 2-way split + decode the last bit of the instruction here. */ + if (opcode->mask >> 16 != 0 && ((insn >> 20) & 0x1) != 0) + return false; + } + break; + + case OP_IMM_INT: + case OP_IMM_WORD: + case OP_NEG_INT: + case OP_INT: + case OP_MAPPED_INT: + case OP_MSB: + case OP_REG_PAIR: + case OP_PCREL: + case OP_REPEAT_PREV_REG: + case OP_REPEAT_DEST_REG: + case OP_SAVE_RESTORE_FP_LIST: + case OP_HI20_INT: + case OP_HI20_PCREL: + case OP_INT_WORD: + case OP_UINT_WORD: + case OP_PC_WORD: + case OP_GPREL_WORD: + case OP_DONT_CARE: + case OP_HI20_SCALE: + case OP_COPY_BITS: + case OP_CP0SEL: + break; + } + + if (*s == 'm' || *s == '+' || *s == '-' || *s == '`') + ++s; + } + } + return true; +} + +/* Print the arguments for INSN, which is described by OPCODE. + Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC + as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL + operand is for a branch or jump. */ + +static void +print_insn_args (struct disassemble_info *info, + const struct nanomips_opcode *opcode, + const struct nanomips_operand *(*decode_operand) (const char *), + uint64_t insn, bfd_vma insn_pc, unsigned int length) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + void *is = info->stream; + struct nanomips_print_arg_state state; + const struct nanomips_operand *operand; + const char *s; + bool pending_sep = false; + bool pending_space = true; + + init_print_arg_state (&state); + for (s = opcode->args; *s; ++s) + { + switch (*s) + { + case ',': + pending_sep = true; + break; + case '(': + if (pending_sep) + { + infprintf (is, dis_style_text, ","); + pending_sep = false; + } + /* fall-through */ + case ')': + infprintf (is, dis_style_text, "%c", *s); + break; + + case '#': + ++s; + infprintf (is, dis_style_text, "%c%c", *s, *s); + break; + + default: + operand = decode_operand (s); + if (!operand) + { + /* xgettext:c-format */ + infprintf (is, dis_style_text, + _("# internal error, undefined operand in `%s %s'"), + opcode->name, opcode->args); + return; + } + + /* Defer printing the comma separator for CP0-select values since + the preceding register output is also defered. */ + if (operand->type != OP_DONT_CARE + && operand->type != OP_CP0SEL + && pending_sep) + { + infprintf (is, dis_style_text, ","); + pending_sep = false; + } + + if (operand->type != OP_DONT_CARE && pending_space) + infprintf (is, dis_style_text, "\t"); + pending_space = false; + + { + bfd_vma base_pc = 0; + bool have_reloc = ((info->flags & INSN_HAS_RELOC) != 0); + + if (!have_reloc) + base_pc = insn_pc; + + if ((operand->type == OP_PCREL + || operand->type == OP_HI20_PCREL + || operand->type == OP_NON_ZERO_PCREL_S1 + || operand->type == OP_PC_WORD) + && !have_reloc) + base_pc += length; + + if (operand->type == OP_INT_WORD + || operand->type == OP_UINT_WORD + || operand->type == OP_PC_WORD + || operand->type == OP_GPREL_WORD + || operand->type == OP_IMM_WORD) + print_insn_arg (info, &state, opcode, operand, base_pc, + insn >> 32); + else if (operand->type != OP_DONT_CARE) + print_insn_arg (info, &state, opcode, operand, base_pc, + nanomips_extract_operand (operand, insn)); + } + if (*s == 'm' || *s == '+' || *s == '-' || *s == '`') + ++s; + break; + } + } +} + +enum match_kind +{ + MATCH_NONE, + MATCH_FULL, + MATCH_SHORT +}; + +/* Disassemble nanoMIPS instructions. */ + +static int +_print_insn_nanomips (bfd_vma memaddr_base, struct disassemble_info *info) +{ + const fprintf_styled_ftype infprintf = info->fprintf_styled_func; + const struct nanomips_opcode *op, *opend; + void *is = info->stream; + bfd_byte buffer[2]; + uint64_t higher = 0; + unsigned int length; + int status; + uint64_t insn; + + bfd_vma memaddr = memaddr_base; + + info->bytes_per_chunk = 2; + info->display_endian = info->endian; + info->insn_info_valid = 1; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + length = 2; + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + if ((insn & 0xfc00) == 0x6000) + { + unsigned imm; + /* This is a 48-bit nanoMIPS instruction. */ + status = (*info->read_memory_func) (memaddr + 2, buffer, 4, info); + if (status != 0) + { + infprintf (is, dis_style_text, "0x%x (expected 48 bits): ", + (unsigned) insn); + (*info->memory_error_func) (status, memaddr + 2, info); + return -1; + } + if (info->endian == BFD_ENDIAN_BIG) + imm = bfd_getb16 (buffer); + else + imm = bfd_getl16 (buffer); + higher = (imm << 16); + + status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info); + + if (info->endian == BFD_ENDIAN_BIG) + imm = bfd_getb16 (buffer); + else + imm = bfd_getl16 (buffer); + higher = higher | imm; + + length += 4; + } + else if ((insn & 0x1000) == 0x0) + { + /* This is a 32-bit nanoMIPS instruction. */ + higher = insn; + + status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); + if (status != 0) + { + infprintf (is, dis_style_text, "0x%x (expected 32 bits): ", + (unsigned) higher); + (*info->memory_error_func) (status, memaddr + 2, info); + return -1; + } + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + insn = insn | (higher << 16); + + length += 2; + } + + /* FIXME: Should probably use a hash table on the major opcode here. */ + const struct nanomips_opcode *opcodes; + int num_opcodes; + struct nanomips_operand const *(*decode) (const char *); + + opcodes = nanomips_opcodes; + num_opcodes = bfd_nanomips_num_opcodes; + decode = decode_nanomips_operand; + + opend = opcodes + num_opcodes; + for (op = opcodes; op < opend; op++) + { + if (op->pinfo != INSN_MACRO + && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) + && (insn & op->mask) == op->match + && ((length == 2 && (op->mask & 0xffff0000) == 0) + || (length == 6 + && (op->mask & 0xffff0000) == 0) + || (length == 4 && (op->mask & 0xffff0000) != 0))) + { + if (!nanomips_opcode_is_member (op, nanomips_isa, nanomips_ase, + nanomips_processor) + || (op->pinfo2 & INSN2_CONVERTED_TO_COMPACT)) + continue; + + if (!validate_insn_args (op, decode, insn, info)) + continue; + + infprintf (is, dis_style_mnemonic, "%s%s", op->name, + (show_arch_insn ? op->suffix : "")); + + if (length == 6) + insn |= (higher << 32); + + if (op->args[0]) + print_insn_args (info, op, decode, insn, memaddr, length); + + /* Figure out instruction type and branch delay information. */ + if ((op->pinfo2 & INSN2_UNCOND_BRANCH) != 0) + { + if ((op->pinfo & (INSN_WRITE_GPR_31 | INSN_WRITE_1)) != 0) + info->insn_type = dis_jsr; + else + info->insn_type = dis_branch; + } + else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0) + { + if ((op->pinfo & INSN_WRITE_GPR_31) != 0) + info->insn_type = dis_condjsr; + else + info->insn_type = dis_condbranch; + } + else if ((op->pinfo & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0) + info->insn_type = dis_dref; + + return length; + } + } + + infprintf (is, dis_style_immediate, "0x%x", (unsigned) insn); + info->insn_type = dis_noninsn; + + return length; +} + +/* Set up the options and disassemble. */ + +int +print_insn_nanomips (bfd_vma memaddr, struct disassemble_info *info) +{ + set_default_nanomips_dis_options (info); + parse_nanomips_dis_options (info->disassembler_options); + + return _print_insn_nanomips (memaddr, info); +} + +/* Print description of nanoMIPS-specific command-line options. */ + +void +print_nanomips_disassembler_options (FILE *stream) +{ + unsigned int i; + + fprintf (stream, _("\n\ +The following nanoMIPS specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + fprintf (stream, _("\n\ + no-aliases Use canonical instruction forms.\n")); + + fprintf (stream, _("\n\ + show-arch-insn Print extended mnemonics in disassembly including\n\ + suffix as in the architecture reference manual.\n")); + + fprintf (stream, _("\n\ + virt Recognize the virtualization ASE instructions.\n")); + + fprintf (stream, _("\n\ + mxu Recognize the MXU ASE instructions.\n")); + + fprintf (stream, _("\n\ + gpr-names=ABI Print GPR names according to specified ABI.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + fpr-names=ABI Print FPR names according to specified ABI.\n\ + Default: numeric.\n")); + + fprintf (stream, _("\n\ + cp0-names=ARCH Print CP0 register names according to\n\ + specified architecture.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + hwr-names=ARCH Print HWR names according to specified \n\ + architecture.\n\ + Default: based on binary being disassembled.\n")); + + fprintf (stream, _("\n\ + reg-names=ABI Print GPR and FPR names according to\n\ + specified ABI.\n")); + + fprintf (stream, _("\n\ + reg-names=ARCH Print CP0 register and HWR names according to\n\ + specified architecture.\n")); + + fprintf (stream, _("\n\ + For the options above, the following values are supported for \"ABI\":\n\ + ")); + for (i = 0; i < ARRAY_SIZE (nanomips_abi_choices); i++) + fprintf (stream, " %s", nanomips_abi_choices[i].name); + fprintf (stream, _("\n")); + + fprintf (stream, _("\n\ + For the options above, The following values are supported for \"ARCH\":\n\ + ")); + for (i = 0; i < ARRAY_SIZE (nanomips_arch_choices); i++) + if (*nanomips_arch_choices[i].name != '\0') + fprintf (stream, " %s", nanomips_arch_choices[i].name); + fprintf (stream, _("\n")); + + fprintf (stream, _("\n")); +} + +/* nanoMIPS hook to predict instruction length from opcode bits. */ + +int +nanomips_predict_insn_length (bfd_vma memaddr_base, + int previous_octect ATTRIBUTE_UNUSED, + struct disassemble_info *info) +{ + bfd_byte buffer[2]; + unsigned int length; + uint64_t insn; + bfd_vma memaddr = memaddr_base; + int status; + + status = (*info->read_memory_func) (memaddr, buffer, 2, info); + if (status != 0) + { + (*info->memory_error_func) (status, memaddr, info); + return -1; + } + + length = 2; + + if (info->endian == BFD_ENDIAN_BIG) + insn = bfd_getb16 (buffer); + else + insn = bfd_getl16 (buffer); + + if ((insn & 0xfc00) == 0x6000) + length += 4; + else if ((insn & 0x1000) == 0x0) + length += 2; + + return length; +} diff --git a/opcodes/nanomips-formats.h b/opcodes/nanomips-formats.h new file mode 100644 index 00000000000..e477313886d --- /dev/null +++ b/opcodes/nanomips-formats.h @@ -0,0 +1,265 @@ +/* nanomips-formats.h + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING3. If not, + see . */ + +#include "libiberty.h" + +#define INT_BIAS(SIZE, LSB, MAX_VAL, BIAS, SHIFT, PRINT_HEX) \ + { \ + static const struct nanomips_int_operand op = { \ + { OP_INT, SIZE, LSB, 0, 0 }, MAX_VAL, BIAS, SHIFT, PRINT_HEX \ + }; \ + return &op.root; \ + } + +#define INT_ADJ(SIZE, LSB, MAX_VAL, SHIFT, PRINT_HEX) \ + INT_BIAS(SIZE, LSB, MAX_VAL, 0, SHIFT, PRINT_HEX) + +#define UINT(SIZE, LSB) \ + INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, false) + +#define SINT(SIZE, LSB) \ + INT_ADJ(SIZE, LSB, (1 << ((SIZE) - 1)) - 1, 0, false) + +#define HINT(SIZE, LSB) \ + INT_ADJ(SIZE, LSB, (1 << (SIZE)) - 1, 0, true) + +#define BIT(SIZE, LSB, BIAS) \ + { \ + static const struct nanomips_int_operand op = { \ + { OP_INT, SIZE, LSB, 0, 0 }, (1 << (SIZE)) - 1, BIAS, 0, false \ + }; \ + return &op.root; \ + } + +#define MAPPED_INT(SIZE, LSB, MAP, PRINT_HEX) \ + { \ + typedef char ATTRIBUTE_UNUSED \ + static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \ + static const struct nanomips_mapped_int_operand op = { \ + { OP_MAPPED_INT, SIZE, LSB, 0, 0 }, MAP, PRINT_HEX \ + }; \ + return &op.root; \ + } + +#define MSB(SIZE, LSB, BIAS, ADD_LSB, OPSIZE) \ + { \ + static const struct nanomips_msb_operand op = { \ + { OP_MSB, SIZE, LSB, 0, 0 }, BIAS, ADD_LSB, OPSIZE \ + }; \ + return &op.root; \ + } + +#define REG(SIZE, LSB, BANK) \ + { \ + static const struct nanomips_reg_operand op = { \ + { OP_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, 0 \ + }; \ + return &op.root; \ + } + +#define OPTIONAL_REG(SIZE, LSB, BANK) \ + { \ + static const struct nanomips_reg_operand op = { \ + { OP_OPTIONAL_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, 0 \ + }; \ + return &op.root; \ + } + +#define MAPPED_REG(SIZE, LSB, BANK, MAP) \ + { \ + typedef char ATTRIBUTE_UNUSED \ + static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \ + static const struct nanomips_reg_operand op = { \ + { OP_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, MAP \ + }; \ + return &op.root; \ + } + +#define SPLIT_MAPPED_REG(SIZE, LSB, SIZE_T, LSB_T, BANK, MAP) \ + { \ + typedef char ATTRIBUTE_UNUSED \ + static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \ + static const struct nanomips_reg_operand op = { \ + { OP_REG, SIZE, LSB, SIZE_T, LSB_T }, OP_REG_##BANK, MAP \ + }; \ + return &op.root; \ + } + +#define OPTIONAL_MAPPED_REG(SIZE, LSB, BANK, MAP) \ + { \ + typedef char ATTRIBUTE_UNUSED \ + static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \ + static const struct nanomips_reg_operand op = { \ + { OP_OPTIONAL_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, MAP \ + }; \ + return &op.root; \ + } + +#define REG_PAIR(SIZE, LSB, BANK, MAP) \ + { \ + typedef char ATTRIBUTE_UNUSED \ + static_assert1[(1 << (SIZE)) == ARRAY_SIZE (MAP##1)]; \ + typedef char ATTRIBUTE_UNUSED \ + static_assert2[(1 << (SIZE)) == ARRAY_SIZE (MAP##2)]; \ + static const struct nanomips_reg_pair_operand op = { \ + { OP_REG_PAIR, SIZE, LSB, 0, 0 }, OP_REG_##BANK, MAP##1, MAP##2 \ + }; \ + return &op.root; \ + } + +#define PCREL(SIZE, LSB, IS_SIGNED, SHIFT, ALIGN_LOG2, INCLUDE_ISA_BIT, \ + FLIP_ISA_BIT) \ + { \ + static const struct nanomips_pcrel_operand op = { \ + { { OP_PCREL, SIZE, LSB, 0, 0 }, \ + (1 << ((SIZE) - (IS_SIGNED))) - 1, 0, SHIFT, true }, \ + ALIGN_LOG2, INCLUDE_ISA_BIT, FLIP_ISA_BIT \ + }; \ + return &op.root.root; \ + } + +#define JUMP(SIZE, LSB, SHIFT) \ + PCREL (SIZE, LSB, false, SHIFT, SIZE + SHIFT, true, false) + +#define JALX(SIZE, LSB, SHIFT) \ + PCREL (SIZE, LSB, false, SHIFT, SIZE + SHIFT, true, true) + +#define BRANCH(SIZE, LSB, SHIFT) \ + PCREL (SIZE, LSB, true, SHIFT, 0, true, false) + +#define SPECIAL(SIZE, LSB, TYPE) \ + { \ + static const struct nanomips_operand op = { OP_##TYPE, SIZE, LSB, 0, 0 }; \ + return &op; \ + } + +#define PREV_CHECK(SIZE, LSB, GT_OK, LT_OK, EQ_OK, ZERO_OK) \ + { \ + static const struct nanomips_check_prev_operand op = { \ + { OP_CHECK_PREV, SIZE, LSB, 0, 0 }, GT_OK, LT_OK, EQ_OK, ZERO_OK \ + }; \ + return &op.root; \ + } + +#define IMM_INT_BIAS(SIZE, LSB, MAX_VAL, BIAS, SHIFT, PRINT_HEX) \ + { \ + static const struct nanomips_int_operand op = { \ + { OP_IMM_INT, SIZE, LSB, 0, 0 }, MAX_VAL, BIAS, SHIFT, PRINT_HEX \ + }; \ + return &op.root; \ + } + +#define IMM_INT_ADJ(SIZE, LSB, MAX_VAL, SHIFT, PRINT_HEX) \ + IMM_INT_BIAS(SIZE, LSB, MAX_VAL, 0, SHIFT, PRINT_HEX) + +#define UINT_SPLIT(SIZE, LSB, SHIFT, SIZE_TOP, LSB_TOP) \ + { \ + static const struct nanomips_int_operand op = { \ + { OP_INT, SIZE, LSB, SIZE_TOP, LSB_TOP }, \ + (1 << (SIZE)) - 1, 0, SHIFT, 0 \ + }; \ + return &op.root; \ + } + +#define SINT_SPLIT(SIZE, LSB, SHIFT, SIZE_TOP, LSB_TOP, BIAS) \ + { \ + static const struct nanomips_int_operand op = { \ + { OP_INT, SIZE, LSB, SIZE_TOP, LSB_TOP }, \ + (1 << ((SIZE) -1)) - 1, BIAS, SHIFT, 0 \ + }; \ + return &op.root; \ + } + +#define IMM_SINT_SPLIT(SIZE, LSB, SHIFT, SIZE_TOP, LSB_TOP, BIAS) \ + { \ + static const struct nanomips_int_operand op = { \ + { OP_IMM_INT, SIZE, LSB, SIZE_TOP, LSB_TOP }, \ + (1 << ((SIZE) -1)) - 1, BIAS, SHIFT, false \ + }; \ + return &op.root; \ + } + +#define HINT_SPLIT(SIZE, LSB, SIZE_T, LSB_T) \ + SINT_SPLIT(SIZE, LSB, 0, SIZE_T, LSB_T) + +#define SPLIT_MAPPED_REG_PAIR(SIZE, LSB, SIZE_T, LSB_T, BANK, MAP1, MAP2) \ + { \ + typedef char ATTRIBUTE_UNUSED \ + static_assert1[(1 << (SIZE)) == ARRAY_SIZE (MAP1)]; \ + typedef char ATTRIBUTE_UNUSED \ + static_assert2[(1 << (SIZE)) == ARRAY_SIZE (MAP2)]; \ + static const struct nanomips_reg_pair_operand op = { \ + { OP_REG_PAIR, SIZE, LSB, SIZE_T, LSB_T }, OP_REG_##BANK, \ + MAP1, MAP2 \ + }; \ + return &op.root; \ + } + +#define BRANCH_UNORD_SPLIT(SIZE, SHIFT) \ + { \ + static const struct nanomips_pcrel_operand op = { \ + { { OP_PCREL, SIZE, 1, 1, 0 }, \ + (1 << ((SIZE) - 1)) - 1, 0, SHIFT, true }, \ + 0, false, false \ + }; \ + return &op.root.root; \ + } + +#define BRANCH_SPLIT(SIZE, LSB, SHIFT, SIZE_TOP, LSB_TOP) \ + { \ + static const struct nanomips_pcrel_operand op = { \ + { { OP_PCREL, SIZE, 1, SIZE_TOP, LSB_TOP }, \ + (1 << ((SIZE) - 1)) - 1, LSB, SHIFT, true }, \ + 0, false, false \ + }; \ + return &op.root.root; \ + } + +#define SPECIAL_SPLIT(SIZE, LSB, SIZE_T, LSB_T, TYPE) \ + { \ + static const struct nanomips_operand op = { OP_##TYPE, SIZE, LSB, SIZE_T, LSB_T }; \ + return &op; \ + } + +#define SPECIAL_WORD(BIAS, TYPE) \ + { \ + static const struct nanomips_int_operand op = { { OP_##TYPE, 0, 0, 0, 0 }, \ + 0x7fffffff, BIAS, 0, false }; \ + return &op.root; \ + } + +#define MAPPED_PREV_CHECK(SIZE, LSB, BANK, MAP, GT_OK, LT_OK, EQ_OK, ZERO_OK) \ + { \ + typedef char ATTRIBUTE_UNUSED \ + static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \ + static const struct nanomips_mapped_check_prev_operand op = { \ + { OP_MAPPED_CHECK_PREV, SIZE, LSB, 0, 0 }, OP_REG_##BANK, MAP, \ + GT_OK, LT_OK, EQ_OK, ZERO_OK \ + }; \ + return &op.root; \ + } + +#define BASE_OFFSET_CHECK(SIZE, LSB, CONST_OK, EXPR_OK) \ + { \ + static const struct nanomips_base_check_offset_operand op = { \ + { OP_BASE_CHECK_OFFSET, SIZE, LSB, 0, 0 }, OP_REG_GP, \ + CONST_OK, EXPR_OK \ + }; \ + return &op.root; \ + } diff --git a/opcodes/nanomips-opc.c b/opcodes/nanomips-opc.c new file mode 100644 index 00000000000..d6e5523fc56 --- /dev/null +++ b/opcodes/nanomips-opc.c @@ -0,0 +1,807 @@ +/* nanomips-opc.c. nanoMIPS opcode table. + Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. + Contributed by MIPS Tech LLC. + Written by Faraz Shahbazker + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "opcode/nanomips.h" +#include "nanomips-formats.h" + +static unsigned char reg_0_map[] = { 0 }; +static unsigned char reg_28_map[] = { 28 }; +static unsigned char reg_29_map[] = { 29 }; +static unsigned char reg_31_map[] = { 31 }; +static unsigned char reg_m16_map[] = { 16, 17, 18, 19, 4, 5, 6, 7 }; +static unsigned char reg_q_map[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; + +static unsigned char reg_4to5_map[] = { + 8, 9, 10, 11, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 +}; + +static unsigned char reg_4to5_srcmap[] = { + 8, 9, 10, 0, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 +}; + +static unsigned char reg_4or5_map[] = { 4, 5 }; + +static unsigned char reg_gpr2d_map1[] = { 4, 5, 6, 7 }; +static unsigned char reg_gpr2d_map2[] = { 5, 6, 7, 8 }; + +static int int_b_map[] = { + 0, 4, 8, 12, 16, 20, 24, 28 +}; + +static int int_c_map[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 255, 65535, 14, 15 +}; + +static int word_byte_map[] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 3, 0, 0, 0, 0, 0, 0, 0, + 2, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0 +}; + +static int int_mask_map[] = { + 0x1, 0x3, 0x7, 0xf, + 0x1f, 0x3f, 0x7f, 0xff, + 0x1ff, 0x3ff, 0x7ff, 0xfff, + 0x1fff, 0x3fff, 0x7fff, 0xffff, + 0x1ffff, 0x3ffff, 0x7ffff, 0xfffff, + 0x1fffff, 0x3fffff, 0x7fffff, 0xffffff, + 0x1ffffff,0x3ffffff,0x7ffffff,0xfffffff, + 0x1fffffff, 0x3fffffff, 0x7fffffff, 0xffffffff +}; + +/* Return the nanomips_operand structure for the operand at the + beginning of P. */ + +/* FIXME: Unused cases left commented in-place for quick reminder + of which character strings are unused. */ +const struct nanomips_operand * +decode_nanomips_operand (const char *p) +{ + switch (p[0]) + { + case 'm': + switch (p[1]) + { + case 'a': MAPPED_REG (0, 0, GP, reg_28_map); + case 'b': SPECIAL (5, 5, NON_ZERO_REG); + case 'c': OPTIONAL_MAPPED_REG (3, 4, GP, reg_m16_map); + case 'd': MAPPED_REG (3, 7, GP, reg_m16_map); + case 'e': MAPPED_REG (3, 1, GP, reg_m16_map); + case 'f': MAPPED_PREV_CHECK (3, 7, GP, reg_m16_map, true, false, false, false); + case 'g': MAPPED_PREV_CHECK (3, 4, GP, reg_m16_map, false, true, false, false); + case 'h': MAPPED_PREV_CHECK (3, 7, GP, reg_m16_map, false, true, true, false); + case 'i': MAPPED_PREV_CHECK (3, 4, GP, reg_m16_map, true, false, true, false); + case 'j': REG (5, 0, GP); + case 'k': SPECIAL (0, 0, REPEAT_DEST_REG); + case 'l': MAPPED_REG (3, 4, GP, reg_m16_map); + case 'm': MAPPED_REG (3, 7, GP, reg_q_map); + case 'n': SPECIAL_SPLIT (5, 0, 1, 9, SAVE_RESTORE_LIST); + case 'p': REG (5, 5, GP); + case 'q': SPLIT_MAPPED_REG_PAIR (2, 8, 1, 3, GP, reg_gpr2d_map1, + reg_gpr2d_map2); + case 'r': SPLIT_MAPPED_REG_PAIR (2, 8, 1, 3, GP, reg_gpr2d_map2, + reg_gpr2d_map1); + case 's': MAPPED_REG (0, 0, GP, reg_29_map); + case 't': SPECIAL (0, 0, REPEAT_PREV_REG); + case 'u': SPLIT_MAPPED_REG (4, 5, 1, 9, GP, reg_4to5_map); + case 'v': SPLIT_MAPPED_REG (4, 0, 1, 4, GP, reg_4to5_map); + case 'w': SPLIT_MAPPED_REG (4, 5, 1, 9, GP, reg_4to5_srcmap); + case 'x': SPLIT_MAPPED_REG (4, 0, 1, 4, GP, reg_4to5_srcmap); + case 'y': MAPPED_REG (0, 0, GP, reg_31_map); + case 'z': UINT (0, 0); /* Literal 0 */ + case 'A': INT_ADJ (7, 0, 127, 2, false); /* (0 .. 127) << 2 */ + case 'B': MAPPED_INT (3, 0, int_b_map, false); + case 'C': MAPPED_INT (4, 0, int_c_map, true); + case 'D': BRANCH_UNORD_SPLIT (10, 1); + case 'E': BRANCH_UNORD_SPLIT (7, 1); + case 'F': SPECIAL (4, 0, NON_ZERO_PCREL_S1); + case 'G': INT_ADJ (4, 4, 15, 4, false); + case 'H': INT_ADJ (2, 1, 3, 1, false); /* (0 .. 3) << 1 */ + case 'I': INT_ADJ (7, 0, 126, 0, false); /* (-1 .. 126) */ + case 'J': INT_ADJ (4, 0, 15, 2, false); /* (0 .. 15) << 2 */ + case 'K': HINT (3, 0); + case 'L': UINT (2, 0); /* (0 .. 3) */ + case 'M': INT_ADJ (3, 0, 8, 0, false); /* (1 .. 8) */ + case 'N': UINT_SPLIT (2, 8, 2, 1, 3); /* split encoded 2-bit offset << 2 */ + case 'O': IMM_INT_ADJ (7, 0, 127, 2, false); /* (0 .. 127) << 2 */ + case 'P': HINT (2, 0); + case 'Q': SINT_SPLIT (4, 0, 0, 1, 4, 0); + case 'R': INT_ADJ (5, 0, 31, 2, false); /* (0 .. 31) << 2 */ + case 'S': INT_ADJ (6, 0, 63, 2, false); /* (0 .. 63) << 2 */ + case 'Z': UINT (0, 0); /* 0 only */ + } + break; + + case '-': + switch (p[1]) + { + case 'a': SPECIAL (5, 16, DONT_CARE); + case 'b': SPECIAL_SPLIT (8, 9, 5, 16, DONT_CARE); + case 'i': REG (0, 0, GP); /* Ignored register operand. */ + case 'm': SPECIAL_SPLIT (5, 11, 5, 21, COPY_BITS); + case 'n': SPECIAL_SPLIT (5, 11, 5, 16, COPY_BITS); + } + break; + + case '+': + switch (p[1]) + { + case 'A': BIT (5, 0, 0); /* (0 .. 31) */ + case 'B': MSB (5, 6, 1, true, 32); /* (1 .. 32), 32-bit op */ + case 'C': MSB (5, 6, 1, false, 32); /* (1 .. 32), 32-bit op */ + case 'D': SPECIAL (4, 16, SAVE_RESTORE_FP_LIST); + case 'E': BIT (5, 0, 32); /* (32 .. 63) */ + case 'F': MSB (5, 6, 33, true, 64); /* (33 .. 64), 64-bit op */ + case 'G': MSB (5, 6, 33, false, 64); /* (33 .. 64), 64-bit op */ + case 'H': MSB (5, 6, 1, false, 64); /* (1 .. 32), 64-bit op */ + case 'I': BIT (5, 6, 0); /* (0 .. 31) */ + case 'J': HINT (19, 0); + case 'K': SPECIAL_SPLIT (20, 2, 1, 0, HI20_PCREL); /* tri-part 20-bit */ + case 'L': HINT (10, 16); + case 'M': HINT (18, 0); + case 'N': INT_ADJ (9, 3, 511, 3, false); /* 9-bit << 3 */ + case 'O': SPECIAL_WORD (0, GPREL_WORD); + case 'P': SPECIAL_WORD (6, IMM_WORD); + case 'Q': SPECIAL_WORD (0, UINT_WORD); + case 'R': SPECIAL_WORD (0, INT_WORD); + case 'S': SPECIAL_WORD (0, PC_WORD); + + case 'i': HINT (5, 16); + case 'j': SINT_SPLIT (9, 0, 0, 1, 15, 0); + case 'p': SINT_SPLIT (7, 2, 2, 1, 15, 0); /* split 7-bit signed << 2 */ + case 'q': SINT_SPLIT (6, 3, 3, 1, 15, 0); /* split 6-bit signed << 3 */ + case 'r': BRANCH_UNORD_SPLIT (21, 1); /* split 21-bit signed << 1 */ + case 's': IMM_SINT_SPLIT (21, 1, 1, 1, 0, 2); /* split (21-bit signed + 2) << 1 */ + case 't': SPECIAL (5, 21, NON_ZERO_REG); + case 'u': BRANCH_UNORD_SPLIT (25, 1); + case 'v': MAPPED_INT (5, 6, word_byte_map, false); + case 'w': BIT (2, 9, 0); /* (0 .. 3) */ + + case '*': INT_ADJ (4, 7, 15, 1, false); /* (0 .. 15) << 1 */ + case '|': UINT (1, 6); /* 0/1 */ + case ';': UINT (2, 21); /* (0 .. 3) */ + case '1': UINT (18, 0); + case '2': INT_ADJ (16, 2, (1<<16) - 1, 2, false); + case '3': INT_ADJ (17, 1, (1<<17) - 1, 1, false); + case '4': INT_ADJ (18, 3, (1<<18)-1, 3, false); /* 18-bit << 3 */ + case '5': SPLIT_MAPPED_REG (4, 21, 1, 25, GP, reg_4to5_srcmap); + case '6': MAPPED_INT (5, 6, int_mask_map, true); + case '7': MAPPED_REG (1, 24, GP, reg_4or5_map); + case '8': HINT (23, 3); + case '9': UINT (7, 11); + } + break; + + case '.': INT_ADJ (19, 2, (1<<19) - 1, 2, false); + case '<': BIT (5, 0, 0); /* (0 .. 31) */ +/* case '>': BIT (5, 11, 32); /\* (32 .. 63) *\/ */ + case '\\': BIT (3, 21, 0); /* (0 .. 7) */ + case '|': INT_ADJ (3, 12, 8, 0, false); /* 1 .. 8 */ + case '~': BRANCH_UNORD_SPLIT (11, 1); /* split 11-bit signed << 1 */ + case '@': SINT (10, 11); + case '^': HINT (5, 11); + case '!': UINT (1, 10); + case '$': UINT (1, 3); + case '*': REG (2, 18, ACC); +/* case '&': REG (2, 23, ACC); */ + + case '0': SINT (6, 16); + case '1': BIT (5, 11, 0); /* (0 .. 31) */ + case '2': BIT (5, 16, 0); /* (0 .. 31) */ + case '3': BIT (3, 13, 0); + case '4': BIT (4, 12, 0); + case '5': HINT (8, 13); + case '7': REG (2, 14, ACC); + case '8': HINT (7, 14); + + case 'C': HINT (23, 3); + case 'D': REG (5, 11, FP); + case 'E': REG (5, 21, COPRO); + case 'G': REG (5, 16, COPRO); + case 'H': UINT (5, 11); + case 'J': SPECIAL (5, 11, CP0SEL); + case 'K': REG (5, 16, HW); +/* case 'M': REG (3, 13, CCC); */ +/* case 'N': REG (3, 18, CCC); */ + case 'O': REG (10, 11, CP0); + case 'P': REG (5, 16, CP0SEL); +/* case 'Q': UINT (5, 11); */ + case 'R': REG (5, 11, FP); + case 'S': REG (5, 16, FP); + case 'T': REG (5, 21, FP); + case 'V': OPTIONAL_REG (5, 16, FP); + +/* case 'a': JUMP (26, 0, 1); */ + case 'b': REG (5, 16, GP); + case 'c': BASE_OFFSET_CHECK (5, 16, true, false); + case 'd': REG (5, 11, GP); + case 'e': REG (5, 3, GP); + case 'g': HINT (12, 0); + case 'h': SPECIAL (12, 0, NEG_INT); + case 'i': UINT (12, 0); + case 'j': UINT (16, 0); + case 'k': HINT (5, 21); + case 'n': SPECIAL_SPLIT (11, 2, 10, 16, SAVE_RESTORE_LIST); + case 'o': UINT (12, 0); + case 'p': BRANCH_UNORD_SPLIT (14, 1); +/* case 'q': BRANCH_UNORD_SPLIT (20, 1); - unused */ + case 'r': OPTIONAL_REG (5, 16, GP); + case 's': REG (5, 16, GP); + case 't': REG (5, 21, GP); + case 'u': SPECIAL_SPLIT (20, 2, 1, 0, HI20_INT); /* tri-part 20-bit */ + case 'v': OPTIONAL_REG (5, 16, GP); + case 'w': OPTIONAL_REG (5, 21, GP); + case 'x': SPECIAL_SPLIT (20, 2, 1, 0, HI20_SCALE); /* tri-part 20-bit */ + case 'z': MAPPED_REG (0, 0, GP, reg_0_map); + } + return 0; +} + +#define LM INSN_LOAD_MEMORY +#define SM INSN_STORE_MEMORY + +#define WR_1 INSN_WRITE_1 +#define WR_2 INSN_WRITE_2 +#define RD_1 INSN_READ_1 +#define RD_2 INSN_READ_2 +#define RD_3 INSN_READ_3 +#define MOD_1 (WR_1|RD_1) +#define MOD_2 (WR_2|RD_2) +#define FP_S INSN_FP_S +#define FP_D INSN_FP_D + + /* Write dsp accumulators */ +#define WR_a INSN_WRITE_ACC + /* Read dsp accumulators */ +#define RD_a INSN_READ_ACC + +/* Flags used in pinfo2. */ +#define CTC INSN2_CONVERTED_TO_COMPACT +#define UBR INSN2_UNCOND_BRANCH +#define CBR INSN2_COND_BRANCH +#define ALIAS INSN2_ALIAS + +/* For 32-bit nanoMIPS instructions. */ +#define WR_31 INSN_WRITE_GPR_31 + +/* nanoMIPS MT ASE support. */ +#define MT32 ASE_MT + +/* nanoMIPS instruction subset. */ +#define xNMS ASE_xNMS + +/* Base ISA for nanoMIPS. */ +#define I38 INSN_ISAN32R6 +#define I70 INSN_ISAN64R6 + +const struct nanomips_opcode nanomips_opcodes[] = { +/* These instructions appear first so that the disassembler will find + them first. The assemblers uses a hash table based on the + instruction name anyhow. */ +/* name, suffix, args, match, mask, pinfo pinfo2, membership, ase */ +/* Pure macros */ +{"la", "", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I38, 0}, +{"dla", "", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I38, 0}, +/* Precedence=1 */ +{"aluipc", "", "t,+K", 0xe0000002, 0xfc000002, WR_1, 0, I38, 0}, /* ALUIPC */ +{"break", "[16]", "", 0x1010, 0xffff, 0, INSN2_ALIAS, I38, 0}, +{"break", "[16]", "mK", 0x1010, 0xfff8, 0, 0, I38, 0}, +{"break", "[32]", "", 0x00100000, 0xffffffff, 0, INSN2_ALIAS, I38, 0}, +{"break", "[32]", "+J", 0x00100000, 0xfff80000, 0, 0, I38, 0}, +{"dvp", "", "-a", 0x20000390, 0xffe0ffff, 0, INSN2_ALIAS, I38, 0}, /* DVP */ +{"dvp", "", "t,-a", 0x20000390, 0xfc00ffff, WR_1, 0, I38, 0}, +{"nop", "[16]", "", 0x9008, 0xffff, 0, 0, I38, 0}, /* NOP[16] */ +{"nop", "[32]", "", 0x8000c000, 0xffffffff, 0, 0, I38, 0}, /* NOP */ +{"sdbbp", "[16]", "", 0x1018, 0xffff, 0, INSN2_ALIAS, I38, 0}, +{"sdbbp", "[16]", "mK", 0x1018, 0xfff8, 0, 0, I38, 0}, +{"sdbbp", "[32]", "", 0x00180000, 0xffffffff, 0, INSN2_ALIAS, I38, 0}, +{"sdbbp", "[32]", "+J", 0x00180000, 0xfff80000, 0, 0, I38, 0}, +{"move", "", "mb,mj", 0x1000, 0xfc00, WR_1|RD_2, 0, I38, 0}, /* preceded by BREAK, SDBBP */ +{"move", "", "d,s", 0x20000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* OR */ +{"move", "", "d,s", 0x20000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* ADDU */ +{"sigrie", "", "+J", 0x00000000, 0xfff80000, 0, 0, I38, 0}, +{"synci", "[u12]", "o(b)", 0x87e03000, 0xffe0f000, RD_2, 0, I38, 0}, /* SYNCI[U12] */ +{"synci", "[s9]", "+j(b)", 0xa7e01800, 0xffe07f00, RD_2, 0, I38, 0}, /* SYNCI[S9] */ +{"jrc", "[16]", "mp", 0xd800, 0xfc1f, RD_1, 0, I38, 0}, /* JRC[16] */ +{"jrc", "[32]", "s", 0x48000000, 0xffe0ffff, RD_1, INSN2_ALIAS, I38, 0}, /* JALRC */ +{"jalrc", "[16]", "mp", 0xd810, 0xfc1f, WR_31|RD_1, 0, I38, 0}, /* JALRC[16] */ +{"jalrc", "[16]", "my,mp", 0xd810, 0xfc1f, WR_31|RD_1, INSN2_ALIAS, I38, 0}, /* JALRC[16] */ +{"jalrc", "[32]", "s", 0x4be00000, 0xffe0ffff, RD_1, INSN2_ALIAS, I38, 0}, /* JALRC[32] */ +{"jalrc", "[32]", "t,s", 0x48000000, 0xfc00ffff, WR_1|RD_2, 0, I38, 0}, +{"jalrc", "", "mp,-i", 0xd810, 0xfc1f, WR_31|RD_1, INSN2_ALIAS, I38, 0}, /* JALRC[16] */ +{"jalrc", "", "s,-i", 0x4be00000, 0xffe0ffff, RD_1, INSN2_ALIAS, I38, 0}, /* JALRC[32] */ +{"jr", "", "mp", 0xd800, 0xfc1f, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JRC */ +{"jr", "", "s", 0x48000000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC */ +{"jalr", "", "my,mp", 0xd810, 0xfc1f, WR_31|RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC[16] */ +{"jalr", "", "mp", 0xd810, 0xfc1f, WR_31|RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC[16] */ +{"jalr", "", "s", 0x4be00000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC */ +{"jalr", "", "t,s", 0x48000000, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC */ +{"lui", "", "t,u", 0xe0000000, 0xfc000002, WR_1, 0, I38, 0}, +{"li", "[16]", "md,mI", 0xd000, 0xfc00, WR_1, 0, I38, 0}, /* LI[16] */ +{"li", "", "mb,mZ", 0x1000, 0xfc1f, WR_1, INSN2_ALIAS, I38, 0}, /* MOVE[16] */ +{"li", "[32]", "+t,j", 0x00000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I38, 0}, /* ADDIU[32] */ +{"li", "[neg]", "t,h", 0x80008000, 0xfc1ff000, WR_1, INSN2_ALIAS, I38, 0}, /* ADDIU[NEG] */ +{"li", "", "t,x", 0xe0000000, 0xfc000002, WR_1, INSN2_ALIAS, I38, 0}, /* LUI */ +{"li", "[48]", "mp,+Q", 0x6000, 0xfc1f, WR_1, 0, 0, xNMS}, /* LI[48] */ +{"li", "", "+t,A", 0, (int) M_LI, INSN_MACRO, INSN2_MACRO, I38, 0}, +{"ext", "", "t,r,+A,+C", 0x8000f000, 0xfc00f820, WR_1|RD_2, 0, 0, xNMS}, +{"ext", "", "t,r,+A,+C", 0, (int) M_EXT, INSN_MACRO, 0, I38, 0}, + +/* Precedence=0 */ +{"abs", "", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I38, 0}, +{"add", "", "d,v,t", 0x20000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, xNMS}, +{"add", "", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, 0, xNMS}, +{"addi", "", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, 0, xNMS}, +{"addiu", "[r1.sp]", "md,ms,mS", 0x7040, 0xfc40, WR_1|RD_2, 0, I38, 0}, /* ADDIU[R1.SP] */ +{"addiu", "[r2]", "md,mc,mB", 0x9000, 0xfc08, WR_1|RD_2, 0, I38, 0}, /* ADDIU[R2] */ +{"addiu", "[rs5]", "mp,mk,mQ", 0x9008, 0xfc08, MOD_1, INSN2_ALIAS, I38, 0}, /* ADDIU[RS5] */ +{"addiu", "[rs5]", "mp,mQ", 0x9008, 0xfc08, MOD_1, 0, I38, 0}, /* ADDIU[RS5], preceded by NOP[16] */ +{"addiu", "[gp.b]", "t,ma,+1", 0x440c0000, 0xfc1c0000, WR_1|RD_2, 0, I38, 0}, /* ADDIU[GP.B] */ +{"addiu", "[gp.w]", "t,ma,.", 0x40000000, 0xfc000003, WR_1|RD_2, 0, I38, 0}, /* ADDIU[GP.W] */ +{"addiu", "[32]", "+t,r,j", 0x00000000, 0xfc000000, WR_1|RD_2, 0, I38, 0}, /* preceded by SIGRIE */ +{"addiu", "[neg]", "t,r,h", 0x80008000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, /* ADDIU[NEG] */ +{"addiu", "[48]", "mp,mt,+R", 0x6001, 0xfc1f, MOD_1, 0, 0, xNMS}, /* ADDIU[48] */ +{"addiu", "[gp48]", "mp,ma,+O", 0x6002, 0xfc1f, WR_1|RD_2, 0, 0, xNMS}, /* ADDIU[GP48] */ +{"lapc", "[32]", "t,+r", 0x04000000, 0xfc000000, WR_1, INSN2_ALIAS, I38, 0}, /* ADDIUPC */ +{"lapc", "[48]", "mp,+S", 0x6003, 0xfc1f, WR_1, INSN2_ALIAS, 0, xNMS}, /* ADDIUPC[48] */ +{"addiupc", "[32]", "t,+s", 0x04000000, 0xfc000000, WR_1, 0, I38, 0}, +{"addiupc", "[48]", "mp,+P", 0x6003, 0xfc1f, WR_1, 0, 0, xNMS}, /* ADDIUPC[48] */ +{"addiu.b", "", "t,ma,+1", 0x440c0000, 0xfc1c0000, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* ADDIU[GP.B] */ +{"addiu.w", "", "t,ma,.", 0x40000000, 0xfc000003, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* ADDIU[GP.W] */ +{"addu", "[16]", "me,mc,md", 0xb000, 0xfc01, WR_1|RD_2|RD_3, 0, I38, 0}, /* ADDU[16] */ +{"addu", "[4x4]", "mu,mt,mv", 0x3c00, 0xfd08, MOD_1|RD_3, 0, 0, xNMS}, /* ADDU[4X4] */ +{"addu", "[4x4]", "mu,mv,mk", 0x3c00, 0xfd08, MOD_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* ADDU[4X4] */ +{"addu", "[32]", "d,v,t", 0x20000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"addu", "", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I38, 0}, +{"extw", "", "d,s,t,+I", 0x2000001f, 0xfc00003f, WR_1|RD_2|RD_3, 0, I38, 0}, +{"align", "", "mb,-i,mj,mz", 0x1000, 0xfc00, WR_1|RD_3, INSN2_ALIAS, I38, 0}, /* MOVE[16] */ +{"align", "", "d,-i,s,mz", 0x20000290, 0xffe007ff, WR_1|RD_3, INSN2_ALIAS, I38, 0}, /* MOVE[32] */ +{"align", "", "d,s,t,+v", 0x2000001f, 0xfc00003f, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* EXTW */ +{"and", "[16]", "md,mk,ml", 0x5008, 0xfc0f, MOD_1|RD_3, INSN2_ALIAS, I38, 0}, /* AND[16] */ +{"and", "[16]", "md,ml,mk", 0x5008, 0xfc0f, MOD_1|RD_2, INSN2_ALIAS, I38, 0}, /* AND[16] */ +{"and", "[16]", "md,ml", 0x5008, 0xfc0f, MOD_1|RD_2, 0, I38, 0}, /* AND[16] */ +{"and", "[32]", "d,v,t", 0x20000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"and", "[32]", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I38, 0}, +{"andi", "[16]", "md,mc,mC", 0xf000, 0xfc00, WR_1|RD_2, 0, I38, 0}, /* ANDI[16] */ +{"andi", "[32]", "t,r,g", 0x80002000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, +{"andi", "", "t,r,+6", 0x8000f000, 0xfc00f83f, WR_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* EXT */ +{"balc", "[16]", "mD", 0x3800, 0xfc00, WR_31, 0, I38, 0}, /* BALC[16] */ +{"balc", "[32]", "+u", 0x2a000000, 0xfe000000, WR_31, 0, I38, 0}, +{"bal", "", "mD", 0x3800, 0xfc00, WR_31, INSN2_ALIAS|UBR|CTC, I38, 0}, /* BALC[16] */ +{"bal", "", "+u", 0x2a000000, 0xfe000000, WR_31, INSN2_ALIAS|UBR|CTC, I38, 0}, /* BALC */ +{"balrsc", "", "+t,s", 0x48008000, 0xfc00ffff, WR_1|RD_2, 0, I38, 0}, +{"balrsc", "", "s", 0x4be08000, 0xffe0ffff, RD_1|WR_31, INSN2_ALIAS, I38, 0}, /* BALRSC */ +{"bbeqzc", "", "t,1,~", 0xc8040000, 0xfc1f0000, RD_1, 0, 0, xNMS}, +{"bbnezc", "", "t,1,~", 0xc8140000, 0xfc1f0000, RD_1, 0, 0, xNMS}, +{"bc", "[16]", "mD", 0x1800, 0xfc00, 0, 0, I38, 0}, /* BC[16] */ +{"bc", "[32]", "+u", 0x28000000, 0xfe000000, 0, 0, I38, 0}, +{"b", "", "mD", 0x1800, 0xfc00, 0, INSN2_ALIAS|UBR|CTC, I38, 0}, /* BC[16] */ +{"b", "", "+u", 0x28000000, 0xfe000000, 0, INSN2_ALIAS|UBR|CTC, I38, 0}, /* BC */ +{"beqzc", "[16]", "md,mE", 0x9800, 0xfc00, RD_1, 0, I38, 0}, /* BEQZC[16] */ +{"beqzc", "[32]", "t,p", 0x88000000, 0xfc1fc000, RD_1, INSN2_ALIAS, I38, 0}, /* BEQC */ +{"beqzc", "[32]", "s,p", 0x88000000, 0xffe0c000, RD_1, INSN2_ALIAS, I38, 0}, /* BEQC */ +{"beqz", "", "md,mE", 0x9800, 0xfc00, RD_1, INSN2_ALIAS|CBR|CTC, I38, 0}, /* BEQZC[16] */ +{"beqz", "", "t,p", 0x88000000, 0xfc1fc000, RD_1, INSN2_ALIAS|CBR|CTC, I38, 0}, /* BEQC */ +{"beqz", "", "s,p", 0x88000000, 0xffe0c000, RD_1, INSN2_ALIAS|CBR|CTC, I38, 0}, /* BEQC */ +{"beqc", "[16]", "md,z,mE", 0x9800, 0xfc00, RD_1, INSN2_ALIAS, I38, 0}, /* BEQZC[16] */ +{"beqc", "[16]", "z,md,mE", 0x9800, 0xfc00, RD_1, INSN2_ALIAS, I38, 0}, /* BEQZC[16] */ +{"beqc", "[16]", "ml,mf,mF", 0xd800, 0xfc00, RD_1|RD_2, 0, 0, xNMS}, /* BEQC[16], with rs3=rt3 && u[4:1]!=0 */ +{"bnec", "[16]", "md,mi,mF", 0xd800, 0xfc00, RD_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* BNEC[16], with operands commutated */ +{"bnec", "[32]", "s,t,p", 0xa8000000, 0xfc00c000, RD_1|RD_2, 0, I38, 0}, +{"bne", "", "md,z,mE", 0xb800, 0xfc00, RD_1, INSN2_ALIAS|CBR|CTC, I38, 0}, /* BNEZC[16] */ +{"bne", "", "z,md,mE", 0xb800, 0xfc00, RD_2, INSN2_ALIAS|CBR|CTC, I38, 0}, /* BNEZC[16] */ +{"bne", "", "ml,mh,mF", 0xd800, 0xfc00, RD_1|RD_2, INSN2_ALIAS|CBR|CTC, 0, xNMS}, /* BNEC[16], with rs3>=rt3 && u[4:1]!=0 */ +{"bne", "", "md,mi,mF", 0xd800, 0xfc00, RD_1|RD_2, INSN2_ALIAS|CBR|CTC, 0, xNMS}, /* BNEC[16], with operands commutated */ +{"bne", "", "s,t,p", 0xa8000000, 0xfc00c000, RD_1|RD_2, INSN2_ALIAS|CBR|CTC, I38, 0}, /* BNEC */ +{"bne", "", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I38, 0}, +{"bneic", "", "t,+9,~", 0xc8100000, 0xfc1c0000, RD_1, 0, I38, 0}, +{"brsc", "", "s", 0x48008000, 0xffe0ffff, RD_1, 0, I38, 0}, +{"byterevh", "", "t,r", 0x8000d608, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* ROTX t,s,8,24 */ +{"byterevw", "", "t,r", 0x8000d218, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* ROTX t,s,24,8 */ +{"cache", "", "k,+j(b)", 0xa4003900, 0xfc007f00, RD_3, 0, I38, 0}, +{"cache", "", "k,A(c)", 0, (int) M_CACHE_AC, INSN_MACRO, 0, I38, 0}, +{"cfc1", "", "t,G", 0xa000103b, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, I38, 0}, +{"cfc1", "", "t,S", 0xa000103b, 0xfc00ffff, WR_1|RD_2, 0, I38, 0}, +{"cftc1", "", "t,G", 0x20001e30, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"cftc1", "", "t,S", 0x20001e30, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"cftc2", "", "t,G", 0x20002e30, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"clo", "", "t,s", 0x20004b3f, 0xfc00ffff, WR_1|RD_2, 0, 0, xNMS}, +{"clz", "", "t,s", 0x20005b3f, 0xfc00ffff, WR_1|RD_2, 0, 0, xNMS}, +{"cop2_1", "", "C", 0x20000002, 0xfc000007, 0, 0, I38, 0}, +{"ctc1", "", "t,G", 0xa000183b, 0xfc00ffff, RD_1|WR_2, INSN2_ALIAS, I38, 0}, +{"ctc1", "", "t,S", 0xa000183b, 0xfc00ffff, RD_1|WR_2, 0, I38, 0}, +{"cttc1", "", "t,G", 0x20001e70, 0xfc00ffff, RD_1|WR_2, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"cttc1", "", "t,S", 0x20001e70, 0xfc00ffff, RD_1|WR_2, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"cttc2", "", "t,G", 0x20002e70, 0xfc00ffff, RD_1|WR_2, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"dabs", "", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I38, 0}, +{"daddiu", "[neg]", "t,r,h", 0x80008000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, /* DADDIU[NEG] */ +{"deret", "", "", 0x2000e37f, 0xffffffff, 0, 0, I38, 0}, +{"di", "", "", 0x2000477f, 0xffffffff, 0, INSN2_ALIAS, I38, 0}, +{"di", "", "w", 0x2000477f, 0xfc1fffff, WR_1, 0, I38, 0}, +{"div", "", "d,v,t", 0x20000118, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"div", "", "d,v,I", 0, (int) M_DIV_I, INSN_MACRO, 0, I38, 0}, +{"divu", "", "d,v,t", 0x20000198, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"divu", "", "d,v,I", 0, (int) M_DIVU_I, INSN_MACRO, 0, I38, 0}, +{"dmt", "", "", 0x20010ab0, 0xffffffff, 0, INSN2_ALIAS, 0, MT32}, +{"dmt", "", "t", 0x20010ab0, 0xfc1fffff, WR_1, 0, 0, MT32}, +{"dvpe", "", "", 0x20000ab0, 0xffffffff, 0, INSN2_ALIAS, 0, MT32}, /* DVPE */ +{"dvpe", "", "t", 0x20000ab0, 0xfc1fffff, WR_1, 0, 0, MT32}, +{"ehb", "", "", 0x8000c003, 0xffffffff, 0, 0, I38, 0}, +{"ei", "", "", 0x2000577f, 0xffffffff, 0, INSN2_ALIAS, I38, 0}, +{"ei", "", "t", 0x2000577f, 0xfc1fffff, WR_1, 0, I38, 0}, +{"emt", "", "", 0x20010eb0, 0xffffffff, 0, INSN2_ALIAS, 0, MT32}, +{"emt", "", "t", 0x20010eb0, 0xfc1fffff, WR_1, 0, 0, MT32}, +{"eret", "", "", 0x2000f37f, 0xffffffff, 0, 0, I38, 0}, +{"eretnc", "", "", 0x2001f37f, 0xffffffff, 0, 0, I38, 0}, +{"evpe", "", "", 0x20000eb0, 0xffffffff, 0, INSN2_ALIAS, 0, MT32}, /* EVPE */ +{"evpe", "", "t", 0x20000eb0, 0xfc1fffff, WR_1, 0, 0, MT32}, +{"evp", "", "-a", 0x20000790, 0xffe0ffff, 0, INSN2_ALIAS, I38, 0}, /* EVP */ +{"evp", "", "t,-a", 0x20000790, 0xfc00ffff, WR_1, 0, I38, 0}, +{"fork", "", "d,s,t", 0x20000228, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, MT32}, +{"ins", "", "t,r,+A,+B", 0x8000e000, 0xfc00f820, WR_1|RD_2, 0, 0, xNMS}, +{"ins", "", "t,r,+A,+B", 0, (int) M_INS, INSN_MACRO, 0, I38, 0}, +{"j", "", "mp", 0xd800, 0xfc1f, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, +{"j", "", "+u", 0x28000000, 0xfe000000, 0, INSN2_ALIAS|UBR|CTC, I38, 0}, /* BC */ +{"j", "", "s", 0x48000000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC */ +{"jrc.hb", "", "s", 0x48001000, 0xffe0ffff, RD_1, INSN2_ALIAS, I38, 0}, /* JALRC.HB */ +{"jr.hb", "", "s", 0x48001000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC.HB */ +{"jalrc.hb", "", "s", 0x4be01000, 0xffe0ffff, RD_1, INSN2_ALIAS, I38, 0}, /* JALRC.HB */ +{"jalrc.hb", "", "t,s", 0x48001000, 0xfc00ffff, WR_1|RD_2, 0, I38, 0}, +{"jalr.hb", "", "s", 0x4be01000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC.HB */ +{"jalr.hb", "", "t,s", 0x48001000, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC.HB */ +/* SVR4 PIC code requires special handling for jal, so it must be a macro. */ +{"jal", "", "my,mp", 0xd810, 0xfc1f, WR_31|RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC[16] */ +{"jal", "", "mp", 0xd810, 0xfc1f, WR_31|RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC[16] */ +{"jal", "", "s", 0x4be00000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC */ +{"jal", "", "t,s", 0x48000000, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, I38, 0}, /* JALRC */ +{"jal", "", "A", 0, (int) M_JAL_A, INSN_MACRO, 0, I38, 0}, +{"jal", "", "+u", 0x2a000000, 0xfe000000, WR_31, INSN2_ALIAS|UBR|CTC, I38, 0}, /* BALC */ +{"lb", "[16]", "md,mL(ml)", 0x5c00, 0xfc0c, WR_1|RD_3, 0, I38, 0}, /* LB[16] */ +{"lb", "[gp]", "t,+1(ma)", 0x44000000, 0xfc1c0000, WR_1|RD_3, 0, I38, 0}, /* LB[GP] */ +{"lb", "[u12]", "t,o(b)", 0x84000000, 0xfc00f000, WR_1|RD_3, 0, I38, 0}, /* LB[U12] */ +{"lb", "[s9]", "t,+j(b)", 0xa4000000, 0xfc007f00, WR_1|RD_3, 0, I38, 0}, /* LB[S9] */ +{"lb", "", "t,A(c)", 0, (int) M_LB_AC, INSN_MACRO, 0, I38, 0}, +{"lbu", "[16]", "md,mL(ml)", 0x5c08, 0xfc0c, WR_1|RD_3, 0, I38, 0}, /* LBU[16] */ +{"lbu", "[gp]", "t,+1(ma)", 0x44080000, 0xfc1c0000, WR_1|RD_3, 0, I38, 0}, /* LBU[GP] */ +{"lbu", "[u12]", "t,o(b)", 0x84002000, 0xfc00f000, WR_1|RD_3, 0, I38, 0}, /* LBU[U12] */ +{"lbu", "[s9]", "t,+j(b)", 0xa4001000, 0xfc007f00, WR_1|RD_3, 0, I38, 0}, /* LBU[S9] */ +{"lbu", "", "t,A(c)", 0, (int) M_LBU_AC, INSN_MACRO, 0, I38, 0}, +{"lbux", "", "d,s(t)", 0x20000107, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"lbx", "", "d,s(t)", 0x20000007, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"ld", "", "t,A(c)", 0, (int) M_LD_AC, INSN_MACRO, 0, I38, 0}, +{"lh", "[16]", "md,mH(ml)", 0x7c00, 0xfc09, WR_1|RD_3, 0, I38, 0}, /* LH[16] */ +{"lh", "[gp]", "t,+3(ma)", 0x44100000, 0xfc1c0001, WR_1|RD_3, 0, I38, 0}, /* LH[GP] */ +{"lh", "[u12]", "t,o(b)", 0x84004000, 0xfc00f000, WR_1|RD_3, 0, I38, 0}, /* LH[U12] */ +{"lh", "[s9]", "t,+j(b)", 0xa4002000, 0xfc007f00, WR_1|RD_3, 0, I38, 0}, /* LH[S9] */ +{"lh", "", "t,A(c)", 0, (int) M_LH_AC, INSN_MACRO, 0, I38, 0}, +{"lhu", "[16]", "md,mH(ml)", 0x7c08, 0xfc09, WR_1|RD_3, 0, I38, 0}, /* LHU[16] */ +{"lhu", "[gp]", "t,+3(ma)", 0x44100001, 0xfc1c0001, WR_1|RD_3, 0, I38, 0}, /* LHU[GP] */ +{"lhu", "[u12]", "t,o(b)", 0x84006000, 0xfc00f000, WR_1|RD_3, 0, I38, 0}, /* LHU[U12] */ +{"lhu", "[s9]", "t,+j(b)", 0xa4003000, 0xfc007f00, WR_1|RD_3, 0, I38, 0}, /* LHU[S9] */ +{"lhu", "", "t,A(c)", 0, (int) M_LHU_AC, INSN_MACRO, 0, I38, 0}, +{"lhux", "", "d,s(t)", 0x20000307, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"lhuxs", "", "d,s(t)", 0x20000347, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"lhx", "", "d,s(t)", 0x20000207, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"lhxs", "", "d,s(t)", 0x20000247, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"li.d", "", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I38, 0}, +{"li.s", "", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I38, 0}, +{"ll", "", "t,+p(b)", 0xa4005100, 0xfc007f03, WR_1|RD_3, 0, I38, 0}, +{"ll", "", "t,A(c)", 0, (int) M_LL_AC, INSN_MACRO, 0, I38, 0}, +{"llwp", "", "t,e,(b)", 0xa4005101, 0xfc00ff07, WR_1|WR_2|RD_3, 0, 0, xNMS}, +{"lsa", "", "d,v,t,+w", 0x2000000f, 0xfc0001ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"lw", "[16]", "md,mJ(ml)", 0x1400, 0xfc00, WR_1|RD_3, 0, I38, 0}, /* LW[16] */ +{"lw", "[4x4]", "mu,mN(mv)", 0x7400, 0xfc00, WR_1|RD_3, 0, 0, xNMS}, /* LW[4X4] */ +{"lw", "[sp]", "mp,mR(ms)", 0x3400, 0xfc00, WR_1|RD_3, 0, I38, 0}, /* LW[SP] */ +{"lw", "[gp16]", "md,mO(ma)", 0x5400, 0xfc00, WR_1|RD_3, 0, I38, 0}, /* LW[GP16] */ +{"lw", "[gp]", "t,.(ma)", 0x40000002, 0xfc000003, WR_1|RD_3, 0, I38, 0}, /* LW[GP] */ +{"lw", "[gp16]", "md,mA(ma)", 0x5400, 0xfc00, WR_1|RD_3, 0, I38, 0}, /* LW[GP16] */ +{"lw", "[u12]", "t,o(b)", 0x84008000, 0xfc00f000, WR_1|RD_3, 0, I38, 0}, /* LW[U12] */ +{"lw", "[s9]", "t,+j(b)", 0xa4004000, 0xfc007f00, WR_1|RD_3, 0, I38, 0}, /* LW[S9] */ +{"lw", "", "t,A(c)", 0, (int) M_LW_AC, INSN_MACRO, 0, I38, 0}, +{"lwm", "", "t,+j(b),|", 0xa4000400, 0xfc000f00, WR_1|RD_3, 0, 0, xNMS}, /* LWM */ +{"lwpc", "[48]", "mp,+S", 0x600b, 0xfc1f, WR_1, 0, 0, xNMS}, /* LWPC[48] */ +{"lwx", "", "d,s(t)", 0x20000407, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"lwxs", "[16]", "me,ml(md)", 0x5001, 0xfc01, WR_1|RD_2|RD_3, 0, I38, 0}, /* LWXS[16] */ +{"lwxs", "[32]", "d,s(t)", 0x20000447, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"mfc0", "", "t,O", 0x20000030, 0xfc0007ff, WR_1, INSN2_ALIAS, I38, 0}, /* MFC0 with named register */ +{"mfc0", "", "t,P,J", 0x20000030, 0xfc0007ff, WR_1, INSN2_ALIAS, I38, 0}, /* MFC0 with named register & select */ +{"mfc0", "", "t,G,J", 0x20000030, 0xfc0007ff, WR_1, 0, I38, 0}, +{"mfhc0", "", "t,O", 0x20000038, 0xfc0007ff, WR_1, INSN2_ALIAS, I38, 0}, /* MFHC0 with named register */ +{"mfhc0", "", "t,P,J", 0x20000038, 0xfc0007ff, WR_1, INSN2_ALIAS, I38, 0}, /* MFHC0 with named register & select*/ +{"mfhc0", "", "t,G,J", 0x20000038, 0xfc0007ff, WR_1, 0, I38, 0}, +{"mftc0", "", "t,O", 0x20000230, 0xfc0007ff, WR_1, INSN2_ALIAS, 0, MT32}, /* MFTR with named register */ +{"mftc0", "", "t,P,J", 0x20000230, 0xfc0007ff, WR_1, INSN2_ALIAS, 0, MT32}, /* MFTR with named register & select */ +{"mfthc0", "", "t,O", 0x20000238, 0xfc0007ff, WR_1, INSN2_ALIAS, 0, MT32}, /* MFTR with named register */ +{"mfthc0", "", "t,P,J", 0x20000238, 0xfc0007ff, WR_1, INSN2_ALIAS, 0, MT32}, /* MFTR with named register & select*/ +{"mftc1", "", "t,S", 0x20001630, 0xfc00ffff, WR_1|RD_2|FP_S, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mftc1", "", "t,G", 0x20001630, 0xfc00ffff, WR_1|RD_2|FP_S, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mftc2", "", "t,G", 0x20002630, 0xfc00ffff, WR_1, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mftdsp", "", "t", 0x20100e30, 0xfc1fffff, WR_1, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mftgpr", "", "t,s", 0x20000630, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mfthc1", "", "t,S", 0x20001638, 0xfc00ffff, WR_1|RD_2|FP_D, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mfthc1", "", "t,G", 0x20001638, 0xfc00ffff, WR_1|RD_2|FP_D, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mfthc2", "", "t,G", 0x20002638, 0xfc00ffff, WR_1, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mfthi", "", "t", 0x20010e30, 0xfc1fffff, WR_1|RD_a, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mfthi", "", "t,*", 0x20010e30, 0xfc13ffff, WR_1|RD_a, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mftlo", "", "t", 0x20000e30, 0xfc1fffff, WR_1|RD_a, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mftlo", "", "t,*", 0x20000e30, 0xfc13ffff, WR_1|RD_a, INSN2_ALIAS, 0, MT32}, /* MFTR */ +{"mftr", "", "t,s,!,H,$", 0x20000230, 0xfc0003f7, WR_1, 0, 0, MT32}, +{"mod", "", "d,v,t", 0x20000158, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"mod", "", "d,v,I", 0, (int) M_MOD_I, INSN_MACRO, 0, I38, 0}, +{"modu", "", "d,v,t", 0x200001d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"modu", "", "d,v,I", 0, (int) M_MODU_I, INSN_MACRO, 0, I38, 0}, +{"move.balc", "", "+7,+5,+r", 0x08000000, 0xfc000000, WR_1|RD_2, 0, 0, xNMS}, +{"move.bal", "", "+7,+5,+r", 0x08000000, 0xfc000000, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, 0, xNMS}, /* MOVE.BALC */ +{"movep", "", "mq,mx,mw", 0xbc00, 0xfc00, WR_1|RD_2|RD_3, 0, 0, xNMS}, /* MOVEP */ +{"movep", "", "mr,mw,mx", 0xbc00, 0xfc00, WR_1|RD_2|RD_3, INSN2_ALIAS, 0, xNMS}, /* MOVEP */ +{"movep", "[rev]", "mv,mu,mq", 0xfc00, 0xfc00, WR_1|WR_2|RD_3, 0, 0, xNMS}, /* MOVEP[REV] */ +{"movep", "[rev]", "mu,mv,mr", 0xfc00, 0xfc00, WR_1|WR_2|RD_3, INSN2_ALIAS, 0, xNMS}, /* MOVEP[REV] */ +{"movn", "", "d,v,t", 0x20000610, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"movz", "", "d,v,t", 0x20000210, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"mtc0", "", "t,O", 0x20000070, 0xfc0007ff, RD_1, INSN2_ALIAS, I38, 0}, /* MTC0 with named register */ +{"mtc0", "", "t,P,J", 0x20000070, 0xfc0007ff, RD_1, INSN2_ALIAS, I38, 0}, /* MTCO with named register & select */ +{"mtc0", "", "t,G,J", 0x20000070, 0xfc0007ff, RD_1, 0, I38, 0}, +{"mthc0", "", "t,O", 0x20000078, 0xfc0007ff, RD_1, INSN2_ALIAS, I38, 0}, /* MTHC0 with named register */ +{"mthc0", "", "t,P,J", 0x20000078, 0xfc0007ff, RD_1, INSN2_ALIAS, I38, 0}, /* MTHC0 with named register & select */ +{"mthc0", "", "t,G,J", 0x20000078, 0xfc0007ff, RD_1, 0, I38, 0}, +{"mttc0", "", "t,O", 0x20000270, 0xfc0007ff, RD_1, INSN2_ALIAS, 0, MT32}, /* MTTR with named register */ +{"mttc0", "", "t,P,J", 0x20000270, 0xfc0007ff, RD_1, INSN2_ALIAS, 0, MT32}, /* MTTR with named register & select */ +{"mtthc0", "", "t,O", 0x20000278, 0xfc0007ff, RD_1, INSN2_ALIAS, 0, MT32}, /* MTTR with named register*/ +{"mtthc0", "", "t,P,J", 0x20000278, 0xfc0007ff, RD_1, INSN2_ALIAS, 0, MT32}, /* MTTR with named register & select */ +{"mttc1", "", "t,S", 0x20001670, 0xfc00ffff, RD_1|WR_2|FP_S, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mttc1", "", "t,G", 0x20001670, 0xfc00ffff, RD_1|WR_2|FP_S, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mttc2", "", "t,G", 0x20002670, 0xfc00ffff, RD_1, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mttgpr", "", "t,s", 0x20000670, 0xfc00ffff, RD_1|WR_2, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mtthc1", "", "t,S", 0x20001678, 0xfc00ffff, RD_1|WR_2|FP_D, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mtthc1", "", "t,G", 0x20001678, 0xfc00ffff, RD_1|WR_2|FP_D, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mtthc2", "", "t,G", 0x20002678, 0xfc00ffff, RD_1, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mtthi", "", "t", 0x20010e70, 0xfc1fffff, RD_1|WR_a, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mtthi", "", "t,*", 0x20010e70, 0xfc13ffff, RD_1|WR_a, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mttlo", "", "t", 0x20000e70, 0xfc1fffff, RD_1|WR_a, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mttlo", "", "t,*", 0x20000e70, 0xfc13ffff, RD_1|WR_a, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mttdsp", "", "t", 0x20100e70, 0xfc1fffff, RD_1, INSN2_ALIAS, 0, MT32}, /* MTTR */ +{"mttr", "", "t,s,!,H,$", 0x20000270, 0xfc0003f7, RD_1, 0, 0, MT32}, +{"muh", "", "d,v,t", 0x20000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"muhu", "", "d,v,t", 0x200000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"mul", "[4x4]", "mu,mt,mv", 0x3c08, 0xfd08, MOD_1|RD_3, 0, 0, xNMS}, /* MUL[4X4] */ +{"mul", "[4x4]", "mu,mv,mk", 0x3c08, 0xfd08, MOD_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* MUL[4X4] */ +{"mul", "[32]", "d,v,t", 0x20000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"mul", "", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I38, 0}, +{"mulu", "", "d,v,t", 0x20000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"neg", "", "d,w", 0x20000190, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* SUB */ +{"negu", "", "d,w", 0x200001d0, 0xfc1f07ff, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* SUBU */ +{"not", "[16]", "md,ml", 0x5000, 0xfc0f, WR_1|RD_2, 0, I38, 0}, /* NOT[16] */ +{"not", "[32]", "d,v", 0x200002d0, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* NOR */ +{"nor", "", "d,v,t", 0x200002d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"nor", "", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I38, 0}, +{"or", "[16]", "md,mk,ml", 0x500c, 0xfc0f, WR_1|RD_3, INSN2_ALIAS, I38, 0}, /* OR[16] */ +{"or", "[16]", "md,ml,mk", 0x500c, 0xfc0f, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* OR[16] */ +{"or", "[16]", "md,ml", 0x500c, 0xfc0f, WR_1|RD_2, 0, I38, 0}, /* OR[16] */ +{"or", "[32]", "d,v,t", 0x20000290, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"or", "", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I38, 0}, +{"ori", "", "t,r,g", 0x80000000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, +{"pause", "", "", 0x8000c005, 0xffffffff, 0, 0, I38, 0}, +{"pref", "[u12]", "k,o(b)", 0x84003000, 0xfc00f000, RD_3, 0, I38, 0}, /* PREF[U12] */ +{"pref", "[s9]", "k,+j(b)", 0xa4001800, 0xfc007f00, RD_3, 0, I38, 0}, /* PREF[S9], preceded by SYNCI[S9] */ +{"pref", "", "k,A(c)", 0, (int) M_PREF_AC, INSN_MACRO, 0, I38, 0}, +{"rdhwr", "", "t,K", 0x200001c0, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, xNMS}, +{"rdpgpr", "", "t,s", 0x2000e17f, 0xfc00ffff, WR_1|RD_2, 0, I38, 0}, +{"rem", "", "d,v,t", 0x20000158, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* MOD */ +{"rem", "", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I38, 0}, +{"remu", "", "d,v,t", 0x200001d8, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* MODU */ +{"restore", "[32]", "+N,n", 0x80003002, 0xfc00f003, 0, 0, I38, 0}, +{"restore.jrc", "[16]", "mG", 0x1d00, 0xff0f, 0, 0, I38, 0}, /* RESTORE.JRC[16] */ +{"restore.jrc", "[16]", "mG,mn", 0x1d00, 0xfd00, 0, 0, I38, 0}, /* RESTORE.JRC[16], preceded by RESTORE[16] */ +{"restore.jrc", "[32]", "+N", 0x80003003, 0xfffff007, 0, 0, I38, 0}, /* RESTORE.JRC[32] */ +{"restore.jrc", "[32]", "+N,n", 0x80003003, 0xfc00f003, 0, 0, I38, 0}, +{"jraddiusp", "", "mG", 0x1d00, 0xff0f, 0, INSN2_ALIAS, I38, 0}, /* RESTORE.JRC[16] */ +{"jraddiusp", "", "+N", 0x80003003, 0xfffff007, 0, INSN2_ALIAS, I38, 0}, /* RESTORE.JRC[32] */ +{"jraddiusp", "", "I", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I38, 0}, +{"rol", "", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I38, 0}, +{"rol", "", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I38, 0}, +{"rotrv", "", "d,s,t", 0x200000d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"rotr", "", "t,r,<", 0x8000c0c0, 0xfc00ffe0, WR_1|RD_2, 0, I38, 0}, +{"rotr", "", "d,v,t", 0x200000d0, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* ROTRV */ +{"ror", "", "t,r,<", 0x8000c0c0, 0xfc00ffe0, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* ROTR */ +{"ror", "", "d,v,t", 0x200000d0, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* ROTRV */ +{"ror", "", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I38, 0}, +{"rorv", "", "t,r,<", 0x8000c0c0, 0xfc00ffe0, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* ROTR */ +{"rorv", "", "d,v,t", 0x200000d0, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* ROTRV */ +{"rotl", "", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I38, 0}, +{"rotl", "", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I38, 0}, +{"wsbh", "", "t,r", 0x8000d608, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* ROTX t,s,8,24*/ +{"rotx", "", "t,r,<,+*", 0x8000d000, 0xfc00f860, WR_1|RD_2, INSN2_ALIAS, 0, xNMS}, +{"rotx", "", "t,r,<,+*,+|", 0x8000d000, 0xfc00f820, WR_1|RD_2, 0, 0, xNMS}, +{"save", "[16]", "mG", 0x1c00, 0xff0f, 0, 0, I38, 0}, /* SAVE[16] */ +{"save", "[16]", "mG,mn", 0x1c00, 0xfd00, 0, 0, I38, 0}, /* SAVE[16] */ +{"save", "[32]", "+N,n", 0x80003000, 0xfc00f003, 0, 0, I38, 0}, +{"sb", "[16]", "mm,mL(ml)", 0x5c04, 0xfc0c, RD_1|RD_3, 0, I38, 0}, /* SB[16] */ +{"sb", "[gp]", "t,+1(ma)", 0x44040000, 0xfc1c0000, RD_1|RD_3, 0, I38, 0}, /* SB[GP] */ +{"sb", "[u12]", "t,o(b)", 0x84001000, 0xfc00f000, RD_1|RD_3, 0, I38, 0}, /* SB[U12] */ +{"sb", "[s9]", "t,+j(b)", 0xa4000800, 0xfc007f00, RD_1|RD_3, 0, I38, 0}, /* SB[S9] */ +{"sb", "", "t,A(c)", 0, (int) M_SB_AC, INSN_MACRO, 0, I38, 0}, +{"sbx", "", "d,s(t)", 0x20000087, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, xNMS}, +{"sc", "", "t,+p(b)", 0xa4005900, 0xfc007f03, MOD_1|RD_3, 0, I38, 0}, +{"sc", "", "t,A(c)", 0, (int) M_SC_AC, INSN_MACRO, 0, I38, 0}, +{"scwp", "", "t,e,(b)", 0xa4005901, 0xfc00ff07, MOD_1|WR_2|RD_3, 0, 0, xNMS}, +{"sd", "", "t,A(c)", 0, (int) M_SD_AC, INSN_MACRO, 0, I38, 0}, +{"seb", "", "t,r", 0x20000008, 0xfc00ffff, WR_1|RD_2, 0, 0, xNMS}, +{"seh", "", "t,r", 0x20000048, 0xfc00ffff, WR_1|RD_2, 0, I38, 0}, +{"seqi", "", "t,r,i", 0x80006000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, +{"seq", "", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I38, 0}, +{"seq", "", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I38, 0}, +{"sge", "", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I38, 0}, +{"sge", "", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I38, 0}, +{"sgeu", "", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I38, 0}, +{"sgeu", "", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I38, 0}, +{"sgt", "", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I38, 0}, +{"sgt", "", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I38, 0}, +{"sgtu", "", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I38, 0}, +{"sgtu", "", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I38, 0}, +{"sh", "[16]", "mm,mH(ml)", 0x7c01, 0xfc09, RD_1|RD_3, 0, I38, 0}, /* SH[16] */ +{"sh", "[gp]", "t,+3(ma)", 0x44140000, 0xfc1c0001, RD_1|RD_3, 0, I38, 0}, /* SH[GP] */ +{"sh", "[u12]", "t,o(b)", 0x84005000, 0xfc00f000, RD_1|RD_3, 0, I38, 0}, /* SH[U12] */ +{"sh", "[s9]", "t,+j(b)", 0xa4002800, 0xfc007f00, RD_1|RD_3, 0, I38, 0}, /* SH[S9] */ +{"sh", "", "t,A(c)", 0, (int) M_SH_AC, INSN_MACRO, 0, I38, 0}, +{"shx", "", "d,s(t)", 0x20000287, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, xNMS}, +{"shxs", "", "d,s(t)", 0x200002c7, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, xNMS}, +{"sync", "", "", 0x8000c006, 0xffffffff, 0, 0, I38, 0}, +{"sync", "", "+i", 0x8000c006, 0xffe0ffff, 0, 0, I38, 0}, +{"sle", "", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I38, 0}, +{"sle", "", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I38, 0}, +{"sleu", "", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I38, 0}, +{"sleu", "", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I38, 0}, +{"sllv", "", "d,s,t", 0x20000010, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"sll", "[16]", "md,mc,mM", 0x3000, 0xfc08, WR_1|RD_2, 0, I38, 0}, /* SLL[16] */ +{"sll", "[32]", "t,r,<", 0x8000c000, 0xfc00ffe0, WR_1|RD_2, 0, I38, 0}, /* preceded by EHB, PAUSE, SYNC */ +{"sll", "[32]", "d,v,t", 0x20000010, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* SLLV */ +{"slt", "", "d,v,t", 0x20000350, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"slt", "", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I38, 0}, +{"slti", "", "t,r,i", 0x80004000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, +{"sltiu", "", "t,r,i", 0x80005000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, +{"sltu", "", "d,v,t", 0x20000390, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, /* preceded by DVP */ +{"sltu", "", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I38, 0}, +{"sne", "", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I38, 0}, +{"sne", "", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I38, 0}, +{"sov", "", "d,v,t", 0x200003d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"srav", "", "d,s,t", 0x20000090, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"sra", "", "t,r,<", 0x8000c080, 0xfc00ffe0, WR_1|RD_2, 0, I38, 0}, +{"sra", "", "d,v,t", 0x20000090, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* SRAV */ +{"srlv", "", "d,s,t", 0x20000050, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"srl", "[16]", "md,mc,mM", 0x3008, 0xfc08, WR_1|RD_2, 0, I38, 0}, /* SRL[16] */ +{"srl", "[32]", "t,r,<", 0x8000c040, 0xfc00ffe0, WR_1|RD_2, 0, I38, 0}, +{"srl", "[32]", "d,v,t", 0x20000050, 0xfc0007ff, WR_1|RD_2|RD_3, INSN2_ALIAS, I38, 0}, /* SRLV */ +{"sub", "", "d,v,t", 0x20000190, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, xNMS}, +{"sub", "", "t,r,I", 0, (int) M_SUB_I, INSN_MACRO, 0, 0, xNMS}, +{"subu", "[16]", "me,mc,md", 0xb001, 0xfc01, WR_1|RD_2|RD_3, 0, I38, 0}, /* SUBU[16] */ +{"subu", "[32]", "d,v,t", 0x200001d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"subu", "", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I38, 0}, +{"sw", "[16]", "mm,mJ(ml)", 0x9400, 0xfc00, RD_1|RD_3, 0, I38, 0}, /* SW[16] */ +{"sw", "[sp]", "mp,mR(ms)", 0xb400, 0xfc00, RD_1|RD_3, 0, I38, 0}, /* SW[SP] */ +{"sw", "[4x4]", "mw,mN(mv)", 0xf400, 0xfc00, RD_1|RD_3, 0, 0, xNMS}, /* SW[4X4] */ +{"sw", "[gp16]", "mm,mO(ma)", 0xd400, 0xfc00, RD_1|RD_3, 0, I38, 0}, /* SW[GP16] */ +{"sw", "[gp]", "t,.(ma)", 0x40000003, 0xfc000003, RD_1|RD_3, 0, I38, 0}, /* SW[GP] */ +{"sw", "[gp16]", "mm,mA(ma)", 0xd400, 0xfc00, RD_1|RD_3, 0, I38, 0}, /* SW[GP16] */ +{"sw", "[u12]", "t,o(b)", 0x84009000, 0xfc00f000, RD_1|RD_3, 0, I38, 0}, /* SW[U12] */ +{"sw", "[s9]", "t,+j(b)", 0xa4004800, 0xfc007f00, RD_1|RD_3, 0, I38, 0}, /* SW[S9] */ +{"sw", "", "t,A(c)", 0, (int) M_SW_AC, INSN_MACRO, 0, I38, 0}, +{"swm", "", "t,+j(b),|", 0xa4000c00, 0xfc000f00, RD_1|RD_3, 0, 0, xNMS}, /* SWM */ +{"swpc", "[48]", "mp,+S", 0x600f, 0xfc1f, WR_1, 0, 0, xNMS}, /* SWPC[48] */ +{"swx", "", "d,s(t)", 0x20000487, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, xNMS}, +{"swxs", "", "d,s(t)", 0x200004c7, 0xfc0007ff, RD_1|RD_2|RD_3, 0, 0, xNMS}, +{"syscall", "[16]", "", 0x1008, 0xffff, 0, INSN2_ALIAS, I38, 0}, /* SYSCALL[16] */ +{"syscall", "[16]", "mP", 0x1008, 0xfffc, 0, 0, I38, 0}, /* SYSCALL[16] */ +{"syscall", "[32]", "", 0x00080000, 0xffffffff, 0, INSN2_ALIAS, I38, 0}, +{"syscall", "[32]", "+M", 0x00080000, 0xfffc0000, 0, 0, I38, 0}, +{"teq", "", "s,t", 0x20000000, 0xfc00ffff, RD_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* TEQ */ +{"teq", "", "s,t,^", 0x20000000, 0xfc0007ff, RD_1|RD_2, 0, 0, xNMS}, /* TEQ */ +{"teq", "", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, 0, xNMS}, +{"tne", "", "s,t", 0x20000400, 0xfc00ffff, RD_1|RD_2, INSN2_ALIAS, 0, xNMS}, /* TNE */ +{"tne", "", "s,t,^", 0x20000400, 0xfc0007ff, RD_1|RD_2, 0, 0, xNMS}, /* TNE */ +{"tne", "", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, 0, xNMS}, +{"ualh", "", "t,+j(b)", 0xa4002100, 0xfc007f00, WR_1|RD_3, 0, 0, xNMS}, +{"ualw", "", "t,+j(b)", 0xa4001500, 0xfc007f00, WR_1|RD_3, INSN2_ALIAS, 0, xNMS}, /* UALWM */ +{"ualwm", "", "t,+j(b),|", 0xa4000500, 0xfc000f00, WR_1|RD_3, 0, 0, xNMS}, /* UALWM */ +{"uash", "", "t,+j(b)", 0xa4002900, 0xfc007f00, RD_1|RD_3, 0, 0, xNMS}, +{"uasw", "", "t,+j(b)", 0xa4001d00, 0xfc007f00, RD_1|RD_3, INSN2_ALIAS, 0, xNMS}, /* UASWM */ +{"uaswm", "", "t,+j(b),|", 0xa4000d00, 0xfc000f00, RD_1|RD_3, 0, 0, xNMS}, /* UASWM */ +{"uld", "", "t,A(c)", 0, (int) M_ULD_AC, INSN_MACRO, 0, 0, xNMS}, +{"ulh", "", "t,A(c)", 0, (int) M_ULH_AC, INSN_MACRO, 0, 0, xNMS}, +{"ulw", "", "t,A(c)", 0, (int) M_ULW_AC, INSN_MACRO, 0, 0, xNMS}, +{"usd", "", "t,A(c)", 0, (int) M_USD_AC, INSN_MACRO, 0, 0, xNMS}, +{"ush", "", "t,A(c)", 0, (int) M_USH_AC, INSN_MACRO, 0, 0, xNMS}, +{"usw", "", "t,A(c)", 0, (int) M_USW_AC, INSN_MACRO, 0, 0, xNMS}, +{"wait", "", "", 0x2000c37f, 0xffffffff, 0, INSN2_ALIAS, I38, 0}, +{"wait", "", "+L", 0x2000c37f, 0xfc00ffff, 0, 0, I38, 0}, +{"wrpgpr", "", "t,r", 0x2000f17f, 0xfc00ffff, WR_1|RD_2, 0, I38, 0}, +{"xor", "[16]", "md,mk,ml", 0x5004, 0xfc0f, WR_1|RD_3, INSN2_ALIAS, I38, 0}, /* XOR[16] */ +{"xor", "[16]", "md,ml,mk", 0x5004, 0xfc0f, WR_1|RD_2, INSN2_ALIAS, I38, 0}, /* XOR[16] */ +{"xor", "[16]", "md,ml", 0x5004, 0xfc0f, WR_1|RD_2, 0, I38, 0}, /* XOR[16] */ +{"xor", "[32]", "d,v,t", 0x20000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I38, 0}, +{"xor", "", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I38, 0}, +{"xori", "", "t,r,g", 0x80001000, 0xfc00f000, WR_1|RD_2, 0, I38, 0}, +{"yield", "", "s", 0x20000268, 0xffe0ffff, RD_1, INSN2_ALIAS, 0, MT32}, +{"yield", "", "t,s", 0x20000268, 0xfc00ffff, WR_1|RD_2, 0, 0, MT32}, +}; + +const int bfd_nanomips_num_opcodes = + ((sizeof nanomips_opcodes) / (sizeof (nanomips_opcodes[0]))); From patchwork Fri Jul 17 10:38:56 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsing X-Patchwork-Id: 139393 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7DD534BA2E1F for ; Fri, 17 Jul 2026 10:42:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7DD534BA2E1F Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=SqUquCWL X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from va-2-26.ptr.blmpb.com (va-2-26.ptr.blmpb.com [209.127.231.26]) by sourceware.org (Postfix) with ESMTPS id 7EA644BA2E31 for ; Fri, 17 Jul 2026 10:39:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7EA644BA2E31 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7EA644BA2E31 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=209.127.231.26 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284775; cv=none; b=aLm+oHCMy35jkU76lIfa/bRGogJds59v3NmSU7tRB7fdq0F5sAakYFB9slQXxs5UztBCxyCR549ZbqiZJeIt2OrD+wjXzidt7MdEYUGZvq4yYoact4aw+bQRnPxjtUJ6cTUqTvNMuen9CaFZyZzz2XDEODeCP2FrMB7z7EiAHWc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284775; c=relaxed/simple; bh=+eVe4KP5mnIzQFW8CJDvXj/cKSJy/MD04pynfnwsf+E=; h=DKIM-Signature:Subject:Mime-Version:Message-Id:Date:To:From; b=CnGRdZtSbG4rIs1nq3cMaVJcycIDosGXoxTc3P1SrMxOMfU+kdIsJTZfPxrlJk9LB6tk2tgK3BprZG6+eHje0TrJ6NpGyYdd84tlPAH7kOspJV/UtKTOkjIb8+Cxk4CF23JfrbGZN8FyXz9Is/2Js+wj664ZxJeYlbTxsj2UtBI= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=SqUquCWL DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7EA644BA2E31 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1784284765; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=PRHRbLxAHuvODIWHwV0XA4X03t9RqPMFnwq4uB+u0ek=; b=SqUquCWLFCHK0647WzUSVydGExAmgzDs5pIGrok+IfIfg3jhAFzjo7H50WZoKRoNJXUugF cVksw6JG9FS6lk/TCo0zT9/g6f3SoxBCZdniXQe3C4Lz6u9KAzYsbtCmdPi1DdZGI9nB+r GecTqOFsFD6PUc6cUA5xHxVHeIl5ylhEkpGl9DHCwMb+sIAc3brDsC1s1wT0qGY87njXe2 op/Gb7zlzDszNFz5FZBIfmc9qKlWI1GnffgMde2KTnJS+osscpyQyzXHqBNSTeY8V8ZuUd 8sQGwbT+fKI2iTB9zuldieO88GMbiASQA38WoEloDvwc3qE2/mKFSs1MdWK5yA== X-Lms-Return-Path: References: <20260717103858.199743-1-lei.wang@oss.cipunited.com> Subject: [PATCH 4/6] Readelf for nanoMIPS. Mime-Version: 1.0 X-Original-From: Tsing In-Reply-To: <20260717103858.199743-1-lei.wang@oss.cipunited.com> Message-Id: <20260717103858.199743-5-lei.wang@oss.cipunited.com> Date: Fri, 17 Jul 2026 18:38:56 +0800 X-Mailer: git-send-email 2.39.5 Received: from B1.wok.cipunited.com ([123.52.17.40]) by smtp.feishu.cn with ESMTPS; Fri, 17 Jul 2026 18:39:23 +0800 To: From: "Tsing" X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, MSGID_FROM_MTA_HEADER, RCVD_IN_PBL, SPF_HELO_NONE, SPF_PASS, TXREP, UNWANTED_LANGUAGE_BODY shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: tsing binutils/ * readelf.c (guess_is_rela): Add EM_NANOMIPS. (get_machine_name): Likewise. (dump_relocations): Add support for nanomips relocations. (get_machine_flags): Add support for nanomips flags. (is_32bit_abs_reloc): Add R_NANOMIPS_32. (is_32bit_pcrel_reloc): Add R_NANOMIPS_PC32. (is_64bit_abs_reloc): Add R_NANOMIPS_64. (is_16bit_abs_reloc): Add R_NANOMIPS_UNSIGNED_16. (is_none_reloc): Add R_NANOMIPS_NONE. --- binutils/readelf.c | 422 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 422 insertions(+) diff --git a/binutils/readelf.c b/binutils/readelf.c index a52fe2b8d63..ec9f5ebb484 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -141,6 +141,7 @@ #include "elf/moxie.h" #include "elf/mt.h" #include "elf/msp430.h" +#include "elf/nanomips.h" #include "elf/nds32.h" #include "elf/nfp.h" #include "elf/nios2.h" @@ -1319,6 +1320,7 @@ guess_is_rela (unsigned int e_machine) case EM_MSP430: case EM_MSP430_OLD: case EM_MT: + case EM_NANOMIPS: case EM_NDS32: case EM_NIOS32: case EM_OR1K: @@ -2687,6 +2689,10 @@ dump_relocations (Filedata * filedata, case EM_AMDGPU: rtype = elf_amdgpu_reloc_type (type); break; + + case EM_NANOMIPS: + rtype = elf_nanomips_reloc_type (type); + break; } char *symbol_name = NULL; @@ -3812,6 +3818,7 @@ get_machine_name (unsigned e_machine) case EM_CEVA: return "CEVA Processor Architecture Family"; case EM_CEVA_X2: return "CEVA X2 Processor Family"; case EM_BPF: return "Linux BPF"; + case EM_NANOMIPS: return "nanoMIPS"; case EM_GRAPHCORE_IPU: return "Graphcore Intelligent Processing Unit"; case EM_IMG1: return "Imagination Technologies"; /* 250 */ @@ -5625,6 +5632,38 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine) out = decode_MSP430_machine_flags (out, e_flags); break; + case EM_NANOMIPS: + if (e_flags & EF_NANOMIPS_PIC) + strcat (buf, ", pic"); + + if (e_flags & EF_NANOMIPS_32BITMODE) + strcat (buf, ", 32bitmode"); + + switch ((e_flags & EF_NANOMIPS_MACH)) + { + default: strcat (buf, _(", unknown CPU")); break; + } + + switch ((e_flags & EF_NANOMIPS_ABI)) + { + case E_NANOMIPS_ABI_P32: strcat (buf, ", p32"); break; + case E_NANOMIPS_ABI_P64: strcat (buf, ", p64"); break; + case 0: + /* We simply ignore the field in this case to avoid confusion: + MIPS ELF does not specify EF_MIPS_ABI, it is a GNU extension. + This means it is likely to be an o32 file, but not for + sure. */ + break; + default: strcat (buf, _(", unknown ABI")); break; + } + + switch ((e_flags & EF_NANOMIPS_ARCH)) + { + case E_NANOMIPS_ARCH_32R6: strcat (buf, ", nanomips32r6"); break; + case E_NANOMIPS_ARCH_64R6: strcat (buf, ", nanomips64r6"); break; + default: strcat (buf, _(", unknown ISA")); break; + } + case EM_Z80: out = decode_Z80_machine_flags (out, e_flags); break; @@ -16077,6 +16116,35 @@ target_specific_reloc_handling (Filedata *filedata, } break; } + case EM_NANOMIPS: + { + static Elf_Internal_Sym * saved_sym = NULL; + + if (reloc == NULL) + { + saved_sym = NULL; + return true; + } + + if (reloc_type == 3) + { + saved_sym = symtab + sym_index; + bfd_vma value; + + if (sym_index >= num_syms) + error (_("nanomips reloc contains invalid symbol index %lu\n"), + sym_index); + else + { + value = reloc->r_addend - saved_sym->st_value; + reloc++; + reloc->r_addend += value; + return true; + } + break; + } + break; + } } return false; @@ -16210,6 +16278,8 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) return reloc_type == 1; /* R_MSP430_32 or R_MSP320_ABS32. */ case EM_MT: return reloc_type == 2; /* R_MT_32. */ + case EM_NANOMIPS: + return reloc_type == 1; /* R_NANOMIPS_32. */ case EM_NDS32: return reloc_type == 20; /* R_NDS32_32_RELA. */ case EM_ALTERA_NIOS2: @@ -16332,6 +16402,8 @@ is_32bit_pcrel_reloc (Filedata * filedata, unsigned int reloc_type) return reloc_type == 99; /* R_LARCH_32_PCREL. */ case EM_MICROBLAZE: return reloc_type == 2; /* R_MICROBLAZE_32_PCREL. */ + case EM_NANOMIPS: + return reloc_type == 248; /* R_NANOMIPS_PC32. */ case EM_OR1K: return reloc_type == 9; /* R_OR1K_32_PCREL. */ case EM_PARISC: @@ -16421,6 +16493,8 @@ is_64bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) return reloc_type == 1; /* R_TILEGX_64. */ case EM_MIPS: return reloc_type == 18; /* R_MIPS_64. */ + case EM_NANOMIPS: + return reloc_type == 2; /* R_NANOMIPS_64. */ case EM_KVX: return reloc_type == 3; /* R_KVX_64 */ default: @@ -16534,6 +16608,8 @@ is_16bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) /* Fall through. */ case EM_MSP430_OLD: return reloc_type == 5; /* R_MSP430_16_BYTE. */ + case EM_NANOMIPS: + return reloc_type == 7; /* R_NANOMIPS_UNSIGNED_16 */ case EM_NDS32: return reloc_type == 19; /* R_NDS32_16_RELA. */ case EM_ALTERA_NIOS2: @@ -16818,6 +16894,7 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type) case EM_X86_64: /* R_X86_64_NONE. */ case EM_Z80: /* R_Z80_NONE. */ case EM_WEBASSEMBLY: /* R_WASM32_NONE. */ + case EM_NANOMIPS: /* R_NANOMIPS_NONE. */ return reloc_type == 0; case EM_AARCH64: @@ -19367,6 +19444,23 @@ display_mips_gnu_attribute (const unsigned char * p, return display_tag_value (tag & 1, p, end); } +static unsigned char * +display_nanomips_gnu_attribute (unsigned char * p, + unsigned int tag, + const unsigned char * const end) +{ + if (tag == Tag_GNU_NANOMIPS_ABI_FP) + { + int val; + + READ_ULEB (val, p, end); + printf (" Tag_GNU_NANOMIPS_ABI_FP: "); + return p; + } + + return display_tag_value (tag & 1, p, end); +} + static const unsigned char * display_tic6x_attribute (const unsigned char * p, const unsigned char * const end) @@ -21826,6 +21920,331 @@ process_got_section_contents (Filedata * filedata) return res; } +static void +print_nanomips_ases (unsigned int mask) +{ + if (mask & NANOMIPS_ASE_MT) + fputs ("\n\tMT ASE", stdout); + if (mask & NANOMIPS_ASE_VIRT) + fputs ("\n\tVZ ASE", stdout); + if ((mask & NANOMIPS_ASE_xNMS) == 0) + fputs ("\n\tnanoMIPS subset", stdout); + else if (mask == 0) + fprintf (stdout, "\n\t%s", _("None")); + else if ((mask & ~NANOMIPS_ASE_MASK) != 0) + fprintf (stdout, "\n\t%s (%x)", _("Unknown"), mask & ~NANOMIPS_ASE_MASK); +} + +static void +print_nanomips_isa_ext (unsigned int isa_ext) +{ + switch (isa_ext) + { + case 0: + fputs (_("None"), stdout); + break; + default: + fprintf (stdout, "%s (%d)", _("Unknown"), isa_ext); + } +} + +static int +get_nanomips_reg_size (int reg_size) +{ + return (get_mips_reg_size (reg_size)); +} + +/* DATA points to the contents of a nanoMIPS GOT that starts at VMA PLTGOT. + Print the Address, Access and Initial fields of an entry at VMA ADDR + and return the VMA of the next entry, or -1 if there was a problem. + Does not read from DATA_END or beyond. */ + +static bfd_vma +print_nanomips_got_entry (unsigned char * data, bfd_vma pltgot, bfd_vma addr, + unsigned char * data_end) +{ + printf (" "); + print_vma (addr, LONG_HEX); + printf (" %8d(gp) ", (int) (addr - pltgot)); + + if (data == NULL) + printf ("%*s", is_32bit_elf ? 8 : 16, _("")); + else + { + bfd_vma entry; + unsigned char * from = data + addr - pltgot; + + if (from + (is_32bit_elf ? 4 : 8) > data_end) + { + warn (_("nanoMIPS GOT entry extends beyond the end of available data\n")); + printf ("%*s", is_32bit_elf ? 8 : 16, _("")); + return (bfd_vma) -1; + } + else + { + entry = byte_get (data + addr - pltgot, is_32bit_elf ? 4 : 8); + print_vma (entry, LONG_HEX); + } + } + return addr + (is_32bit_elf ? 4 : 8); +} + +/* Comparison function to sort relocs by increasing offsets. */ + +static /* signed */ int +relcmp (const void *p, const void *q) +{ + Elf_Internal_Rela *sp = (Elf_Internal_Rela *) p; + Elf_Internal_Rela *sq = (Elf_Internal_Rela *) q; + + return (sp->r_offset > sq->r_offset + ? 1 + : (sp->r_offset < sq->r_offset ? -1 : 0)); +} + +/* Pretty-print the nanoMIPS GOT. */ + +static bool +print_nanomips_got (Filedata * filedata) +{ + Elf_Internal_Shdr *sect = NULL; + bfd_vma pltgot = 0; + unsigned char *data_end; + unsigned char *data; + bfd_vma ent = 0; + bfd_vma end; + int addr_size; + int sym_width; + struct { + Elf_Internal_Rela * rels; + unsigned long relsize; + unsigned rindex; + } rtable[3]; + int i; + enum {REL=0, RELA=1, JMPREL=2}; + + /* Clear the relocs. */ + memset (rtable, 0, sizeof (rtable)); + + /* Fetch the GOT. */ + sect = find_section (filedata, ".got"); + + if (sect == NULL) + return true; + + /* This is overly complicated in order to handle dynamic relocations as + either REL or RELA and to handle the case where jump relocations are + embedded within the dynamic relocations section. */ + if (filedata->dynamic_info[DT_REL] != 0) + { + if (!slurp_rel_relocs (filedata, + offset_from_vma (filedata, filedata->dynamic_info[DT_REL], + filedata->dynamic_info[DT_RELENT]), + filedata->dynamic_info[DT_RELSZ], + &rtable[REL].rels, &rtable[REL].relsize)) + return false; + /* Sort for easy lookup. */ + qsort (rtable[REL].rels, rtable[REL].relsize, + sizeof (Elf_Internal_Rela), relcmp); + } + if (filedata->dynamic_info[DT_RELA] != 0) + { + if (!slurp_rel_relocs (filedata, + offset_from_vma (filedata, filedata->dynamic_info[DT_RELA], + filedata->dynamic_info[DT_RELAENT]), + filedata->dynamic_info[DT_RELASZ], + &rtable[RELA].rels, &rtable[RELA].relsize)) + return false; + /* Sort for easy lookup. */ + qsort (rtable[RELA].rels, rtable[RELA].relsize, sizeof (Elf_Internal_Rela), relcmp); + } + if (filedata->dynamic_info[DT_JMPREL] != 0) + { + int rent = ((filedata->dynamic_info[DT_PLTREL] == DT_REL) + ? filedata->dynamic_info[DT_RELENT] : filedata->dynamic_info[DT_RELAENT]); + /* If jump relocations are embedded within regular dynamic relocations, + we don't need to read them again. They have already been read above. */ + if ((filedata->dynamic_info[DT_PLTREL] == DT_REL + && (filedata->dynamic_info[DT_JMPREL] < filedata->dynamic_info[DT_REL] + || filedata->dynamic_info[DT_JMPREL] >= filedata->dynamic_info[DT_REL] + filedata->dynamic_info[DT_RELSZ])) + || (filedata->dynamic_info[DT_PLTREL] == DT_RELA + && (filedata->dynamic_info[DT_JMPREL] < filedata->dynamic_info[DT_RELA] + || filedata->dynamic_info[DT_JMPREL] >= filedata->dynamic_info[DT_RELA] + filedata->dynamic_info[DT_RELASZ]))) + { + if (!slurp_rel_relocs (filedata, + offset_from_vma (filedata, filedata->dynamic_info[DT_JMPREL], rent), + filedata->dynamic_info[DT_PLTRELSZ], + &rtable[JMPREL].rels, &rtable[JMPREL].relsize)) + return false; + /* Sort for easy lookup. */ + qsort (rtable[JMPREL].rels, rtable[JMPREL].relsize, sizeof (Elf_Internal_Rela), relcmp); + } + } + /* Temporary hack. Remove when the linker generate DT_JMPREL. */ + else if (find_section (filedata, ".rel.nanoMIPS.stubs") != NULL) + { + Elf_Internal_Shdr *jumpsect = find_section (filedata, ".rel.nanoMIPS.stubs"); + if (!slurp_rel_relocs (filedata, + offset_from_vma (filedata, jumpsect->sh_addr, + filedata->dynamic_info[DT_RELENT]), + jumpsect->sh_size, + &rtable[JMPREL].rels, &rtable[JMPREL].relsize)) + return false; + } + + pltgot = sect->sh_addr; + + /* Find relocations corresponding to the beginning of the GOT. */ + for (i = REL; i <= JMPREL; i++) + while (rtable[i].rindex < rtable[i].relsize + && rtable[i].rels[rtable[i].rindex].r_offset < pltgot) + rtable[i].rindex++; + + ent = pltgot; + addr_size = (is_32bit_elf ? 4 : 8); + /* Available screen width for symbols is whatever is left over + after everything else, including column-separating whitespaces. */ + sym_width = ((is_32bit_elf ? 80 : 160) - 32 - addr_size * 4); + end = pltgot + sect->sh_size; + + data = (unsigned char *) get_data (NULL, filedata, sect->sh_offset, + end - pltgot, 1, + _("Global Offset Table data")); + data_end = data + (end - pltgot); + + printf (_("\nGOT:\n")); + printf (_(" GP value: ")); + print_vma (ent, LONG_HEX); + printf ("\n\n"); + + /* In a dynamic binary GOT[0] is reserved for the dynamic + loader to store the lazy resolver pointer, however in + a static binary it may well have been omitted and GOT + reduced to a table of addresses. */ + if (data + && data + ent - pltgot + addr_size <= data_end + && byte_get (data + ent - pltgot, addr_size) == 0) + { + printf (_(" Reserved entries:\n")); + printf (_(" %*s %*s %*s Purpose\n"), + (- addr_size * 2) + 1, _("Address"), 12, _("Access"), + (- addr_size * 2) + 1, _("Initial")); + ent = print_nanomips_got_entry (data, pltgot, ent, data_end); + printf (_(" Lazy stub resolver\n")); + if (ent == (bfd_vma) -1) + goto sgot_print_fail; + + if (ent == (bfd_vma) -1) + goto sgot_print_fail; + + /* Check for the MSB of GOT[1] being set, identifying a + GNU object. This entry will be used by some runtime + loaders, to store the module pointer. Otherwise this + is an ordinary local entry. */ + if (data + && data + ent - pltgot + addr_size <= data_end + && (byte_get (data + ent - pltgot, addr_size) + >> (addr_size * 8 - 1)) != 0) + { + printf ("\n"); + ent = print_nanomips_got_entry (data, pltgot, ent, data_end); + printf (_(" Module pointer\n")); + if (ent == (bfd_vma) -1) + goto sgot_print_fail; + } + printf ("\n"); + } + + if (ent < end) + { + printf (_(" Entries:\n")); + printf (_(" %*s %*s %*s %*s Name\n"), + (- addr_size * 2) + 1, _("Address"), 12, _("Access"), + (- addr_size * 2) + 1, _("Value"), -9, _("Type")); + } + + while (ent < end) + { + Elf_Internal_Rela *rel = NULL; + bfd_vma next_ent = print_nanomips_got_entry (data, pltgot, + ent, data_end); + if (next_ent == (bfd_vma) -1) + { + ent = (bfd_vma) -1; + goto sgot_print_fail; + } + + /* Scan all relocations for a match against this GOT slot. */ + for (i = REL; i <= JMPREL; i++) + { + while (rel == NULL && rtable[i].rindex < rtable[i].relsize) + { + if (rtable[i].rels[rtable[i].rindex].r_offset == ent) + rel = &rtable[i].rels[rtable[i].rindex]; + if (rtable[i].rels[rtable[i].rindex].r_offset >= ent) + break; + rtable[i].rindex ++; + } + } + + if (rel != NULL) + { + Elf_Internal_Sym * psym = 0; + + switch (get_reloc_type (filedata, rel->r_info)) + { + case 11: /* R_NANOMIPS_JUMP_SLOT. */ + printf (" %*s ", -10, "Lazy-stub"); break; + case 12: /* R_NANOMIPS_IRELATIVE. */ + printf (" %*s ", -10, "Indirect"); break; + case 10: /* R_NANOMIPS_GLOBAL. */ + case 1: /* R_NANOMIPS_32. */ + case 2: /* R_NANOMIPS_64. */ + printf (" %*s ", -10, "Global"); break; + case 9: /* R_NANOMIPS_RELATIVE. */ + printf (" %*s ", -10, "Local"); break; + default: + break; + } + + if (filedata->dynamic_symbols) + { + psym = (filedata->dynamic_symbols + get_reloc_symindex (rel->r_info)); + + if (valid_dynamic_name (filedata, psym->st_name)) + print_symbol_name (sym_width, get_dynamic_name (filedata, psym->st_name)); + else + printf (_(""), psym->st_name); + } + } + + ent = next_ent; + printf ("\n"); + } + printf ("\n"); + + sgot_print_fail: + if (data) + free (data); + + for (i = REL; i <= JMPREL; i++) + if (rtable[i].rels) + free (rtable[i].rels); + + return (ent != (bfd_vma) -1);; +} + + +static bool +process_nanomips_specific (Filedata * filedata) +{ + process_attributes (filedata, NULL, SHT_GNU_ATTRIBUTES, NULL, + display_nanomips_gnu_attribute); + + /* Pretty-print the GOT. */ + return print_nanomips_got (filedata); +} + static bool process_gnu_liblist (Filedata * filedata) { @@ -24759,6 +25178,9 @@ process_arch_specific (Filedata * filedata) display_riscv_attribute, display_generic_attribute); + case EM_NANOMIPS: + return process_nanomips_specific (filedata); + case EM_NDS32: return process_nds32_specific (filedata); From patchwork Fri Jul 17 10:38:57 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsing X-Patchwork-Id: 139394 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E48664BA2E04 for ; Fri, 17 Jul 2026 10:43:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E48664BA2E04 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=pNqCgsXx X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from va-2-28.ptr.blmpb.com (va-2-28.ptr.blmpb.com [209.127.231.28]) by sourceware.org (Postfix) with ESMTPS id 3F9924BA2E14 for ; Fri, 17 Jul 2026 10:39:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3F9924BA2E14 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3F9924BA2E14 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=209.127.231.28 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284772; cv=none; b=CyArh97CMPEjtlwoFMNiojravabOFO/sR/E3/F9pDqWWAB9vzQXVpkwHuHTGT3RLNQMWdKnzk0u0j5BEvkRV87AfzcjLoi54u9nbjuetKjZWnRkHBUIUeqJvBX/1ohyd0SsoTNy6kSlb8rsp/T7B6LPKu+VlHz9bR/kiu+ukVFU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284772; c=relaxed/simple; bh=b2lQYRIEotc4zWIcqbv1kYtNSUf5aNEvihXUMaK4aoA=; h=DKIM-Signature:Subject:To:Date:Message-Id:Mime-Version:From; b=LxKxhyd6i0fA6lm3zeGH/puK1jpswjfKwDfAhWhdn/VJan4zyaDbX23apVs9G0INea1JtIN3Ev23DnjgRpzNk19798Y2uhBmAQFbmwCcLQpAvNTmgN+3h/k5BDWXYjW+WAAsP6Gl2DNjz5MNJWWHRLMcMVeqJWFkGtidGIblFA0= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=pNqCgsXx DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3F9924BA2E14 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1784284767; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=lnpyupmONr45PulVhtrV8BYQYCouK2obgcuREym2++A=; b=pNqCgsXxYBhpIZmA4r+crn9cMm9XBsjkJLdvv7BpoYTwr2zontafi6GMT/zyvU98ZPTH1u oNgB1xM8K3gOOlq8YGqQoxw1rTGvUmhqZ+Pf27W3YDETn3UXyx+TxN2u3cJFxnx5f3zTNC 8q75d6rGlvF+/MFiIjT2GJI9UbF30c5SyZv/hRE5j+jka0wFxSweuEM1U7FdtIb/WL67WN nOqMry32m96CPqrP+pPrad7kHMh7QUVp8NPy8+PjOeLwm9ekKDtcbPmsufF3P/7sgXnwOo kHZOayYUWGOAe3wmuGkq/qePQZcGQegmRvINmvTe0uXxz3hOgYo4Ys9FrzVR5A== X-Mailer: git-send-email 2.39.5 Subject: [PATCH 5/6] Add nanoMIPS documentation. References: <20260717103858.199743-1-lei.wang@oss.cipunited.com> X-Original-From: Tsing To: Date: Fri, 17 Jul 2026 18:38:57 +0800 Message-Id: <20260717103858.199743-6-lei.wang@oss.cipunited.com> Mime-Version: 1.0 X-Lms-Return-Path: From: "Tsing" Received: from B1.wok.cipunited.com ([123.52.17.40]) by smtp.feishu.cn with ESMTPS; Fri, 17 Jul 2026 18:39:24 +0800 In-Reply-To: <20260717103858.199743-1-lei.wang@oss.cipunited.com> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, LOTS_OF_MONEY, MSGID_FROM_MTA_HEADER, RCVD_IN_PBL, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: tsing binutils/ * doc/binutils.texi: Add entries for nanomips. gas/ * doc/all.texi: Add entries for nanomips. * doc/as.texi: Likewise. * doc/c-nanomips-aliases.texi: New file. * doc/c-nanomips-macros.texi: New file. * doc/c-nanomips.texi: New file. ld/ * gen-doc.texi: Add entries for naonmips. * ld.texi: Likewise. --- binutils/doc/binutils.texi | 7 + gas/doc/all.texi | 1 + gas/doc/as.texi | 189 ++ gas/doc/c-nanomips-aliases.texi | 1527 +++++++++++++++ gas/doc/c-nanomips-macros.texi | 3136 +++++++++++++++++++++++++++++++ gas/doc/c-nanomips.texi | 1499 +++++++++++++++ ld/gen-doc.texi | 1 + ld/ld.texi | 37 + 8 files changed, 6397 insertions(+) create mode 100644 gas/doc/c-nanomips-aliases.texi create mode 100644 gas/doc/c-nanomips-macros.texi create mode 100644 gas/doc/c-nanomips.texi diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi index 198ae8244ef..7325743bade 100644 --- a/binutils/doc/binutils.texi +++ b/binutils/doc/binutils.texi @@ -2857,6 +2857,13 @@ rather than names, for the selected types of registers. You can list the available values of @var{ABI} and @var{ARCH} using the @option{--help} option. +For nanoMIPS, all of the options specified above for the MIPS +architecture are supported. The available values of @var{ABI} +and @var{ARCH} are different from MIPS and can be listed with +the @option{--help} option. In addition, the @option{-Mshow-arch-insn} +option prints extended mnemonics in disassembly, including format +suffixes, as used in the architecture reference manual. + For VAX, you can specify function entry addresses with @option{-M entry:0xf00ba}. You can use this multiple times to properly disassemble VAX binary files that don't contain symbol tables (like diff --git a/gas/doc/all.texi b/gas/doc/all.texi index 83418951b13..0501512edb4 100644 --- a/gas/doc/all.texi +++ b/gas/doc/all.texi @@ -57,6 +57,7 @@ @set MMIX @set MS1 @set MSP430 +@set NANOMIPS @set NDS32 @set NS32K @set OPENRISC diff --git a/gas/doc/as.texi b/gas/doc/as.texi index 5d7772d62d3..9dbc7a453e1 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -500,6 +500,29 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{--no-expand}] [@b{--no-merge-gregs}] [@b{-x}] [@b{--linker-allocated-gregs}] @end ifset +@ifset NANOMIPS + +@emph{Target nanoMIPS options:} + [@b{-EL}] [@b{-EB}] + [@b{-g}[@var{debug level}]] [@b{-G} @var{num}] + [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] + [@b{-m32}] [@b{-m64}] + [@b{-mcmodel=@var{MODEL}}] + [@b{-mpic}] [@b{-mno-pic}] + [@b{-mPIC}] [@b{-mno-PIC}] + [@b{-mpid}] [@b{-mno-pid}] + [@b{-mpcrel}] [@b{-mno-pcrel}] + [@b{-minsn32}] [@b{-mno-insn32}] + [@b{-mmt}] [@b{-mno-mt}] + [@b{-mvirt}] [@b{-mno-virt}] + [@b{-mhard-float}] [@b{-msoft-float}] + [@b{-msingle-float}] [@b{-mdouble-float}] + [@b{-construct-floats}] [@b{-no-construct-floats}] + [@b{-mbalc-stubs}] [@b{-mno-balc-stubs}] + [@b{-mlegacyregs}] [@b{-mno-legacyregs}] + [@b{--linkrelax}] + [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}] +@end ifset @ifset NDS32 @emph{Target NDS32 options:} @@ -1889,6 +1912,146 @@ Meta processor. See the info pages for documentation of the MMIX-specific options. @end ifset +@ifset NANOMIPS +The following options are available when @value{AS} is configured for +a nanoMIPS processor. + +@table @gcctabopt +@item -G @var{num} +This option sets the largest size of an object that can be referenced +implicitly with the @code{gp} register. The default value is 8. + +@cindex nanoMIPS endianness +@cindex endianness, nanoMIPS +@cindex big endian output, nanoMIPS +@item -EB +Generate ``big endian'' format output. + +@cindex little endian output, nanoMIPS +@item -EL +Generate ``little endian'' format output. + +@cindex nanoMIPS ISA +@item -march=@var{cpu} +Generate code for a particular nanoMIPS CPU or ISA level. The following +ISA levels are recognized: @code{32r6}, @code{32r6s}, @code{64r6}. The following CPUs are +recognized: @code{nms1}, @code{i7200}. + +@item -mtune=@var{cpu} +Schedule and tune for a particular nanoMIPS CPU. + +@item -m32 +@itemx -32 +Generate code for the P32 ABI. + +@item -m64 +@itemx -64 +Generate code for the P64 ABI. + +@item -mcmodel=@var{mmodel} +Generate code for a particular C Memory Model. The following memory models +are supported: @code{auto}, @code{medium}, @code{large} + +@item -mpic +@itemx -mno-pic +Generate medium model SVR4-style PIC. This option tells the assembler +to generate SVR4-style position-independent macro expansions. It also +tells the assembler to mark the output file as PIC. +@samp{-mno-pic} turns off this option. + +@item -mPIC +@itemx -mno-PIC +Generate large model SVR4-style PIC. This option tells the assembler +to generate SVR4-style position-independent macro expansions. It also +tells the assembler to mark the output file as PIC. +@samp{-mno-PIC} turns off this option. + +@item -mpid +@itemx -mno-pid +Generate position independent data. This option tells the assembler to +generate data sections that can be repositioned independent of code placement. +It also tells the assembler to mark the output file as PID. +@samp{-mno-pid} turns off this option. + +@item -mpcrel +@itemx -mno-pcrel +Generate PC-relative expansions. This option tells the assembler to +avoid the use of absolute addresses for symbols even when those +addresses may be known at link time. It also tells the assembler to +mark the output file as purely PC-relative. +@samp{-mno-pcrel} turns off this option. + +@item -minsn32 +@itemx -mno-insn32 +Only use 32-bit instruction encodings when generating code for the +nanoMIPS processor. This option inhibits the use of any 16-bit +instructions. This is equivalent to putting @code{.set insn32} at +the start of the assembly file. @samp{-mno-insn32} turns off this +option. This is equivalent to putting @code{.set noinsn32} at the +start of the assembly file. By default @samp{-mno-insn32} is +selected, allowing all instructions to be used. + +@item -mmt +@itemx -mno-mt +Generate code for the MT Application Specific Extension. +This tells the assembler to accept MT instructions. +@samp{-mno-mt} turns off this option. + +@item -mvirt +@itemx -mno-virt +Generate code for the Virtualization Application Specific Extension. +This tells the assembler to accept virtualization instructions. +@samp{-mno-virt} turns off this option. + +@item -msoft-float +@itemx -mhard-float +Disable or enable floating-point instructions. Note that by default +floating-point instructions are always allowed even with CPU targets +that don't have support for these instructions. + +@item -msingle-float +@itemx -mdouble-float +Disable or enable double-precision floating-point operations. Note +that by default double-precision floating-point operations are always +allowed even with CPU targets that don't have support for these +operations. + +@item --construct-floats +@itemx --no-construct-floats +The @samp{--no-construct-floats} option disables the construction of +double width floating point constants by loading the two halves of the +value into the two single width floating point registers that make up +the double width register. By default @samp{--construct-floats} is +selected, allowing construction of these floating point constants. + +@item -mbalc-stubs +@itemx -mno-balc-stubs +Control the BALC stub optimization. The @samp{-mbalc-stubs} option aggregates +multiple out-of-range 16-bit branch-and-link instructions to use a +non-conditional branch-stub with 32-bit range. This gives better code +compression, but can have a negative effect on performance. By default, +@samp{-mno-balc-stubs} is selected, disabling this optimization. + +@item -mlegacyregs +@itemx -mno-legacyregs +Allow the use of legacy MIPS style numeric register formats in assembly. This +option is disabled by default. + +@item --linkrelax +Enable support for link-time relaxations. + +@item --trap +@itemx --no-trap +@itemx --break +@itemx --no-break +Control how to deal with multiplication overflow and division by zero. +@samp{--trap} or @samp{--no-break} (which are synonyms) take a trap exception; +@samp{--break} or @samp{--no-trap} (also synonyms, and the default) take a +break exception. + +@end table +@end ifset + @ifset NDS32 @ifclear man @@ -8162,6 +8325,25 @@ will be: @end table +@subsection nanoMIPS Attributes + +@table @r +@item Tag_nanoGNU_MIPS_ABI_FP (4) +The floating-point ABI used by this object file. The value will be: + +@itemize @bullet +@item +0 for files not affected by the floating-point ABI. +@item +1 for files using the hardware floating-point ABI with a standard +double-precision FPU. +@item +2 for files using the hardware floating-point ABI with a single-precision FPU. +@item +3 for files using the software floating-point ABI. +@end itemize +@end table + @subsection PowerPC Attributes @table @r @@ -8363,6 +8545,9 @@ subject, see the hardware manufacturer's manual. @ifset MSP430 * MSP430-Dependent:: MSP430 Dependent Features @end ifset +@ifset NANOMIPS +* nanoMIPS-Dependent:: nanoMIPS Dependent Features +@end ifset @ifset NDS32 * NDS32-Dependent:: Andes NDS32 Dependent Features @end ifset @@ -8599,6 +8784,10 @@ family. @include c-msp430.texi @end ifset +@ifset NANOMIPS +@include c-nanomips.texi +@end ifset + @ifset NDS32 @include c-nds32.texi @end ifset diff --git a/gas/doc/c-nanomips-aliases.texi b/gas/doc/c-nanomips-aliases.texi new file mode 100644 index 00000000000..71e0308ae00 --- /dev/null +++ b/gas/doc/c-nanomips-aliases.texi @@ -0,0 +1,1527 @@ +@c Copyright(C) 2018-2026 Free Software Foundation, CIP United Inc. +@c Contributed by MIPS Tech LLC. +@c Written by Faraz Shahbazker +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@node nanoMIPS Aliases +@section 1:1 Instruction Aliases + +The nanoMIPS assembler allows multiple mnemonics to select the same +target instruction. These aliases are provided as a convenience to the +user, so that assembly programs can be written without paying too much +attention to type and order of operands, specially where the ISA has +eccentric restrictions. Following is a complete list of the various 1:1 +aliases supported: + +@itemize +@item Disassembly = N indicates that disassembly will show the target instruction instead of the alias form. +@item Size = 16/32 indicates that both 16 and 32-bit aliases are available. +@end itemize + +@multitable @columnfractions 0.25 0.25 0.3 0.05 0.1 +@headitem Alias@tab Condition @tab Target@tab Dis@tab Size +@item @tab @tab @tab @tab +@item +@verbatim +Implicit operand forms +@end verbatim +@tab @tab @tab @tab + +@item +@verbatim +break +@end verbatim + +@tab @tab @verbatim +break 0 +@end verbatim + +@tab Y @tab 16/32 +@item +@verbatim +sdbbp +@end verbatim + +@tab @tab @verbatim +sdbbp 0 +@end verbatim + +@tab Y @tab 16/32 +@item +@verbatim +mfc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mfc0 rt,crs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mfc0 rt,crs,sel +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfhc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mfhc0 rt,crs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfhc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mfhc0 rt,crs,sel +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mtc0 rt,crs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mtc0 rt,crs,sel +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mthc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mthc0 rt,crs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mthc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mthc0 rt,crs,sel +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +rddsp rt +@end verbatim + +@tab @tab @verbatim +rddsp rt,31 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +rdhwr rt,hrs +@end verbatim + +@tab @tab @verbatim +rdhwr rt,hrs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +tne rt,rs +@end verbatim + +@tab @tab @verbatim +tne rt,rs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +teq rt,rs +@end verbatim + +@tab @tab @verbatim +teq rt,rs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +syscall +@end verbatim + +@tab @tab @verbatim +syscall 0 +@end verbatim + +@tab Y @tab 16/32 +@item +@verbatim +wait +@end verbatim + +@tab @tab @verbatim +wait 0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +wrdsp rt +@end verbatim + +@tab @tab @verbatim +wrdsp rt,31 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +yield rs +@end verbatim + +@tab @tab @verbatim +yield $zero, rs +@end verbatim + +@tab Y @tab 32 +@item @tab @tab @tab @tab +@item +@verbatim +General aliases +@end verbatim + +@tab @tab @tab @tab +@item +@verbatim +jrc rs +@end verbatim + +@tab @tab @verbatim +jalrc $zero,rs +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +jalrc $ra,rs +@end verbatim + +@tab @tab @verbatim +jalrc rs +@end verbatim + +@tab N @tab 16 +@item +@verbatim +jalrc rs +@end verbatim + +@tab @tab @verbatim +jalrc $ra,rs +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +li rt,imm +@end verbatim + +@tab 0 <= imm < 65535 @tab @verbatim +addiu rt,rt,imm +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +li rt,imm +@end verbatim + +@tab -4095 <= imm <= 0 @tab @verbatim +addiu[neg] rt,rt,imm +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +li rt,imm +@end verbatim + +@tab imm % 4096 == 0 @tab @verbatim +lui rt,(imm >> 12) +@end verbatim + +@tab N @tab 32 +@item +@verbatim +li rt,0 +@end verbatim + +@tab @tab @verbatim +move rt,$zero +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +addiu rt,rt,imm +@end verbatim + +@tab @tab @verbatim +addiu rt,imm +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +addiu.b rt,gp,ofst +@end verbatim + +@tab 0 <= offset < 2^18 @tab @verbatim +addiu[gp.b] rt,gp,ofst +@end verbatim + +@tab N @tab 32 +@item +@verbatim +addiu.w rt,gp,ofst +@end verbatim + +@tab 0 <= offset < 2^21 +&& offset % 4 == 0 @tab @verbatim +addiu[gp.w] rt,gp,ofst +@end verbatim + +@tab N @tab 32 +@item +@verbatim +align rd,rs,rt,bp +@end verbatim + +@tab bp == 0 @tab @verbatim +move rd,rs +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +align rd,rs,rt,bp +@end verbatim + +@tab bp <> 0 @tab @verbatim +extw rd,rs,rt,(4-bp)<<3 +@end verbatim + +@tab N @tab 32 +@item +@verbatim +and rt,rt,rs +@end verbatim + +@tab @tab @verbatim +and rt,rs +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +and rt,rs,rt +@end verbatim + +@tab @tab @verbatim +and rt,rs +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +beqzc rt,label +@end verbatim + +@tab @tab @verbatim +beqc $zero,rt,label +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +beqc rt,$zero,label +@end verbatim + +@tab @tab @verbatim +beqzc rt,label +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +beqc $zero,rt,label +@end verbatim + +@tab @tab @verbatim +beqzc rt,label +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +beqc rs,rt,label +@end verbatim + +@tab rs > rt @* +&& non-NMS @tab @verbatim +beqc rt,rs,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +blezc rt,label +@end verbatim + +@tab @tab @verbatim +bgec $zero,rt,label +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +bgezc rt,label +@end verbatim + +@tab @tab @verbatim +bgec rt,$zero,label +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +bgtzc rt,label +@end verbatim + +@tab @tab @verbatim +bltc $zero,rt,label +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +bltzc rt,label +@end verbatim + +@tab @tab @verbatim +bltc rt,$zero,label +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +bnezc rt,label +@end verbatim + +@tab @tab @verbatim +bnec $zero,rt,label +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +bnec rt,$zero,label +@end verbatim + +@tab @tab @verbatim +bnezc rt,label +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +bnec $zero,rt,label +@end verbatim + +@tab @tab @verbatim +bnezc rt,label +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +bnec rs,rt,label +@end verbatim + +@tab rs <= rt @* +&& non-NMS @tab @verbatim +bnec rt,rs,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +cftc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,1,3,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +cftc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,1,3,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +cftc2 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,1,5 0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +cttc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,1,3,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +cttc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,1,3,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +cttc2 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,1,5,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +di +@end verbatim + +@tab @tab @verbatim +di $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +dmt +@end verbatim + +@tab @tab @verbatim +dmt $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +dvpe +@end verbatim + +@tab @tab @verbatim +dvpe $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +dvp +@end verbatim + +@tab @tab @verbatim +dvp $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +ei +@end verbatim + +@tab @tab @verbatim +ei $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +emt +@end verbatim + +@tab @tab @verbatim +emt $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +evpe +@end verbatim + +@tab @tab @verbatim +evpe $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +evp +@end verbatim + +@tab @tab @verbatim +evp $zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +jrc.hb rs +@end verbatim + +@tab @tab @verbatim +jalrc.hb $zero,rs +@end verbatim + +@tab N @tab 32 +@item +@verbatim +jalrc.hb rs +@end verbatim + +@tab @tab @verbatim +jalrc.hb $zero,rs +@end verbatim + +@tab N @tab 32 +@item +@verbatim +mftc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,0,0,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftc0 rt,crs,sel +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,0,sel,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,0,sel,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfthc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,0,0,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfthc0 rt,crs,sel +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,0,sel,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfthc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,0,sel,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,1,2,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftc2 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,1,4,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftdsp rt +@end verbatim + +@tab @tab @verbatim +mftr rt,$16,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftgpr rt,rs +@end verbatim + +@tab @tab @verbatim +mftr rt,rs,1,0,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfthc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,1,2,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfthc2 rt,crs +@end verbatim + +@tab @tab @verbatim +mftr rt,crs,1,4,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfthi rt +@end verbatim + +@tab @tab @verbatim +mftr rt,$1,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mfthi rt,acc +@end verbatim + +@tab @tab @verbatim +rs = (acc * 4) + 1 +mftr rt,rs,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftlo rt +@end verbatim + +@tab @tab @verbatim +mftr rt,$0,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mftlo rt,acc +@end verbatim + +@tab @tab @verbatim +rs = (acc * 4) +mftr rt,rs,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +move rd,rs +@end verbatim + +@tab @tab @verbatim +or rd,rs,$zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +move rd,rs +@end verbatim + +@tab @tab @verbatim +addu rd,rs,$zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,0,0,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttc0 rt,crs,sel +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,0,sel,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,0,sel,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtthc0 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,0,0,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtthc0 rt,crs,sel +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,0,sel,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtthc0 rt,crsname[,sel] +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,0,sel,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,1,2,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttc2 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,1,4,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttdsp rt +@end verbatim + +@tab @tab @verbatim +mttr rt,$16,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttgpr rt,rs +@end verbatim + +@tab @tab @verbatim +mttr rt,rs,1,0,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtthc1 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,1,2,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtthc2 rt,crs +@end verbatim + +@tab @tab @verbatim +mttr rt,crs,1,4,1 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtthi rt +@end verbatim + +@tab @tab @verbatim +mttr rt,$1,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mtthi rt,acc +@end verbatim + +@tab @tab @verbatim +rs = (acc * 4) + 1 +mttr rt,rs,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttlo rt +@end verbatim + +@tab @tab @verbatim +mttr rt,$0,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +mttlo rt,acc +@end verbatim + +@tab @tab @verbatim +rs = (acc * 4) +mttr rt,rs,1,1,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +neg rd,rs +@end verbatim + +@tab non-NMS @tab @verbatim +sub rd,$zero,rs +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +negu rd,rs +@end verbatim + +@tab @tab @verbatim +subu rd,$zero,rs +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +not rd,rs +@end verbatim + +@tab @tab @verbatim +nor rd,rs,$zero +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +or rt,rt,rs +@end verbatim + +@tab @tab @verbatim +or rt,rs +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +or rt,rs,rt +@end verbatim + +@tab @tab @verbatim +or rt,rs +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +rem rd,rs,rt +@end verbatim + +@tab @tab @verbatim +mod rd,rs,rt +@end verbatim + +@tab N @tab 32 +@item +@verbatim +jraddiusp imm +@end verbatim + +@tab 0 <= imm < 4096 +&& (imm%16 == 0) @tab @verbatim +restore.jrc imm +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +rotr rd,rs,rt +@end verbatim + +@tab @tab @verbatim +rotrv rd,rs,rt +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +ror rd,rs,shift +@end verbatim + +@tab @tab @verbatim +rotr rd,rs,shift +@end verbatim + +@tab N @tab 32 +@item +@verbatim +ror rd,rs,rt +@end verbatim + +@tab @tab @verbatim +rotrv rd,rs,rt +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +rorv rd,rs,shift +@end verbatim + +@tab @tab @verbatim +rotr rd,rs,shift +@end verbatim + +@tab N @tab 32 +@item +@verbatim +rorv rd,rs,rt +@end verbatim + +@tab @tab @verbatim +rotrv rd,rs,rt +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +sll rd,rs,rt +@end verbatim + +@tab @tab @verbatim +sllv rd,rs,rt +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +sra rd,rs,rt +@end verbatim + +@tab @tab @verbatim +srav rd,rs,rt +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +srl rd,rs,rt +@end verbatim + +@tab @tab @verbatim +srlv rd,rs,rt +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +xor rt,rt,rs +@end verbatim + +@tab @tab @verbatim +xor rt,rs +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +xor rt,rs,rt +@end verbatim + +@tab @tab @verbatim +xor rt,rs +@end verbatim + +@tab Y @tab 16 +@item +@verbatim +andi rt,rs,imm +@end verbatim + +@tab imm = 2x -1,where 12 < x <= 32 @tab @verbatim +ext rt,rs,0,x +@end verbatim + +@tab N @tab 32 +@item +@verbatim +nop +@end verbatim + +@tab @tab @verbatim +sll $zero,rs,0 +@end verbatim + +@tab Y @tab 32 +@item +@verbatim +ualw rt,ofst(rs) +@end verbatim + +@tab non-NMS @tab @verbatim +ualwm rt,ofst(rs),1 +@end verbatim + +@tab Y @tab 32 +@item @tab @tab @tab @tab +@item +@verbatim +Convert-to-compact branch aliases +@end verbatim + +@tab @tab @tab @tab +@item +@verbatim +jr rs +@end verbatim + +@tab @tab @verbatim +jrc rs +@end verbatim + +@tab N @tab 16 +@item +@verbatim +jr rs +@end verbatim + +@tab @tab @verbatim +jalrc $zero,rs +@end verbatim + +@tab N @tab 32 +@item +@verbatim +jalr rd,rs +@end verbatim + +@tab @tab @verbatim +jalrc rd,rs +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +jalr rs +@end verbatim + +@tab @tab @verbatim +jalrc $ra,rs +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +bal label +@end verbatim + +@tab @tab @verbatim +balc label +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +b label +@end verbatim + +@tab @tab @verbatim +bc label +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +beqz rt,label +@end verbatim + +@tab @tab @verbatim +beqc $zero,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +beqz $zero,rt,label +@end verbatim + +@tab @tab @verbatim +beqzc rt,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +beqz rt,$zero,label +@end verbatim + +@tab @tab @verbatim +beqzc rt,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +beq rs,rt,label +@end verbatim + +@tab rs < rt @* +&& non-NMS @tab @verbatim +beqc rs,rt,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +beq rs,rt,label +@end verbatim + +@tab rs > rt @* +&& non-NMS @tab @verbatim +beqc rt,rs,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +beq rs,rt,label +@end verbatim + +@tab @tab @verbatim +beqc rt,rs,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +blez rt,label +@end verbatim + +@tab @tab @verbatim +bgec $zero,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bgez rt,label +@end verbatim + +@tab @tab @verbatim +bgec rt,$zero,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bge rs,rt,label +@end verbatim + +@tab @tab @verbatim +bgec rs,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bgeu rs,rt,label +@end verbatim + +@tab @tab @verbatim +bgeuc rs,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bgtz rt,label +@end verbatim + +@tab @tab @verbatim +bltc $zero,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bltz rt,label +@end verbatim + +@tab @tab @verbatim +bltc rt,$zero,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +blt rs,rt,label +@end verbatim + +@tab @tab @verbatim +bltc rs,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bltu rs,rt,label +@end verbatim + +@tab @tab @verbatim +bltuc rs,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bnez rt,label +@end verbatim + +@tab @tab @verbatim +bnec $zero,rt,label +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +bne rs,rt,label +@end verbatim + +@tab rs >= rt @* +&& non-NMS @tab @verbatim +bnec rs,rt,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +bne rs,rt,label +@end verbatim + +@tab rs <= rt @* +&& non-NMS @tab @verbatim +bnec rt,rs,label +@end verbatim + +@tab N @tab 16 +@item +@verbatim +bne rs,rt,label +@end verbatim + +@tab @tab @verbatim +bnec rs,rt,label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +bposge32 imm +@end verbatim + +@tab @tab @verbatim +bposge32c imm +@end verbatim + +@tab N @tab 32 +@item +@verbatim +j label +@end verbatim + +@tab @tab @verbatim +bc label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +jr.hb rs +@end verbatim + +@tab @tab @verbatim +jalrc.hb $zero,rs +@end verbatim + +@tab N @tab 32 +@item +@verbatim +jalr.hb rs +@end verbatim + +@tab @tab @verbatim +jalrc.hb $zero,rs +@end verbatim + +@tab N @tab 32 +@item +@verbatim +jalr.hb rd,rs +@end verbatim + +@tab @tab @verbatim +jalrc.hb rd,rs +@end verbatim + +@tab N @tab 32 +@item +@verbatim +jal rd,rs +@end verbatim + +@tab @tab @verbatim +jalrc rd,rs +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +jal rs +@end verbatim + +@tab @tab @verbatim +jalrc $ra,rs +@end verbatim + +@tab N @tab 16/32 +@item +@verbatim +jal label +@end verbatim + +@tab @tab @verbatim +balc label +@end verbatim + +@tab N @tab 32 +@item +@verbatim +move.bal rt,rt,label +@end verbatim + +@tab @tab @verbatim +move.balc rd,rt,label +@end verbatim + +@tab N @tab 32 + +@end multitable diff --git a/gas/doc/c-nanomips-macros.texi b/gas/doc/c-nanomips-macros.texi new file mode 100644 index 00000000000..7f4685f8d77 --- /dev/null +++ b/gas/doc/c-nanomips-macros.texi @@ -0,0 +1,3136 @@ +@c Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. +@c Contributed by MIPS Tech LLC +@c Written by Faraz Shahbazker +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@page + +@node nanoMIPS Macros +@section High-level Assembly Macros + +MIPS assemblers have traditionally provided a wider range of +instructions than the MIPS architecture itself. These extra +instructions are usually referred to as ``macro'' instructions +@footnote{The term ``macro'' is somewhat overloaded here, since +these macros have no relation to those defined by @code{.macro}, +@pxref{Macro,, @code{.macro}}.}. nanoMIPS assembler continues +support for many traditionally supported instructions. + +Some nanoMIPS macro instructions extend an underlying architectural +instruction while others are entirely new. An example of the former +type is @code{and}, which allows the third operand to be either a +register or an arbitrary immediate value. Examples of the latter type +include @code{bgt}, which branches to the third operand when the +first operand is greater than the second operand. + +One of the most common extensions provided by macros is to expand memory +offsets to the full address range (32 or 64 bits) and to allow symbolic +offsets such as @samp{my_data + 4} to be used in place of integer +constants. For example, the architectural instruction @code{lbu} allows +only an unsigned 12-bit offset, whereas the macro @code{lbu} allows code +such as @samp{lbu $a0,array+32769}. The implementation of these symbolic +offsets depends on several factors, such as whether the assembler is +generating SVR4-style PIC (selected by @option{-mpic}, @pxref{nanoMIPS +Options,, Assembler options}), the size of symbols, +and the small data limit (@pxref{nanoMIPS Small Data,, Controlling the +use of small data accesses}). + +@table @code +@item gprel_p(label) +TRUE if label can be referenced relative to $gp +@item local_p(label) +TRUE if label is locally scoped +@end table + +@table @code +@item @r{Instruction} +@multitable @columnfractions 0.3 0.4 0.3 +@item Condition +@tab Expansion +@tab Remarks +@end multitable + +@item abs rd,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rd <> rt +@end verbatim + +@tab +@verbatim +move rd,rt +bgezc rt,0f +subu rd,0,rt +0: +@end verbatim +@tab + +@item +@verbatim +rd == rt +@end verbatim + +@tab +@verbatim +bgezc rd,0f +subu rd,0,rd +0: +@end verbatim + +@tab +@end multitable +@item la rd,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-4095 <= ofst <= 65535 +@end verbatim + +@tab +@verbatim +addiu rd,rs,ofst +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +li rd,ofst +@end verbatim + +@tab +@item +@verbatim +rs <> 0 +&& rs <> rd +@end verbatim + +@tab +@verbatim +li rd,ofst +addu rd,rd,rs +@end verbatim + +@tab +@c FIXME: alternative expansion +@c move rd,rs +@c addiu48 rd,ofst8 bytes irrespective of rd/rs are gpr3 or gpr4 +@item +@verbatim +rs <> 0 +&& rs == rd +&& NMS +@end verbatim + +@tab +@verbatim +li $at,ofst +addu rd,$at,rs +@end verbatim + +@tab +@item +@verbatim +rs <> 0 +&& rs == rd +@end verbatim + +@tab +@verbatim +addiu[48] rd,rd,ofst +@end verbatim + +@tab +@end multitable +@anchor{x_la_label} +@item la rd,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@tab +@item +@verbatim +(no-PIC + || local_p(label)) +&& gprel_p(label) +&& (cmodel=[medium|auto]) +@end verbatim + +@tab +@verbatim +addiu rd,gp,%gp_rel(label) +@end verbatim + +@tab +@item +@verbatim +(no-PIC + || local_p(label)) +&& NMS +@end verbatim + +@tab +@verbatim +aluipc rd,%pcrel_hi(label) +addiu rd,%pcrel_lo(label) +@end verbatim + +@tab +@item +@verbatim +no-PIC +|| local_p(label) +@end verbatim + +@tab +@verbatim +addiupc[48] rd,label +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& (cmodel=[medium|auto] + || linkrelax) +@end verbatim + +@tab +@verbatim +lw rd,%got_disp(label)($gp) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& cmodel=large +@end verbatim + +@tab +@verbatim +aluipc rd,%got_pcrel_hi(label) +lw rd,%got_lo(label)(rd) +@end verbatim + +@tab +@item +@tab +@tab +@end multitable +@item jal label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +no-PIC +@end verbatim + +@tab +@verbatim +balc label +@end verbatim + +@tab +@item +@verbatim +PIC +@end verbatim + +@tab +@verbatim +lw $at,%got_disp(label)($gp) +jalrc $at +@end verbatim + +@tab +@end multitable +@item jraddiusp imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-4095 <= imm <= 65535 +&& (imm%16 != 0) +@end verbatim + +@tab +@verbatim +addiu $sp,$sp,imm +jrc $ra +@end verbatim + +@tab +@item else + +@tab +@verbatim +li at,imm +addu sp,sp,at +jrc ra +@end verbatim + +@tab +@end multitable +@anchor{x_macro_li}@item li rd,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-1 <= imm <= 126 +@end verbatim + +@tab +@verbatim +li rd,imm +@end verbatim + +@tab +@item +@verbatim +-4095 <= imm <= 65535 +@end verbatim + +@tab +@verbatim +addiu rd,$0,imm +@end verbatim + +@tab +@item +@verbatim +NMS +&& (imm & 0xfff) == 0 +@end verbatim + +@tab +@verbatim +lui rd,%hi(imm) +@end verbatim + +@tab +@item +@verbatim +NMS +@end verbatim + +@tab +@verbatim +lui rd,%hi(imm) +addiu rd,%lo(imm) +@end verbatim + +@tab +@item else + +@tab +@verbatim +li[48] rd,imm +@end verbatim + +@tab +@end multitable +@item li.s rd,immfloat +@multitable @columnfractions 0.3 0.4 0.3 +@item +@xref{x_macro_li,,li}. +@end multitable +@item li.d rd,immdouble +@multitable @columnfractions 0.3 0.4 0.3 +@item +not NMS +@tab +@verbatim +li48 rd+1,%hi32(immdouble) +li48 rd,%lo32(immdouble) +@end verbatim +@tab +@item +-Gx, x >=8 +@tab +@verbatim + ld rd, label + .sdata: +label: + .dword immdouble +@end verbatim +@tab +@xref{x_ld_label,,ld from label}. +@item +-Gx, x < 8 +@tab +@verbatim + ld rd, label + .rodata: +label: + .dword immdouble +@end verbatim +@tab +@xref{x_ld_label,,ld from label}. +@end multitable +@item nor rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +li $at,imm +nor rt,rs,$at +@end verbatim + +@tab +@end multitable +@item rol rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rs == rt +@end verbatim + +@tab +@verbatim +negu $at,rt +rorv rd,rs,$at +@end verbatim + +@tab +@item +@verbatim +rs <> rt +@end verbatim + +@tab +@verbatim +negu rd,rt +rorv rd,rs,rd +@end verbatim + +@tab +@end multitable +@item rol rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +ror rd,rs,rot5 +@end verbatim + +@tab +imm5 = imm & 0x1f@* +rot5 = (32 - imm5) & 0x1f +@end multitable +@item ror rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +ror rd,rs,imm5 +@end verbatim + +@tab +imm5 = imm & 0x1f +@end multitable +@item rotl rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rs == rt +@end verbatim + +@tab +@verbatim +negu $at,rt +rorv rd,rs,$at +@end verbatim + +@tab +@item +@verbatim +rs <> rt +@end verbatim + +@tab +@verbatim +negu rd,rt +rorv rd,rs,rd +@end verbatim + +@tab +@end multitable +@item rotl rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +ror rd,rs,rot5 +@end verbatim + +@tab +imm5 = imm & 0x1f@* +rot5 = (32 - imm5) & 0x1f +@end multitable +@item sge rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +slt rd,rs,rt +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sge rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 <= imm <= 4095 +@end verbatim + +@tab +@verbatim +slti rd,rs,imm +xori rd,rd,1 +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +slt rd,rs,rt +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sgeu rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +sltu rd,rs,rt +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sgeu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 <= imm <= 4095 +@end verbatim + +@tab +@verbatim +sltiu rd,rs,imm +xori rd,rd,1 +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +sltu rd,rs,rt +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sgt rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +slt rd,rt,rs +@end verbatim + +@tab +@end multitable +@item sgt rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +li $at,imm +slt rd,$at,rs +@end verbatim + +@tab +@end multitable +@item sgtu rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +sltu rd,rt,rs +@end verbatim + +@tab +@end multitable +@item sgtu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +li $at,imm +sltu rd,$at,rs +@end verbatim + +@tab +@end multitable +@item sle rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +slt rd,rt,rs +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sle rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +li $at,imm +slt rd,$at,rs +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sleu rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +sltu rd,rt,rs +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sleu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +li $at,imm +sltu rd,$at,rs +xori rd,rd,1 +@end verbatim + +@tab +@end multitable +@item seq rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +sltiu rd,rt,1 +@end verbatim + +@tab +@item +@verbatim +rt == 0 +@end verbatim + +@tab +@verbatim +sltiu rd,rs,1 +@end verbatim + +@tab +@item else + +@tab +@verbatim +xor rd,rs,rt +sltiu rd,rd,1 +@end verbatim + +@tab +@end multitable +@item seq rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +sltiu rd,rs,1 +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +move rd,$0 +@end verbatim + +@tab +Always CLEAR +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +xori rd,rs,imm +sltiu rd,rd,1 +@end verbatim + +@tab +@item +@verbatim +-8192 < imm < 0 +@end verbatim + +@tab +@verbatim +addiu rd,rs,-imm +sltiu rd,rd,1 +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +xor rd,rs,$at +sltiu rd,rd,1 +@end verbatim + +@tab +@end multitable +@item sne rd,rs,rt +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +sltu,rd,$0,rt +@end verbatim + +@tab +@item +@verbatim +rt == 0 +@end verbatim + +@tab +@verbatim +sltu rd,$0,rs +@end verbatim + +@tab +@item else + +@tab +@verbatim +xor rd,rs,rt +sltu rd,$0,rd +@end verbatim + +@tab +@end multitable +@item sne rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +sltu rd,$0,rs +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +addiu rd,$0,1 +@end verbatim + +@tab +Always SET +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +xori rd,rs,imm +sltu rd,$0,rd +@end verbatim + +@tab +@item +@verbatim +-8192 < imm < 0 +@end verbatim + +@tab +@verbatim +addiu rd,rs,-imm +sltu rd,$0,rd +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +xor rd,rs,$at +sltu rd,$0,rd +@end verbatim + +@tab +@end multitable +@item slt rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 < imm < 4096 +@end verbatim + +@tab +@verbatim +slti rd,rs,imm +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +slt rd,rs,$at +@end verbatim + +@tab +@end multitable +@item sltu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +sltiu rd,rs,imm +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +slt rd,rs,$at +@end verbatim + +@tab +@end multitable +@item bgt rs,rt,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rt == 0 +@end verbatim + +@tab +@verbatim +bgtzc rs,label +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +bltzc rt,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +slt $i,rs,rt +bnezc $at,label +@end verbatim + +@tab +@end multitable +@item bgt rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == -1 +@end verbatim + +@tab +@verbatim +beqzc rs,label +@end verbatim + +@tab +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +bgtzc rs,label +@end verbatim + +@tab +@item +@verbatim +imm > GPR_SMAX +@end verbatim + +@tab +@verbatim +nop +@end verbatim + +@tab +Always false +@item +@verbatim +imm == GPR_SMIN +@end verbatim + +@tab +@verbatim +bc label +@end verbatim + +@tab +Always true +@item +@verbatim +0 < imm < 127 +@end verbatim + +@tab +@verbatim +bgeic rs,imm+1,label +@end verbatim + +@tab +@item +@verbatim +imm < 4095 +@end verbatim + +@tab +@verbatim +slti $at,rs,imm+1 +beqzc $at,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm+1 +slt $at,rs,$at +beqzc $at,label +@end verbatim + +@tab +@end multitable +@item bgtu rs,rt,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rt == 0 +@end verbatim + +@tab +@verbatim +bnezc $rs,label +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +nop +@end verbatim + +@tab +Always false +@item else + +@tab +@verbatim +sltu $at,rs,rs +bnezc $at,label +@end verbatim + +@tab +@end multitable +@item bgtu rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +nop +@end verbatim + +@tab +Always false +@item +@verbatim +imm == -1 +&& 32-bit +@end verbatim + +@tab +@verbatim +nop +@end verbatim + +@tab +Always false +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +bnezc $rs,label +@end verbatim + +@tab +@item +@verbatim +0 < imm < 127 +@end verbatim + +@tab +@verbatim +bgeiuc rs,imm+1,label +@end verbatim + +@tab +@item +@verbatim +imm < 4095 +@end verbatim + +@tab +@verbatim +sltiu $at,rs,imm+1 +beqzc $at,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm+1 +sltu $at,rs,$at +beqzc $at,label +@end verbatim + +@tab +@end multitable +@item ble rs,rt,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rt == 0 +@end verbatim + +@tab +@verbatim +blezc rs,label +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +bgezc rt,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +slt $at,rs,rs +beqzc $at,label +@end verbatim + +@tab +@end multitable +@item ble rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm > GPR_SMAX +@end verbatim + +@tab +@verbatim +bc label +@end verbatim + +@tab +Always true +@item +@verbatim +imm == -1 +@end verbatim + +@tab +@verbatim +bltzc rs,label +@end verbatim + +@tab +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +blezc rs,label +@end verbatim + +@tab +@item +@verbatim +0 < imm < 127 +@end verbatim + +@tab +@verbatim +bltic rs,imm+1,label +@end verbatim + +@tab +@item +@verbatim +imm < 4095 +@end verbatim + +@tab +@verbatim +slti $at,rs,imm+1 +bnezc $at,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm+1 +slt $at,rs,$at +bnezc $at,label +@end verbatim + +@tab +@end multitable +@item bleu rs,rt,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rt == 0 +@end verbatim + +@tab +@verbatim +beqzc rs,label +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +bc label +@end verbatim + +@tab +Always true +@item else + +@tab +@verbatim +sltu $at,rs,rt +beqzc $at,label +@end verbatim + +@tab +@end multitable +@item bleu rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == -1 +&& 32-bit +@end verbatim + +@tab +@verbatim +bc label +@end verbatim + +@tab +Always true +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +bc label +@end verbatim + +@tab +Always true +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +beqzc rs,label +@end verbatim + +@tab +@item +@verbatim +0 < imm < 127 +@end verbatim + +@tab +@verbatim +bltiuc rs,imm+1,label +@end verbatim + +@tab +@item +@verbatim +imm < 4095 +@end verbatim + +@tab +@verbatim +slti $at,rs,imm+1 +bnezc $at,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm+1 +slt $at,rs,$at +bnezc $at,label +@end verbatim + +@tab +@end multitable +@item bgezal rs,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim + bltzc rs,0fbalc label +0: +@end verbatim + +@tab +@end multitable +@item bltzal rs,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +bgezc rs,0fbalc label +0: +@end verbatim + +@tab +@end multitable +@item Immediate supported - if immediate doesn't fit, load to register +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@tab +@end multitable +@item add rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +non-NMS +@end verbatim + +@tab +@verbatim +li $at,imm +add rd,rs,$at +@end verbatim + +@tab +@end multitable +@item addu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-4095 <= imm <= 65535 +@end verbatim + +@tab +@verbatim +addiu rd,rs,imm +@end verbatim + +@tab +@item +@verbatim +non-NMS +&& rd == rs +@end verbatim + +@tab +@verbatim +addiu[48] rd,rd,imm +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +addu rd,rs,$at +@end verbatim + +@tab +@end multitable +@item and rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 <= imm < 4096 +@end verbatim + +@tab +@verbatim +andi rd,rs,imm +@end verbatim + +@tab +@item +@verbatim +imm < 0 +|| imm >= 4096 +@end verbatim + +@tab +@verbatim +li $at,imm +and rd,rs,$at +@end verbatim + +@tab +@end multitable +@item sub rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +non-NMS +@end verbatim + +@tab +@verbatim +li $at,imm +sub rt,rs,$at +@end verbatim + +@tab +@end multitable +@item subu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-4095 <= imm <= 65535 +@end verbatim + +@tab +@verbatim +addiu rt,rs,-imm +@end verbatim + +@tab +@item +@verbatim +non-NMS +&& rd == rs +@end verbatim + +@tab +@verbatim +addiu[48] rt,rs,-imm +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +subu rt,rs,$at +@end verbatim + +@tab +@end multitable +@item beq rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 < imm <= 127 +@end verbatim + +@tab +@verbatim +beqic rs,imm,label +@end verbatim + +@tab +@item +@verbatim +else +@end verbatim + +@tab +@verbatim +li $at,imm +beq rs,$at,label +@end verbatim + +@tab +@end multitable +@item bge rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 < imm <= 127 +@end verbatim + +@tab +@verbatim +bgeic rs,imm,label +@end verbatim + +@tab +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +slti $at,rs,imm +beqzc $at,label +@end verbatim + +@tab +@item +@verbatim +imm < 0 +|| imm >= 4096 +@end verbatim + +@tab +@verbatim +li $at,imm +slt $at,rs,$at +beqzc $at,label +@end verbatim + +@tab +@end multitable +@item bgeu rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm <= 127 +@end verbatim + +@tab +@verbatim +bgeiuc rs,imm,label +@end verbatim + +@tab +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +sltiu $at,rs,imm +beqzc $at,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +sltu $at,rs,$at +beqzc $at,label +@end verbatim + +@tab +@end multitable +@item blt rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +bltzc rs,label +@end verbatim + +@tab +@item +@verbatim +imm == 1 +@end verbatim + +@tab +@verbatim +blezc rs,label +@end verbatim + +@tab +@item +@verbatim +0 < imm <= 127 +@end verbatim + +@tab +@verbatim +bltic rs,imm,label +@end verbatim + +@tab +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +slti $at,rs,imm +bnezc $at,label +@end verbatim + +@tab +@item else +@verbatim +imm < 0 +|| imm >= 4096 +@end verbatim + +@tab +@verbatim +li $at,imm +slt $at,rs,$at +bnezc $at,label +@end verbatim + +@tab +@end multitable +@item bltu rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm <= 127 +@end verbatim + +@tab +@verbatim +bltiuc rs,imm,label +@end verbatim + +@tab +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +sltiu $at,rs,imm +bnezc $at,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +sltu $at,rs,$at +bnezc $at,label +@end verbatim + +@tab +@end multitable +@item bne rs,imm,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 < imm <= 127 +@end verbatim + +@tab +@verbatim +bneic rs,imm,label +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +bnec rs,$at,label +@end verbatim + +@tab +@end multitable +@item or rt,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 <= imm < 4096 +@end verbatim + +@tab +@verbatim +ori rt,rs,imm +@end verbatim + +@tab +@item +@verbatim +imm < 0 +|| imm >= 4096 +@end verbatim + +@tab +@verbatim +li $at,imm +or rt,rs,$at +@end verbatim + +@tab +@end multitable +@item slt rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 <= imm < 4096 +@end verbatim + +@tab +@verbatim +slti rd,rs,imm +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +slt rd,rs,$at +@end verbatim + +@tab +@end multitable +@item sltu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm < 4096 +@end verbatim + +@tab +@verbatim +sltiu rd,rs,imm +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +slt rd,rs,$at +@end verbatim + +@tab +@end multitable +@item xor rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 <= imm < 4096 +@end verbatim + +@tab +@verbatim +xori rt,rs,imm +@end verbatim + +@tab +@item +@verbatim +imm < 0 +|| imm >= 4096 +@end verbatim + +@tab +@verbatim +li $at,imm +xor rt,rs,$at +@end verbatim + +@tab +@end multitable +@item teq rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +non-NMS +@end verbatim + +@tab +@verbatim +li $at,imm +teq rs,$at +@end verbatim + +@tab +@end multitable +@item tne rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +non-NMS +@end verbatim + +@tab +@verbatim +li $at,imm +tne rs,$at +@end verbatim + +@tab +@item +@tab +@tab +@end multitable +@anchor{x_cache_ofst}@item cache hint,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-256 <= ofst <= 255 +@end verbatim + +@tab +@verbatim +cache op,ofst(rs) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +@end verbatim + +@tab +@verbatim +addiu $at,rs,ofst +cache op,0($at) +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,ofst +addu $at,$at,rs +cache op,0(rs) +@end verbatim + +@tab +@end multitable +@item cachee hint,ofst(rs) +@multitable @columnfractions 1 0 0 +@item @xref{x_cache_ofst,,cache operation at offset}. +@end multitable +@anchor{x_pref_ofst}@item pref hint,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-256 <= ofst <= 4095 +@end verbatim + +@tab +@verbatim +pref op,ofst(rs) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +@end verbatim + +@tab +@verbatim +addiu $at,rs,ofst +pref op,0($at) +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,ofst +addu $at,$at,rs +pref op,0(rs) +@end verbatim + +@tab +@item +@tab +@tab +@end multitable +@item prefe hint,ofst(rs) +@multitable @columnfractions 1 +@item @xref{x_pref_ofst,,pre-fetch operation at offset}. +@end multitable +@anchor{x_lw_ofst}@item lw rd,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-255 <= ofst <= 4095 +@end verbatim + +@tab +@verbatim +lw rd,ofst(rs) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +&& rd <> rs +@end verbatim + +@tab +@verbatim +addiu rd,rs,ofst +lw rd,0(rd) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +&& rd == rs +@end verbatim + +@tab +@verbatim +addiu rd,rd,ofst +lw rd,0(rd) +@end verbatim + +@tab +@item +@verbatim +rd == rs +@end verbatim +@tab +@verbatim +addiu[48] rs,rs,ofst +lw rd,0(rs) +@end verbatim +@tab +@item +@verbatim +rd <> rs +&& NMS +@end verbatim + +@tab +@verbatim +lui rd,%hi(ofst) +addu rd,rd,rs +lw rd,%lo(ofst)(rd) +@end verbatim +@tab +@item +@verbatim +else +@end verbatim + +@tab +@verbatim +lui $at,%hi(ofst) +addu $at,$at,rs +lw rd,%lo(ofst)($at) +@end verbatim + +@tab +@end multitable +@anchor{x_lw_label}@item lw rd,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +(no-PIC + || local_p(label)) +&& gprel_p(label) +&& (cmodel=[medium|auto]) +@end verbatim + +@tab +@verbatim +lw rd,%gprel(label)($gp) +@end verbatim + +@tab +@item +@verbatim +(no-PIC + || local_p(label)) +&& rd == 0 +&& NMS +@end verbatim + +@tab +@verbatim +aluipc $at,%pcrel_hi(label) +lw rd,%lo(label)($at) +@end verbatim + +@tab +@item +@verbatim +(no-PIC + || local_p(label)) +&& rd <> 0 +&& NMS +@end verbatim + +@tab +@verbatim +aluipc rd,%pcrel_hi(label) +lw rd,%lo(label)(rd) +@end verbatim + +@tab +@item +@verbatim +no-PIC +|| local_p(label) +@end verbatim + +@tab +@verbatim +lwpc rd,label +@end verbatim + +@tab +LW only, not applicable for sub-word loads +@item +@verbatim +PIC +&& !local_p(label) +&& rd == 0 +&& (cmodel=[auto|medium] + || linkrelax) +@end verbatim + +@tab +@verbatim +lw $at,%got_disp(label)($gp) +lw rd,0($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& rd == 0 +&& !local_p(label) +&& cmodel=large +&& NMS +@end verbatim + +@tab +@verbatim +aluipc $at,%got_pcrel_hi(label) +lw at,%got_lo(label)($at) +lw rd,0($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& rd == 0 +&& cmodel=large +@end verbatim + +@tab +@verbatim +lwpc $at,%got_pcrel32(label) +lw rd,0($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& rd <> 0 +&& (cmodel=[auto|medium] + || linkrelax) +@end verbatim + +@tab +@verbatim +lw rd,%got_disp(label)($gp) +lw rd,0(rd) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& rd <> 0 +&& cmodel=large +&& NMS +@end verbatim + +@tab +@verbatim +aluipc rd,%got_pcrel_hi(label) +lw rd,%got_lo(label)(rd) +lw rd,0(rd) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& rd <> 0 +&& cmodel=large +@end verbatim + +@tab +@verbatim +lwpc rd,%got_pcrel32(label) +lw rd,0(rd) +@end verbatim + +@tab +@end multitable +@item lwu rd,ofst(rs) +@itemx lb rd,ofst(rs) +@itemx lbu rd,ofst(rs) +@itemx lh rd,ofst(rs) +@itemx lhu rd,ofst(rs) +@itemx ulh rd,ofst(rs) +@itemx ulw rd,ofst(rs) +@multitable @columnfractions 1 +@item @xref{x_lw_ofst,,lw from ofst}. +@end multitable +@item lwu rd,label +@itemx lb rd,label +@itemx lbu rd,label +@itemx lh rd,label +@itemx lhu rd,label +@itemx ulh rd,label +@itemx ulw rd,label +@multitable @columnfractions 1 +@item @xref{x_lw_label,,lw from label}. +@end multitable +@item ld rd,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-252 <= ofst < 4092 +&& rd == rs +@end verbatim + +@tab +@verbatim +lw rd+1,ofst+4(rs) +lw rd,ofst(rs) +@end verbatim + +@tab +@item +@verbatim +-252 <= ofst < 4092 +&& rd <> rs +@end verbatim + +@tab +@verbatim +lw rd,ofst(rs) +lw rd+1,ofst+4(rs) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +@end verbatim + +@tab +@verbatim +addiu $at,rs,ofst +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@item +@verbatim +%hi(ofst) == %hi(ofst+4) +&& rs == 0 +@end verbatim + +@tab +@verbatim +lui $at,%hi(ofst) +lw rd,%lo(ofst)($at) +lw rd+1,%lo(ofst+4)($at) +@end verbatim + +@tab +@item +@verbatim +%hi(ofst) == %hi(ofst+4) +&& rs <> 0 +@end verbatim + +@tab +@verbatim +lui $at,%hi(ofst) +addu $at,$at,rs +lw rd,%lo(ofst)($at) +lw rd+1,%lo(ofst+4)($at) +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +li $at,ofst +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@item +@verbatim +rs <> 0 +@end verbatim + +@tab +@verbatim +li $at,ofst +addu $at,$at,rs +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@end multitable +@anchor{x_ld_label}@item ld rd,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +(non-PIC + || local_p(label)) +&& gprel_p(label) +&& cmodel=[medium|auto] +@end verbatim + +@tab +@verbatim +lw rd,%gprel(label)($gp) +lw rd+1,%gprel(label+4)($gp) +@end verbatim + +@tab +@item +@verbatim +(non-PIC + || local_p(label)) +&& NMS +@end verbatim + +@tab +@verbatim +aluipc $at,%pcrel_hi(label) +lw rd,%lo(label)($at) +lw rd+1,%lo(label+4)($at) +@end verbatim + +@tab +@item +@verbatim +(non-PIC + || local_p(label)) +@end verbatim + +@tab +@verbatim +lwpc rd,label +lwpc rd+1,label+4 +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& (cmodel=[auto|medium] + || linkrelax) +@end verbatim + +@tab +@verbatim +lw $at,%got_disp(label)($gp) +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& cmodel=large +&& NMS +@end verbatim + +@tab +@verbatim +lui $at,%got_pcrel_hi(label) +lw rd,%got_lo(label)($at) +lw rd+1,%got_lo(label+4)($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& cmodel=large +@end verbatim + +@tab +@verbatim +lwpc rd,%got_pcrel32(label)($at) +lwpc rd+1,%got_pcrel32(label+4)($at) +@end verbatim + +@tab +@item +@tab +@tab +@end multitable +@anchor{x_ll_ofst}@item ll rd,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-256 <= ofst < 255 +@end verbatim + +@tab +@verbatim +ll rd,ofst(rs) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +&& rd <> rs +@end verbatim + +@tab +@verbatim +addiu rd,rs,ofst +ll rd,0(rd) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +&& rd == rs +@end verbatim + +@tab +@verbatim +addiu rd,rd,ofst +ll rd,0(rd) +@end verbatim + +@tab +@item +@verbatim +rd <> rs +@end verbatim + +@tab +@verbatim +li rd,ofst +addu rd,rd,rs +ll rd,0(rd) +@end verbatim + +@tab +@item +@verbatim +rd == rs +@end verbatim + +@tab +@verbatim +li $at,ofst +addu $at,$at,rs +ll rd,0($at) +@end verbatim + +@tab +@end multitable +@anchor{x_ll_label}@item ll rd,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rd == 0 +@end verbatim + +@tab +@verbatim +la $at,label +ll rd,0($at) +@end verbatim + +@tab +@xref{x_la_label,,la of label}. +@item +@verbatim +rd <> 0 +@end verbatim + +@tab +@verbatim +la rd,label +ll rd,0(rd) +@end verbatim +@tab +@xref{x_la_label,,la of label}. +@end multitable +@item lle rd,ofst(rs) +@multitable @columnfractions 1 +@item @xref{x_ll_ofst,,ll from offset}. +@end multitable +@item lle rd,label +@multitable @columnfractions 1 +@item @xref{x_ll_label,,ll from label}. +@end multitable +@anchor{x_llwp_ofst}@item llwp rd,ru,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rs == 0 && rd != 0 +@end verbatim +@tab +@verbatim +li rd,ofst +llwp rd,ru,(rd) +@end verbatim +@tab +@item +@verbatim +rs == 0 && ru != 0 +@end verbatim +@tab +@verbatim +li ru,ofst +llwp rd,ru,(ru) +@end verbatim +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +&& rd != 0 +@end verbatim +@tab +@verbatim +addiu rd,rs,ofst +llwp rd,ru,(rd) +@end verbatim +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +&& ru != 0 +@end verbatim +@tab +@verbatim +addiu ru,rs,ofst +llwp rd,ru,(ru) +@end verbatim +@tab +@item +@verbatim +rd != 0 +@end verbatim +@tab +@verbatim +li rd,ofst +addiu rd,rd,rs +llwp rd,ru,(rd) +@end verbatim +@tab +@item +@verbatim +ru != 0 +@end verbatim +@tab +@verbatim +li ru,ofst +addiu ru,ru,rs +llwp rd,ru,(ru) +@end verbatim +@tab +@end multitable +@anchor{x_llwp_label}@item llwp rd,ru,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rd != 0 +@end verbatim +@tab +@verbatim +la rd,label +llwp rd,ru,(rd) +@end verbatim +@tab +@xref{x_la_label,,la of label}. +@item +@verbatim +ru != 0 +@end verbatim +@tab +@verbatim +la ru,label +llwp rd,ru,(ru) +@end verbatim +@tab +@xref{x_la_label,,la of label}. +@end multitable +@item llwpe rd,ru,ofst(rs) +@multitable @columnfractions 1 +@item @xref{x_llwp_ofst,,llwp from offset}. +@item +@end multitable +@item llwpe rd,ru,label +@multitable @columnfractions 1 +@item @xref{x_llwp_label,,llwp from label}. +@item +@end multitable +@anchor{x_sw_ofst}@item sw rd,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +-256 <= ofst < 4095 +@end verbatim + +@tab +@verbatim +sw rd,ofst(rs) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +&& rd <> rs +@end verbatim + +@tab +@verbatim +addiu $at,rs,ofst +sw rd,0($at) +@end verbatim + +@tab +@item +@tab +@verbatim +li $at,%hi(ofst) +addu $at,$at,rs +sw rd,%lo(ofst)($at) +@end verbatim + +@tab +@item +@tab +@verbatim +li $at,%hi(ofst) +addu $at,$at,rs +sw rd,%lo(ofst)($at) +@end verbatim + +@tab +@end multitable +@anchor{x_sw_label}@item sw rd,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +(no-PIC + || local_p(label)) +&& gprel_p(label) +&& cmodel=[medium|auto] +@end verbatim + +@tab +@verbatim +sw rd,%gprel(label)($gp) +@end verbatim + +@tab +@item +@verbatim +(no-PIC + || local_p(label)) +&& NMS +@end verbatim + +@tab +@verbatim +aluipc $at,%pcrel_hi(label)($gp) +sw rd,%lo(label)($at) +@end verbatim + +@tab +@item +@verbatim +(no-PIC + || local_p(label)) +@end verbatim + +@tab +@verbatim +swpc rd,label +@end verbatim + +@tab +SW only, not applicable for sub-word stores +@item +@verbatim +PIC +&& !local_p(label) +&& (cmodel=[auto|medium] + || linkrelax) +@end verbatim + +@tab +@verbatim +lw $at,%got_disp(label)($gp) +sw rd,0($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& cmodel=large +&& NMS +@end verbatim + +@tab +@verbatim +aluipc $at,%got_pcrel_hi(label) +lw $at,%got_lo(label)($at) +lw rd,0($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +&& cmodel=large +@end verbatim + +@tab +@verbatim +lwpc $at,label +lw rd,0($at) +@end verbatim + +@tab +@end multitable +@item sb rd,ofst(rs) +@itemx sh rd,ofst(rs) +@itemx ush rd,ofst(rs) +@itemx usw rd,ofst(rs) +@multitable @columnfractions 1 +@item @xref{x_sw_ofst,,sw to offset}. +@item +@end multitable +@item sc rd,ofst(rs) +@itemx sce rd,ofst(rs) +@multitable @columnfractions 1 +@item @xref{x_ll_ofst,,ll from offset}. +@end multitable +@item sb rd,label +@itemx sh rd,label +@itemx ush rd,label +@itemx usw rd,label +@multitable @columnfractions 1 +@item @xref{x_sw_label,,sw to label}. +@item +@end multitable +@item sd rd,label +@itemx uld rd,label +@itemx usd rd,label +@multitable @columnfractions 1 +@item @xref{x_ld_label,,ld from label}. +@end multitable +@item sc rd,label +@itemx sce rd,label +@multitable @columnfractions 1 +@item @xref{x_ll_label,,ll from label}. +@end multitable +@anchor{x_scwp_ofst}@item scwp rd,ru,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +rs == 0 +@end verbatim +@tab +@verbatim +li $at,ofst +scwp rd,ru,($at) +@end verbatim +@tab +@item +@verbatim +-4095 <= ofst <= 65535 +@end verbatim +@tab +@verbatim +addiu $at,rs,ofst +scwp rd,ru,($at) +@end verbatim +@tab +@item else +@tab +@verbatim +li $at,ofst +addiu $at,$at,rs +scwp rd,ru,($at) +@end verbatim +@tab +@end multitable +@anchor{x_scwp_label}@item scwp rd,ru,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +la $at,label +scwp rd,ru,($at) +@end verbatim +@tab +@xref{x_la_label,,la of label}. +@end multitable +@item scwpe rd,ru,ofst(rs) +@multitable @columnfractions 1 +@item @xref{x_scwp_ofst,,scwp to offset}. +@item +@end multitable +@item scwpe rd,ru,label +@multitable @columnfractions 1 +@item @xref{x_scwp_label,,scwp to label}. +@end multitable +@item Division & Multiplication +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@tab +@end multitable +@item div rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +break +@end verbatim + +@tab +@item +@verbatim +imm == 1 +@end verbatim + +@tab +@verbatim +move rd,rs +@end verbatim + +@tab +@item +@verbatim +imm == -1 +@end verbatim + +@tab +@verbatim +negu rd,rs +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +div rd,rs,$at +@end verbatim + +@tab +@end multitable +@item divu rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +break +@end verbatim + +@tab +@item +@verbatim +imm == 1 +@end verbatim + +@tab +@verbatim +move rd,rs +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +divu rd,rs,$at +@end verbatim + +@tab +@end multitable +@item rem rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +imm == 0 +@end verbatim + +@tab +@verbatim +break +@end verbatim + +@tab +@item +@verbatim +imm == 1 +@end verbatim + +@tab +@verbatim +move rd,$0 +@end verbatim + +@tab +@item +@verbatim +imm == -1 +@end verbatim + +@tab +@verbatim +move rd,$0 +@end verbatim + +@tab +@item else + +@tab +@verbatim +li $at,imm +mod rd,rs,$at +@end verbatim + +@tab +@end multitable +@item mul rd,rs,imm +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@verbatim +li $at,imm +mul rd,rs,$at +@end verbatim + +@tab +@end multitable +@item ofst operations +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@tab +@end multitable +@item ld rd,ofst(rs) +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +0 <= ofst < 4092 +&& rd == rs +@end verbatim + +@tab +@verbatim +lw rd+1,ofst+4(rs) +lw rd,ofst(rs) +@end verbatim + +@tab +@item +@verbatim +0 <= ofst < 4092 +&& rd <> rs +@end verbatim + +@tab +@verbatim +lw rd,ofst(rs) +lw rd+1,ofst+4(rs) +@end verbatim + +@tab +@item +@verbatim +-4095 <= ofst < 65536 +@end verbatim + +@tab +@verbatim +addiu $at,rs,ofst +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@item +@verbatim +%hi(ofst) == %hi(ofst+4) +&& rs == 0 +@end verbatim + +@tab +@verbatim +lui $at,%hi(ofst) +lw rd,%lo(ofst)($at) +lw rd+1,%lo(ofst+4)($at) +@end verbatim + +@tab +@item +@verbatim +%hi(ofst) == %hi(ofst+4) +&& rs <> 0 +@end verbatim + +@tab +@verbatim +lui $at,%hi(ofst) +addu $at,$at,rs +lw rd,%lo(ofst)($at) +lw rd+1,%lo(ofst+4)($at) +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +li $at,ofst +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@item +@verbatim +rs == 0 +@end verbatim + +@tab +@verbatim +li $at,ofst +addu $at,$at,rs +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@end multitable +@item ld rd,label +@multitable @columnfractions 0.3 0.4 0.3 +@item +no-PIC +&& gprel_p(label) + +@tab +@verbatim +lw rd,%gprel(label)($gp) +lw rd+1,%gprel(label+4)($gp) +@end verbatim + +@tab +@item +@verbatim +no-PIC +@end verbatim + +@tab +@verbatim +lui $at,%hi(label) +lw rd,%lo(label)($at) +lw rd+1,%lo(labe+4)($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& local_p(label) +@end verbatim + +@tab +@verbatim +lw $at,%got_page(label)($gp) +lw rd,%got_ofst(label)($at) +lw rd+1,%got_ofst(label+4)($at) +@end verbatim + +@tab +@item +@verbatim +PIC +&& !local_p(label) +@end verbatim + +@tab +@verbatim +lw $at,%got_disp(label)($gp) +lw rd,0($at) +lw rd+1,4($at) +@end verbatim + +@tab +@end multitable +@item NMS expansions +@multitable @columnfractions 0.3 0.4 0.3 +@item +@tab +@tab +@end multitable +@item Instruction +@multitable @columnfractions 0.3 0.4 0.3 +@item +@verbatim +Conditions +@end verbatim + +@tab +@verbatim +Expansion +@end verbatim + +@tab +Remarks and supplementary calculations +@end multitable +@item ext rt,rs,pos,size +@multitable @columnfractions 0.3 0.4 0.3 +@item (pos + size) > 31 +@tab +@verbatim +srl rt,rs,pos +@end verbatim +@tab +@item else +@tab +@verbatim +sll rt,rs,(31-pos-size) +srl rt,rt,(31-size) +@end verbatim +@tab +@end multitable +@item ins rt,rs,pos,size +@multitable @columnfractions 0.3 0.4 0.3 +@item rt == rs +@tab +@verbatim +extw $at,rt,rs,pos +extw rt,$at,rt,(1+size-pos) +extw rt,rt,rt,(31-size) +@end verbatim +@tab +@item pos == 0 && size == 31 +@tab +@verbatim +move rt,rs +@end verbatim +@tab +@item pos != 0 +@tab +@verbatim +extw rt,rt,rt,pos +extw rt,rt,rs,(1+size-pos) +extw rt,rt,rt,(31-size) +@end verbatim +@tab +@item else +@tab +@verbatim +extw rt,rt,rs,(1+size-pos) +extw rt,rt,rt,(31-size) +@end verbatim +@tab +@end multitable +@end table + +Note that while the assembler provides these macros for +compatibility, it does not make any attempt to optimize them with the +surrounding code. diff --git a/gas/doc/c-nanomips.texi b/gas/doc/c-nanomips.texi new file mode 100644 index 00000000000..9b3295cf25f --- /dev/null +++ b/gas/doc/c-nanomips.texi @@ -0,0 +1,1499 @@ +@c Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. +@c Contributed by MIPS Tech LLC. +@c Written by Faraz Shahbazker +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + +@macro doleft{TEXT} +@flushleft \TEXT\ +@end flushleft +@end macro + +@ifset GENERIC +@page +@node nanoMIPS-Dependent +@chapter nanoMIPS Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter nanoMIPS Dependent Features +@end ifclear + +@cindex nanoMIPS processor + +@menu +* nanoMIPS Options:: Assembler Options +* nanoMIPS Directives:: Assembler Directives +* nanoMIPS Reloc Operators:: Explicit Relocation Operators +* nanoMIPS Macros:: High-level Assembly Macros +* nanoMIPS Aliases:: 1:1 Instruction Aliases +* nanoMIPS Small Data:: Small Data Access +* nanoMIPS Relocations:: Using relocation operators for different + addressing modes +* nanoMIPS Instruction Selection:: Controlling Instruction Selection +* nanoMIPS Transformations:: Controlling Linker Relaxation +* nanoMIPS Syntax:: Syntactical Considerations +@end menu + +@node nanoMIPS Options +@section Assembler Options + +The nanoMIPS configurations of @sc{gnu} @code{@value{AS}} support these +special options: + +@table @code +@cindex -G option (nanoMIPS) +@item -G @var{num} +Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. +@xref{nanoMIPS Small Data, , Controlling the use of small data accesses}. + +@cindex @code{-EB} option (nanoMIPS) +@cindex @code{-EL} option (nanoMIPS) +@cindex nanoMIPS big-endian output +@cindex nanoMIPS little-endian output +@cindex big-endian output, nanoMIPS +@cindex little-endian output, nanoMIPS +@item -EB +@itemx -EL +Any nanoMIPS configuration of @code{@value{AS}} can select big-endian or +little-endian output at run time (unlike the other @sc{gnu} development +tools, which must be configured for one or the other). Use @samp{-EB} +to select big-endian output, and @samp{-EL} for little-endian. + +@item -march=@var{arch} +Generate code for a particular nanoMIPS @var{arch}, which can be the +name of a generic nanoMIPS @var{ISA} or the name of a particular +@var{CPU}. Valid @var{ISA} value are: + +@quotation +32r6, +32r6s, +64r6 +@end quotation + +Valid @var{CPU} value are: +@quotation +i7200, +nms1 +@end quotation + +@item -mtune=@var{cpu} +Schedule and tune for a particular nanoMIPS CPU. Valid @var{cpu} values are +identical to @samp{-march=@var{cpu}}. + +@item -m32 +Generate code for the p32 ABI. + +@item -m64 +Generate code for the p64 ABI. + +@item -mcmodel=@var{mmodel} +Generate code for a particular C Memory Model. The following memory models +are supported: @code{auto}, @code{medium}, @code{large} + +@item -mpic +@itemx -mno-pic +Generate medium model SVR4-style PIC. This option tells the assembler +to generate SVR4-style position-independent macro expansions. It also +tells the assembler to mark the output file as PIC. +@samp{-mno-pic} turns off this option. + +@item -mPIC +@itemx -mno-PIC +Generate large model SVR4-style PIC. This option tells the assembler +to generate SVR4-style position-independent macro expansions. It also +tells the assembler to mark the output file as PIC. +@samp{-mno-PIC} turns off this option. + +@item -mpid +@itemx -mno-pid +Generate position independent data. This option tells the assembler to +generate data sections that can be repositioned independent of code placement. +It also tells the assembler to mark the output file as PID. +@samp{-mno-pid} turns off this option. + +@item -mpcrel +@itemx -mno-pcrel +Generate PC-relative expansions. This option tells the assembler to +avoid the use of absolute addresses for symbols even when those +addresses may be known at link time. It also tells the assembler to +mark the output file as purely PC-relative. +@samp{-mno-pcrel} turns off this option. + +@item --linkrelax +Enable link-time relaxation features. The assembler will generate +additional relocations to allow the linker to expand/relax object +code and preserve correctness. + +@item -minsn32 +@itemx -mno-insn32 +Only use 32-bit instruction encodings. This option inhibits the use +of 16-bit and 48-bit instructions. This is equivalent to putting +@code{.module insn32} at the start of the assembly file. +@samp{-mno-insn32} turns off this option. This is equivalent to +putting @code{.module noinsn32} at the start of the assembly file. By +default @samp{-mno-insn32} is selected, allowing all instructions to +be used. + +@item -mmt +@itemx -mno-mt +Generate code for the MT Application Specific Extension. +This tells the assembler to accept MT instructions. +@samp{-mno-mt} turns off this option. + +@item -mvirt +@itemx -mno-virt +Generate code for the Virtualization Application Specific Extension. +This tells the assembler to accept Virtualization instructions. +@samp{-mno-virt} turns off this option. + +@item -msoft-float +@itemx -mhard-float +Disable or enable floating-point instructions. Note that by default +floating-point instructions are always allowed even with CPU targets +that don't have support for these instructions. + +@item -msingle-float +@itemx -mdouble-float +Disable or enable double-precision floating-point operations. Note +that by default double-precision floating-point operations are always +allowed even with CPU targets that don't have support for these +operations. + +@item --construct-floats +@itemx --no-construct-floats +The @code{--no-construct-floats} option disables the construction of +floating point constants in code by loading the values from memory +instead. + +By default @code{--construct-floats} is selected, allowing construction +of these floating point constants. + +@item -mbalc-stubs +@itemx -mno-balc-stubs +Consolidate multiple out-of-range call instructions to a function to +16-bit calls to a stub with transfers control to the function. The +@samp{-mbalc-stubs} option improves code compression at the cost +of performance, since each transformed call requires two control +transfers. + +This optimization is disabled by default. + +@item -mlegacyregs +Allow the use of legacy MIPS style numeric register formats in +nanoMIPS assembly. + +@item --trap +@itemx --no-break +@c FIXME! (1) reflect these options (next item too) in option summaries; + +@item --break +@itemx --no-trap +Generate code to take a break exception rather than a trap exception when an +error is detected. This is the default. + +@end table + +@node nanoMIPS Directives +@section Assembler Directives + +@menu +* nanoMIPS Controls:: Directives to control assembler behaviour & state +* nanoMIPS ISA:: Directives to override the ISA +* nanoMIPS CodeGen Concepts:: Directives to control memory model and addressing +* nanoMIPS CodeGen Specifics:: Directives to control code generation +* nanoMIPS DataGen:: Directives for data sections +* nanoMIPS Floating-Point:: Directives to override floating-point options +* nanoMIPS ASE Overrides:: Directives for generation of ASE instructions +* nanoMIPS Compatibility:: Directives for compatibility with MIPS assembly +@end menu + +@node nanoMIPS Controls +@subsection Directives to control assembler behaviour & state +@table @code +@item @code{.set} + +@cindex nanoMIPS option control +The @code{.set} directive allows changing various options that control +behaviour at any point within an assembly file. The syntax is identical +to the @code{.set} directive used to assign values to symbols. The +nanoMIPS assembler supports a number of built-in special symbols, which +when set to certain values change the behaviour of the assembler from +that point onwards. The change in the behaviour remains in effect till +the next @code{.set} directive which affects that particular behaviour. + +@item @code{.module} + +@cindex nanoMIPS module control +@kindex @code{.module} +The @code{.module} directive allows command line options to be set directly +from assembly. The format of the directive matches the @code{.set} +directive but only those options which are relevant to a whole module are +supported. The effect of a @code{.module} directive is the same as the +corresponding command line option. Where @code{.set} directives support +returning to a default then the @code{.module} directives do not as they +define the defaults. + +Module-level directives must appear first in assembly, before any +instructions. + +@item @code{.set push} +@itemx @code{.set pop} + +@cindex nanoMIPS option stack +@kindex @code{.set push} +@kindex @code{.set pop} +The directives @code{.set push} and @code{.set pop} may be used to save +and restore the current settings for all the options which are +controlled by @code{.set}. The @code{.set push} directive saves the +current settings on what can be considered a virtual assembler settings +``stack''. The @code{.set pop} directive pops the ``stack'' and restores +the assembler state to what it was before the most recent @code{.set push}. + +These directives can be useful inside an macro which must change an +option but does not want to change the state of the code which invoked +the macro. +@end table + +@node nanoMIPS ISA +@subsection Directives to override the ISA +@table @code +@cindex nanoMIPS CPU override +@item .set arch=@var{isa} +@kindex .set arch=@var{isa} +@itemx .set arch=@var{cpu} +@item .module arch=@var{isa} +@kindex .module arch=@var{isa} +@itemx .module arch=@var{cpu} +The @code{.set arch=@var{isa}} directive changes the effective CPU +target and allows the assembler to use instructions specific to a +particular ISA or CPU. All ISA and CPUs supported by the +@samp{-march} command line option are also selectable by this +directive. The original value is restored by @code{.set +arch=default}. + +Valid @var{isa} value are: +@quotation +32r6, +32r6s, +64r6 +@end quotation + +Valid @var{cpu} value are: +@quotation +i7200, +nms1 +@end quotation +@end table + +@node nanoMIPS CodeGen Concepts +@subsection Directives to control memory model and addressing +These directives indirectly control how built-in macros are expanded. +Some of them also set or clear corresponding flags in the ELF header. + +@table @code +@item .set mcmodel=auto +@itemx .set mcmodel=medium +@itemx .set mcmodel=large +@itemx .module mcmodel=auto +@itemx .module mcmodel=medium +@itemx .module mcmodel=large +@cindex Control code/data memory models +@kindex .set mcmodel=auto +@kindex .set mcmodel=medium +@kindex .set mcmodel=large +These directives specify the memory model that the assembler uses for +generating macro expansions. The directive @code{.set mcmodel=auto} +defers most decisions about the range of the code/data layout to +link-time relaxation. It requires linker relaxation to be enabled and +a capable linker. The directive @code{.set mcmodel=medium} assumes +that the GP-relative region (which includes the GOT in PIC) must not +exceed 2MiB and the total code size for a final link must not exceed +32MiB. The directive @code{.set mcmodel=large} implies no limits. +@c FIXME: not true for 64-bits, perhaps specify a 2GB limit. + +@item .set pic[012] +@itemx .module pic[012] +@kindex .set pic0 +@kindex .set pic1 +@kindex .set pic2 +@kindex .module pic0 +@kindex .module pic1 +@kindex .module pic2 +The @code{.set pic1} directive enables position independent code(PIC) +generation for built-in macros, using the medium memory model. The +@code{.set pic2} directive enables PIC generation, using the large +memory model. The @code{.set pic0} directive disables PIC generation. +If PIC is enabled, the corresponding flag in the ELF header is also set. +Position independent code generation is disabled by default. + +@item .set pid +@itemx .set nopid +@itemx .module pid +@itemx .module nopid +@kindex .set pid +@kindex .set nopid +@kindex .module pid +@kindex .module nopid +The @code{.set pid} directive enables the position independent +expansion of data addresses for built-in macros. It also sets the PID +flag in the ELF header. The @code{.set nopid} directive disables such +expansions. + +An object with the PID flag is guaranteed to not contain any absolute +or PC-relative references to data. All data references are through the +$gp register. Data sections can be re-positioned independent of code +sections by changing the value of @var{_gp}. This is disabled by +default. + +@item .set pcrel +@itemx .set nopcrel +@itemx .module pcrel +@itemx .module nopcrel +@kindex .set pcrel +@kindex .set nopcrel +@kindex .module pcrel +@kindex .module nopcrel +The @code{.set pcrel} directive enables the PC-relative expansion of +address calculation for built-in macros. It also sets the PC-relative +flag in the ELF header. The @code{.set pcrel} directive disables +PC-relative expansions. An object with the PC-relative flag is +guaranteed to not contain any absolute address calculation. This +is disabled by default. + +@item .linkrelax +@kindex .linkrelax +The @code{.linkrelax} directive enable linker relaxations for an +assembly unit. It also sets the LINKRELAX flag in the ELF header. +Linker relaxation is disabled by default. +@end table + + +@node nanoMIPS CodeGen Specifics +@subsection Directives to control code generation +@table @code + +@item .set insn32 +@itemx .set noinsn32 +@cindex nanoMIPS 32-bit instruction generation override +@kindex @code{.set insn32} +@kindex @code{.set noinsn32} +The directive @code{.set insn32} makes the assembler use only 32-bit +instruction encodings when generating code for the nanoMIPS processor. +This directive inhibits the use of any 16-bit or 48-bit instructions +from that point on in the assembly. The @code{.set noinsn32} directive +allows 16-bit and 48-bit instructions to be accepted. + +@item .set reorder +@itemx .set noreorder +@cindex Compatibility with MIPS instruction re-ordering +@kindex @code{.set reorder} +@kindex @code{.set noreorder} +The traditional MIPS assembler uses re-ordering of instructions to fill +delay slots in delayed branch instructions. If reordering is enabled, +the assembler can move an instruction above a delayed branch +instructions in to the delay slot of the instruction. If it is disabled, +the assembler must insert a nop instruction in the delay slot, to +satisfy pipeline constraints. Where the assembler is not free to adjust +the user-specified order of instructions, a NOP is inserted in the +delay slot instead. + +The nanoMIPS architecture does not have delayed instructions. The branch +instructions are termed as compact (as opposed to delayed) branch +instructions. The assembler does provide aliases from delayed to compact +branch mnemonics for portability, however it cannot simply gloss over +semantic differences between the two. The nanoMIPS assembler will +attempt to convert a delayed branch to a compact branch. With +re-ordering enabled, this is simply interpreting one instruction +mnemonic (bal) as another (balc). With reordering disabled, the +conversion is only possible if the instruction in the delay slot is a +NOP instruction, since the NOP can be trivially dropped without changing +the effect of an assembly fragment. + +The following table compares the behaviour of MIPS and nanoMIPS for +commonly encountered input patterns: + +@multitable @columnfractions 0.2 0.2 0.2 0.2 0.2 +@headitem +Input assembly +@tab +Generated MIPS object +@tab +Remarks +@tab +Generated nanoMIPS object +@tab +Remarks +@item +@item +@smallformat +@verbatim +.set reorder +move $a0,$s0 +bal $ra,foo +@end verbatim +@end smallformat +@tab +@smallformat +@verbatim +bal $ra,foo +move $a0,$s0 +@end verbatim +@end smallformat +@tab +Instructions re-ordered to fill delay slot. Move happens before control +transfer due to delayed branch semantics. +@tab +@smallformat +@verbatim +move $a0,$s0 +balc $ra,foo +@end verbatim +@end smallformat +@tab +Delayed branch converted to compact branch. +@item +@smallformat +@verbatim +.set reorder +move $a0,$s0 +beq $a0,$a1,foo +@end verbatim +@end smallformat +@tab +@smallformat +@verbatim +move $a0,$s0 +beq $a0,$a1,foo +nop +@end verbatim +@end smallformat +@tab +Re-ordering inhibited by dependency. NOP inserted automatically to fill +delay slot. +@tab +@smallformat +@verbatim +move $a0,$s0 +beqc $a0,$a1,foo +@end verbatim +@end smallformat +@tab +Delayed branch converted to compact branch. +@item +@smallformat +@verbatim +.set noreorder +move $a0,$s0 +bal $ra, foo +nop +@end verbatim +@end smallformat +@tab +@smallformat +@verbatim +move $a0,$s0 +bal $ra, foo +nop +@end verbatim +@end smallformat +@tab +Explicit NOP in delay slot +@tab +@smallformat +@verbatim +move $a0,$s0 +balc $ra,foo +@end verbatim +@end smallformat +@tab +Delayed branch converted to compact branch, NOP removed. +@item +@smallformat +@verbatim +.set noreorder +bal $ra, foo +move $a0,$s0 +@end verbatim +@end smallformat +@tab +@smallformat +@verbatim +bal $ra, foo +move $a0,$s0 +@end verbatim +@end smallformat +@tab +Explicit instruction in delay slot. +@tab +- +@tab +Signal error. Cannot convert to compact branch. +@item +@smallformat +@verbatim +.set noreorder +move $a0,$s0 +bal $ra, foo +@end verbatim +@end smallformat +@tab +@smallformat +@verbatim +move $a0,$s0 +bal $ra, foo + +@end verbatim +@end smallformat +@tab +Unpredictable or illegal instruction in delay slot +@tab +@smallformat +@verbatim +move $a0,$s0 +balc $ra,foo +@end verbatim +@end smallformat +@tab +Delayed branch converted to compact branch, NOP removed. +@end multitable + +Finding a useful operations to perform in delay slots is important to +get the best performance from the execution pipeline on MIPS +architecture. Traditionally, MIPS assembly programmers have preferred to +control the utilization of delay slots directly, rather than rely on the +assembler. A lot of handwritten MIPS assembly follows the pattern in row +4 above. Here reordering is disabled and the instruction in the delay +slot is not a NOP. The nanoMIPS assembler will fail to convert the +delayed branch to a compact branch and will signal an error. + +Reversing the order of the branch and the subsequent instruction is +sufficient for the nanoMIPS assembler, as in row 5 above. However the +output will behave unpredictably when assembled for MIPS, because +whatever instruction or data happens to be in the delay slot position in +the output will get executed before the branch. The safest and most +reliable alternative is row 1. It delegates maximum control to the +assembler and generates the most efficient code for both MIPS and +nanoMIPS. Note that re-ordering is enabled by default on both MIPS and +nanoMIPS. If it is not disabled any where preceding a branch fragment, +it need not be explicitly re-enabled for each branch. + +@item @code{.set linkrelax} +@itemx @code{.set nolinkrelax} +@cindex Directives to control linker relaxation over a region +@kindex @code{.set linkrelax} +@kindex @code{.set nolinkrelax} +The directive @code{.set linkrelax} emits a place-holder to indicate +that linker relaxations are enabled in the following region. When +relaxation is enabled, the assembler will emit additional relocations +to direct the linker. The @code{.set nolinkrelax} directive emits +a place-holder to indicate that linker relaxations are disabled in the +following region. + +@item @code{.set legacyregs} +@itemx @code{.set nolegacyregs} +@cindex nanoMIPS legacy register names +@kindex @code{.set legacyregs} +@kindex @code{.set nolegacyregs} +The directive @code{.set legacyregs} allows the use of MIPS-compatible +numeric register formats. The names and usage conventions of general +purpose registers for the nanoMIPS ABI is different from the MIPS +ABI. The nanoMIPS assembler rejects numeric formats by default, to +force the user to re-think register usage when porting MIPS code. The +@code{.set nolegacyregs} directive disables these register +identifiers. + +@item @code{.set macro} +@itemx @code{.set nomacro} +@kindex @code{.set macro} +@kindex @code{.set nomacro} +Some times it is undesirable to have one assembly instruction expand +to several machine instructions. The directive @code{.set nomacro} +tells the assembler to prohibit such expansions. @code{.set macro} +restores the default behavior. Note that this behaviour is a departure +from the MIPS assembler which only warns about generation of macros +after @code{.set nomacro}. + +@item @code{.set at=@var{reg}} +@cindex @code{at} register, nanoMIPS +@kindex @code{.set at=@var{reg}} +Some macro instructions need a temporary register to store intermediate +results. This register is usually @code{$r1}, also known as @code{$at}, +but it can be changed to any core register @var{reg} using +@code{.set at=@var{reg}}. Note that @code{$at} always refers +to @code{$r1} regardless of which register is being used as the +temporary register. + +@item @code{.set at} +@itemx @code{.set noat} +@kindex @code{.set at} +@kindex @code{.set noat} +Implicit uses of the temporary register in macros could interfere with +explicit uses in the assembly code. The assembler therefore warns +whenever it sees an explicit use of the temporary register. The directive +@code{.set noat} silences this warning while @code{.set at} restores +the default behavior. It is safe to use @code{.set noat} while +@code{.set nomacro} is in effect since single-instruction macros +never need a temporary register. + +@item .cpsetup +@cindex nanoMIPS GP-setup +@kindex @code{cpsetup} + +This directive maps to the GP-setup sequence for position independent +code. + +@example +lapc.b $gp, _gp +@end example + +@end table + +@node nanoMIPS DataGen +@subsection Directives for data sections +@table @code + +@item @code{.bss} +@cindex Zero-initialized data +@kindex @code{.bss} +The @code{.bss} directive starts the declaration of a zero-initialized +data section. This can also be achieved using the @code{.section} +directive. It is provided for compatibility with MIPS. + +@item @code{.sbss} +@cindex Zero-initialized data +@kindex @code{.sbss} +The @code{.sbss} directive starts the declaration of a zero-initialized +small data section. This can also be achieved using the @code{.section} +directive. It is provided for compatibility with MIPS. + +@item @code{.rdata} +@cindex Read-only data +@kindex @code{.rdata} +The @code{.rdata} directive starts the declaration of a read-only data +section. This can also be achieved using the @code{.section} +directive. It is provided for compatibility with MIPS. + +@item @code{.sdata} +@cindex Small data +@kindex @code{.sdata} +The @code{.sdata} directive starts the declaration of an initialized +small data section. This can also be achieved using the @code{.section} +directive. It is provided for compatibility with MIPS. + +@item @code{.sbyte} +@cindex Signed byte expressions +@kindex @code{.sbyte} +@code{.sbyte} expects zero or more expressions, separated by commas. +Each expression is assembled into the next byte, similar to @code{.byte} +psuedo-op. The GNU assembler interprets all expressions are unsigned by +default. If the expression for @code{.sbyte} consists of a +label-difference, the assembler will emit necessary relocation to +interpreted the result as a signed 8-bit value. + +@item @code{.shword} +@cindex Signed half-word expressions +@kindex @code{.shword} +@code{.shword} expects zero or more expressions, separated by commas. +Each expression is assembled into the next half-word, similar to +@code{.hword} psuedo-op. If the expression consists of a +label-difference, the assembler will emit necessary relocation to +interpreted the result as a signed 16-bit value. + +@item @code{.ehword} +@cindex Exception handler address +@kindex @code{.ehword} expects a symbol. sThe directive allocates a +word-sized memory region and emits a PC-relative relocation to +calculate the address of that symbol. +@end table + +@node nanoMIPS Floating-Point +@subsection Directives to override floating-point options + +@table @code +@item .gnu_attribute 4,[0123] +The directives @code{.gnu_attribute 4,} selects one of the supported +FP ABIs. @xref{Supported FP ABIs}. + +@item .set softfloat +@itemx .set hardfloat +@itemx .module softfloat +@itemx .module hardfloat +@kindex @code{.set softfloat} +@kindex @code{.set hardfloat} +@kindex @code{.module softfloat} +@kindex @code{.module hardfloat} +The directives @code{.set softfloat} and @code{.set hardfloat} provide +finer control of disabling and enabling float-point instructions. +These directives always override the default (that hard-float +instructions are accepted) or the command-line options +(@samp{-msoft-float} and @samp{-mhard-float}). + +@item .set singlefloat +@itemx .set doublefloat +@itemx .module singlefloat +@itemx .module doublefloat +@kindex @code{.set singlefloat} +@kindex @code{.set doublefloat} +@kindex @code{.module singlefloat} +@kindex @code{.module doublefloat} +The directives @code{.set singlefloat} and @code{.set doublefloat} +provide finer control of disabling and enabling double-precision +float-point operations. These directives always override the default +(that double-precision operations are accepted) or the command-line +options (@samp{-msingle-float} and @samp{-mdouble-float}). + +@end table + +@anchor{Supported FP ABIs} @subsubsection Supported FP ABIs +The supported floating-point ABI variants are: + +@table @code +@item 0 - No floating-point +This variant is used to indicate that floating-point is not used within +the module at all and therefore has no impact on the ABI. This is the +default. + +@item 1 - Double-precision +This variant indicates that double-precision support is used. This means +that 64-bit wide floating-point registers are required. + +@item 2 - Single-precision +This variant indicates that single-precision support is used. Double +precision operations will be supported via soft-float routines. + +@item 3 - Soft-float +This variant indicates that although floating-point support is used all +operations are emulated in software. This means the ABI is modified to +pass all floating-point data in general-purpose registers. + +@end table + +@node nanoMIPS ASE Overrides +@subsection Directives for generation of ASE instructions + +@table @code + +@item .set mt +@itemx .set nomt +@itemx .module mt +@itemx .module nomt +@cindex nanoMIPS MT instruction generation override +@kindex @code{.set mt} +@kindex @code{.set nomt} +@kindex @code{.module mt} +@kindex @code{.module nomt} +The directive @code{.set mt} makes the assembler accept instructions +from the Multi Threading Application Specific Extension from that point +on in the assembly. The @code{.set nomt} directive prevents MT +instructions from being accepted. + +@item .set virt +@itemx .set novirt +@itemx .module virt +@itemx .module novirt +@cindex Virtualization instruction generation override +@kindex @code{.set virt} +@kindex @code{.set novirt} +@kindex @code{.module virt} +@kindex @code{.module novirt} +The directive @code{.set virt} makes the assembler accept instructions +from the Virtualization Application Specific Extension from that point +on in the assembly. The @code{.set novirt} directive prevents Virtualization +instructions from being accepted. + +@end table + +@node nanoMIPS Compatibility +@subsection Directives for compatibility with MIPS assembly + +These assembler directives are accepted without any verification or +effect, for compatibility with MIPS. +@table @code +@item .cpadd +@item .cpload +@item .cplocal +@item .crestore +@item .cpreturn +@item .set nomips16 +@item .set noMIPS-16 +@item .set nomicromips +@item .set move +@item @code{.set nomove} +@item .set volatile +@item .set novolatile +@item .set nobopt +@item .set noforbidden-slots +@item .set oddspreg +@end table + +@node nanoMIPS Reloc Operators +@section Explicit Relocation Operators +@table @code +@item %lo + +Unsigned 12-bit low-part of 32-bit value. +@example +%lo(@var{X}) = @var{X} & 0xfff +@end example +@item %hi + +Signed 20-bit high-part of 32-bit value. +@example +%hi(@var{X}) = @var{X} & 0xfffff000 +@end example +@item %gprel + +GP-relative displacement, size depends on type of operation and data layout. +@item %gprel_hi +Signed 20-bit high part of a GP-relative displacement. +@item %gprel_lo +Unsigned 12-bit low part of a GP-relative displacement. +@item %got_disp +19-bit (scaled) GOT displacement for address calculation or data access. +@item %got_call +19-bit (scaled) GOT displacement to load address for a function call. +@item %got_pcrel_hi +Signed 20-bit high part of GOT displacement from next PC. +@item %got_pcrel_lo +Unsigned 12-bit low part of GOT displacement. +@item %got_pcrel32 +Full 32-bit signed GOT displacement from next PC. +@item %got_page +Marks the first level of indirection for GOT-relative data access +(either a load or a store). This is relaxed out by the linker. +@item %got_ofst +Marks the second level of indirection for GOT-relative data access +(either a load or a store). +@item %pcrel_hi +Signed 20-bit high part of PC-relative displacement. +@item %pcrel_lo +Unsigned 12-bit low part of PC-relative displacement. Map to @code{%lo}. + +@item %tlsgd +GP-relative displacement to global dynamic TLS slot, size depends on +type of operation. + +@item %tlsld + +GP-relative displacement to local dynamic TLS slot, size depends on type +of operation. + +@item %dtprel + +Unsigned offset to a thread-local dynamic variable from current thread +pointer, size depends on type of operation. + +@item %tprel + +Unsigned offset to a thread-local static variable from current thread +pointer, size depends on type of operation. + +@item %gottprel + +19-bit (scaled) GOT displacement to a TLS slot. + +@item %gottprel_pc32 + +Full 32-bit signed GOT displacement to a TLS slot from next PC. + +@item %gp_rel + +Provided for compatibility with MIPS. Map to @code{%gprel}. + +@item %call16 + +Provided for compatibility with MIPS. Map to @code{%got_call}. + +@item %got + +Provided for compatibility with MIPS. Map to @code{%got_disp}. +@end table + +@include c-nanomips-macros.texi + +@include c-nanomips-aliases.texi + +@node nanoMIPS Small Data +@section Small Data Access + +@cindex small data, nanoMIPS +@cindex @code{gp} register, nanoMIPS +It often takes multiple instructions to load data from a symbol. +For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion +of @samp{lw $a0,addr} is usually: + +@example +lui $a0,%hi(addr) +lw $a0,%lo(addr)($a0) +@end example + +The sequence is longer when @samp{addr} is a 64-bit symbol. + +In order to cut down on this overhead, nanoMIPS architecture allows the +programmer to set aside a 2 megabyte ``small data'' area and guarantees +that all data of size @var{n} and smaller will be placed in that area. +The limit @var{n} is passed to both the assembler and the linker using +the command-line option @option{-G @var{n}}, @pxref{nanoMIPS Options,, +Assembler options}. Note that the same value of @var{n} must be used +when linking and when assembling all input files to the link; any +inconsistency could cause a relocation overflow error. + +The size of an object in the @code{.bss} section is set by the +@code{.comm} or @code{.lcomm} directive that defines it. The size of +an external object may be set with the @code{.extern} directive. For +example, @samp{.extern sym,4} declares that the object at @code{sym} +is 4 bytes in length, while leaving @code{sym} otherwise undefined. + +When no @option{-G} option is given, the default limit is 8 bytes. +The option @option{-G 0} prevents any data from being automatically +classified as small. + +It is also possible to mark specific objects as small by putting them in +the special sections @code{.sdata}, @code{.ssdata}, @code{.sbss} and +@code{.ssbss}, which are ``small'' counterparts of @code{.data} and +@code{.bss} respectively for different types of data. The toolchain +will treat such data as small regardless of the @option{-G} setting. + +On startup, systems that support a small data area are expected to +initialize register @code{$r28}, also known as @code{$gp}, in such a +way that small data can be accessed using a 21-bit offset from that +register for word/double-word types. The offset restriction is 18-bits +in the case of sub-word and floating point types. For example, when +@samp{addr} is small data, the @samp{lw $a0,addr} instruction above is +equivalent to: + +@example +lw $a0,%gprel(addr)($gp) +@end example + +Small data is also supported for SVR4-style PIC. + +@node nanoMIPS Relocations +@section Using relocation operators for different addressing modes + +@menu +* Optimized GP-relative access:: +* General GP-relative access:: +* 32-bit absolute addressing and immediate construction:: +* PC-relative addressing:: +* Indirect addressing for small PIC model:: +* Indirect addressing for large PIC model:: +@end menu + +@node Optimized GP-relative access +@subsection Optimized GP-relative access + +The nanoMIPS architecture allows various fundamental data types, up to +16 bytes in size, to be accessed directly relative to the designated +Global Pointer ($gp) register. GP-relative access allows for data +load/store and address calculations to be performed in a single 16 or +32-bit instruction, using an offset from the $gp register. The range +of the offset and hence the size of the reachable GP-relative region, +also called the small data region, varies with the type, size and +alignment of the data object being accessed. These limits form the +basis of the medium memory model. + +@multitable @columnfractions .4 .6 +@headitem Data type @tab GP-relative offset range +@item aligned word @tab 19-bit scaled (2MiB) +@item aligned dword @tab 18-bit scaled (2MiB) +@item aligned half-word @tab 17-bit scaled (512KiB) +@item aligned float @tab 16-bit scaled (512KiB) +@item [word] aligned double @tab 16-bit scaled (512KiB) +@item unaligned word @tab 18-bit (512KiB) +@item unaligned dword @tab 18-bit (512KiB) +@item unaligned half-word @tab 18-bit (512KiB) +@item byte @tab 18-bit (512KiB) +@end multitable + +The object file contains relocations which the linker attempts to +resolve when doing the data layout. Even with the medium memory model, +there is no guarantee that all GP-relative accesses will be +optimized. If the linker can not find a data layout that allows all +GP-relative accesses to be optimized, it will either + +@itemize +@item +Expand some accesses to use multiple instructions: this indicates that +although the total amount of small data is less than 2MB, the offset +range requirements for all types/alignment cannot be satisfied. The +linker can rewrite some accesses to use multiple +instructions. However, if expansion is inhibited or not implemented, +the link will fail. +@item +Fail to link: this indicates that the total amount of small data is +greater than 2MB. The solution is to recompile using either the +large or the automatic memory model. +@end itemize + +Thus, the linker has final control of whether optimized GP-relative +access is viable. Assembler directives can be used to disallow +expansions at either module-level or per-access. +@xref{nanoMIPS Transformations, ,Controlling Linker Relaxation}. +Assembly language syntax for requesting GP-relative access consists +of 2 elements: +@subsubsection Explicitly requested GP-relative access + +The user can explicitly request GP-relative access with the %gprel +relocation operator. This operator can only be used for load/store +instructions with $gp as the base register or address calculation with +$gp as a source operand. The assembler will match the operation and +select the an appropriate relocation for each access. Examples: +@example + lw $a0, %gprel(foo)($gp) + l.s $f0, %gprel(bar)($gp) + addiu $a0, $gp, %gprel(foo) +@end example + +By itself, this does not guarantee that foo will end up within the +small data region. If the layout is such that it happens to be within +range, the link will succeed. Otherwise the linker may fail or expand +the operation to multiple instructions, as explained above. +@subsubsection Implicit GP-relative access through canonical named sections + +Small data sections are typically named `.sbss'/`.ssbss' +(zero-initialized) or `.sdata'/`.ssdata'. The linker places these +sections close to $gp and complains if they are outside the GP-relative +range. If access to an object within a small data sections is made by +assembler macros, where the addressing mode is unspecified, the +assembler will choose a GP-relative expansion. + +@example + lw $a0, foo + @expansion{} lw $a0, %gprel(foo) ($gp) + + la $a0, bar + @expansion{} addiu $a0, $gp, %gprel(foo) +@end example +Declaration of data in small data sections can be achieved by naming +sections using the @code{.section} directive or by +@code{comm/lcomm/extern} declarations, provided the declared size of the +object is less than the small data limit specified by @code{-Gnum}. + +Compiler generated code uses a combination of data declaration in named +small data sections and explicitly requested GP-relative access in +instructions in order to guarantee GP-relative access. + +@node General GP-relative access +@subsection General GP-relative access + +If optimized access is not an objective, the full 32-bit address space +is reachable by GP-relative addressing. This corresponds to the large +memory model. For address calculation with full nanoMIPS ISA, use the +48-bit instruction + +@example + lui $a0, %gprel_hi (foo) + ori $a0, $a0, %gprel_lo(foo) + addu $a0, $a0, $gp +@end example + +For loads/stores use the following sequence: + +@example + lui $a0, %gprel_hi (foo) + addu $a0, $a0, $gp + lw $a0, %gprel_lo(foo) ($a0) +@end example + +With a linker capable of doing expansions, the preferred approach is +to use the automatic memory model with optimized GP-relative +sequences. The linker will convert select accesses to non-optimized +sequences where necessary. + + +@node 32-bit absolute addressing and immediate construction +@subsection 32-bit absolute addressing and immediate construction + +The nanoMIPS assembler provides macros which automatically find the +best way to materialize an address of immediate value in a +register. The macros are called li and la for constants and addresses +respectively. This section demonstrates explicit coding methods for +predictable code size and addressing modes. + +Address calculation for full nanoMIPS ISA with 48-bit instructions can +trivially be done with + +@example + li $a0, foo +@end example + +With only 32-bit instructions or when restricted to the nanoMIPS +subset, use the following combination: + +@example + lui $a0, %hi(foo) + ori $a0, %lo(foo) +@end example + +Immediate construction for full nanoMIPS ISA can be trivially done with: + +@example + li $a0, @var{imm} +@end example + +Here, depending on the immediate value, the assembler will pick a +16-bit, 32-bit or 48-bit instruction. + +For immediate construction using only 32-bit instructions, or when +restricted to the nanoMIPS subset, the preferred option is: + +@example + lui $a0, %hi(@var{imm}) + ori $a0, %lo(@var{imm}) +@end example + +This sequence breaks the immediate value in to a 20-bit high part and +a 12-bit unsigned low part. However, the traditional (16-bit high + +16-bit signed-low) form, typical to MIPS, is also supported: + +@example + lui $a0, @code{imm_hi16} + addiu $a0, @code{imm_lo16} +@end example + +Here, +@display +@code{imm_lo16} = (short) @code{imm} and @code{imm_hi16} = ((@code{imm} - @code{imm_lo16}) >> 16) +@end display +These interpretations borrow from the definition of %hi & %lo on +MIPS, so that MIPS code can continue to work correctly on +nanoMIPS. Note the use of ADDIU instruction for the signed low-part. + +@node PC-relative addressing +@subsection PC-relative addressing + +Address calculation within a +-1MB region of current PC can be done +with a single 32-bit instruction: + +@example + lapc.h $a0, foo +@end example + +For full nanoMIPS ISA, the example below selects a 48-bit instruction +which can reach any address within 32-bits (+-2GB) of the PC. + +@example + lapc.b $a0, foo +@end example + +For address calculation using only 32-bit instructions, or when +restricted to the nanoMIPS subset, use: + +@example + aluipc $a0, %pcrel_hi (foo) + ori $a0, $a0, %lo(foo) +@end example + +The ALUIPC instruction generates a 4k-aligned address, unlike +MIPS. This can be considered as the address of the 4k page that +contains the address foo. The subsequent ORI introduces the offset +within that 4k page and is not really PC-relative. The user can insert +any number of instructions between the high & low part calculations +above, without having to adjust the addend for the low part. Owing to +these differences, the typical MIPS PC-relative address calculation +fragment below will NOT work correctly on nanoMIPS: + +@example + aluipc $a0, %pcrel_hi (foo) ; not 4k-aligned + ori $a0, $a0, %pcrel_lo(foo+4) ; addend reflects difference in + ; PC of high and low steps +@end example + +PC-relative address calculation typically needs more power than the +corresponding absolute address calculation. The latter should be +preferred for low-power applications, whenever possible. + +@node Indirect addressing for small PIC model +@subsection Indirect addressing for small PIC model (-fpic) + +The linker places the GOT section in the small data area. GOT entries +can be directly accessed as: + +@example + lw $a0, %got_disp (foo) ($gp) +@end example + +This mechanism is agnostic to symbol visibility or preemption. A +capable linker will relax or expand the sequence to optimized the +access. The linker may also place small data directly in the +GP-relative region, so even when the GOT section is less than 2MiB, it +may be too big to satisfy medium memory model constraints. + +@node Indirect addressing for large PIC model +@subsection Indirect addressing for large PIC model (-fPIC) + +When the GOT spills out of the GP-relative range, 32-bit displacements +are required. Calculating displacements relative to the PC instead of +GP is preferred, since it gives shorter load sequences. For the full +nanoMIPS ISA, this can be done with a single 48-bit instruction: + +@example + lwpc $a0, %got_pcrel32 (foo) +@end example + +For address calculation using only 32-bit instructions, or when +restricted to the nanoMIPS subset, use: + +@example + aluipc $a0, %got_pcrel_hi (foo) + lw $a0, %got_lo (foo) ($a0) +@end example + +As with GP-relative access, the preferred approach is to use small PIC +sequences and let the linker convert select accesses to large PIC +sequences where necessary. + +@node nanoMIPS Instruction Selection +@section Controlling Instruction Selection + +@subsection Syntax for instruction selection + +The nanoMIPS ISA can use the same primary mnemonic to denote multiple +target instructions. This happens when the ISA has encodings of an +instruction with different instruction sizes, or of same instruction +size but with different operand types. The assembler syntax allows 2 +ways for the user to specify the target instruction for such a +mnemonic: + +@enumerate +@item +Size-suffixes (16/32/48) can be used to force the instruction size. If +there is no instruction of the specified size of if the operands do +not match for that size, the instruction will be rejected. It is +guaranteed that neither the assembler nor the linker will expand an +explicitly sized instruction in to multiple instructions. The linker +may still translate this instruction to another, more efficient +instruction of the same size. + +@example + balc16 foo # 16-bit call, fails if foo is outside + # 11-bit signed range + li32 $a0, 100 # force 32-bit instruction even though + # 16-bit encoding is possible + addiu48 $a0, $a1, 1000 # force 48-bit instruction even + # though 32-bit encoding is possible +@end example + +By default, the assembler will always select the smallest sized +instruction for the given operands. Size suffixes are useful when +constructing branch tables, to ensure that all blocks within the table +have the same size. + +@item +Format suffixes from the architecture reference manual can also be +used to select a specific encoding. Suffixes are enclosed in square +brackets, matching the convention used in the architecture +reference. If the operands do not match the format suffix, the +instruction will be rejected. It is guaranteed that neither the +assembler nor the linker will expand an explicitly selected +instruction in to multiple instructions or translate it in to any +other instruction. + +@example + addiu[gp.w] $a0, $gp, %gprel(foo) # word-aligned GP-relative + # address calculation + lw[s9] $a0, 128($a1) # load word with signed 9-bit offset even + # when unsigned 12-bit is possible + addu[4x4] $s2, $s3, $s2 # select 4-bit register encoding +@end example + +The ability to specify format suffixes serves little practical +purpose, since the tools will try to find the most efficient encoding +for an operation. It is provided as an aid for development and +testing. For example, the @code{[4x4]} suffix in the case above forces the +assembler to check whether the operands satisfy the requested +encoding. +@end enumerate + +@subsection Options to control instruction disassembly + +The assembler provides multiple instruction formats and mnemonics to +target the same instruction encoding by means of 1:1 aliases. There +are 2 disassembler options that control how instructions may be +disassembled: + +@table @code +@item -Mno-aliases +Disassembles all variants of an instruction to its most generic +representation + +@item -Mshow-arch-insn +Prints the format suffix for each instruction in square brackets +according to the architecture reference manual. This only affects the +disassembly of those instructions that have format suffixes. +@end table + +@node nanoMIPS Transformations +@section Controlling Linker Relaxation + +nanoMIPS ABI provides support for linker relaxations and +expansions. Relaxation means that the linker can remove a group of +instructions (typically, 1 or 2) or translate them in to more +efficient sequences. Expansion is the translation of an instruction +which would be out-of-range due to code or data layout, in to a +sequence capable of expressing the necessary extended range. The +assembler provides directives and command-line options to control +linker transformations. + +@menu +* nanoMIPS relax modules:: Module level control +* nanoMIPS relax fragments:: Controlling relaxation of code fragments +* nanoMIPS relax special:: Special handling of assembly constructs +@end menu + +@node nanoMIPS relax modules +@subsection Module level control + +Linker relaxations is disabled by default in the assembler. It can be +enabled for an assembly unit using the command-line option +@option{--linkrelax} The assembly directive @code{.linkrelax'} also +has the same effect. It must be specified before any instruction in +the assembly file. + +@node nanoMIPS relax fragments +@subsection Controlling relaxation of code fragments + +@subsubsection Control by blocks + +The directive @code{.set nolinkrelax} can be used to inhibit relaxation +within an assembly file, until a corresponding @code{.set linkrelax} +directive is encountered. This is only effective when linker +relaxation is enabled for the assembly unit. This can be used for +low-level code which employs fixed PC-relative offsets or for vectored +tables where each code element must be of the same fixed size. These +directives cause the assembler to emit relocations to mark the point +where relaxation is to be enabled or disabled. + +For example, the following fragment disables linker relaxation only +for the setup and call to foo: + +@example + .set nolinkrelax + beq $a0, $a1, 8 + move $a0, $t8 + sw $a4, 0($t8) + balc foo + .set linkrelax +@end example + +The following fragment disables linker relaxation for the function foo: +@example + .text + .set nolinkrelax + .type foo,@@function + foo: + ... + jr $ra + .set linkrelax +@end example + +@subsubsection One instruction at a time + +Each instruction can be marked to say that no relaxation or +transformation is to be performed on this instruction. This is done +the creating an explicit @samp{R_NANOMIPS_FIXED} relocation for +it. This is automatically extended to cases where the user requests an +instruction with a specific encoding. For example, both fragments +below have the same effect, which is to disallow any kind of +transformation by the linker, even as the PC-relative relocation gets +fixed up correctly. + +@example + .reloc 1f, R_NANOMIPS_FIXED + 1: lapc $a0, foo +@end example + +@example + lapc[32] $a0, foo +@end example +@subsubsection By instruction size + +It is possible to let the linker perform translations while keeping +the instruction size fixed. The assembler does this automatically when +an instruction has a size-suffix. This is useful for creating branch +tables or vector tables, where each element is required to have the +same size, specified at assembly time. For example, +@example + vtable: + bc32 foo + bc32 bar + bc32 baz +@end example +@node nanoMIPS relax special +@subsection Special handling of assembly constructs + +Certain assembly constructs need special handling by way of marker +relocations to allow linker translations to happen correctly. The +objective is to capture all the information necessary to preserve +correctness, that is available at assembly time but not available at +link time. + +@subsubsection Alignment Directives + +Alignment directives have the effect of padding the location counter +to a specific boundary. The GNU assembler also accepts a fill pattern +to be used for the padding and the maximum amount of padding to be +inserted. When the linker expands or relaxes instructions, any +alignment point following those instructions is liable to move. If the +alignment point moves backwards, some of the padding inserted by the +assembler can be removed. If it move forward, more padding, possibly +of a user-specified pattern needs to be inserted. In this case, the +total amount of padding, including what is inserted by the assembler +and the linker, must not exceed the user-specified maximum +padding. The assembler will emit an @samp{R_NANOMIPS_ALIGN} relocation +for each alignment point and an @samp{R_NANOMIPS_FILL} relocation +where user-specified padding is required. The exact details of the +alignment and padding relocations are covered in the nanoMIPS P32 psABI +supplement. + +@subsubsection Save/restore markers + +The nanoMIPS ABI allows SAVE & RESTORE instructions to be relaxed from +32-bit to 16-bit encodings as a consequence of GP-setup +optimization. These instructions are not relocated, so the linker +needs additional markers to be emitted in order to find these +instructions. These markers are needed only when generating position +independent code, if the assembler selects a 32-bit encoding for a +SAVE or RESTORE operation and saves $gp. These markers are emitted +automatically by the assembler when relaxations are enabled. + +@subsubsection Label-difference expressions + +Label difference expressions are used to create jump tables and +calculate code offsets. If any code between 2 labels undergoes +relaxation or expansion, the difference between the labels can +change. On the other hand, if there is no relocation or relaxable code +between 2 labels, then their difference can be considered as constant, +or fixed at assembly. A label difference that can change due to +relaxation must be represented by relocations so that it may be +re-calculated after relaxation. The assembler takes care of deciding +if label difference relocations are needed and emitting them, so the +user can use label differences in assembly code even in the presence +of linker relaxation. + +@node nanoMIPS Syntax +@section Syntactical Considerations +@menu +* nanoMIPS-Chars:: Special Characters +@end menu + +@node nanoMIPS-Chars +@subsection Special Characters + +@cindex line comment character, nanoMIPS +@cindex nanoMIPS line comment character +The presence of a @samp{#} on a line indicates the start of a comment +that extends to the end of the current line. + +If a @samp{#} appears as the first character of a line, the whole line +is treated as a comment, but in this case the line can also be a +logical line number directive (@pxref{Comments}) or a +preprocessor control command (@pxref{Preprocessing}). + +@cindex line separator, nanoMIPS +@cindex statement separator, nanoMIPS +@cindex nanoMIPS line separator +The @samp{;} character can be used to separate statements on the same +line. diff --git a/ld/gen-doc.texi b/ld/gen-doc.texi index 561869f485a..2c98698482a 100644 --- a/ld/gen-doc.texi +++ b/ld/gen-doc.texi @@ -15,6 +15,7 @@ @set M68HC11 @set M68K @set MIPS +@set nanoMIPS @set MMIX @set MSP430 @set NDS32 diff --git a/ld/ld.texi b/ld/ld.texi index 9d6618a4307..caf4d7e4a8e 100644 --- a/ld/ld.texi +++ b/ld/ld.texi @@ -27,6 +27,7 @@ @set M68HC11 @set M68K @set MIPS +@set nanoMIPS @set MMIX @set MSP430 @set NDS32 @@ -152,6 +153,9 @@ in the section entitled ``GNU Free Documentation License''. @ifset MIPS * MIPS:: ld and MIPS family @end ifset +@ifset nanoMIPS +* nanoMIPS:: ld and nanoMIPS family +@end ifset @ifset POWERPC * PowerPC ELF32:: ld and PowerPC 32-bit ELF Support @end ifset @@ -3990,6 +3994,39 @@ executables. If a shared library is generated with a DSBT index of 0, the The @samp{--no-merge-exidx-entries} switch disables the merging of adjacent exidx entries in frame unwind info. +@kindex --compact-branches +@item --compact-branches +@kindex --no-compact-branches +@item --compact-branches +These options control the generation of compact instructions by the linker +in the PLT entries for MIPS R6. + +@end table + +@c man end +@end ifset + +@ifset nanoMIPS +@subsection Options specific to nanoMIPS targets + +@c man begin OPTIONS + +The following options are supported to control link time expansion and +relaxation rules. + +@table @gcctabopt + +@kindex --insn32 +@item --insn32 +@kindex --no-insn32 +@itemx --no-insn32 +These options control the choice of nanoMIPS instructions used in code +generated by the linker, such as that in the PLT or lazy binding stubs, +or in relaxation. If @samp{--insn32} is used, then the linker only uses +32-bit instruction encodings. By default or if @samp{--no-insn32} is +used, all instruction encodings are used, including 16-bit ones where +possible. + @end table @c man end From patchwork Fri Jul 17 10:38:58 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsing X-Patchwork-Id: 139473 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B53BB4BA2E38 for ; Sat, 18 Jul 2026 15:10:19 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B53BB4BA2E38 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=m42pCMgj X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from va-2-29.ptr.blmpb.com (va-2-29.ptr.blmpb.com [209.127.231.29]) by sourceware.org (Postfix) with ESMTPS id 4053B4BA23C6 for ; Fri, 17 Jul 2026 10:39:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4053B4BA23C6 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4053B4BA23C6 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=209.127.231.29 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284777; cv=none; b=kUI3UAFdhT7qEAn7XOLPIGPbNHoNQmkEj1NfU5+jtGFz8FCKZvtBKaAiIqQPSDtb/o7JRz99qt4gLdqHQSORjeRM0U6JchHmBckJ3BIVlMBqvHGcS0plSass1rtAfOeXItXIJKkluqTN2F2Zj714CECYIuKJEniEqUlZfeYC3y4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784284777; c=relaxed/simple; bh=VkNssgDAKnWDAIDXpQ8S898ghrAmshq0bUVOeCk2VNE=; h=DKIM-Signature:To:Subject:Message-Id:Mime-Version:From:Date; b=alIXdHgFiuQYkwcd1NysRxvujsxlMUut5wRetChxporqgaehMp5rbqDMqpqvmQTe4ygAM/U1rrgy0/ccozKAdRgu9L9nxwBHgVxkltYQktCKBHA0r6U5POKL6nTHpR7m2pnyUjMiTXzW+jdgOTzpzjS62JcycAFYXZnExUy0UKQ= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=oss.cipunited.com header.i=@oss.cipunited.com header.a=rsa-sha256 header.s=feishu2303200042 header.b=m42pCMgj DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4053B4BA23C6 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1784284768; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=S1vHCGbWyeoX+pYL+/jjCtpUQATp6qfxU8NWjKKhruE=; b=m42pCMgj44FA965tvsVrQo2WxZB/NEqzIrSRSM/jVUbUsY2a1oqIRdihdxGvFsn5BiGtOd YPNyGlJPnFcGDuz/eQj0RAhTDH61B2lFRORVW59WzN9o50qZGg2L2QvRXOch58zUZlvjFv 5Kvp2EDqP33NnganrpjJqfx/e55hCUIX6rDaFh6DzkzKod92gfWK5d83hZoAskviCbiIPz dGUJP35WjKzCxcEfmb2ESNnG1l7FPvHCxHFTmlQRQl3CNzlw4j1nAjmYsba8Lby3c7rH9h qn5LoIonsk8AYjqM5p74asGDD3jOQ960afKLNlcs/U09RI6bq2mI4e02DGoZxg== Received: from B1.wok.cipunited.com ([123.52.17.40]) by smtp.feishu.cn with ESMTPS; Fri, 17 Jul 2026 18:39:26 +0800 In-Reply-To: <20260717103858.199743-1-lei.wang@oss.cipunited.com> To: Subject: [PATCH 6/6] Add nanoMIPS tests. X-Mailer: git-send-email 2.39.5 Message-Id: <20260717103858.199743-7-lei.wang@oss.cipunited.com> X-Lms-Return-Path: Mime-Version: 1.0 X-Original-From: Tsing References: <20260717103858.199743-1-lei.wang@oss.cipunited.com> From: "Tsing" Date: Fri, 17 Jul 2026 18:38:58 +0800 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, PROLO_LEO1, RCVD_IN_PBL, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, UNWANTED_LANGUAGE_BODY shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-Mailman-Approved-At: Sat, 18 Jul 2026 15:08:57 +0000 X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org From: tsing binutils/testsuite/ * binutils-all/objdump.exp (cpus_expected): Add nanomips. Expect the debug_ranges test to fail. gas/testsuite/ * gas/all/gas.exp: Expect the relax tests to fail. * gas/cfi/cfi.exp: Add cfi-nanomips-1 test. * gas/cfi/cfi-nanomips-1.d: New file. * gas/elf/elf.exp: Expect the groupauto tests to fail. * gas/elf/section2.e-nanomips: New file. * gas/nanomips: New directory. * gas/nanomips/nanomips.exp: New file. --- binutils/testsuite/binutils-all/objdump.exp | 3 +- gas/testsuite/gas/all/gas.exp | 6 +- gas/testsuite/gas/cfi/cfi-nanomips-1.d | 29 + gas/testsuite/gas/cfi/cfi.exp | 5 +- gas/testsuite/gas/elf/elf.exp | 6 + gas/testsuite/gas/elf/section2.e-nanomips | 8 + gas/testsuite/gas/nanomips/abi32-pic.d | 94 + gas/testsuite/gas/nanomips/abi32-pic.s | 38 + gas/testsuite/gas/nanomips/abi32.d | 79 + gas/testsuite/gas/nanomips/abi32.s | 70 + gas/testsuite/gas/nanomips/abs.d | 17 + gas/testsuite/gas/nanomips/abs.s | 4 + gas/testsuite/gas/nanomips/add.d | 24 + gas/testsuite/gas/nanomips/add.s | 13 + gas/testsuite/gas/nanomips/addu.d | 23 + gas/testsuite/gas/nanomips/addu.s | 9 + gas/testsuite/gas/nanomips/aent.d | 13 + gas/testsuite/gas/nanomips/aent.s | 16 + gas/testsuite/gas/nanomips/and.d | 35 + gas/testsuite/gas/nanomips/and.s | 23 + gas/testsuite/gas/nanomips/baddata1.l | 3 + gas/testsuite/gas/nanomips/baddata1.s | 9 + gas/testsuite/gas/nanomips/beq.d | 39 + gas/testsuite/gas/nanomips/beq.s | 22 + gas/testsuite/gas/nanomips/bge.d | 53 + gas/testsuite/gas/nanomips/bge.s | 24 + gas/testsuite/gas/nanomips/bgeu.d | 44 + gas/testsuite/gas/nanomips/bgeu.s | 21 + gas/testsuite/gas/nanomips/blt.d | 52 + gas/testsuite/gas/nanomips/blt.s | 24 + gas/testsuite/gas/nanomips/bltu.d | 44 + gas/testsuite/gas/nanomips/bltu.s | 21 + .../gas/nanomips/cp0-names-numeric.d | 44 + gas/testsuite/gas/nanomips/cp0-names.d | 43 + gas/testsuite/gas/nanomips/cp0-names.s | 38 + .../gas/nanomips/cp0sel-names-numeric.d | 236 ++ gas/testsuite/gas/nanomips/cp0sel-names.d | 235 ++ gas/testsuite/gas/nanomips/cp0sel-names.s | 236 ++ gas/testsuite/gas/nanomips/ctc.d | 87 + gas/testsuite/gas/nanomips/ctc.s | 66 + gas/testsuite/gas/nanomips/debug-dis.d | 18 + gas/testsuite/gas/nanomips/debug-dis.s | 12 + gas/testsuite/gas/nanomips/div.d | 45 + gas/testsuite/gas/nanomips/div.s | 31 + gas/testsuite/gas/nanomips/empty.s | 3 + gas/testsuite/gas/nanomips/expr-const.d | 11 + gas/testsuite/gas/nanomips/expr-const.s | 24 + gas/testsuite/gas/nanomips/expr-ill.l | 7 + gas/testsuite/gas/nanomips/expr-ill.s | 20 + gas/testsuite/gas/nanomips/expr-sym.d | 71 + gas/testsuite/gas/nanomips/expr-sym.s | 36 + gas/testsuite/gas/nanomips/expr-vol.d | 17 + gas/testsuite/gas/nanomips/expr-vol.s | 17 + gas/testsuite/gas/nanomips/expr1.d | 18 + gas/testsuite/gas/nanomips/expr1.s | 9 + .../gas/nanomips/gpr-names-numeric.d | 44 + gas/testsuite/gas/nanomips/gpr-names.d | 44 + gas/testsuite/gas/nanomips/gpr-names.s | 38 + .../gas/nanomips/hwr-names-numeric.d | 59 + .../gas/nanomips/hwr-names-numeric.s | 53 + .../gas/nanomips/insn-suffix-error.l | 20 + .../gas/nanomips/insn-suffix-error.s | 22 + gas/testsuite/gas/nanomips/isa-errors.l | 7 + gas/testsuite/gas/nanomips/isa-errors.s | 9 + gas/testsuite/gas/nanomips/jal.d | 21 + gas/testsuite/gas/nanomips/jal.s | 11 + gas/testsuite/gas/nanomips/jalr.l | 3 + gas/testsuite/gas/nanomips/jalr.s | 15 + gas/testsuite/gas/nanomips/la-lpic-mclarge.d | 116 + gas/testsuite/gas/nanomips/la-lpic-mcmedium.d | 116 + gas/testsuite/gas/nanomips/la-mclarge-pcrel.d | 116 + gas/testsuite/gas/nanomips/la-mclarge.d | 115 + gas/testsuite/gas/nanomips/la-pcrel.d | 116 + gas/testsuite/gas/nanomips/la-pic-mclarge.d | 116 + gas/testsuite/gas/nanomips/la-pic.d | 156 ++ gas/testsuite/gas/nanomips/la.d | 115 + gas/testsuite/gas/nanomips/la.s | 82 + gas/testsuite/gas/nanomips/lb.d | 176 ++ gas/testsuite/gas/nanomips/lb.s | 72 + gas/testsuite/gas/nanomips/ld-reloc.d | 86 + gas/testsuite/gas/nanomips/ld-reloc.s | 34 + gas/testsuite/gas/nanomips/ld.d | 174 ++ gas/testsuite/gas/nanomips/ld.s | 145 ++ gas/testsuite/gas/nanomips/li.d | 16 + gas/testsuite/gas/nanomips/li.s | 9 + gas/testsuite/gas/nanomips/lif-pic.d | 16 + gas/testsuite/gas/nanomips/lifloat-mem.d | 20 + gas/testsuite/gas/nanomips/lifloat-nms.d | 20 + gas/testsuite/gas/nanomips/lifloat.d | 15 + gas/testsuite/gas/nanomips/lifloat.s | 6 + gas/testsuite/gas/nanomips/lineno.d | 86 + gas/testsuite/gas/nanomips/lineno.s | 54 + gas/testsuite/gas/nanomips/linkrelax-dis.d | 30 + gas/testsuite/gas/nanomips/linkrelax-dis.s | 14 + gas/testsuite/gas/nanomips/linkrelax-relocs.d | 79 + gas/testsuite/gas/nanomips/linkrelax.d | 17 + gas/testsuite/gas/nanomips/linkrelax.s | 54 + gas/testsuite/gas/nanomips/mcmodel-err.l | 3 + gas/testsuite/gas/nanomips/mcmodel-err.s | 2 + gas/testsuite/gas/nanomips/mcmodel.l | 0 gas/testsuite/gas/nanomips/mcmodel.s | 3 + gas/testsuite/gas/nanomips/move.d | 14 + gas/testsuite/gas/nanomips/move.s | 3 + gas/testsuite/gas/nanomips/mt-ase.d | 651 +++++ gas/testsuite/gas/nanomips/mt-ase.s | 656 +++++ gas/testsuite/gas/nanomips/mvh.d | 16 + gas/testsuite/gas/nanomips/mvh.s | 12 + gas/testsuite/gas/nanomips/nanomips-error.l | 26 + gas/testsuite/gas/nanomips/nanomips-error.s | 46 + .../gas/nanomips/nanomips-exc-noalias.d | 254 ++ gas/testsuite/gas/nanomips/nanomips-exc.s | 282 ++ gas/testsuite/gas/nanomips/nanomips-exc32.d | 198 ++ gas/testsuite/gas/nanomips/nanomips-subset.d | 37 + gas/testsuite/gas/nanomips/nanomips-subset.s | 23 + gas/testsuite/gas/nanomips/nanomips.d | 2317 ++++++++++++++++ gas/testsuite/gas/nanomips/nanomips.exp | 557 ++++ gas/testsuite/gas/nanomips/nanomips.l | 10 + gas/testsuite/gas/nanomips/nanomips.s | 2034 +++++++++++++++ gas/testsuite/gas/nanomips/nanomips32.d | 2309 ++++++++++++++++ .../gas/nanomips/nanomips64@nanomips.d | 2318 +++++++++++++++++ .../gas/nanomips/nanomips64@nanomips32.d | 2309 ++++++++++++++++ .../gas/nanomips/nms@la-lpic-mclarge.d | 206 ++ .../gas/nanomips/nms@la-lpic-mcmedium.d | 206 ++ .../gas/nanomips/nms@la-mclarge-pcrel.d | 206 ++ gas/testsuite/gas/nanomips/nms@la-mclarge.d | 206 ++ gas/testsuite/gas/nanomips/nms@la-pcrel.d | 176 ++ .../gas/nanomips/nms@la-pic-mclarge.d | 156 ++ gas/testsuite/gas/nanomips/nms@la.d | 175 ++ gas/testsuite/gas/nanomips/nms@lif-pic-mem.d | 23 + gas/testsuite/gas/nanomips/nms@lif-pic.d | 21 + gas/testsuite/gas/nanomips/nms@save-error.l | 10 + gas/testsuite/gas/nanomips/nms@save-error.s | 26 + .../gas/nanomips/nolinkrelax-relocs.d | 14 + gas/testsuite/gas/nanomips/nolinkrelax.d | 17 + gas/testsuite/gas/nanomips/rol.d | 28 + gas/testsuite/gas/nanomips/rol.s | 22 + gas/testsuite/gas/nanomips/save-error.l | 16 + gas/testsuite/gas/nanomips/save-error.s | 42 + gas/testsuite/gas/nanomips/save-relocs.d | 22 + gas/testsuite/gas/nanomips/save.d | 64 + gas/testsuite/gas/nanomips/save.s | 94 + gas/testsuite/gas/nanomips/sb.d | 175 ++ gas/testsuite/gas/nanomips/sb.s | 71 + 143 files changed, 20764 insertions(+), 4 deletions(-) create mode 100644 gas/testsuite/gas/cfi/cfi-nanomips-1.d create mode 100644 gas/testsuite/gas/elf/section2.e-nanomips create mode 100644 gas/testsuite/gas/nanomips/abi32-pic.d create mode 100644 gas/testsuite/gas/nanomips/abi32-pic.s create mode 100644 gas/testsuite/gas/nanomips/abi32.d create mode 100644 gas/testsuite/gas/nanomips/abi32.s create mode 100644 gas/testsuite/gas/nanomips/abs.d create mode 100644 gas/testsuite/gas/nanomips/abs.s create mode 100644 gas/testsuite/gas/nanomips/add.d create mode 100644 gas/testsuite/gas/nanomips/add.s create mode 100644 gas/testsuite/gas/nanomips/addu.d create mode 100644 gas/testsuite/gas/nanomips/addu.s create mode 100644 gas/testsuite/gas/nanomips/aent.d create mode 100644 gas/testsuite/gas/nanomips/aent.s create mode 100644 gas/testsuite/gas/nanomips/and.d create mode 100644 gas/testsuite/gas/nanomips/and.s create mode 100644 gas/testsuite/gas/nanomips/baddata1.l create mode 100644 gas/testsuite/gas/nanomips/baddata1.s create mode 100644 gas/testsuite/gas/nanomips/beq.d create mode 100644 gas/testsuite/gas/nanomips/beq.s create mode 100644 gas/testsuite/gas/nanomips/bge.d create mode 100644 gas/testsuite/gas/nanomips/bge.s create mode 100644 gas/testsuite/gas/nanomips/bgeu.d create mode 100644 gas/testsuite/gas/nanomips/bgeu.s create mode 100644 gas/testsuite/gas/nanomips/blt.d create mode 100644 gas/testsuite/gas/nanomips/blt.s create mode 100644 gas/testsuite/gas/nanomips/bltu.d create mode 100644 gas/testsuite/gas/nanomips/bltu.s create mode 100644 gas/testsuite/gas/nanomips/cp0-names-numeric.d create mode 100644 gas/testsuite/gas/nanomips/cp0-names.d create mode 100644 gas/testsuite/gas/nanomips/cp0-names.s create mode 100644 gas/testsuite/gas/nanomips/cp0sel-names-numeric.d create mode 100644 gas/testsuite/gas/nanomips/cp0sel-names.d create mode 100644 gas/testsuite/gas/nanomips/cp0sel-names.s create mode 100644 gas/testsuite/gas/nanomips/ctc.d create mode 100644 gas/testsuite/gas/nanomips/ctc.s create mode 100644 gas/testsuite/gas/nanomips/debug-dis.d create mode 100644 gas/testsuite/gas/nanomips/debug-dis.s create mode 100644 gas/testsuite/gas/nanomips/div.d create mode 100644 gas/testsuite/gas/nanomips/div.s create mode 100644 gas/testsuite/gas/nanomips/empty.s create mode 100644 gas/testsuite/gas/nanomips/expr-const.d create mode 100644 gas/testsuite/gas/nanomips/expr-const.s create mode 100644 gas/testsuite/gas/nanomips/expr-ill.l create mode 100644 gas/testsuite/gas/nanomips/expr-ill.s create mode 100644 gas/testsuite/gas/nanomips/expr-sym.d create mode 100644 gas/testsuite/gas/nanomips/expr-sym.s create mode 100644 gas/testsuite/gas/nanomips/expr-vol.d create mode 100644 gas/testsuite/gas/nanomips/expr-vol.s create mode 100644 gas/testsuite/gas/nanomips/expr1.d create mode 100644 gas/testsuite/gas/nanomips/expr1.s create mode 100644 gas/testsuite/gas/nanomips/gpr-names-numeric.d create mode 100644 gas/testsuite/gas/nanomips/gpr-names.d create mode 100644 gas/testsuite/gas/nanomips/gpr-names.s create mode 100644 gas/testsuite/gas/nanomips/hwr-names-numeric.d create mode 100644 gas/testsuite/gas/nanomips/hwr-names-numeric.s create mode 100644 gas/testsuite/gas/nanomips/insn-suffix-error.l create mode 100644 gas/testsuite/gas/nanomips/insn-suffix-error.s create mode 100644 gas/testsuite/gas/nanomips/isa-errors.l create mode 100644 gas/testsuite/gas/nanomips/isa-errors.s create mode 100644 gas/testsuite/gas/nanomips/jal.d create mode 100644 gas/testsuite/gas/nanomips/jal.s create mode 100644 gas/testsuite/gas/nanomips/jalr.l create mode 100644 gas/testsuite/gas/nanomips/jalr.s create mode 100644 gas/testsuite/gas/nanomips/la-lpic-mclarge.d create mode 100644 gas/testsuite/gas/nanomips/la-lpic-mcmedium.d create mode 100644 gas/testsuite/gas/nanomips/la-mclarge-pcrel.d create mode 100644 gas/testsuite/gas/nanomips/la-mclarge.d create mode 100644 gas/testsuite/gas/nanomips/la-pcrel.d create mode 100644 gas/testsuite/gas/nanomips/la-pic-mclarge.d create mode 100644 gas/testsuite/gas/nanomips/la-pic.d create mode 100644 gas/testsuite/gas/nanomips/la.d create mode 100644 gas/testsuite/gas/nanomips/la.s create mode 100644 gas/testsuite/gas/nanomips/lb.d create mode 100644 gas/testsuite/gas/nanomips/lb.s create mode 100644 gas/testsuite/gas/nanomips/ld-reloc.d create mode 100644 gas/testsuite/gas/nanomips/ld-reloc.s create mode 100644 gas/testsuite/gas/nanomips/ld.d create mode 100644 gas/testsuite/gas/nanomips/ld.s create mode 100644 gas/testsuite/gas/nanomips/li.d create mode 100644 gas/testsuite/gas/nanomips/li.s create mode 100644 gas/testsuite/gas/nanomips/lif-pic.d create mode 100644 gas/testsuite/gas/nanomips/lifloat-mem.d create mode 100644 gas/testsuite/gas/nanomips/lifloat-nms.d create mode 100644 gas/testsuite/gas/nanomips/lifloat.d create mode 100644 gas/testsuite/gas/nanomips/lifloat.s create mode 100644 gas/testsuite/gas/nanomips/lineno.d create mode 100644 gas/testsuite/gas/nanomips/lineno.s create mode 100644 gas/testsuite/gas/nanomips/linkrelax-dis.d create mode 100644 gas/testsuite/gas/nanomips/linkrelax-dis.s create mode 100644 gas/testsuite/gas/nanomips/linkrelax-relocs.d create mode 100644 gas/testsuite/gas/nanomips/linkrelax.d create mode 100644 gas/testsuite/gas/nanomips/linkrelax.s create mode 100644 gas/testsuite/gas/nanomips/mcmodel-err.l create mode 100644 gas/testsuite/gas/nanomips/mcmodel-err.s create mode 100644 gas/testsuite/gas/nanomips/mcmodel.l create mode 100644 gas/testsuite/gas/nanomips/mcmodel.s create mode 100644 gas/testsuite/gas/nanomips/move.d create mode 100644 gas/testsuite/gas/nanomips/move.s create mode 100644 gas/testsuite/gas/nanomips/mt-ase.d create mode 100644 gas/testsuite/gas/nanomips/mt-ase.s create mode 100644 gas/testsuite/gas/nanomips/mvh.d create mode 100644 gas/testsuite/gas/nanomips/mvh.s create mode 100644 gas/testsuite/gas/nanomips/nanomips-error.l create mode 100644 gas/testsuite/gas/nanomips/nanomips-error.s create mode 100644 gas/testsuite/gas/nanomips/nanomips-exc-noalias.d create mode 100644 gas/testsuite/gas/nanomips/nanomips-exc.s create mode 100644 gas/testsuite/gas/nanomips/nanomips-exc32.d create mode 100644 gas/testsuite/gas/nanomips/nanomips-subset.d create mode 100644 gas/testsuite/gas/nanomips/nanomips-subset.s create mode 100644 gas/testsuite/gas/nanomips/nanomips.d create mode 100644 gas/testsuite/gas/nanomips/nanomips.exp create mode 100644 gas/testsuite/gas/nanomips/nanomips.l create mode 100644 gas/testsuite/gas/nanomips/nanomips.s create mode 100644 gas/testsuite/gas/nanomips/nanomips32.d create mode 100644 gas/testsuite/gas/nanomips/nanomips64@nanomips.d create mode 100644 gas/testsuite/gas/nanomips/nanomips64@nanomips32.d create mode 100644 gas/testsuite/gas/nanomips/nms@la-lpic-mclarge.d create mode 100644 gas/testsuite/gas/nanomips/nms@la-lpic-mcmedium.d create mode 100644 gas/testsuite/gas/nanomips/nms@la-mclarge-pcrel.d create mode 100644 gas/testsuite/gas/nanomips/nms@la-mclarge.d create mode 100644 gas/testsuite/gas/nanomips/nms@la-pcrel.d create mode 100644 gas/testsuite/gas/nanomips/nms@la-pic-mclarge.d create mode 100644 gas/testsuite/gas/nanomips/nms@la.d create mode 100644 gas/testsuite/gas/nanomips/nms@lif-pic-mem.d create mode 100644 gas/testsuite/gas/nanomips/nms@lif-pic.d create mode 100644 gas/testsuite/gas/nanomips/nms@save-error.l create mode 100644 gas/testsuite/gas/nanomips/nms@save-error.s create mode 100644 gas/testsuite/gas/nanomips/nolinkrelax-relocs.d create mode 100644 gas/testsuite/gas/nanomips/nolinkrelax.d create mode 100644 gas/testsuite/gas/nanomips/rol.d create mode 100644 gas/testsuite/gas/nanomips/rol.s create mode 100644 gas/testsuite/gas/nanomips/save-error.l create mode 100644 gas/testsuite/gas/nanomips/save-error.s create mode 100644 gas/testsuite/gas/nanomips/save-relocs.d create mode 100644 gas/testsuite/gas/nanomips/save.d create mode 100644 gas/testsuite/gas/nanomips/save.s create mode 100644 gas/testsuite/gas/nanomips/sb.d create mode 100644 gas/testsuite/gas/nanomips/sb.s diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp index 734f93298ed..164597f7013 100644 --- a/binutils/testsuite/binutils-all/objdump.exp +++ b/binutils/testsuite/binutils-all/objdump.exp @@ -37,7 +37,7 @@ set cpus_expected [list] lappend cpus_expected aarch64 alpha am33-2 arc ARC700 ARCv2 arm cris lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 iamcu ip2022 lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k MCore mep c5 h1 MicroBlaze -lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k +lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nanomips nds32 n1h_v3 ns32k lappend cpus_expected or1k or1knd pj powerpc pyramid riscv romp rs6000 s390 sh sparc lappend cpus_expected tic54x tilegx tms320c30 tms320c4x tms320c54x lappend cpus_expected v850 vax x86-64 xscale xtensa z8k z8001 z8002 @@ -260,6 +260,7 @@ if { ![istarget "*-*-aix*"] && ![istarget "*c54x-*-*"] && ![istarget "alpha-*-*vms*"] && ![istarget "i?86-*-msdos"] + && ![istarget "nanomips*-*-*"] && [file normalize "$LD"] == [file normalize "$objdir/../ld/ld-new"]} then { run_dump_test multi-1 run_dump_test multi-2 diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index 46451fb5a90..ae2a25000df 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -166,6 +166,7 @@ switch -glob $target_triplet { mn10200-*-* { } mn10300-*-* { } msp430*-*-* { } + nanomips*-*-* { } nds32*-*-* { } pdp11-*-* { } tic30*-*-* { } @@ -419,7 +420,8 @@ run_dump_test sleb128-9 # .byte is 32 bits on tic4x, and .p2align isn't supported on tic54x # .space is different on hppa*-hpux. # MeP put bytes into packets. -if { ![istarget "tic4x*-*-*"] && ![istarget "tic54x*-*-*"] && ![istarget "hppa*-*-hpux*"] && ![istarget "mep*-*-*"] } { +# nanoMIPS does not like variable leb128s +if { ![istarget "tic4x*-*-*"] && ![istarget "tic54x*-*-*"] && ![istarget "hppa*-*-hpux*"] && ![istarget "mep*-*-*"] && ![istarget "nanomips*-*-*"] } { run_dump_test relax } @@ -455,6 +457,7 @@ if { [istarget "i?86-*-*"] || [istarget "x86_64-*-*"] } { switch -glob $target_triplet { alpha*-*-* { } mips*-*-* { } + nanomips*-*-* { } *c54x*-*-* { } z80-*-* { } default { @@ -474,6 +477,7 @@ switch -glob $target_triplet { iq2000-*-* { } microblaze-*-* { } mips*-*-* { } + nanomips*-*-* { } score*-*-* { } xtensa*-*-* { } m68hc1*-*-* - diff --git a/gas/testsuite/gas/cfi/cfi-nanomips-1.d b/gas/testsuite/gas/cfi/cfi-nanomips-1.d new file mode 100644 index 00000000000..25e855d3f88 --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-nanomips-1.d @@ -0,0 +1,29 @@ +#readelf: -wf +#name: CFI on nanoMIPS, 1 +#source: cfi-mips-1.s +#as: -march=32r6 -mlegacyregs +Contents of the .eh_frame section: + +0+0000 0+0014 0+0000 CIE + Version: 1 + Augmentation: "zR" + Code alignment factor: 1 + Data alignment factor: -4 + Return address column: 31 + Augmentation data: 0b + + DW_CFA_def_cfa_register: r29 + DW_CFA_def_cfa: r29 ofs 0 + DW_CFA_nop + DW_CFA_nop + +0+0018 0+001c 0+001c FDE cie=0+0000 pc=0+0000..0+0018 + DW_CFA_advance_loc: 2 to 0+0002 + DW_CFA_def_cfa_offset: 8 + DW_CFA_advance_loc: 2 to 0+0004 + DW_CFA_offset: r30 at cfa-8 + DW_CFA_advance_loc: 2 to 0+0006 + DW_CFA_def_cfa: r30 ofs 8 + DW_CFA_advance_loc: 14 to 0+0014 + DW_CFA_def_cfa: r29 ofs 0 + DW_CFA_nop diff --git a/gas/testsuite/gas/cfi/cfi.exp b/gas/testsuite/gas/cfi/cfi.exp index de518446a13..a58fd56ee81 100644 --- a/gas/testsuite/gas/cfi/cfi.exp +++ b/gas/testsuite/gas/cfi/cfi.exp @@ -110,7 +110,8 @@ if { [istarget "i*86-*-*"] || [istarget "x86_64-*-*"] } then { if { [regexp "elf64\[_-\]sparc" [lindex $nm_status 1]] } then { run_dump_test "cfi-sparc64-1" } - +} elseif { [istarget "nanomips*-*"] } then { + run_dump_test "cfi-nanomips-1" } else { return } @@ -134,7 +135,7 @@ if { ![istarget "hppa64*-*"] } then { run_dump_test "cfi-common-5" } # Some targets don't support PC relative cfi directives - if { ![istarget "mips*-*"] } then { + if { ![istarget "mips*-*"] && ![istarget "nanomips*-*"] } then { run_dump_test "cfi-common-6" } run_dump_test "cfi-common-7" diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp index 5580c494c54..0262219e661 100644 --- a/gas/testsuite/gas/elf/elf.exp +++ b/gas/testsuite/gas/elf/elf.exp @@ -94,6 +94,9 @@ if { [is_elf_format] } then { set target_machine -riscv set dump_opts {{as -mno-relax}} } + if {[istarget "nanomips*-*-*"]} then { + set target_machine -nanomips + } if {[istarget "rl78-*-*"]} then { set target_machine -rl78 } @@ -157,6 +160,7 @@ if { [is_elf_format] } then { switch -glob $target_triplet { hppa64*-*-hpux* { } + nanomips*-*-* { } riscv*-*-* { } default { run_dump_test "groupautoa" $dump_opts @@ -164,6 +168,7 @@ if { [is_elf_format] } then { } switch -glob $target_triplet { hppa64*-*-hpux* { } + nanomips*-*-* { } riscv*-*-* { } xtensa*-*-* { } default { @@ -183,6 +188,7 @@ if { [is_elf_format] } then { mn10200-*-* { } mn10300-*-* { } msp43*-*-* { } + nanomips*-*-* { } rl78-*-* { } riscv*-*-* { } rx-*-* { } diff --git a/gas/testsuite/gas/elf/section2.e-nanomips b/gas/testsuite/gas/elf/section2.e-nanomips new file mode 100644 index 00000000000..fd94cee4db7 --- /dev/null +++ b/gas/testsuite/gas/elf/section2.e-nanomips @@ -0,0 +1,8 @@ + +Symbol table '.symtab' contains 5 entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name + +0: 0+0 +0 +NOTYPE +LOCAL +DEFAULT +UND + +1: 0+0 +0 +SECTION +LOCAL +DEFAULT +1.* + +2: 0+0 +0 +SECTION +LOCAL +DEFAULT +2.* + +3: 0+0 +0 +SECTION +LOCAL +DEFAULT +3.* + +4: 0+0 +0 +SECTION +LOCAL +DEFAULT +4.* diff --git a/gas/testsuite/gas/nanomips/abi32-pic.d b/gas/testsuite/gas/nanomips/abi32-pic.d new file mode 100644 index 00000000000..698c175ae83 --- /dev/null +++ b/gas/testsuite/gas/nanomips/abi32-pic.d @@ -0,0 +1,94 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS -m32 (SVR4 PIC) +#as: -EB + +.*: +file format.* + +Disassembly of section .text\: +[0-9a-f]+ <[^>]+> e380 0002 aluipc gp,%pcrel_hi\([0-9a-f]+ <_gp>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 _gp +[0-9a-f]+ <[^>]+> 039c 0000 addiu gp,gp,0 + [0-9a-f]+: R_NANOMIPS_LO12 _gp +[0-9a-f]+ <[^>]+> e094 5244 lui a0,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8084 0678 ori a0,a0,0x678 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ \) + [0-9a-f]+: R_NANOMIPS_PCHI20 shared +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 .sdata +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ \) + [0-9a-f]+: R_NANOMIPS_PCHI20 unshared +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 .data +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ \) + [0-9a-f]+: R_NANOMIPS_PCHI20 end +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 end +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 end +[0-9a-f]+ <[^>]+> 4020 0002 lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_CALL end +[0-9a-f]+ <[^>]+> d830 jalrc at +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\(00000000 \) + [0-9a-f]+: R_NANOMIPS_PCHI20 shared +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .sdata +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\(00000000 \) + [0-9a-f]+: R_NANOMIPS_PCHI20 unshared +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .data +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ \) + [0-9a-f]+: R_NANOMIPS_PCHI20 end +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 end +[0-9a-f]+ <[^>]+> 4020 0002 lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_PAGE \.sdata +[0-9a-f]+ <[^>]+> 8481 8000 lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .sdata +[0-9a-f]+ <[^>]+> 84a1 8000 lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .sdata\+0x4 +[0-9a-f]+ <[^>]+> 4020 0002 lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_PAGE .data +[0-9a-f]+ <[^>]+> 8481 8000 lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .data +[0-9a-f]+ <[^>]+> 84a1 8000 lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .data\+0x4 +[0-9a-f]+ <[^>]+> 4020 0002 lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_PAGE end +[0-9a-f]+ <[^>]+> 8481 8000 lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST end +[0-9a-f]+ <[^>]+> 84a1 8000 lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST end\+0x4 +[0-9a-f]+ <[^>]+> e020 0002 aluipc at,%pcrel_hi\(00000000 \) + [0-9a-f]+: R_NANOMIPS_PCHI20 shared +[0-9a-f]+ <[^>]+> 8481 9000 sw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 .sdata +[0-9a-f]+ <[^>]+> e020 0002 aluipc at,%pcrel_hi\(00000000 \) + [0-9a-f]+: R_NANOMIPS_PCHI20 unshared +[0-9a-f]+ <[^>]+> 8481 9000 sw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> 4020 0002 lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_PAGE .sdata +[0-9a-f]+ <[^>]+> 8481 9000 sw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .sdata +[0-9a-f]+ <[^>]+> 84a1 9000 sw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .sdata\+0x4 +[0-9a-f]+ <[^>]+> 4020 0002 lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_PAGE .data +[0-9a-f]+ <[^>]+> 8481 9000 sw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .data +[0-9a-f]+ <[^>]+> 84a1 9000 sw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .data\+0x4 +[0-9a-f]+ <[^>]+> e090 07fc lui a0,%hi\(0x3ff00000\) +[0-9a-f]+ <[^>]+> 10a0 move a1,zero +[0-9a-f]+ <[^>]+> 4020 0002 lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_PAGE .rodata +[0-9a-f]+ <[^>]+> 8481 8000 lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .rodata +[0-9a-f]+ <[^>]+> 84a1 8000 lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST .rodata\+0x4 +[0-9a-f]+ <[^>]+> 0085 0064 addiu a0,a1,100 +[0-9a-f]+ <[^>]+> 8084 5001 sltiu a0,a0,1 +[0-9a-f]+ <[^>]+> 0085 0064 addiu a0,a1,100 +[0-9a-f]+ <[^>]+> 2080 2390 sltu a0,zero,a0 +[0-9a-f]+ <[^>]+> 1085 move a0,a1 +#pass diff --git a/gas/testsuite/gas/nanomips/abi32-pic.s b/gas/testsuite/gas/nanomips/abi32-pic.s new file mode 100644 index 00000000000..c6a441d82f2 --- /dev/null +++ b/gas/testsuite/gas/nanomips/abi32-pic.s @@ -0,0 +1,38 @@ + .sdata +shared: + .word 11 + + .data +unshared: + .word 1 + .word 2 + .word 3 + .word 4 + + .text + .ent func +func: + .cpsetup $25 + li $4, 0x12345678 + la $4, shared + la $4, unshared + la $4, end + j end + jal end + lw $4, shared + lw $4, unshared + lw $4, end + ld $4, shared + ld $4, unshared + ld $4, end + sw $4, shared + sw $4, unshared + sd $4, shared + sd $4, unshared + li.d $4, 1.0 + li.d $4, 1.9 + seq $4, $5, -100 + sne $4, $5, -100 + move $4, $5 + .end func +end: diff --git a/gas/testsuite/gas/nanomips/abi32.d b/gas/testsuite/gas/nanomips/abi32.d new file mode 100644 index 00000000000..1394e530424 --- /dev/null +++ b/gas/testsuite/gas/nanomips/abi32.d @@ -0,0 +1,79 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS 32-bit ABI +#as: -EB --linkrelax + +.*: +file format.* + +Disassembly of section \.text: +[0-9a-f]+ e094 5244 lui a0,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8084 0678 ori a0,a0,0x678 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sdata +[0-9a-f]+ <[^>]+> e080 0000 lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data +[0-9a-f]+ <[^>]+> 8084 0000 ori a0,a0,0x0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> e080 0000 lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 end +[0-9a-f]+ <[^>]+> 8084 0000 ori a0,a0,0x0 + [0-9a-f]+: R_NANOMIPS_LO12 end +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 end +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 end +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sdata +[0-9a-f]+ <[^>]+> e080 0000 lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> e080 0000 lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 end +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 end +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sdata +[0-9a-f]+ <[^>]+> 40a0 0002 lw a1,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sdata\+0x4 +[0-9a-f]+ <[^>]+> e020 0000 lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data +[0-9a-f]+ <[^>]+> 8481 8000 lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> 84a1 8000 lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x4 +[0-9a-f]+ <[^>]+> e020 0000 lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 end +[0-9a-f]+ <[^>]+> 8481 8000 lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 end +[0-9a-f]+ <[^>]+> 84a1 8000 lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 end\+0x4 +[0-9a-f]+ <[^>]+> 4080 0003 sw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sdata +[0-9a-f]+ <[^>]+> e020 0000 lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data +[0-9a-f]+ <[^>]+> 8481 9000 sw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> 4080 0003 sw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sdata +[0-9a-f]+ <[^>]+> 40a0 0003 sw a1,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sdata\+0x4 +[0-9a-f]+ <[^>]+> e020 0000 lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data +[0-9a-f]+ <[^>]+> 8481 9000 sw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> 84a1 9000 sw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x4 +[0-9a-f]+ <[^>]+> e090 07fc lui a0,%hi\(0x3ff00000\) +[0-9a-f]+ <[^>]+> 10a0 move a1,zero +[0-9a-f]+ <[^>]+> e020 0000 lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.rodata +[0-9a-f]+ <[^>]+> 8481 8000 lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.rodata +[0-9a-f]+ <[^>]+> 84a1 8000 lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.rodata\+0x4 +[0-9a-f]+ <[^>]+> 0085 0064 addiu a0,a1,100 +[0-9a-f]+ <[^>]+> 8084 5001 sltiu a0,a0,1 +[0-9a-f]+ <[^>]+> 0085 0064 addiu a0,a1,100 +[0-9a-f]+ <[^>]+> 2080 2390 sltu a0,zero,a0 +[0-9a-f]+ <[^>]+> 1085 move a0,a1 +#pass diff --git a/gas/testsuite/gas/nanomips/abi32.s b/gas/testsuite/gas/nanomips/abi32.s new file mode 100644 index 00000000000..6856ddb4fd4 --- /dev/null +++ b/gas/testsuite/gas/nanomips/abi32.s @@ -0,0 +1,70 @@ + + .sdata +shared: .word 11 + + .data +unshared: + .word 1 + .word 2 + .word 3 + .word 4 + + .text +func: + li $4, 0x12345678 # 0000 lui a0,0x1234 + # 0004 ori a0,a0,0x5678 + la $4, shared # 0008 addiu a0,gp,shared + la $4, unshared # 000c lui a0,hi(unshared) + # 0010 addiu a0,a0,lo(unshared) + la $4, end # 0014 lui a0,hi(end) + # 0018 addiu a0,a0,lo(end) + j end # 001c j end + jal end # 0020 jal end + lw $4, shared # 0024 lw a0,shared(gp) + lw $4, unshared # 0028 lui a0,hi(unshared) + # 002c lw a0,lo(unshared)(a0) + lw $4, end # 0030 lui a0,hi(end) + # 0034 lw a0,lo(end)(a0) + ld $4, shared # 0038 lw a0,shared(gp) + # 003c lw a1,shared+4(gp) + ld $4, unshared # 0040 lui at,hi(unshared) + # 0044 lw a0,lo(unshared)(at) + # 0048 lw a1,lo(unshared)+4(at) + ld $4, end # 004c lui at,hi(end) + # 0050 lw a0,lo(end)(at) + # 0054 lw a1,lo(end)+4(at) + sw $4, shared # 0058 sw a0,shared(gp) + sw $4, unshared # 005c lui at,hi(unshared) + # 0060 sw a0,lo(unshared)(at) + sd $4, shared # 0064 sw a0,shared(gp) + # 0068 sw a1,shared+4(gp) + sd $4, unshared # 006c lui at,hi(unshared) + # 0070 sw a0,lo(unshared)(at) + # 0074 sw a1,lo(unshared)+4(at) + li.d $4, 1.0 # 00d0 lui a0,0x3ff0 + # 00d4 move a1,zero + li.d $4, 1.9 # 00d8 lui at,hi(F1.9) + # 00dc lw a0,lo(F1.9)(at) + # 00e0 lw a1,lo(F1.9)+4(at) + seq $4, $5, -100 # 00f4 addiu a0,a1,100 + # 00f8 sltiu a0,a0,1 + sne $4, $5, -100 # 00fc addiu a0,a1,100 + # 0100 sltu a0,zero,a0 + move $4, $5 # 0104 move a0,a1 + +# Not available in 32-bit mode +# dla $4, shared +# dla $4, unshared +# uld $4, unshared +# usd $4, unshared + +# Should produce warnings given -mgp32 +# bgt $4, 0x7fffffff, end +# bgtu $4, 0xffffffff, end +# ble $4, 0x7fffffff, end +# bleu $4, 0xffffffff, end + +# Should produce warnings given -mfp32 +# add.d $f1, $f2, $f3 + +end: diff --git a/gas/testsuite/gas/nanomips/abs.d b/gas/testsuite/gas/nanomips/abs.d new file mode 100644 index 00000000000..20bf00d63c1 --- /dev/null +++ b/gas/testsuite/gas/nanomips/abs.d @@ -0,0 +1,17 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS abs +#source: abs.s + +# Test the abs macro (nanoMIPS). + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +0+0000 8804 8000 bgezc a0,00000008 <.*> + 0: R_NANOMIPS_PC14_S1 .* +0+0004 2080 21d0 negu a0,a0 +0+0008 <.L\^_0> 1085 move a0,a1 +0+000a <.L\^_0\+0x2> 8805 8000 bgezc a1,00000012 <.*> + a: R_NANOMIPS_PC14_S1 .* +0+000e <.L\^_0\+0x6> 20a0 21d0 negu a0,a1 +#pass diff --git a/gas/testsuite/gas/nanomips/abs.s b/gas/testsuite/gas/nanomips/abs.s new file mode 100644 index 00000000000..c4f5c4d720f --- /dev/null +++ b/gas/testsuite/gas/nanomips/abs.s @@ -0,0 +1,4 @@ +# Source file used to test the abs macro. +foo: + abs $4 + abs $4, $5 diff --git a/gas/testsuite/gas/nanomips/add.d b/gas/testsuite/gas/nanomips/add.d new file mode 100644 index 00000000000..7f96ac8a337 --- /dev/null +++ b/gas/testsuite/gas/nanomips/add.d @@ -0,0 +1,24 @@ +#objdump: -dr --no-show-raw-insn +#name: nanoMIPS add +#source: add.s + +# Test the add macro for nanoMIPS + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: addiu a0,a0,0 + 4: li at,1 + 8: add a0,a0,at + c: li at,32768 + 10: add a0,a0,at + 14: lui at,%hi\(0xffff8000\) + 18: add a0,a0,at + 1c: lui at,%hi\(0x10000\) + 20: add a0,a0,at + 24: li at,0x1a5a5 + 2a: add a0,a0,at + 2e: addiu a0,a0,1 +#pass diff --git a/gas/testsuite/gas/nanomips/add.s b/gas/testsuite/gas/nanomips/add.s new file mode 100644 index 00000000000..150aebfbd1a --- /dev/null +++ b/gas/testsuite/gas/nanomips/add.s @@ -0,0 +1,13 @@ +# Source file used to test the add macro. + +foo: + add $4, $4, 0 + add $4, $4, 1 + add $4, $4, 0x8000 + add $4, $4, -0x8000 + add $4, $4, 0x10000 + add $4, $4, 0x1a5a5 + +# addu is handled the same way add is; just confirm that it isn't +# totally broken. + addu $4, $4, 1 diff --git a/gas/testsuite/gas/nanomips/addu.d b/gas/testsuite/gas/nanomips/addu.d new file mode 100644 index 00000000000..62bff6a3a29 --- /dev/null +++ b/gas/testsuite/gas/nanomips/addu.d @@ -0,0 +1,23 @@ +#objdump: -dr --no-show-raw-insn +#name: nanoMIPS addu +#source: addu.s +#as: + +# Test the add macro for nanoMIPS + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: addiu a0,a0,0 + 4: addiu a0,a0,1 + 8: addiu a0,a0,32768 + c: lui at,%hi\(0xffff8000\) + 10: addu a0,a0,at + 14: lui at,%hi\(0x10000\) + 18: addu a0,a0,at + 1c: lui at,%hi\(0x1a000\) + 20: ori at,at,0x5a5 + 24: addu a0,a0,at +#pass diff --git a/gas/testsuite/gas/nanomips/addu.s b/gas/testsuite/gas/nanomips/addu.s new file mode 100644 index 00000000000..2bbbd23004c --- /dev/null +++ b/gas/testsuite/gas/nanomips/addu.s @@ -0,0 +1,9 @@ +# Source file used to test the add macro. + +foo: + addu $a0, $a0, 0 + addu $a0, $a0, 1 + addu $a0, $a0, 0x8000 + addu $a0, $a0, -0x8000 + addu $a0, $a0, 0x10000 + addu $a0, $a0, 0x1a5a5 diff --git a/gas/testsuite/gas/nanomips/aent.d b/gas/testsuite/gas/nanomips/aent.d new file mode 100644 index 00000000000..a319bcdcb12 --- /dev/null +++ b/gas/testsuite/gas/nanomips/aent.d @@ -0,0 +1,13 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS .aent directive + +# Test the .aent directive retains function symbol type annotation. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +0+0000 sllv t4,a0,a2 +0+0004 srav a4,a6,t0 +0+0008 sllv t4,a0,a2 +0+000c srav a4,a6,t0 +#pass diff --git a/gas/testsuite/gas/nanomips/aent.s b/gas/testsuite/gas/nanomips/aent.s new file mode 100644 index 00000000000..fc9e94d8f5f --- /dev/null +++ b/gas/testsuite/gas/nanomips/aent.s @@ -0,0 +1,16 @@ + .text + + .globl foo + .ent foo +foo: + sllv $2, $4, $6 + srav $8, $10, $12 + + .globl bar + .aent bar +bar: + sllv $2, $4, $6 + srav $8, $10, $12 + + .end foo + .size foo, . - foo diff --git a/gas/testsuite/gas/nanomips/and.d b/gas/testsuite/gas/nanomips/and.d new file mode 100644 index 00000000000..c0e8f201789 --- /dev/null +++ b/gas/testsuite/gas/nanomips/and.d @@ -0,0 +1,35 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS and + +# Test the and macro for nanoMIPS + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +0+0000 andi a0,a0,0x0 +0+0004 andi a0,a0,0x1 +0+0008 li at,32768 +0+000c and a0,a0,at +0+0010 lui at,%hi\(0xffff8000\) +0+0014 and a0,a0,at +0+0018 lui at,%hi\(0x10000\) +0+001c and a0,a0,at +0+0020 lui at,%hi\(0x1a000\) +0+0024 ori at,at,0x5a5 +0+0028 and a0,a0,at +0+002c li at,0 +0+0030 nor a0,a1,at +0+0034 li at,1 +0+0038 nor a0,a1,at +0+003c li at,32768 +0+0040 nor a0,a1,at +0+0044 lui at,%hi\(0xffff8000\) +0+0048 nor a0,a1,at +0+004c lui at,%hi\(0x10000\) +0+0050 nor a0,a1,at +0+0054 lui at,%hi\(0x1a000\) +0+0058 ori at,at,0x5a5 +0+005c nor a0,a1,at +0+0060 ori a0,a1,0x0 +0+0064 xori a0,a1,0x0 +#pass diff --git a/gas/testsuite/gas/nanomips/and.s b/gas/testsuite/gas/nanomips/and.s new file mode 100644 index 00000000000..a23b907caea --- /dev/null +++ b/gas/testsuite/gas/nanomips/and.s @@ -0,0 +1,23 @@ +# Source file used to test the and macro. + .text +foo: + and $4, $4, 0 + and $4, $4, 1 + and $4, $4, 0x8000 + and $4, $4, -0x8000 + and $4, $4, 0x10000 + and $4, $4, 0x1a5a5 + +# nor, or, and xor are handled by the same code. There is a special +# case for nor, so we test all variants. + + nor $4, $5, 0 + nor $4, $5, 1 + nor $4, $5, 0x8000 + nor $4, $5, -0x8000 + nor $4, $5, 0x10000 + nor $4, $5, 0x1a5a5 + + or $4, $5, 0 + + xor $4, $5, 0 diff --git a/gas/testsuite/gas/nanomips/baddata1.l b/gas/testsuite/gas/nanomips/baddata1.l new file mode 100644 index 00000000000..6d09cca933f --- /dev/null +++ b/gas/testsuite/gas/nanomips/baddata1.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:8: Error: cannot represent BFD_RELOC_8 relocation in this object file format +.*:9: Error: cannot represent BFD_RELOC_8 relocation in this object file format diff --git a/gas/testsuite/gas/nanomips/baddata1.s b/gas/testsuite/gas/nanomips/baddata1.s new file mode 100644 index 00000000000..0a901078aec --- /dev/null +++ b/gas/testsuite/gas/nanomips/baddata1.s @@ -0,0 +1,9 @@ +# Source file used to some bad data declarations. + + .globl x + + .data +foo: + # no way these are going to hold the pointers. + .byte x + .byte x+1 diff --git a/gas/testsuite/gas/nanomips/beq.d b/gas/testsuite/gas/nanomips/beq.d new file mode 100644 index 00000000000..d3700ba57b4 --- /dev/null +++ b/gas/testsuite/gas/nanomips/beq.d @@ -0,0 +1,39 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS beq + +# Test the beq macro on nanoMIPS + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> beqc a0,a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> beqzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> beqic a0,1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC11_S1 text_label +[0-9a-f]+ <[^>]*> li at,32768 +[0-9a-f]+ <[^>]*> beqc a0,at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> beqc a0,at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> beqc a0,at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori at,at,0x5a5 +[0-9a-f]+ <[^>]*> beqc a0,at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bnezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label + \.\.\. +[0-9a-f]+ <[^>]*> bc 00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 text_label +[0-9a-f]+ <[^>]*> balc 00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 text_label +[0-9a-f]+ <[^>]*> bc 00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 external_label +[0-9a-f]+ <[^>]*> balc 00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 external_label +#pass diff --git a/gas/testsuite/gas/nanomips/beq.s b/gas/testsuite/gas/nanomips/beq.s new file mode 100644 index 00000000000..2dbfd2b084d --- /dev/null +++ b/gas/testsuite/gas/nanomips/beq.s @@ -0,0 +1,22 @@ +# Source file used to test the beq macro. + .text +text_label: + beq $4, $5, text_label + beq $4, 0, text_label + beq $4, 1, text_label + beq $4, 0x8000, text_label + beq $4, -0x8000, text_label + beq $4, 0x10000, text_label + beq $4, 0x1a5a5, text_label + +# bne is handled by the same code as beq. Just sanity check. + bne $4, 0, text_label + +# Test that branches which overflow are converted to jumps. + .space 0x20000 + b text_label + bal text_label + +# Branch to an external label. + b external_label + bal external_label diff --git a/gas/testsuite/gas/nanomips/bge.d b/gas/testsuite/gas/nanomips/bge.d new file mode 100644 index 00000000000..1480125aee0 --- /dev/null +++ b/gas/testsuite/gas/nanomips/bge.d @@ -0,0 +1,53 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS bge + + +# Test the bge macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> bgec a0,a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> blezc a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgtzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgeic a0,2,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC11_S1 text_label +[0-9a-f]+ <[^>]*> li at,32768 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori at,at,0x5a5 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgtzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bltzc a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgtzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgec a0,a1,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> bnezc at,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +#pass diff --git a/gas/testsuite/gas/nanomips/bge.s b/gas/testsuite/gas/nanomips/bge.s new file mode 100644 index 00000000000..a90b927a5b2 --- /dev/null +++ b/gas/testsuite/gas/nanomips/bge.s @@ -0,0 +1,24 @@ +# Source file used to test the bge macro. + +text_label: + bge $4, $5, text_label + bge $4, $0, text_label + bge $0, $5, text_label + bge $4, 0, text_label + bge $4, 1, text_label + bge $4, 2, text_label + bge $4, 0x8000, text_label + bge $4, -0x8000, text_label + bge $4, 0x10000, text_label + bge $4, 0x1a5a5, text_label + +# bgt is handled like bge, except when both arguments are registers. +# Just sanity check it otherwise. + bgt $4, $5, text_label + bgt $4, $0, text_label + bgt $0, $5, text_label + bgt $4, 0, text_label + +# Branch to an external label. + bge $4, $5, external_label + bgt $4, $5, external_label diff --git a/gas/testsuite/gas/nanomips/bgeu.d b/gas/testsuite/gas/nanomips/bgeu.d new file mode 100644 index 00000000000..8209a3bbfc4 --- /dev/null +++ b/gas/testsuite/gas/nanomips/bgeu.d @@ -0,0 +1,44 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS bgeu + +# Test the bgeu macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> bgeuc a0,a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bnezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgeiuc a0,2,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC11_S1 text_label +[0-9a-f]+ <[^>]*> li at,32768 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori at,at,0x5a5 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bnezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bnezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgeuc a0,a1,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> bnezc at,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +#pass diff --git a/gas/testsuite/gas/nanomips/bgeu.s b/gas/testsuite/gas/nanomips/bgeu.s new file mode 100644 index 00000000000..578bcd6a345 --- /dev/null +++ b/gas/testsuite/gas/nanomips/bgeu.s @@ -0,0 +1,21 @@ +# Source file used to test the bgeu macro. + +text_label: + bgeu $4, $5, text_label + # A second argument of 0 or $0 is always true + bgeu $4, 1, text_label + bgeu $4, 2, text_label + bgeu $4, 0x8000, text_label + bgeu $4, -0x8000, text_label + bgeu $4, 0x10000, text_label + bgeu $4, 0x1a5a5, text_label + +# bgtu is handled like bgeu, except when both arguments are registers. +# Just sanity check it otherwise. + bgtu $4, $5, text_label + bgtu $4, $0, text_label + bgtu $4, 0, text_label + +# Branch to an external label. + bgeu $4, $5, external_label + bgtu $4, $5, external_label diff --git a/gas/testsuite/gas/nanomips/blt.d b/gas/testsuite/gas/nanomips/blt.d new file mode 100644 index 00000000000..6b3c0fffaaf --- /dev/null +++ b/gas/testsuite/gas/nanomips/blt.d @@ -0,0 +1,52 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS blt + +# Test the blt macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> bltc a0,a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bltzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgtzc a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bltzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> blezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bltic a0,2,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC11_S1 text_label +[0-9a-f]+ <[^>]*> li at,32768 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori at,at,0x5a5 +[0-9a-f]+ <[^>]*> slt at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> blezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bgezc a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> blezc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bltc a0,a1,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +[0-9a-f]+ <[^>]*> slt at,a1,a0 +[0-9a-f]+ <[^>]*> beqzc at,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +#pass diff --git a/gas/testsuite/gas/nanomips/blt.s b/gas/testsuite/gas/nanomips/blt.s new file mode 100644 index 00000000000..956ee14ccdc --- /dev/null +++ b/gas/testsuite/gas/nanomips/blt.s @@ -0,0 +1,24 @@ +# Source file used to test the blt macro. + +text_label: + blt $4, $5, text_label + blt $4, $0, text_label + blt $0, $5, text_label + blt $4, 0, text_label + blt $4, 1, text_label + blt $4, 2, text_label + blt $4, 0x8000, text_label + blt $4, -0x8000, text_label + blt $4, 0x10000, text_label + blt $4, 0x1a5a5, text_label + +# ble is handled like blt, except when both arguments are registers. +# Just sanity check it otherwise. + ble $4, $5, text_label + ble $4, $0, text_label + ble $0, $5, text_label + ble $4, 0, text_label + +# Branch to an external label. + blt $4, $5, external_label + ble $4, $5, external_label diff --git a/gas/testsuite/gas/nanomips/bltu.d b/gas/testsuite/gas/nanomips/bltu.d new file mode 100644 index 00000000000..c34f02c65d6 --- /dev/null +++ b/gas/testsuite/gas/nanomips/bltu.d @@ -0,0 +1,44 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS bltu + +# Test the bltu macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> bltuc a0,a1,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> beqzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bltiuc a0,2,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC11_S1 text_label +[0-9a-f]+ <[^>]*> li at,32768 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> lui at,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori at,at,0x5a5 +[0-9a-f]+ <[^>]*> sltu at,a0,at +[0-9a-f]+ <[^>]*> bnezc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> beqzc at,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> beqzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> beqzc a0,00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 text_label +[0-9a-f]+ <[^>]*> bltuc a0,a1,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +[0-9a-f]+ <[^>]*> sltu at,a1,a0 +[0-9a-f]+ <[^>]*> beqzc at,00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC14_S1 external_label +#pass diff --git a/gas/testsuite/gas/nanomips/bltu.s b/gas/testsuite/gas/nanomips/bltu.s new file mode 100644 index 00000000000..80c9106b657 --- /dev/null +++ b/gas/testsuite/gas/nanomips/bltu.s @@ -0,0 +1,21 @@ +# Source file used to test the bltu macro. + +text_label: + bltu $4, $5, text_label + # A second argument of 0 or $0 is always false + bltu $4, 1, text_label + bltu $4, 2, text_label + bltu $4, 0x8000, text_label + bltu $4, -0x8000, text_label + bltu $4, 0x10000, text_label + bltu $4, 0x1a5a5, text_label + +# bleu is handled like bltu, except when both arguments are registers. +# Just sanity check it otherwise. + bleu $4, $5, text_label + bleu $4, $0, text_label + bleu $4, 0, text_label + +# Branch to an external label. + bltu $4, $5, external_label + bleu $4, $5, external_label diff --git a/gas/testsuite/gas/nanomips/cp0-names-numeric.d b/gas/testsuite/gas/nanomips/cp0-names-numeric.d new file mode 100644 index 00000000000..076547febe9 --- /dev/null +++ b/gas/testsuite/gas/nanomips/cp0-names-numeric.d @@ -0,0 +1,44 @@ +#objdump: -dr -M gpr-names=numeric,cp0-names=numeric +#name: nanoMIPS CP0 register disassembly (numeric) +#source: cp0-names.s + +# Check objdump's handling of -M cp0-names=foo options. + +.*: +file format .*nanomips.* + +Disassembly of section .text: + +0+0000 : + 0: 2000 0070 mtc0 \$0,\$0 + 4: 2001 0070 mtc0 \$0,\$1 + 8: 2002 0070 mtc0 \$0,\$2 + c: 2003 0070 mtc0 \$0,\$3 + 10: 2004 0070 mtc0 \$0,\$4 + 14: 2005 0070 mtc0 \$0,\$5 + 18: 2006 0070 mtc0 \$0,\$6 + 1c: 2007 0070 mtc0 \$0,\$7 + 20: 2008 0070 mtc0 \$0,\$8 + 24: 2009 0070 mtc0 \$0,\$9 + 28: 200a 0070 mtc0 \$0,\$10 + 2c: 200b 0070 mtc0 \$0,\$11 + 30: 200c 0070 mtc0 \$0,\$12 + 34: 200d 0070 mtc0 \$0,\$13 + 38: 200e 0070 mtc0 \$0,\$14 + 3c: 200f 0070 mtc0 \$0,\$15 + 40: 2010 0070 mtc0 \$0,\$16 + 44: 2011 0070 mtc0 \$0,\$17 + 48: 2012 0070 mtc0 \$0,\$18 + 4c: 2013 0070 mtc0 \$0,\$19 + 50: 2014 0070 mtc0 \$0,\$20 + 54: 2015 0070 mtc0 \$0,\$21 + 58: 2016 0070 mtc0 \$0,\$22 + 5c: 2017 0070 mtc0 \$0,\$23 + 60: 2018 0070 mtc0 \$0,\$24 + 64: 2019 0070 mtc0 \$0,\$25 + 68: 201a 0070 mtc0 \$0,\$26 + 6c: 201b 0070 mtc0 \$0,\$27 + 70: 201c 0070 mtc0 \$0,\$28 + 74: 201d 0070 mtc0 \$0,\$29 + 78: 201e 0070 mtc0 \$0,\$30 + 7c: 201f 0070 mtc0 \$0,\$31 +#pass diff --git a/gas/testsuite/gas/nanomips/cp0-names.d b/gas/testsuite/gas/nanomips/cp0-names.d new file mode 100644 index 00000000000..495181075b3 --- /dev/null +++ b/gas/testsuite/gas/nanomips/cp0-names.d @@ -0,0 +1,43 @@ +#objdump: -dr -M gpr-names=numeric,cp0-names=32r6 +#name: nanoMIPS CP0 register disassembly \(32r6\) +#source: cp0-names.s + +# Check objdump's handling of -M cp0-names=foo options. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +0+0000 : + 0: 2000 0070 mtc0 \$0,index + 4: 2001 0070 mtc0 \$0,random + 8: 2002 0070 mtc0 \$0,entrylo0 + c: 2003 0070 mtc0 \$0,entrylo1 + 10: 2004 0070 mtc0 \$0,context + 14: 2005 0070 mtc0 \$0,pagemask + 18: 2006 0070 mtc0 \$0,wired + 1c: 2007 0070 mtc0 \$0,hwrena + 20: 2008 0070 mtc0 \$0,badvaddr + 24: 2009 0070 mtc0 \$0,count + 28: 200a 0070 mtc0 \$0,entryhi + 2c: 200b 0070 mtc0 \$0,compare + 30: 200c 0070 mtc0 \$0,status + 34: 200d 0070 mtc0 \$0,cause + 38: 200e 0070 mtc0 \$0,epc + 3c: 200f 0070 mtc0 \$0,prid + 40: 2010 0070 mtc0 \$0,config + 44: 2011 0070 mtc0 \$0,lladdr + 48: 2012 0070 mtc0 \$0,watchlo,0 + 4c: 2013 0070 mtc0 \$0,watchhi,0 + 50: 2014 0070 mtc0 \$0,xcontext + 54: 2015 0070 mtc0 \$0,\$21 + 58: 2016 0070 mtc0 \$0,\$22 + 5c: 2017 0070 mtc0 \$0,debug + 60: 2018 0070 mtc0 \$0,depc + 64: 2019 0070 mtc0 \$0,perfctl,0 + 68: 201a 0070 mtc0 \$0,errctl + 6c: 201b 0070 mtc0 \$0,cacheerr + 70: 201c 0070 mtc0 \$0,taglo,0 + 74: 201d 0070 mtc0 \$0,taghi,0 + 78: 201e 0070 mtc0 \$0,errorepc + 7c: 201f 0070 mtc0 \$0,desave diff --git a/gas/testsuite/gas/nanomips/cp0-names.s b/gas/testsuite/gas/nanomips/cp0-names.s new file mode 100644 index 00000000000..aa1c9451fbf --- /dev/null +++ b/gas/testsuite/gas/nanomips/cp0-names.s @@ -0,0 +1,38 @@ +# source file to test objdump's disassembly using various styles of +# CP0 register names. + + .text +text_label: + + mtc0 $0, $0 + mtc0 $0, $1 + mtc0 $0, $2 + mtc0 $0, $3 + mtc0 $0, $4 + mtc0 $0, $5 + mtc0 $0, $6 + mtc0 $0, $7 + mtc0 $0, $8 + mtc0 $0, $9 + mtc0 $0, $10 + mtc0 $0, $11 + mtc0 $0, $12 + mtc0 $0, $13 + mtc0 $0, $14 + mtc0 $0, $15 + mtc0 $0, $16 + mtc0 $0, $17 + mtc0 $0, $18 + mtc0 $0, $19 + mtc0 $0, $20 + mtc0 $0, $21 + mtc0 $0, $22 + mtc0 $0, $23 + mtc0 $0, $24 + mtc0 $0, $25 + mtc0 $0, $26 + mtc0 $0, $27 + mtc0 $0, $28 + mtc0 $0, $29 + mtc0 $0, $30 + mtc0 $0, $31 diff --git a/gas/testsuite/gas/nanomips/cp0sel-names-numeric.d b/gas/testsuite/gas/nanomips/cp0sel-names-numeric.d new file mode 100644 index 00000000000..67c32373be6 --- /dev/null +++ b/gas/testsuite/gas/nanomips/cp0sel-names-numeric.d @@ -0,0 +1,236 @@ +#objdump: -dr -M gpr-names=numeric,cp0-names=numeric +#name: nanoMIPS CP0 with sel register disassembly \(numeric\) +#source: cp0sel-names.s + +# Check objdump's handling of -M cp0-names=foo options. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +0+0000 : + 0: 2000 0870 mtc0 \$0,\$0,1 + 4: 2000 1070 mtc0 \$0,\$0,2 + 8: 2000 1870 mtc0 \$0,\$0,3 + c: 2000 2070 mtc0 \$0,\$0,4 + 10: 2000 2870 mtc0 \$0,\$0,5 + 14: 2000 3070 mtc0 \$0,\$0,6 + 18: 2000 3870 mtc0 \$0,\$0,7 + 1c: 2001 0870 mtc0 \$0,\$1,1 + 20: 2001 1070 mtc0 \$0,\$1,2 + 24: 2001 1870 mtc0 \$0,\$1,3 + 28: 2001 2070 mtc0 \$0,\$1,4 + 2c: 2001 2870 mtc0 \$0,\$1,5 + 30: 2001 3070 mtc0 \$0,\$1,6 + 34: 2001 3870 mtc0 \$0,\$1,7 + 38: 2002 0870 mtc0 \$0,\$2,1 + 3c: 2002 1070 mtc0 \$0,\$2,2 + 40: 2002 1870 mtc0 \$0,\$2,3 + 44: 2002 2070 mtc0 \$0,\$2,4 + 48: 2002 2870 mtc0 \$0,\$2,5 + 4c: 2002 3070 mtc0 \$0,\$2,6 + 50: 2002 3870 mtc0 \$0,\$2,7 + 54: 2003 0870 mtc0 \$0,\$3,1 + 58: 2003 1070 mtc0 \$0,\$3,2 + 5c: 2003 1870 mtc0 \$0,\$3,3 + 60: 2003 2070 mtc0 \$0,\$3,4 + 64: 2003 2870 mtc0 \$0,\$3,5 + 68: 2003 3070 mtc0 \$0,\$3,6 + 6c: 2003 3870 mtc0 \$0,\$3,7 + 70: 2004 0870 mtc0 \$0,\$4,1 + 74: 2004 1070 mtc0 \$0,\$4,2 + 78: 2004 1870 mtc0 \$0,\$4,3 + 7c: 2004 2070 mtc0 \$0,\$4,4 + 80: 2004 2870 mtc0 \$0,\$4,5 + 84: 2004 3070 mtc0 \$0,\$4,6 + 88: 2004 3870 mtc0 \$0,\$4,7 + 8c: 2005 0870 mtc0 \$0,\$5,1 + 90: 2005 1070 mtc0 \$0,\$5,2 + 94: 2005 1870 mtc0 \$0,\$5,3 + 98: 2005 2070 mtc0 \$0,\$5,4 + 9c: 2005 2870 mtc0 \$0,\$5,5 + a0: 2005 3070 mtc0 \$0,\$5,6 + a4: 2005 3870 mtc0 \$0,\$5,7 + a8: 2006 0870 mtc0 \$0,\$6,1 + ac: 2006 1070 mtc0 \$0,\$6,2 + b0: 2006 1870 mtc0 \$0,\$6,3 + b4: 2006 2070 mtc0 \$0,\$6,4 + b8: 2006 2870 mtc0 \$0,\$6,5 + bc: 2006 3070 mtc0 \$0,\$6,6 + c0: 2006 3870 mtc0 \$0,\$6,7 + c4: 2007 0870 mtc0 \$0,\$7,1 + c8: 2007 1070 mtc0 \$0,\$7,2 + cc: 2007 1870 mtc0 \$0,\$7,3 + d0: 2007 2070 mtc0 \$0,\$7,4 + d4: 2007 2870 mtc0 \$0,\$7,5 + d8: 2007 3070 mtc0 \$0,\$7,6 + dc: 2007 3870 mtc0 \$0,\$7,7 + e0: 2008 0870 mtc0 \$0,\$8,1 + e4: 2008 1070 mtc0 \$0,\$8,2 + e8: 2008 1870 mtc0 \$0,\$8,3 + ec: 2008 2070 mtc0 \$0,\$8,4 + f0: 2008 2870 mtc0 \$0,\$8,5 + f4: 2008 3070 mtc0 \$0,\$8,6 + f8: 2008 3870 mtc0 \$0,\$8,7 + fc: 2009 0870 mtc0 \$0,\$9,1 + 100: 2009 1070 mtc0 \$0,\$9,2 + 104: 2009 1870 mtc0 \$0,\$9,3 + 108: 2009 2070 mtc0 \$0,\$9,4 + 10c: 2009 2870 mtc0 \$0,\$9,5 + 110: 2009 3070 mtc0 \$0,\$9,6 + 114: 2009 3870 mtc0 \$0,\$9,7 + 118: 200a 0870 mtc0 \$0,\$10,1 + 11c: 200a 1070 mtc0 \$0,\$10,2 + 120: 200a 1870 mtc0 \$0,\$10,3 + 124: 200a 2070 mtc0 \$0,\$10,4 + 128: 200a 2870 mtc0 \$0,\$10,5 + 12c: 200a 3070 mtc0 \$0,\$10,6 + 130: 200a 3870 mtc0 \$0,\$10,7 + 134: 200b 0870 mtc0 \$0,\$11,1 + 138: 200b 1070 mtc0 \$0,\$11,2 + 13c: 200b 1870 mtc0 \$0,\$11,3 + 140: 200b 2070 mtc0 \$0,\$11,4 + 144: 200b 2870 mtc0 \$0,\$11,5 + 148: 200b 3070 mtc0 \$0,\$11,6 + 14c: 200b 3870 mtc0 \$0,\$11,7 + 150: 200c 0870 mtc0 \$0,\$12,1 + 154: 200c 1070 mtc0 \$0,\$12,2 + 158: 200c 1870 mtc0 \$0,\$12,3 + 15c: 200c 2070 mtc0 \$0,\$12,4 + 160: 200c 2870 mtc0 \$0,\$12,5 + 164: 200c 3070 mtc0 \$0,\$12,6 + 168: 200c 3870 mtc0 \$0,\$12,7 + 16c: 200d 0870 mtc0 \$0,\$13,1 + 170: 200d 1070 mtc0 \$0,\$13,2 + 174: 200d 1870 mtc0 \$0,\$13,3 + 178: 200d 2070 mtc0 \$0,\$13,4 + 17c: 200d 2870 mtc0 \$0,\$13,5 + 180: 200d 3070 mtc0 \$0,\$13,6 + 184: 200d 3870 mtc0 \$0,\$13,7 + 188: 200e 0870 mtc0 \$0,\$14,1 + 18c: 200e 1070 mtc0 \$0,\$14,2 + 190: 200e 1870 mtc0 \$0,\$14,3 + 194: 200e 2070 mtc0 \$0,\$14,4 + 198: 200e 2870 mtc0 \$0,\$14,5 + 19c: 200e 3070 mtc0 \$0,\$14,6 + 1a0: 200e 3870 mtc0 \$0,\$14,7 + 1a4: 200f 0870 mtc0 \$0,\$15,1 + 1a8: 200f 1070 mtc0 \$0,\$15,2 + 1ac: 200f 1870 mtc0 \$0,\$15,3 + 1b0: 200f 2070 mtc0 \$0,\$15,4 + 1b4: 200f 2870 mtc0 \$0,\$15,5 + 1b8: 200f 3070 mtc0 \$0,\$15,6 + 1bc: 200f 3870 mtc0 \$0,\$15,7 + 1c0: 2010 0870 mtc0 \$0,\$16,1 + 1c4: 2010 1070 mtc0 \$0,\$16,2 + 1c8: 2010 1870 mtc0 \$0,\$16,3 + 1cc: 2010 2070 mtc0 \$0,\$16,4 + 1d0: 2010 2870 mtc0 \$0,\$16,5 + 1d4: 2010 3070 mtc0 \$0,\$16,6 + 1d8: 2010 3870 mtc0 \$0,\$16,7 + 1dc: 2011 0870 mtc0 \$0,\$17,1 + 1e0: 2011 1070 mtc0 \$0,\$17,2 + 1e4: 2011 1870 mtc0 \$0,\$17,3 + 1e8: 2011 2070 mtc0 \$0,\$17,4 + 1ec: 2011 2870 mtc0 \$0,\$17,5 + 1f0: 2011 3070 mtc0 \$0,\$17,6 + 1f4: 2011 3870 mtc0 \$0,\$17,7 + 1f8: 2012 0870 mtc0 \$0,\$18,1 + 1fc: 2012 1070 mtc0 \$0,\$18,2 + 200: 2012 1870 mtc0 \$0,\$18,3 + 204: 2012 2070 mtc0 \$0,\$18,4 + 208: 2012 2870 mtc0 \$0,\$18,5 + 20c: 2012 3070 mtc0 \$0,\$18,6 + 210: 2012 3870 mtc0 \$0,\$18,7 + 214: 2013 0870 mtc0 \$0,\$19,1 + 218: 2013 1070 mtc0 \$0,\$19,2 + 21c: 2013 1870 mtc0 \$0,\$19,3 + 220: 2013 2070 mtc0 \$0,\$19,4 + 224: 2013 2870 mtc0 \$0,\$19,5 + 228: 2013 3070 mtc0 \$0,\$19,6 + 22c: 2013 3870 mtc0 \$0,\$19,7 + 230: 2014 0870 mtc0 \$0,\$20,1 + 234: 2014 1070 mtc0 \$0,\$20,2 + 238: 2014 1870 mtc0 \$0,\$20,3 + 23c: 2014 2070 mtc0 \$0,\$20,4 + 240: 2014 2870 mtc0 \$0,\$20,5 + 244: 2014 3070 mtc0 \$0,\$20,6 + 248: 2014 3870 mtc0 \$0,\$20,7 + 24c: 2015 0870 mtc0 \$0,\$21,1 + 250: 2015 1070 mtc0 \$0,\$21,2 + 254: 2015 1870 mtc0 \$0,\$21,3 + 258: 2015 2070 mtc0 \$0,\$21,4 + 25c: 2015 2870 mtc0 \$0,\$21,5 + 260: 2015 3070 mtc0 \$0,\$21,6 + 264: 2015 3870 mtc0 \$0,\$21,7 + 268: 2016 0870 mtc0 \$0,\$22,1 + 26c: 2016 1070 mtc0 \$0,\$22,2 + 270: 2016 1870 mtc0 \$0,\$22,3 + 274: 2016 2070 mtc0 \$0,\$22,4 + 278: 2016 2870 mtc0 \$0,\$22,5 + 27c: 2016 3070 mtc0 \$0,\$22,6 + 280: 2016 3870 mtc0 \$0,\$22,7 + 284: 2017 0870 mtc0 \$0,\$23,1 + 288: 2017 1070 mtc0 \$0,\$23,2 + 28c: 2017 1870 mtc0 \$0,\$23,3 + 290: 2017 2070 mtc0 \$0,\$23,4 + 294: 2017 2870 mtc0 \$0,\$23,5 + 298: 2017 3070 mtc0 \$0,\$23,6 + 29c: 2017 3870 mtc0 \$0,\$23,7 + 2a0: 2018 0870 mtc0 \$0,\$24,1 + 2a4: 2018 1070 mtc0 \$0,\$24,2 + 2a8: 2018 1870 mtc0 \$0,\$24,3 + 2ac: 2018 2070 mtc0 \$0,\$24,4 + 2b0: 2018 2870 mtc0 \$0,\$24,5 + 2b4: 2018 3070 mtc0 \$0,\$24,6 + 2b8: 2018 3870 mtc0 \$0,\$24,7 + 2bc: 2019 0870 mtc0 \$0,\$25,1 + 2c0: 2019 1070 mtc0 \$0,\$25,2 + 2c4: 2019 1870 mtc0 \$0,\$25,3 + 2c8: 2019 2070 mtc0 \$0,\$25,4 + 2cc: 2019 2870 mtc0 \$0,\$25,5 + 2d0: 2019 3070 mtc0 \$0,\$25,6 + 2d4: 2019 3870 mtc0 \$0,\$25,7 + 2d8: 201a 0870 mtc0 \$0,\$26,1 + 2dc: 201a 1070 mtc0 \$0,\$26,2 + 2e0: 201a 1870 mtc0 \$0,\$26,3 + 2e4: 201a 2070 mtc0 \$0,\$26,4 + 2e8: 201a 2870 mtc0 \$0,\$26,5 + 2ec: 201a 3070 mtc0 \$0,\$26,6 + 2f0: 201a 3870 mtc0 \$0,\$26,7 + 2f4: 201b 0870 mtc0 \$0,\$27,1 + 2f8: 201b 1070 mtc0 \$0,\$27,2 + 2fc: 201b 1870 mtc0 \$0,\$27,3 + 300: 201b 2070 mtc0 \$0,\$27,4 + 304: 201b 2870 mtc0 \$0,\$27,5 + 308: 201b 3070 mtc0 \$0,\$27,6 + 30c: 201b 3870 mtc0 \$0,\$27,7 + 310: 201c 0870 mtc0 \$0,\$28,1 + 314: 201c 1070 mtc0 \$0,\$28,2 + 318: 201c 1870 mtc0 \$0,\$28,3 + 31c: 201c 2070 mtc0 \$0,\$28,4 + 320: 201c 2870 mtc0 \$0,\$28,5 + 324: 201c 3070 mtc0 \$0,\$28,6 + 328: 201c 3870 mtc0 \$0,\$28,7 + 32c: 201d 0870 mtc0 \$0,\$29,1 + 330: 201d 1070 mtc0 \$0,\$29,2 + 334: 201d 1870 mtc0 \$0,\$29,3 + 338: 201d 2070 mtc0 \$0,\$29,4 + 33c: 201d 2870 mtc0 \$0,\$29,5 + 340: 201d 3070 mtc0 \$0,\$29,6 + 344: 201d 3870 mtc0 \$0,\$29,7 + 348: 201e 0870 mtc0 \$0,\$30,1 + 34c: 201e 1070 mtc0 \$0,\$30,2 + 350: 201e 1870 mtc0 \$0,\$30,3 + 354: 201e 2070 mtc0 \$0,\$30,4 + 358: 201e 2870 mtc0 \$0,\$30,5 + 35c: 201e 3070 mtc0 \$0,\$30,6 + 360: 201e 3870 mtc0 \$0,\$30,7 + 364: 201f 0870 mtc0 \$0,\$31,1 + 368: 201f 1070 mtc0 \$0,\$31,2 + 36c: 201f 1870 mtc0 \$0,\$31,3 + 370: 201f 2070 mtc0 \$0,\$31,4 + 374: 201f 2870 mtc0 \$0,\$31,5 + 378: 201f 3070 mtc0 \$0,\$31,6 + 37c: 201f 3870 mtc0 \$0,\$31,7 +#pass diff --git a/gas/testsuite/gas/nanomips/cp0sel-names.d b/gas/testsuite/gas/nanomips/cp0sel-names.d new file mode 100644 index 00000000000..0fd8ff42392 --- /dev/null +++ b/gas/testsuite/gas/nanomips/cp0sel-names.d @@ -0,0 +1,235 @@ +#objdump: -dr -M gpr-names=numeric,cp0-names=32r6 +#name: nanoMIPS CP0 with sel register disassembly + +# Check objdump's handling of -M cp0-names=foo options. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +0+0000 : + 0: 2000 0870 mtc0 \$0,mvpcontrol + 4: 2000 1070 mtc0 \$0,mvpconf0 + 8: 2000 1870 mtc0 \$0,mvpconf1 + c: 2000 2070 mtc0 \$0,vpcontrol + 10: 2000 2870 mtc0 \$0,\$0,5 + 14: 2000 3070 mtc0 \$0,\$0,6 + 18: 2000 3870 mtc0 \$0,\$0,7 + 1c: 2001 0870 mtc0 \$0,vpecontrol + 20: 2001 1070 mtc0 \$0,vpeconf0 + 24: 2001 1870 mtc0 \$0,vpeconf1 + 28: 2001 2070 mtc0 \$0,yqmask + 2c: 2001 2870 mtc0 \$0,vpeschedule + 30: 2001 3070 mtc0 \$0,vpeschefback + 34: 2001 3870 mtc0 \$0,vpeopt + 38: 2002 0870 mtc0 \$0,tcstatus + 3c: 2002 1070 mtc0 \$0,tcbind + 40: 2002 1870 mtc0 \$0,tcrestart + 44: 2002 2070 mtc0 \$0,tchalt + 48: 2002 2870 mtc0 \$0,tccontext + 4c: 2002 3070 mtc0 \$0,tcschedule + 50: 2002 3870 mtc0 \$0,tcschefback + 54: 2003 0870 mtc0 \$0,\$3,1 + 58: 2003 1070 mtc0 \$0,\$3,2 + 5c: 2003 1870 mtc0 \$0,\$3,3 + 60: 2003 2070 mtc0 \$0,\$3,4 + 64: 2003 2870 mtc0 \$0,\$3,5 + 68: 2003 3070 mtc0 \$0,\$3,6 + 6c: 2003 3870 mtc0 \$0,tcopt + 70: 2004 0870 mtc0 \$0,contextconfig + 74: 2004 1070 mtc0 \$0,userlocal + 78: 2004 1870 mtc0 \$0,xcontextconfig + 7c: 2004 2070 mtc0 \$0,\$4,4 + 80: 2004 2870 mtc0 \$0,\$4,5 + 84: 2004 3070 mtc0 \$0,\$4,6 + 88: 2004 3870 mtc0 \$0,\$4,7 + 8c: 2005 0870 mtc0 \$0,pagegrain + 90: 2005 1070 mtc0 \$0,segctl0 + 94: 2005 1870 mtc0 \$0,segctl1 + 98: 2005 2070 mtc0 \$0,segctl2 + 9c: 2005 2870 mtc0 \$0,pwbase + a0: 2005 3070 mtc0 \$0,pwfield + a4: 2005 3870 mtc0 \$0,pwsize + a8: 2006 0870 mtc0 \$0,srsconf0 + ac: 2006 1070 mtc0 \$0,srsconf1 + b0: 2006 1870 mtc0 \$0,srsconf2 + b4: 2006 2070 mtc0 \$0,srsconf3 + b8: 2006 2870 mtc0 \$0,srsconf4 + bc: 2006 3070 mtc0 \$0,pwctl + c0: 2006 3870 mtc0 \$0,\$6,7 + c4: 2007 0870 mtc0 \$0,\$7,1 + c8: 2007 1070 mtc0 \$0,\$7,2 + cc: 2007 1870 mtc0 \$0,\$7,3 + d0: 2007 2070 mtc0 \$0,\$7,4 + d4: 2007 2870 mtc0 \$0,\$7,5 + d8: 2007 3070 mtc0 \$0,\$7,6 + dc: 2007 3870 mtc0 \$0,\$7,7 + e0: 2008 0870 mtc0 \$0,badinst + e4: 2008 1070 mtc0 \$0,badinstrp + e8: 2008 1870 mtc0 \$0,\$8,3 + ec: 2008 2070 mtc0 \$0,\$8,4 + f0: 2008 2870 mtc0 \$0,\$8,5 + f4: 2008 3070 mtc0 \$0,\$8,6 + f8: 2008 3870 mtc0 \$0,\$8,7 + fc: 2009 0870 mtc0 \$0,\$9,1 + 100: 2009 1070 mtc0 \$0,\$9,2 + 104: 2009 1870 mtc0 \$0,\$9,3 + 108: 2009 2070 mtc0 \$0,\$9,4 + 10c: 2009 2870 mtc0 \$0,\$9,5 + 110: 2009 3070 mtc0 \$0,\$9,6 + 114: 2009 3870 mtc0 \$0,\$9,7 + 118: 200a 0870 mtc0 \$0,\$10,1 + 11c: 200a 1070 mtc0 \$0,\$10,2 + 120: 200a 1870 mtc0 \$0,\$10,3 + 124: 200a 2070 mtc0 \$0,guestctl1 + 128: 200a 2870 mtc0 \$0,guestctl2 + 12c: 200a 3070 mtc0 \$0,guestctl3 + 130: 200a 3870 mtc0 \$0,\$10,7 + 134: 200b 0870 mtc0 \$0,\$11,1 + 138: 200b 1070 mtc0 \$0,\$11,2 + 13c: 200b 1870 mtc0 \$0,\$11,3 + 140: 200b 2070 mtc0 \$0,guestctl0ext + 144: 200b 2870 mtc0 \$0,\$11,5 + 148: 200b 3070 mtc0 \$0,\$11,6 + 14c: 200b 3870 mtc0 \$0,\$11,7 + 150: 200c 0870 mtc0 \$0,intctl + 154: 200c 1070 mtc0 \$0,srsctl + 158: 200c 1870 mtc0 \$0,srsmap + 15c: 200c 2070 mtc0 \$0,view_ipl + 160: 200c 2870 mtc0 \$0,srsmap2 + 164: 200c 3070 mtc0 \$0,guestctl0 + 168: 200c 3870 mtc0 \$0,gtoffset + 16c: 200d 0870 mtc0 \$0,\$13,1 + 170: 200d 1070 mtc0 \$0,\$13,2 + 174: 200d 1870 mtc0 \$0,\$13,3 + 178: 200d 2070 mtc0 \$0,view_ripl + 17c: 200d 2870 mtc0 \$0,nestedexc + 180: 200d 3070 mtc0 \$0,\$13,6 + 184: 200d 3870 mtc0 \$0,\$13,7 + 188: 200e 0870 mtc0 \$0,\$14,1 + 18c: 200e 1070 mtc0 \$0,nestedepc + 190: 200e 1870 mtc0 \$0,\$14,3 + 194: 200e 2070 mtc0 \$0,\$14,4 + 198: 200e 2870 mtc0 \$0,\$14,5 + 19c: 200e 3070 mtc0 \$0,\$14,6 + 1a0: 200e 3870 mtc0 \$0,\$14,7 + 1a4: 200f 0870 mtc0 \$0,ebase + 1a8: 200f 1070 mtc0 \$0,cdmmbase + 1ac: 200f 1870 mtc0 \$0,cmgcrbase + 1b0: 200f 2070 mtc0 \$0,\$15,4 + 1b4: 200f 2870 mtc0 \$0,\$15,5 + 1b8: 200f 3070 mtc0 \$0,\$15,6 + 1bc: 200f 3870 mtc0 \$0,\$15,7 + 1c0: 2010 0870 mtc0 \$0,config1 + 1c4: 2010 1070 mtc0 \$0,config2 + 1c8: 2010 1870 mtc0 \$0,config3 + 1cc: 2010 2070 mtc0 \$0,config4 + 1d0: 2010 2870 mtc0 \$0,config5 + 1d4: 2010 3070 mtc0 \$0,\$16,6 + 1d8: 2010 3870 mtc0 \$0,\$16,7 + 1dc: 2011 0870 mtc0 \$0,\$17,1 + 1e0: 2011 1070 mtc0 \$0,\$17,2 + 1e4: 2011 1870 mtc0 \$0,\$17,3 + 1e8: 2011 2070 mtc0 \$0,\$17,4 + 1ec: 2011 2870 mtc0 \$0,\$17,5 + 1f0: 2011 3070 mtc0 \$0,\$17,6 + 1f4: 2011 3870 mtc0 \$0,\$17,7 + 1f8: 2012 0870 mtc0 \$0,watchlo,1 + 1fc: 2012 1070 mtc0 \$0,watchlo,2 + 200: 2012 1870 mtc0 \$0,watchlo,3 + 204: 2012 2070 mtc0 \$0,watchlo,4 + 208: 2012 2870 mtc0 \$0,watchlo,5 + 20c: 2012 3070 mtc0 \$0,watchlo,6 + 210: 2012 3870 mtc0 \$0,watchlo,7 + 214: 2013 0870 mtc0 \$0,watchhi,1 + 218: 2013 1070 mtc0 \$0,watchhi,2 + 21c: 2013 1870 mtc0 \$0,watchhi,3 + 220: 2013 2070 mtc0 \$0,watchhi,4 + 224: 2013 2870 mtc0 \$0,watchhi,5 + 228: 2013 3070 mtc0 \$0,watchhi,6 + 22c: 2013 3870 mtc0 \$0,watchhi,7 + 230: 2014 0870 mtc0 \$0,\$20,1 + 234: 2014 1070 mtc0 \$0,\$20,2 + 238: 2014 1870 mtc0 \$0,\$20,3 + 23c: 2014 2070 mtc0 \$0,\$20,4 + 240: 2014 2870 mtc0 \$0,\$20,5 + 244: 2014 3070 mtc0 \$0,\$20,6 + 248: 2014 3870 mtc0 \$0,\$20,7 + 24c: 2015 0870 mtc0 \$0,\$21,1 + 250: 2015 1070 mtc0 \$0,\$21,2 + 254: 2015 1870 mtc0 \$0,\$21,3 + 258: 2015 2070 mtc0 \$0,\$21,4 + 25c: 2015 2870 mtc0 \$0,\$21,5 + 260: 2015 3070 mtc0 \$0,\$21,6 + 264: 2015 3870 mtc0 \$0,\$21,7 + 268: 2016 0870 mtc0 \$0,\$22,1 + 26c: 2016 1070 mtc0 \$0,\$22,2 + 270: 2016 1870 mtc0 \$0,\$22,3 + 274: 2016 2070 mtc0 \$0,\$22,4 + 278: 2016 2870 mtc0 \$0,\$22,5 + 27c: 2016 3070 mtc0 \$0,\$22,6 + 280: 2016 3870 mtc0 \$0,\$22,7 + 284: 2017 0870 mtc0 \$0,tracecontrol + 288: 2017 1070 mtc0 \$0,tracecontrol2 + 28c: 2017 1870 mtc0 \$0,usertracedata1 + 290: 2017 2070 mtc0 \$0,traceibpc + 294: 2017 2870 mtc0 \$0,tracedbpc + 298: 2017 3070 mtc0 \$0,debug2 + 29c: 2017 3870 mtc0 \$0,\$23,7 + 2a0: 2018 0870 mtc0 \$0,\$24,1 + 2a4: 2018 1070 mtc0 \$0,tracecontrol3 + 2a8: 2018 1870 mtc0 \$0,usertracedata2 + 2ac: 2018 2070 mtc0 \$0,\$24,4 + 2b0: 2018 2870 mtc0 \$0,\$24,5 + 2b4: 2018 3070 mtc0 \$0,\$24,6 + 2b8: 2018 3870 mtc0 \$0,\$24,7 + 2bc: 2019 0870 mtc0 \$0,perfcnt,1 + 2c0: 2019 1070 mtc0 \$0,perfctl,2 + 2c4: 2019 1870 mtc0 \$0,perfcnt,3 + 2c8: 2019 2070 mtc0 \$0,perfctl,4 + 2cc: 2019 2870 mtc0 \$0,perfcnt,5 + 2d0: 2019 3070 mtc0 \$0,perfctl,6 + 2d4: 2019 3870 mtc0 \$0,perfcnt,7 + 2d8: 201a 0870 mtc0 \$0,\$26,1 + 2dc: 201a 1070 mtc0 \$0,\$26,2 + 2e0: 201a 1870 mtc0 \$0,\$26,3 + 2e4: 201a 2070 mtc0 \$0,\$26,4 + 2e8: 201a 2870 mtc0 \$0,\$26,5 + 2ec: 201a 3070 mtc0 \$0,\$26,6 + 2f0: 201a 3870 mtc0 \$0,\$26,7 + 2f4: 201b 0870 mtc0 \$0,\$27,1 + 2f8: 201b 1070 mtc0 \$0,\$27,2 + 2fc: 201b 1870 mtc0 \$0,\$27,3 + 300: 201b 2070 mtc0 \$0,\$27,4 + 304: 201b 2870 mtc0 \$0,\$27,5 + 308: 201b 3070 mtc0 \$0,\$27,6 + 30c: 201b 3870 mtc0 \$0,\$27,7 + 310: 201c 0870 mtc0 \$0,datalo,1 + 314: 201c 1070 mtc0 \$0,taglo,2 + 318: 201c 1870 mtc0 \$0,datalo,3 + 31c: 201c 2070 mtc0 \$0,taglo,4 + 320: 201c 2870 mtc0 \$0,datalo,5 + 324: 201c 3070 mtc0 \$0,taglo,6 + 328: 201c 3870 mtc0 \$0,datalo,7 + 32c: 201d 0870 mtc0 \$0,datahi,1 + 330: 201d 1070 mtc0 \$0,taghi,2 + 334: 201d 1870 mtc0 \$0,datahi,3 + 338: 201d 2070 mtc0 \$0,taghi,4 + 33c: 201d 2870 mtc0 \$0,datahi,5 + 340: 201d 3070 mtc0 \$0,taghi,6 + 344: 201d 3870 mtc0 \$0,datahi,7 + 348: 201e 0870 mtc0 \$0,\$30,1 + 34c: 201e 1070 mtc0 \$0,\$30,2 + 350: 201e 1870 mtc0 \$0,\$30,3 + 354: 201e 2070 mtc0 \$0,\$30,4 + 358: 201e 2870 mtc0 \$0,\$30,5 + 35c: 201e 3070 mtc0 \$0,\$30,6 + 360: 201e 3870 mtc0 \$0,\$30,7 + 364: 201f 0870 mtc0 \$0,\$31,1 + 368: 201f 1070 mtc0 \$0,kscratch1 + 36c: 201f 1870 mtc0 \$0,kscratch2 + 370: 201f 2070 mtc0 \$0,kscratch3 + 374: 201f 2870 mtc0 \$0,kscratch4 + 378: 201f 3070 mtc0 \$0,kscratch5 + 37c: 201f 3870 mtc0 \$0,kscratch6 + \.\.\. diff --git a/gas/testsuite/gas/nanomips/cp0sel-names.s b/gas/testsuite/gas/nanomips/cp0sel-names.s new file mode 100644 index 00000000000..f65d26cc1ad --- /dev/null +++ b/gas/testsuite/gas/nanomips/cp0sel-names.s @@ -0,0 +1,236 @@ +# source file to test objdump's disassembly using various styles of +# CP0 (w/ non-zero select code) register names. + + .set noreorder + .set noat + + .globl text_label + .text +text_label: + + mtc0 $0, $0, 1 + mtc0 $0, $0, 2 + mtc0 $0, $0, 3 + mtc0 $0, $0, 4 + mtc0 $0, $0, 5 + mtc0 $0, $0, 6 + mtc0 $0, $0, 7 + mtc0 $0, $1, 1 + mtc0 $0, $1, 2 + mtc0 $0, $1, 3 + mtc0 $0, $1, 4 + mtc0 $0, $1, 5 + mtc0 $0, $1, 6 + mtc0 $0, $1, 7 + mtc0 $0, $2, 1 + mtc0 $0, $2, 2 + mtc0 $0, $2, 3 + mtc0 $0, $2, 4 + mtc0 $0, $2, 5 + mtc0 $0, $2, 6 + mtc0 $0, $2, 7 + mtc0 $0, $3, 1 + mtc0 $0, $3, 2 + mtc0 $0, $3, 3 + mtc0 $0, $3, 4 + mtc0 $0, $3, 5 + mtc0 $0, $3, 6 + mtc0 $0, $3, 7 + mtc0 $0, $4, 1 + mtc0 $0, $4, 2 + mtc0 $0, $4, 3 + mtc0 $0, $4, 4 + mtc0 $0, $4, 5 + mtc0 $0, $4, 6 + mtc0 $0, $4, 7 + mtc0 $0, $5, 1 + mtc0 $0, $5, 2 + mtc0 $0, $5, 3 + mtc0 $0, $5, 4 + mtc0 $0, $5, 5 + mtc0 $0, $5, 6 + mtc0 $0, $5, 7 + mtc0 $0, $6, 1 + mtc0 $0, $6, 2 + mtc0 $0, $6, 3 + mtc0 $0, $6, 4 + mtc0 $0, $6, 5 + mtc0 $0, $6, 6 + mtc0 $0, $6, 7 + mtc0 $0, $7, 1 + mtc0 $0, $7, 2 + mtc0 $0, $7, 3 + mtc0 $0, $7, 4 + mtc0 $0, $7, 5 + mtc0 $0, $7, 6 + mtc0 $0, $7, 7 + mtc0 $0, $8, 1 + mtc0 $0, $8, 2 + mtc0 $0, $8, 3 + mtc0 $0, $8, 4 + mtc0 $0, $8, 5 + mtc0 $0, $8, 6 + mtc0 $0, $8, 7 + mtc0 $0, $9, 1 + mtc0 $0, $9, 2 + mtc0 $0, $9, 3 + mtc0 $0, $9, 4 + mtc0 $0, $9, 5 + mtc0 $0, $9, 6 + mtc0 $0, $9, 7 + mtc0 $0, $10, 1 + mtc0 $0, $10, 2 + mtc0 $0, $10, 3 + mtc0 $0, $10, 4 + mtc0 $0, $10, 5 + mtc0 $0, $10, 6 + mtc0 $0, $10, 7 + mtc0 $0, $11, 1 + mtc0 $0, $11, 2 + mtc0 $0, $11, 3 + mtc0 $0, $11, 4 + mtc0 $0, $11, 5 + mtc0 $0, $11, 6 + mtc0 $0, $11, 7 + mtc0 $0, $12, 1 + mtc0 $0, $12, 2 + mtc0 $0, $12, 3 + mtc0 $0, $12, 4 + mtc0 $0, $12, 5 + mtc0 $0, $12, 6 + mtc0 $0, $12, 7 + mtc0 $0, $13, 1 + mtc0 $0, $13, 2 + mtc0 $0, $13, 3 + mtc0 $0, $13, 4 + mtc0 $0, $13, 5 + mtc0 $0, $13, 6 + mtc0 $0, $13, 7 + mtc0 $0, $14, 1 + mtc0 $0, $14, 2 + mtc0 $0, $14, 3 + mtc0 $0, $14, 4 + mtc0 $0, $14, 5 + mtc0 $0, $14, 6 + mtc0 $0, $14, 7 + mtc0 $0, $15, 1 + mtc0 $0, $15, 2 + mtc0 $0, $15, 3 + mtc0 $0, $15, 4 + mtc0 $0, $15, 5 + mtc0 $0, $15, 6 + mtc0 $0, $15, 7 + mtc0 $0, $16, 1 + mtc0 $0, $16, 2 + mtc0 $0, $16, 3 + mtc0 $0, $16, 4 + mtc0 $0, $16, 5 + mtc0 $0, $16, 6 + mtc0 $0, $16, 7 + mtc0 $0, $17, 1 + mtc0 $0, $17, 2 + mtc0 $0, $17, 3 + mtc0 $0, $17, 4 + mtc0 $0, $17, 5 + mtc0 $0, $17, 6 + mtc0 $0, $17, 7 + mtc0 $0, $18, 1 + mtc0 $0, $18, 2 + mtc0 $0, $18, 3 + mtc0 $0, $18, 4 + mtc0 $0, $18, 5 + mtc0 $0, $18, 6 + mtc0 $0, $18, 7 + mtc0 $0, $19, 1 + mtc0 $0, $19, 2 + mtc0 $0, $19, 3 + mtc0 $0, $19, 4 + mtc0 $0, $19, 5 + mtc0 $0, $19, 6 + mtc0 $0, $19, 7 + mtc0 $0, $20, 1 + mtc0 $0, $20, 2 + mtc0 $0, $20, 3 + mtc0 $0, $20, 4 + mtc0 $0, $20, 5 + mtc0 $0, $20, 6 + mtc0 $0, $20, 7 + mtc0 $0, $21, 1 + mtc0 $0, $21, 2 + mtc0 $0, $21, 3 + mtc0 $0, $21, 4 + mtc0 $0, $21, 5 + mtc0 $0, $21, 6 + mtc0 $0, $21, 7 + mtc0 $0, $22, 1 + mtc0 $0, $22, 2 + mtc0 $0, $22, 3 + mtc0 $0, $22, 4 + mtc0 $0, $22, 5 + mtc0 $0, $22, 6 + mtc0 $0, $22, 7 + mtc0 $0, $23, 1 + mtc0 $0, $23, 2 + mtc0 $0, $23, 3 + mtc0 $0, $23, 4 + mtc0 $0, $23, 5 + mtc0 $0, $23, 6 + mtc0 $0, $23, 7 + mtc0 $0, $24, 1 + mtc0 $0, $24, 2 + mtc0 $0, $24, 3 + mtc0 $0, $24, 4 + mtc0 $0, $24, 5 + mtc0 $0, $24, 6 + mtc0 $0, $24, 7 + mtc0 $0, $25, 1 + mtc0 $0, $25, 2 + mtc0 $0, $25, 3 + mtc0 $0, $25, 4 + mtc0 $0, $25, 5 + mtc0 $0, $25, 6 + mtc0 $0, $25, 7 + mtc0 $0, $26, 1 + mtc0 $0, $26, 2 + mtc0 $0, $26, 3 + mtc0 $0, $26, 4 + mtc0 $0, $26, 5 + mtc0 $0, $26, 6 + mtc0 $0, $26, 7 + mtc0 $0, $27, 1 + mtc0 $0, $27, 2 + mtc0 $0, $27, 3 + mtc0 $0, $27, 4 + mtc0 $0, $27, 5 + mtc0 $0, $27, 6 + mtc0 $0, $27, 7 + mtc0 $0, $28, 1 + mtc0 $0, $28, 2 + mtc0 $0, $28, 3 + mtc0 $0, $28, 4 + mtc0 $0, $28, 5 + mtc0 $0, $28, 6 + mtc0 $0, $28, 7 + mtc0 $0, $29, 1 + mtc0 $0, $29, 2 + mtc0 $0, $29, 3 + mtc0 $0, $29, 4 + mtc0 $0, $29, 5 + mtc0 $0, $29, 6 + mtc0 $0, $29, 7 + mtc0 $0, $30, 1 + mtc0 $0, $30, 2 + mtc0 $0, $30, 3 + mtc0 $0, $30, 4 + mtc0 $0, $30, 5 + mtc0 $0, $30, 6 + mtc0 $0, $30, 7 + mtc0 $0, $31, 1 + mtc0 $0, $31, 2 + mtc0 $0, $31, 3 + mtc0 $0, $31, 4 + mtc0 $0, $31, 5 + mtc0 $0, $31, 6 + mtc0 $0, $31, 7 + + .space 8 diff --git a/gas/testsuite/gas/nanomips/ctc.d b/gas/testsuite/gas/nanomips/ctc.d new file mode 100644 index 00000000000..546e3b10fa3 --- /dev/null +++ b/gas/testsuite/gas/nanomips/ctc.d @@ -0,0 +1,87 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS CTC instructions + +# Check nanoMIPS convert-to-compact branch instructions + +.*: +file format .*nanomips.* + +Disassembly of section .text: +[0-9a-f]+ <[^>]*> 1800 bc [0-9a-f]+ <[^>]+> + 0: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 1800 bc [0-9a-f]+ <[^>]+> + 2: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 2800 0000 bc [0-9a-f]+ <[^>]+> + 4: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 3800 balc [0-9a-f]+ <[^>]+> + 8: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 8a40 0000 beqzc s2,[0-9a-f]+ <[^>]+> + a: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 8a40 0000 beqzc s2,[0-9a-f]+ <[^>]+> + e: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 9900 beqzc s2,[0-9a-f]+ <[^>]+> + 12: R_NANOMIPS_PC7_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> da3f beqc s3,a0,[0-9a-f]+ <[^>]+> + 14: R_NANOMIPS_PC4_S1 ext +[0-9a-f]+ <[^>]*> da3f beqc s3,a0,[0-9a-f]+ <[^>]+> + 16: R_NANOMIPS_PC4_S1 ext +[0-9a-f]+ <[^>]*> 8a60 0000 beqzc s3,[0-9a-f]+ <[^>]+> + 18: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> 8a60 0000 beqzc s3,[0-9a-f]+ <[^>]+> + 1c: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> 8a72 0000 beqc s2,s3,[0-9a-f]+ <[^>]+> + 20: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> 8a72 0000 beqc s2,s3,[0-9a-f]+ <[^>]+> + 24: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> 9980 beqzc s3,[0-9a-f]+ <[^>]+> + 28: R_NANOMIPS_PC7_S1 ext +[0-9a-f]+ <[^>]*> 8a60 0000 beqzc s3,[0-9a-f]+ <[^>]+> + 2a: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> b900 bnezc s2,[0-9a-f]+ <[^>]+> + 2e: R_NANOMIPS_PC7_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> aa40 0000 bnezc s2,[0-9a-f]+ <[^>]+> + 30: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> b900 bnezc s2,[0-9a-f]+ <[^>]+> + 34: R_NANOMIPS_PC7_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> d9cf bnec a0,s3,[0-9a-f]+ <[^>]+> + 36: R_NANOMIPS_PC4_S1 ext +[0-9a-f]+ <[^>]*> d9cf bnec a0,s3,[0-9a-f]+ <[^>]+> + 38: R_NANOMIPS_PC4_S1 ext +[0-9a-f]+ <[^>]*> aa60 0000 bnezc s3,[0-9a-f]+ <[^>]+> + 3a: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> aa60 0000 bnezc s3,[0-9a-f]+ <[^>]+> + 3e: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> aa53 0000 bnec s3,s2,[0-9a-f]+ <[^>]+> + 42: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> aa53 0000 bnec s3,s2,[0-9a-f]+ <[^>]+> + 46: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> b980 bnezc s3,[0-9a-f]+ <[^>]+> + 4a: R_NANOMIPS_PC7_S1 ext +[0-9a-f]+ <[^>]*> aa60 0000 bnezc s3,[0-9a-f]+ <[^>]+> + 4c: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> 8812 8000 bgezc s2,[0-9a-f]+ <[^>]+> + 50: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> a812 8000 bltzc s2,[0-9a-f]+ <[^>]+> + 54: R_NANOMIPS_PC14_S1 ext +[0-9a-f]+ <[^>]*> d880 jrc a0 +[0-9a-f]+ <[^>]*> d840 jrc t4 +[0-9a-f]+ <[^>]*> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]*> 2800 0000 bc [0-9a-f]+ <[^>]+> + 60: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 2800 0000 bc [0-9a-f]+ <[^>]*> + 64: R_NANOMIPS_PC25_S1 \*ABS\*\+0x100 +[0-9a-f]+ <[^>]*> 2a00 0000 balc [0-9a-f]+ <[^>]+> + 68: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]*> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]*> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]*> d890 jalrc a0 +[0-9a-f]+ <[^>]*> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]*> 4885 0000 jalrc a0,a1 +[0-9a-f]+ <[^>]*> 4885 0000 jalrc a0,a1 +[0-9a-f]+ <[^>]*> d850 jalrc t4 +[0-9a-f]+ <[^>]*> d850 jalrc t4 +[0-9a-f]+ <[^>]*> d850 jalrc t4 +[0-9a-f]+ <[^>]*> 4804 1000 jrc.hb a0 +[0-9a-f]+ <[^>]*> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]*> 4885 1000 jalrc.hb a0,a1 +[0-9a-f]+ <[^>]*> 9008 nop +#pass diff --git a/gas/testsuite/gas/nanomips/ctc.s b/gas/testsuite/gas/nanomips/ctc.s new file mode 100644 index 00000000000..ec778949860 --- /dev/null +++ b/gas/testsuite/gas/nanomips/ctc.s @@ -0,0 +1,66 @@ + .text + .set reorder +reorder: + b 1f # bc16 + b16 1f # bc16 + b32 1f # bc32 (pre-r6 beq32) + + bal 1f # balc + + beqz $s2,1f # beqzc16 s2,1f [PC7] + beqz32 $s2,1f # beqzc32 s2,1f + beqz16 $s2,1f # beqzc16 s2,1f + + beq16 $s3,$a0,ext # beqzc16 s3,ext [PC7] + beq16 $a0,$s3,ext # beqzc16 s3,ext + beq $s3,$zero,ext # beqzc s3,ext [PC21] + beq $zero,$s3,ext # beqzc s3,ext + beq $s3,$s2,ext # beqc s2,s3,ext [PC16] + beq $s2,$s3,ext # beqc s2,s3,ext + beqz16 $s3,ext # beqzc16 s3,ext [PC7] + beqzc $s3, ext # beqzc s3, ext [new reloc=PC21] + + bnez $s2, 1f # bnezc16 s2, 1f [PC7] + bnez32 $s2, 1f # bnezc32 s2, 1f [PC7] + bnez16 $s2, 1f # bnezc16 s2, 1f + + bne16 $s3, $a0, ext # bnezc16 s3, ext [PC7] + bne16 $a0, $s3, ext # bnezc16 s3, ext + bne $s3, $zero, ext # bnezc s3, ext [PC21] + bne $zero, $s3, ext # bnezc s3, ext [PC21] + bne $s3, $s2, ext # bnec s2, s3, ext [PC16] + bne $s2, $s3, ext # bnec s2, s3, ext + bnez16 $s3, ext # bnezc16 s3, ext [PC7] + bnezc $s3, ext # bnezc s3, ext [new reloc=PC21] + + bgez $s2, ext # bgezc s2, ext + bltz $s2, ext # bgezc s2, ext + + j16 $a0 # jrc16 a0 + jr $t4 # jrc16 t4 + + jrc32 $t4 # jic t4, 0 + j 1f # bc32 + j 0x100 # bc32 + + jal 1f # balc + + j32 $a0 # jic a0, 0 + jr32 $a0 # jic a0, 0 + + jalr $a0 # jalrc16 a0 + + jalr32 $a0 # jalrc a0 + jalr $a0, $a1 # jalrc a0, a1 + jalr32 $a0, $a1 # jalrc a0, a1 + + jalr $t4 # jalrc16 t4 + jalr16 $t4 # jalrc16 t4 + + jalr16 $ra, $t4 # jalrc16 t4 + jr.hb $a0 # jrc.hb a0 + jalr.hb $a0 # jalrc.hb a0 + jalr.hb $a0, $a1 # jalrc.hb a0, a1 + +1: + nop diff --git a/gas/testsuite/gas/nanomips/debug-dis.d b/gas/testsuite/gas/nanomips/debug-dis.d new file mode 100644 index 00000000000..e430f5f94d5 --- /dev/null +++ b/gas/testsuite/gas/nanomips/debug-dis.d @@ -0,0 +1,18 @@ +#objdump: -dr +#name: nanoMIPS disassembly with debug location info + +.*: file format .* + +Disassembly of section \.text: + +00000000 : + 0: 1800 bc 0 + 0: R_NANOMIPS_PC10_S1 foo + +00000002 <.L4>: + 2: 9008 nop + +00000004 : + 4: 0000 0000 .* + 4: R_NANOMIPS_32 \.L4 +#pass diff --git a/gas/testsuite/gas/nanomips/debug-dis.s b/gas/testsuite/gas/nanomips/debug-dis.s new file mode 100644 index 00000000000..052bf863925 --- /dev/null +++ b/gas/testsuite/gas/nanomips/debug-dis.s @@ -0,0 +1,12 @@ +# Test disassembly with debug location info + .file 1 "debug-dis.s" + .text +foo: + .loc 1 10 0 +.L3: + b foo +.L4: + nop + .loc 1 20 0 +b: + .word .L4 # this should remain symbol-relative. diff --git a/gas/testsuite/gas/nanomips/div.d b/gas/testsuite/gas/nanomips/div.d new file mode 100644 index 00000000000..eccc359104c --- /dev/null +++ b/gas/testsuite/gas/nanomips/div.d @@ -0,0 +1,45 @@ +#objdump: -dr --no-show-raw-insn -mnanomips:isa64r6 +#name: nanoMIPS div + +# Test the div macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: div zero,a0,a1 + 4: div a0,a0,a1 + 8: div a0,a1,a2 + c: move a0,a0 + e: move a0,a1 + 10: neg a0,a0 + 14: neg a0,a1 + 18: li at,2 + 1c: div a0,a0,at + 20: li at,2 + 24: div a0,a1,at + 28: li at,32768 + 2c: div a0,a0,at + 30: li at,32768 + 34: div a0,a1,at + 38: lui at,%hi\(0xffff8000\) + 3c: div a0,a0,at + 40: lui at,%hi\(0xffff8000\) + 44: div a0,a1,at + 48: lui at,%hi\(0x10000\) + 4c: div a0,a0,at + 50: lui at,%hi\(0x10000\) + 54: div a0,a1,at + 58: li at,0x1a5a5 + 5e: div a0,a0,at + 62: li at,0x1a5a5 + 68: div a0,a1,at + 6c: divu zero,a0,a1 + 70: divu a0,a0,a1 + 74: divu a0,a1,a2 + 78: move a0,a0 + 7a: mod a0,a1,a2 + 7e: li at,2 + 82: modu a0,a1,at +#pass diff --git a/gas/testsuite/gas/nanomips/div.s b/gas/testsuite/gas/nanomips/div.s new file mode 100644 index 00000000000..c241c7a46d7 --- /dev/null +++ b/gas/testsuite/gas/nanomips/div.s @@ -0,0 +1,31 @@ + + # Source file used to test the div macro. +foo: + div $0,$4,$5 + div $4,$5 + div $4,$5,$6 + div $4,1 + div $4,$5,1 + div $4,-1 + div $4,$5,-1 + div $4,2 + div $4,$5,2 + div $4,0x8000 + div $4,$5,0x8000 + div $4,-0x8000 + div $4,$5,-0x8000 + div $4,0x10000 + div $4,$5,0x10000 + div $4,0x1a5a5 + div $4,$5,0x1a5a5 + +# divu is like div, except when both arguments are registers. +# Just sanity check it otherwise. + divu $0,$4,$5 + divu $4,$5 + divu $4,$5,$6 + divu $4,1 + +# mod is like div, modu is like divu + mod $4,$5,$6 + modu $4,$5,2 diff --git a/gas/testsuite/gas/nanomips/empty.s b/gas/testsuite/gas/nanomips/empty.s new file mode 100644 index 00000000000..f30bd3cc93c --- /dev/null +++ b/gas/testsuite/gas/nanomips/empty.s @@ -0,0 +1,3 @@ +# An empty source file for tests that need no instructions. + + # No actual contents necessary! diff --git a/gas/testsuite/gas/nanomips/expr-const.d b/gas/testsuite/gas/nanomips/expr-const.d new file mode 100644 index 00000000000..2793e37502b --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-const.d @@ -0,0 +1,11 @@ +#name: Constant expression evaluation +#objdump: -sj.text + +.*: file format .*nanomips.* + +Contents of section \.text: + 0000 00000000 00000127 00000020 011fdd00.* + 0010 00000000 0000000e 00000001 0006f600.* + 0020 00000000 00000016 00000001 fffc0300.* + 0030 00000000 00000127 00000000 00000127.* + 0040 00000001 00000001 00000001 00000001.* diff --git a/gas/testsuite/gas/nanomips/expr-const.s b/gas/testsuite/gas/nanomips/expr-const.s new file mode 100644 index 00000000000..bd65a951646 --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-const.s @@ -0,0 +1,24 @@ +# Check that general const expression evaluations work as expected +# after introducing special handling for expressions as relocations. + + .text + .equ sym1,10 + .equ sym2,8 +test: + .dword (0x123 + 4) + .word (0x100 >> 3) + .hword (0x123 - 4) + .byte (0x100 - 0x123) + + .dword (sym1 + 4) + .word (sym1 >> 3) + .hword (sym1 - 4) + .byte (0x100 - sym1) + + .dword ((sym1 + sym2) + 4) + .word ((sym1 + 1) >> 3) + .hword ((sym1 >> 4) - 4) + .byte (0x1 + (sym1 - sym2)) + + .dword (0x123 + 4):2 + .word ((sym1 + 1) >> 3):4 diff --git a/gas/testsuite/gas/nanomips/expr-ill.l b/gas/testsuite/gas/nanomips/expr-ill.l new file mode 100644 index 00000000000..8e89a9aafc8 --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-ill.l @@ -0,0 +1,7 @@ +.*expr-ill.s: Assembler messages: +.*expr-ill.s:16: Error: Expression too complex to relocate! +.*expr-ill.s:17: Error: Expression too complex to relocate! +.*expr-ill.s:18: Error: Expression too complex to relocate! +.*expr-ill.s:19: Warning: unresolvable or nonpositive repeat count; using 1 +.*expr-ill.s:20: Warning: unresolvable or nonpositive repeat count; using 1 +#pass diff --git a/gas/testsuite/gas/nanomips/expr-ill.s b/gas/testsuite/gas/nanomips/expr-ill.s new file mode 100644 index 00000000000..830d6ff3b13 --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-ill.s @@ -0,0 +1,20 @@ +# Test representation of various symbolic expressions as relocations. +# This only works for PABI currently. + + .text + .linkrelax +foo: + jrc $a0 +.L3: + nop +.L4: + bc .L3 +.L2: + jrc $ra + +b: + .word (.L4 - .L2) - .L3 + .word .L3 >> .L4 + .word (.L2 >> 1) + 3 + .word (.L2 >> 1):-2 + .word (.L2 >> 1):.L3 diff --git a/gas/testsuite/gas/nanomips/expr-sym.d b/gas/testsuite/gas/nanomips/expr-sym.d new file mode 100644 index 00000000000..ceed202d4f3 --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-sym.d @@ -0,0 +1,71 @@ +#name: Symbolic expression evaluation on nanoMIPS +#DUMPPROG: readelf +#readelf: -Wr +#source: expr-sym.s + +#... +Relocation section '\.rela\.data' at offset 0x[0-9a-f]+ contains 62 entries: + Offset Info Type Sym\. Value Symbol's Name \+ Addend +00000000 [0-9a-f]+01 R_NANOMIPS_32 00000010 \.L2 \+ 0 +00000004 [0-9a-f]+01 R_NANOMIPS_32 00000010 \.L2 \+ 0 +00000008 [0-9a-f]+07 R_NANOMIPS_UNSIGNED_16 00000000 \.L3 \+ 0 +0000000a [0-9a-f]+05 R_NANOMIPS_UNSIGNED_8 00000004 \.L4 \+ 0 +0000000c [0-9a-f]+01 R_NANOMIPS_32 00000010 \.L2 \+ 2 +00000010 [0-9a-f]+07 R_NANOMIPS_UNSIGNED_16 00000000 \.L3 - 3 +00000012 [0-9a-f]+05 R_NANOMIPS_UNSIGNED_8 00000004 \.L4 - 6 +00000014 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000010 \.L2 \+ 0 +00000014 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000014 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000014 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000018 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000000 \.L3 - a +00000018 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000018 [0-9a-f]+07 R_NANOMIPS_UNSIGNED_16 0 +0000001a [0-9a-f]+03 R_NANOMIPS_NEG 00000004 \.L4 \+ 0 +0000001a [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000010 \.L2 \+ 0 +0000001a [0-9a-f]+05 R_NANOMIPS_UNSIGNED_8 0 +0000001c [0-9a-f]+03 R_NANOMIPS_NEG 00000000 \.L3 \+ 0 +0000001c [0-9a-f]+01 R_NANOMIPS_32 00000010 \.L2 \+ 0 +00000020 [0-9a-f]+03 R_NANOMIPS_NEG 00000004 \.L4 \+ 4 +00000020 [0-9a-f]+07 R_NANOMIPS_UNSIGNED_16 00000010 \.L2 \+ 0 +00000022 [0-9a-f]+03 R_NANOMIPS_NEG 00000004 \.L4 - a +00000022 [0-9a-f]+05 R_NANOMIPS_UNSIGNED_8 00000000 \.L3 \+ 0 +00000024 [0-9a-f]+03 R_NANOMIPS_NEG 00000010 \.L2 \- 3 +00000024 [0-9a-f]+01 R_NANOMIPS_32 00000004 \.L4 \+ 0 +00000028 [0-9a-f]+03 R_NANOMIPS_NEG 00000000 \.L3 \- 5 +00000028 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000004 \.L4 \+ 0 +00000028 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000028 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002c [0-9a-f]+03 R_NANOMIPS_NEG 00000004 \.L4 - 6 +0000002c [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002c [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002c [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002c [0-9a-f]+07 R_NANOMIPS_UNSIGNED_16 00000000 \.L3 \+ 0 +0000002e [0-9a-f]+03 R_NANOMIPS_NEG 00000010 \.L2 - 7 +0000002e [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002e [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002e [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002e [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000000 \.L3 \+ 0 +0000002e [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002e [0-9a-f]+05 R_NANOMIPS_UNSIGNED_8 0 +0000002f [0-9a-f]+03 R_NANOMIPS_NEG 00000010 \.L2 - 7 +0000002f [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002f [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002f [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002f [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000000 \.L3 \+ 0 +0000002f [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +0000002f [0-9a-f]+05 R_NANOMIPS_UNSIGNED_8 0 +00000030 [0-9a-f]+03 R_NANOMIPS_NEG 00000010 \.L2 \- 7 +00000030 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000030 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000030 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000030 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000000 \.L3 \+ 0 +00000030 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000030 [0-9a-f]+05 R_NANOMIPS_UNSIGNED_8 0 +00000032 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000004 \.L4 \+ 6 +00000032 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000032 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 0 +00000032 [0-9a-f]+08 R_NANOMIPS_SIGNED_16 0 +00000034 [0-9a-f]+03 R_NANOMIPS_NEG 00000010 \.L2 \+ 0 +00000034 [0-9a-f]+04 R_NANOMIPS_ASHIFTR_1 00000000 \.L3 \+ 0 +00000034 [0-9a-f]+06 R_NANOMIPS_SIGNED_8 0 +#pass diff --git a/gas/testsuite/gas/nanomips/expr-sym.s b/gas/testsuite/gas/nanomips/expr-sym.s new file mode 100644 index 00000000000..52ae0faf970 --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-sym.s @@ -0,0 +1,36 @@ +# Test representation of various symbolic expressions as relocations. +# This only works for PABI currently. + + .text + .linkrelax +foo: +.L3: + bal foo1 +.L4: + addiu $t4, $gp,%gprel(foo) +.L2: + .align 4 + .data +b: + .word .L2:2 + .hword .L3 + .byte .L4 + + .word .L2 + 2 + .hword .L3 - 3 + .byte (.L4 + 4) - 10 + + .word .L2 >> 4 + .hword (.L3 - 10) >> 2 + .byte (.L2 - .L4) >> 1 + + .word (.L2 - .L3) + .hword (.L2 + 4) - .L4 + .byte (.L3 - 10) - .L4 + + .word .L4 - (.L2 + 3) + .word (.L4 - (.L3 + 5)) >> 3 + .hword .L3 - ((.L4 + 6) >> 3) + .byte ((.L3 - ((.L2 + 7) >> 3)) >> 2):3 + .shword (.L4 + 6) >> 3 + .sbyte (.L3 - .L2) >> 1 diff --git a/gas/testsuite/gas/nanomips/expr-vol.d b/gas/testsuite/gas/nanomips/expr-vol.d new file mode 100644 index 00000000000..bd86ff07dbe --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-vol.d @@ -0,0 +1,17 @@ +#objdump: -dr --show-raw-insn +#name: Expressions with volatile labels on nanoMIPS + +.*\.o: +file format .*nanomips.* + +Disassembly of section \.text: + +[0-9a-f]+ : + 0: 9008 nop + +[0-9a-f]+ <\$LVL2>: + 2: 90e9 addiu a3,a3,1 + +[0-9a-f]+ <\$LVL3>: + 4: 0200 00e8 li s0,232 + 8: dbe0 jrc ra +#pass \ No newline at end of file diff --git a/gas/testsuite/gas/nanomips/expr-vol.s b/gas/testsuite/gas/nanomips/expr-vol.s new file mode 100644 index 00000000000..ae6038d8d26 --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr-vol.s @@ -0,0 +1,17 @@ +/* verify disassembly with local volatile labels. */ + + .text + .ent test +test: + nop +$LVL2 = . + addiu $a3,$a3,1 +$L2: +$LVL3 = . + li $s0,232 + jrc $ra + .end test + + .data +.word $LVL3 +.word $LVL2 diff --git a/gas/testsuite/gas/nanomips/expr1.d b/gas/testsuite/gas/nanomips/expr1.d new file mode 100644 index 00000000000..b4f81edae5f --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr1.d @@ -0,0 +1,18 @@ +#name: nanoMIPS expression 1 +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+0000 : + 0: 8484 8000 lw a0,0\(a0\) + 0: R_NANOMIPS_LO12 foo + 4: 164e lw a0,56\(a0\) + 6: 8484 8000 lw a0,0\(a0\) + 6: R_NANOMIPS_LO12 foo\+0x8 + a: 8484 8000 lw a0,0\(a0\) + a: R_NANOMIPS_LO12 foo\+0x8 + e: 8484 8000 lw a0,0\(a0\) + e: R_NANOMIPS_LO12 foo\+0x8 +#pass diff --git a/gas/testsuite/gas/nanomips/expr1.s b/gas/testsuite/gas/nanomips/expr1.s new file mode 100644 index 00000000000..71c46231ac8 --- /dev/null +++ b/gas/testsuite/gas/nanomips/expr1.s @@ -0,0 +1,9 @@ + .globl foo + .ent foo +foo: + lw $4,%lo(foo)($4) + lw $4,((10 + 4) * 4)($4) + lw $4,%lo (2 * 4) + foo($4) + lw $4,%lo((2 * 4) + foo)($4) + lw $4,(((%lo ((2 * 4) + foo))))($4) + .end foo diff --git a/gas/testsuite/gas/nanomips/gpr-names-numeric.d b/gas/testsuite/gas/nanomips/gpr-names-numeric.d new file mode 100644 index 00000000000..b4f9ad028f5 --- /dev/null +++ b/gas/testsuite/gas/nanomips/gpr-names-numeric.d @@ -0,0 +1,44 @@ +#objdump: -dr --no-show-raw-insn -M gpr-names=numeric +#name: nanoMIPS GPR disassembly (numeric) +#source: gpr-names.s + +# Check objdump's handling of -M gpr-names=foo options. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: lui \$0,0x0 + 4: lui \$1,0x0 + 8: lui \$2,0x0 + c: lui \$3,0x0 + 10: lui \$4,0x0 + 14: lui \$5,0x0 + 18: lui \$6,0x0 + 1c: lui \$7,0x0 + 20: lui \$8,0x0 + 24: lui \$9,0x0 + 28: lui \$10,0x0 + 2c: lui \$11,0x0 + 30: lui \$12,0x0 + 34: lui \$13,0x0 + 38: lui \$14,0x0 + 3c: lui \$15,0x0 + 40: lui \$16,0x0 + 44: lui \$17,0x0 + 48: lui \$18,0x0 + 4c: lui \$19,0x0 + 50: lui \$20,0x0 + 54: lui \$21,0x0 + 58: lui \$22,0x0 + 5c: lui \$23,0x0 + 60: lui \$24,0x0 + 64: lui \$25,0x0 + 68: lui \$26,0x0 + 6c: lui \$27,0x0 + 70: lui \$28,0x0 + 74: lui \$29,0x0 + 78: lui \$30,0x0 + 7c: lui \$31,0x0 +#pass diff --git a/gas/testsuite/gas/nanomips/gpr-names.d b/gas/testsuite/gas/nanomips/gpr-names.d new file mode 100644 index 00000000000..6b922d084a0 --- /dev/null +++ b/gas/testsuite/gas/nanomips/gpr-names.d @@ -0,0 +1,44 @@ +#objdump: -dr --no-show-raw-insn -M gpr-names=32 +#name: nanoMIPS GPR disassembly +#source: gpr-names.s + +# Check objdump's handling of -M gpr-names=foo options. + +.*: +file format .*nanomips.* + +Disassembly of section .text: + +00000000 : + 0: lui zero,0x0 + 4: lui at,0x0 + 8: lui t4,0x0 + c: lui t5,0x0 + 10: lui a0,0x0 + 14: lui a1,0x0 + 18: lui a2,0x0 + 1c: lui a3,0x0 + 20: lui a4,0x0 + 24: lui a5,0x0 + 28: lui a6,0x0 + 2c: lui a7,0x0 + 30: lui t0,0x0 + 34: lui t1,0x0 + 38: lui t2,0x0 + 3c: lui t3,0x0 + 40: lui s0,0x0 + 44: lui s1,0x0 + 48: lui s2,0x0 + 4c: lui s3,0x0 + 50: lui s4,0x0 + 54: lui s5,0x0 + 58: lui s6,0x0 + 5c: lui s7,0x0 + 60: lui t8,0x0 + 64: lui t9,0x0 + 68: lui k0,0x0 + 6c: lui k1,0x0 + 70: lui gp,0x0 + 74: lui sp,0x0 + 78: lui fp,0x0 + 7c: lui ra,0x0 +#pass diff --git a/gas/testsuite/gas/nanomips/gpr-names.s b/gas/testsuite/gas/nanomips/gpr-names.s new file mode 100644 index 00000000000..305951bb0a1 --- /dev/null +++ b/gas/testsuite/gas/nanomips/gpr-names.s @@ -0,0 +1,38 @@ +# source file to test objdump's disassembly using various styles of +# GPR names. + + .set noat + .text +text_label: + lui $0,0 + lui $1,0 + lui $2,0 + lui $3,0 + lui $4,0 + lui $5,0 + lui $6,0 + lui $7,0 + lui $8,0 + lui $9,0 + lui $10,0 + lui $11,0 + lui $12,0 + lui $13,0 + lui $14,0 + lui $15,0 + lui $16,0 + lui $17,0 + lui $18,0 + lui $19,0 + lui $20,0 + lui $21,0 + lui $22,0 + lui $23,0 + lui $24,0 + lui $25,0 + lui $26,0 + lui $27,0 + lui $28,0 + lui $29,0 + lui $30,0 + lui $31,0 diff --git a/gas/testsuite/gas/nanomips/hwr-names-numeric.d b/gas/testsuite/gas/nanomips/hwr-names-numeric.d new file mode 100644 index 00000000000..10b8dae6055 --- /dev/null +++ b/gas/testsuite/gas/nanomips/hwr-names-numeric.d @@ -0,0 +1,59 @@ +#objdump: -dr -M gpr-names=numeric,hwr-names=numeric +#name: nanoMIPS HWR disassembly \(numeric\) + +# Check objdump's handling of -M hwr-names=foo options. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +0+0000 : + 0: 2000 01c0 rdhwr \$0,\$0 + 4: 2001 01c0 rdhwr \$0,\$1 + 8: 2002 01c0 rdhwr \$0,\$2 + c: 2003 01c0 rdhwr \$0,\$3 + 10: 2004 01c0 rdhwr \$0,\$4 + 14: 2005 01c0 rdhwr \$0,\$5 + 18: 2006 01c0 rdhwr \$0,\$6 + 1c: 2007 01c0 rdhwr \$0,\$7 + 20: 2008 01c0 rdhwr \$0,\$8 + 24: 2009 01c0 rdhwr \$0,\$9 + 28: 200a 01c0 rdhwr \$0,\$10 + 2c: 200b 01c0 rdhwr \$0,\$11 + 30: 200c 01c0 rdhwr \$0,\$12 + 34: 200d 01c0 rdhwr \$0,\$13 + 38: 200e 01c0 rdhwr \$0,\$14 + 3c: 200f 01c0 rdhwr \$0,\$15 + 40: 2010 01c0 rdhwr \$0,\$16 + 44: 2011 01c0 rdhwr \$0,\$17 + 48: 2012 01c0 rdhwr \$0,\$18 + 4c: 2013 01c0 rdhwr \$0,\$19 + 50: 2014 01c0 rdhwr \$0,\$20 + 54: 2015 01c0 rdhwr \$0,\$21 + 58: 2016 01c0 rdhwr \$0,\$22 + 5c: 2017 01c0 rdhwr \$0,\$23 + 60: 2018 01c0 rdhwr \$0,\$24 + 64: 2019 01c0 rdhwr \$0,\$25 + 68: 201a 01c0 rdhwr \$0,\$26 + 6c: 201b 01c0 rdhwr \$0,\$27 + 70: 201c 01c0 rdhwr \$0,\$28 + 74: 201d 01c0 rdhwr \$0,\$29 + 78: 201e 01c0 rdhwr \$0,\$30 + 7c: 201f 01c0 rdhwr \$0,\$31 + 80: 2004 01c0 rdhwr \$0,\$4 + 84: 2004 09c0 rdhwr \$0,\$4,1 + 88: 2004 11c0 rdhwr \$0,\$4,2 + 8c: 2004 19c0 rdhwr \$0,\$4,3 + 90: 2004 21c0 rdhwr \$0,\$4,4 + 94: 2004 29c0 rdhwr \$0,\$4,5 + 98: 2004 31c0 rdhwr \$0,\$4,6 + 9c: 2004 39c0 rdhwr \$0,\$4,7 + a0: 2004 41c0 rdhwr \$0,\$4,8 + a4: 2004 49c0 rdhwr \$0,\$4,9 + a8: 2004 51c0 rdhwr \$0,\$4,10 + ac: 2004 59c0 rdhwr \$0,\$4,11 + b0: 2004 61c0 rdhwr \$0,\$4,12 + b4: 2004 69c0 rdhwr \$0,\$4,13 + b8: 2004 71c0 rdhwr \$0,\$4,14 + bc: 2004 79c0 rdhwr \$0,\$4,15 +#pass diff --git a/gas/testsuite/gas/nanomips/hwr-names-numeric.s b/gas/testsuite/gas/nanomips/hwr-names-numeric.s new file mode 100644 index 00000000000..fd4dbf88120 --- /dev/null +++ b/gas/testsuite/gas/nanomips/hwr-names-numeric.s @@ -0,0 +1,53 @@ +# source file to test objdump's disassembly of HWR (hardware register) names. + + .text +text_label: + rdhwr $0, $0 + rdhwr $0, $1 + rdhwr $0, $2 + rdhwr $0, $3 + rdhwr $0, $4 + rdhwr $0, $5 + rdhwr $0, $6 + rdhwr $0, $7 + rdhwr $0, $8 + rdhwr $0, $9 + rdhwr $0, $10 + rdhwr $0, $11 + rdhwr $0, $12 + rdhwr $0, $13 + rdhwr $0, $14 + rdhwr $0, $15 + rdhwr $0, $16 + rdhwr $0, $17 + rdhwr $0, $18 + rdhwr $0, $19 + rdhwr $0, $20 + rdhwr $0, $21 + rdhwr $0, $22 + rdhwr $0, $23 + rdhwr $0, $24 + rdhwr $0, $25 + rdhwr $0, $26 + rdhwr $0, $27 + rdhwr $0, $28 + rdhwr $0, $29 + rdhwr $0, $30 + rdhwr $0, $31 + + rdhwr $0, $4, 0 + rdhwr $0, $4, 1 + rdhwr $0, $4, 2 + rdhwr $0, $4, 3 + rdhwr $0, $4, 4 + rdhwr $0, $4, 5 + rdhwr $0, $4, 6 + rdhwr $0, $4, 7 + rdhwr $0, $4, 8 + rdhwr $0, $4, 9 + rdhwr $0, $4, 10 + rdhwr $0, $4, 11 + rdhwr $0, $4, 12 + rdhwr $0, $4, 13 + rdhwr $0, $4, 14 + rdhwr $0, $4, 15 diff --git a/gas/testsuite/gas/nanomips/insn-suffix-error.l b/gas/testsuite/gas/nanomips/insn-suffix-error.l new file mode 100644 index 00000000000..84a20232125 --- /dev/null +++ b/gas/testsuite/gas/nanomips/insn-suffix-error.l @@ -0,0 +1,20 @@ +.*.s: Assembler messages: +.*.s:3: Error: unrecognized opcode `addiu\[r1.sp\]32 \$a0,\$sp,8' +.*.s:4: Error: unrecognized opcode `addiu\[r2\]32 \$a0,\$a1,4' +.*.s:5: Error: unrecognized opcode `addiu\[rs5\]48 \$t0,\$t0,3' +.*.s:6: Error: unrecognized opcode `addiu\[gp.b\]16 \$a0,\$gp,%gprel\(test8\)' +.*.s:7: Error: unrecognized opcode `addiu\[gp.w\]16 \$a0,\$gp,%gprel\(test8\)' +.*.s:8: Error: unrecognized opcode `addiu\[neg\]48 \$a0,\$a1,-4' +.*.s:9: Error: unrecognized opcode `addiu\[32\]48 \$a0,\$a1,64' +.*.s:10: Error: unrecognized opcode `addiu\[48\]32 \$a0,\$a0,12' +.*.s:11: Error: unrecognized opcode `addiu\[gp48\]16 \$a0,\$gp,%gprel\(test8\)' +.*.s:13: Error: unrecognized opcode `lw\[16\]32 \$a0,8\(\$a1\)' +.*.s:14: Error: unrecognized opcode `lw\[4x4\]32 \$a1,12\(\$a2\)' +.*.s:15: Error: unrecognized opcode `lw\[gp16\]48 \$a3,24\(\$gp\)' +.*.s:16: Error: unrecognized opcode `lw\[gp16\]32 \$a3,%gprel\(test8\)\(\$gp\)' +.*.s:17: Error: unrecognized opcode `lw\[sp\]32 \$a3,20\(\$sp\)' +.*.s:18: Error: unrecognized opcode `lw\[gp\]16 \$a3,224\(\$gp\)' +.*.s:19: Error: unrecognized opcode `lw\[gp\]48 \$a3,%gprel\(test8\)\(\$gp\)' +.*.s:20: Error: unrecognized opcode `lw\[s9\]48 \$a3,20\(\$s0\)' +.*.s:21: Error: unrecognized opcode `lw\[u12\]16 \$a3,20\(\$s1\)' +.*.s:22: Error: unrecognized opcode `lwpc\[48\]32 \$a3,test8' diff --git a/gas/testsuite/gas/nanomips/insn-suffix-error.s b/gas/testsuite/gas/nanomips/insn-suffix-error.s new file mode 100644 index 00000000000..2a4e3a6605a --- /dev/null +++ b/gas/testsuite/gas/nanomips/insn-suffix-error.s @@ -0,0 +1,22 @@ + .text +test8: + addiu[r1.sp]32 $a0,$sp,8 + addiu[r2]32 $a0,$a1,4 + addiu[rs5]48 $t0,$t0,3 + addiu[gp.b]16 $a0,$gp,%gprel(test8) + addiu[gp.w]16 $a0,$gp,%gprel(test8) + addiu[neg]48 $a0,$a1,-4 + addiu[32]48 $a0,$a1,64 + addiu[48]32 $a0,$a0,12 + addiu[gp48]16 $a0,$gp,%gprel(test8) + + lw[16]32 $a0,8($a1) + lw[4x4]32 $a1,12($a2) + lw[gp16]48 $a3,24($gp) + lw[gp16]32 $a3,%gprel(test8)($gp) + lw[sp]32 $a3,20($sp) + lw[gp]16 $a3,224($gp) + lw[gp]48 $a3,%gprel(test8)($gp) + lw[s9]48 $a3,20($s0) + lw[u12]16 $a3,20($s1) + lwpc[48]32 $a3,test8 diff --git a/gas/testsuite/gas/nanomips/isa-errors.l b/gas/testsuite/gas/nanomips/isa-errors.l new file mode 100644 index 00000000000..4cee744743f --- /dev/null +++ b/gas/testsuite/gas/nanomips/isa-errors.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:2: Error: nanoMIPS does not support MIPS16 ASE +.*:4: Error: cannot change ISA from nanoMIPS to mips32r2 +.*:6: Error: cannot change ISA from nanoMIPS to mips32 +.*:7: Error: cannot change ISA from nanoMIPS to mips0 +.*:8: Error: cannot change ISA from nanoMIPS to mips32r5 +.*:9: Error: cannot change ISA from nanoMIPS to mips64 diff --git a/gas/testsuite/gas/nanomips/isa-errors.s b/gas/testsuite/gas/nanomips/isa-errors.s new file mode 100644 index 00000000000..9ff9bd81e68 --- /dev/null +++ b/gas/testsuite/gas/nanomips/isa-errors.s @@ -0,0 +1,9 @@ +.text + .set mips16 + .set arch=32r6 + .set mips32r2 + .set arch=64r6 + .set mips32 + .set mips0 + .set arch=mips32r5 + .set arch=mips64 diff --git a/gas/testsuite/gas/nanomips/jal.d b/gas/testsuite/gas/nanomips/jal.d new file mode 100644 index 00000000000..c10ab9e93be --- /dev/null +++ b/gas/testsuite/gas/nanomips/jal.d @@ -0,0 +1,21 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS ELF jal +#source: jal.s +#as: -mlegacyregs + +# Test the jal macro (nanoMIPS). + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> jalrc t9 +[0-9a-f]+ <[^>]*> jalrc a0,t9 +[0-9a-f]+ <[^>]*> balc 00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 text_label +[0-9a-f]+ <[^>]*> balc 00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 external_text_label +[0-9a-f]+ <[^>]*> bc 00000000 <.*> +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 text_label +[0-9a-f]+ <[^>]*> bc 00000000 +[ ]*[0-9a-f]+: R_NANOMIPS_PC25_S1 external_text_label +#pass diff --git a/gas/testsuite/gas/nanomips/jal.s b/gas/testsuite/gas/nanomips/jal.s new file mode 100644 index 00000000000..2c4822b7e5d --- /dev/null +++ b/gas/testsuite/gas/nanomips/jal.s @@ -0,0 +1,11 @@ +# Source file used to test the jal macro. + .globl text_label +text_label: + jal $25 + jal $4,$25 + jal text_label + jal external_text_label + +# Test j as well + j text_label + j external_text_label diff --git a/gas/testsuite/gas/nanomips/jalr.l b/gas/testsuite/gas/nanomips/jalr.l new file mode 100644 index 00000000000..a7a8ab90310 --- /dev/null +++ b/gas/testsuite/gas/nanomips/jalr.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:1: Error: invalid operands.* +.*:9: Error: invalid operands.* diff --git a/gas/testsuite/gas/nanomips/jalr.s b/gas/testsuite/gas/nanomips/jalr.s new file mode 100644 index 00000000000..97eb26299f3 --- /dev/null +++ b/gas/testsuite/gas/nanomips/jalr.s @@ -0,0 +1,15 @@ + jalr $32 + jalr $31 + jalr $7, $7 + jalr $31, $2 + jalr $0 + jalr $0, $31 + jalr $31, $0 + + jalr.hb $32 + jalr.hb $31 + jalr.hb $7, $7 + jalr.hb $31, $2 + jalr.hb $0 + jalr.hb $0, $31 + jalr.hb $31, $0 diff --git a/gas/testsuite/gas/nanomips/la-lpic-mclarge.d b/gas/testsuite/gas/nanomips/la-lpic-mclarge.d new file mode 100644 index 00000000000..3a96cac7f33 --- /dev/null +++ b/gas/testsuite/gas/nanomips/la-lpic-mclarge.d @@ -0,0 +1,116 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS la PIC large memory model +#as: -mPIC -mcmodel=large -G0 +#source: la.s + +# Test the la macro with mPIC and large memory model + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la-lpic-mcmedium.d b/gas/testsuite/gas/nanomips/la-lpic-mcmedium.d new file mode 100644 index 00000000000..8a0803c79dd --- /dev/null +++ b/gas/testsuite/gas/nanomips/la-lpic-mcmedium.d @@ -0,0 +1,116 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS la PIC medium memory model +#as: -mPIC -mcmodel=medium -G0 +#source: la.s + +# Test the la macro with mPIC and large memory model + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 608b 0000 0000 lwpc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_GOTPC_I32 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la-mclarge-pcrel.d b/gas/testsuite/gas/nanomips/la-mclarge-pcrel.d new file mode 100644 index 00000000000..15cef6aaa8e --- /dev/null +++ b/gas/testsuite/gas/nanomips/la-mclarge-pcrel.d @@ -0,0 +1,116 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS PC-relative la using li[48] for large memory model +#source: la.s +#as: -mlegacyregs -mpcrel + +# Test the la macro PC-relative expansion for mcmodel=large + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 42: R_NANOMIPS_PC_I32 data_label +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 48: R_NANOMIPS_PC_I32 big_external_data_label +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 4e: R_NANOMIPS_PC_I32 small_external_data_label +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 54: R_NANOMIPS_PC_I32 big_external_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 5a: R_NANOMIPS_PC_I32 small_external_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 60: R_NANOMIPS_PC_I32 big_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 66: R_NANOMIPS_PC_I32 small_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 6c: R_NANOMIPS_PC_I32 data_label\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 72: R_NANOMIPS_PC_I32 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 78: R_NANOMIPS_PC_I32 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 7e: R_NANOMIPS_PC_I32 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 84: R_NANOMIPS_PC_I32 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 8a: R_NANOMIPS_PC_I32 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 90: R_NANOMIPS_PC_I32 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 96: R_NANOMIPS_PC_I32 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 9c: R_NANOMIPS_PC_I32 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + a2: R_NANOMIPS_PC_I32 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + a8: R_NANOMIPS_PC_I32 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + ae: R_NANOMIPS_PC_I32 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + b4: R_NANOMIPS_PC_I32 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + ba: R_NANOMIPS_PC_I32 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + c0: R_NANOMIPS_PC_I32 data_label-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + c6: R_NANOMIPS_PC_I32 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + cc: R_NANOMIPS_PC_I32 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + d2: R_NANOMIPS_PC_I32 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + d8: R_NANOMIPS_PC_I32 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + de: R_NANOMIPS_PC_I32 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + e4: R_NANOMIPS_PC_I32 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + ea: R_NANOMIPS_PC_I32 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + f0: R_NANOMIPS_PC_I32 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + f6: R_NANOMIPS_PC_I32 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + fc: R_NANOMIPS_PC_I32 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 102: R_NANOMIPS_PC_I32 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 108: R_NANOMIPS_PC_I32 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 10e: R_NANOMIPS_PC_I32 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 114: R_NANOMIPS_PC_I32 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 11a: R_NANOMIPS_PC_I32 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 120: R_NANOMIPS_PC_I32 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 126: R_NANOMIPS_PC_I32 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 12c: R_NANOMIPS_PC_I32 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 132: R_NANOMIPS_PC_I32 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 138: R_NANOMIPS_PC_I32 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 152: R_NANOMIPS_PC_I32 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la-mclarge.d b/gas/testsuite/gas/nanomips/la-mclarge.d new file mode 100644 index 00000000000..558c7b49739 --- /dev/null +++ b/gas/testsuite/gas/nanomips/la-mclarge.d @@ -0,0 +1,115 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS la using li[48] for large memory model +#source: la.s + +# Test the la macro for mcmodel=large + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> li a0,0 +[0-9a-f]+ <[^>]*> li a0,1 +[0-9a-f]+ <[^>]*> li a0,32768 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> li a0,0x1a5a5 +[0-9a-f]+ <[^>]*> addiu a0,a1,0 +[0-9a-f]+ <[^>]*> addiu a0,a1,1 +[0-9a-f]+ <[^>]*> addiu a0,a1,32768 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> li a0,0x1a5a5 +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.data +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_data_label +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_data_label +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_common +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_common +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.bss +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.sbss +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.data\+0x1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_common\+0x1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.sbss\+0x1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.data\+0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_common\+0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.sbss\+0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.data-0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_common-0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_common-0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.bss-0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.sbss-0x8000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.data\+0x10000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x10000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_common\+0x10000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x10000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.sbss\+0x10000 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 \.sbss\+0x1a5a5 +[0-9a-f]+ <[^>]*> addiu a0,a1,0 +[0-9a-f]+ <[^>]*> li a0,0x123456 +[0-9a-f]+ <[^>]*> li a0,0x123456 +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> li a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_I32 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la-pcrel.d b/gas/testsuite/gas/nanomips/la-pcrel.d new file mode 100644 index 00000000000..f20e64d52e7 --- /dev/null +++ b/gas/testsuite/gas/nanomips/la-pcrel.d @@ -0,0 +1,116 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS la using li[48] PC-relative +#as: -mlegacyregs -mpcrel +#source: la.s + +# Test PC-relative expansion of the la macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 42: R_NANOMIPS_PC_I32 data_label +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 48: R_NANOMIPS_PC_I32 big_external_data_label +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 4c: R_NANOMIPS_GPREL19_S2 small_external_data_label +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 52: R_NANOMIPS_PC_I32 big_external_common +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 56: R_NANOMIPS_GPREL19_S2 small_external_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 5c: R_NANOMIPS_PC_I32 big_local_common +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 60: R_NANOMIPS_GPREL19_S2 .sbss +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 66: R_NANOMIPS_PC_I32 data_label\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 6c: R_NANOMIPS_PC_I32 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 70: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 76: R_NANOMIPS_PC_I32 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 7a: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 80: R_NANOMIPS_PC_I32 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 84: R_NANOMIPS_GPREL19_S2 .sbss\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 8a: R_NANOMIPS_PC_I32 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 90: R_NANOMIPS_PC_I32 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 94: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 9a: R_NANOMIPS_PC_I32 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 9e: R_NANOMIPS_GPREL19_S2 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + a4: R_NANOMIPS_PC_I32 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + a8: R_NANOMIPS_GPREL19_S2 .sbss\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + ae: R_NANOMIPS_PC_I32 data_label-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + b4: R_NANOMIPS_PC_I32 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + ba: R_NANOMIPS_PC_I32 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + c0: R_NANOMIPS_PC_I32 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + c6: R_NANOMIPS_PC_I32 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + cc: R_NANOMIPS_PC_I32 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + d2: R_NANOMIPS_PC_I32 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + d8: R_NANOMIPS_PC_I32 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + de: R_NANOMIPS_PC_I32 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + e2: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + e8: R_NANOMIPS_PC_I32 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + ec: R_NANOMIPS_GPREL19_S2 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + f2: R_NANOMIPS_PC_I32 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + f6: R_NANOMIPS_GPREL19_S2 .sbss\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + fc: R_NANOMIPS_PC_I32 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 102: R_NANOMIPS_PC_I32 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 106: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 10c: R_NANOMIPS_PC_I32 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 110: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 116: R_NANOMIPS_PC_I32 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 11a: R_NANOMIPS_GPREL19_S2 .sbss\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + 134: R_NANOMIPS_PC_I32 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la-pic-mclarge.d b/gas/testsuite/gas/nanomips/la-pic-mclarge.d new file mode 100644 index 00000000000..a73c31226b7 --- /dev/null +++ b/gas/testsuite/gas/nanomips/la-pic-mclarge.d @@ -0,0 +1,116 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS la-pic large memory model +#as: -mpic -mcmodel=large +#source: la.s + +# Test the la macro with mpic and large memory model + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6083 0000 0000 lapc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la-pic.d b/gas/testsuite/gas/nanomips/la-pic.d new file mode 100644 index 00000000000..8c5ae9f2536 --- /dev/null +++ b/gas/testsuite/gas/nanomips/la-pic.d @@ -0,0 +1,156 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS la-pic +#as: -mpic -G0 +#source: la.s + +# Test the la macro with -mpic. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 44: R_NANOMIPS_PCHI20 data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 48: R_NANOMIPS_LO12 .data +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 4c: R_NANOMIPS_GOT_DISP big_external_data_label +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 50: R_NANOMIPS_GOT_DISP small_external_data_label +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 54: R_NANOMIPS_GOT_DISP big_external_common +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 58: R_NANOMIPS_GOT_DISP small_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 5c: R_NANOMIPS_PCHI20 big_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 60: R_NANOMIPS_LO12 .bss +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 64: R_NANOMIPS_PCHI20 small_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 68: R_NANOMIPS_LO12 .bss\+0x3e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 6c: R_NANOMIPS_PCHI20 data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 70: R_NANOMIPS_LO12 .data\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 74: R_NANOMIPS_GOT_DISP big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 78: R_NANOMIPS_GOT_DISP small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 7c: R_NANOMIPS_GOT_DISP big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 80: R_NANOMIPS_GOT_DISP small_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 84: R_NANOMIPS_PCHI20 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 88: R_NANOMIPS_LO12 .bss\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 8c: R_NANOMIPS_PCHI20 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 90: R_NANOMIPS_LO12 .bss\+0x3e9 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 94: R_NANOMIPS_PCHI20 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 98: R_NANOMIPS_LO12 .data\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 9c: R_NANOMIPS_GOT_DISP big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + a0: R_NANOMIPS_GOT_DISP small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + a4: R_NANOMIPS_GOT_DISP big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + a8: R_NANOMIPS_GOT_DISP small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + ac: R_NANOMIPS_PCHI20 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + b0: R_NANOMIPS_LO12 .bss\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + b4: R_NANOMIPS_PCHI20 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + b8: R_NANOMIPS_LO12 .bss\+0x83e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + bc: R_NANOMIPS_PCHI20 data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + c0: R_NANOMIPS_LO12 .data-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + c4: R_NANOMIPS_GOT_DISP big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + c8: R_NANOMIPS_GOT_DISP small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + cc: R_NANOMIPS_GOT_DISP big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + d0: R_NANOMIPS_GOT_DISP small_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + d4: R_NANOMIPS_PCHI20 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + d8: R_NANOMIPS_LO12 .bss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + dc: R_NANOMIPS_PCHI20 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + e0: R_NANOMIPS_LO12 .bss-0x7c18 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + e4: R_NANOMIPS_PCHI20 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + e8: R_NANOMIPS_LO12 .data\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + ec: R_NANOMIPS_GOT_DISP big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + f0: R_NANOMIPS_GOT_DISP small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + f4: R_NANOMIPS_GOT_DISP big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + f8: R_NANOMIPS_GOT_DISP small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + fc: R_NANOMIPS_PCHI20 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 100: R_NANOMIPS_LO12 .bss\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 104: R_NANOMIPS_PCHI20 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 108: R_NANOMIPS_LO12 .bss\+0x103e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 10c: R_NANOMIPS_PCHI20 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 110: R_NANOMIPS_LO12 .data\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 114: R_NANOMIPS_GOT_DISP big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 118: R_NANOMIPS_GOT_DISP small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 11c: R_NANOMIPS_GOT_DISP big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 120: R_NANOMIPS_GOT_DISP small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 124: R_NANOMIPS_PCHI20 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 128: R_NANOMIPS_LO12 .bss\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 12c: R_NANOMIPS_PCHI20 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 130: R_NANOMIPS_LO12 .bss\+0x1a98d +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + 14c: R_NANOMIPS_GOT_DISP big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la.d b/gas/testsuite/gas/nanomips/la.d new file mode 100644 index 00000000000..7e3686e5dcf --- /dev/null +++ b/gas/testsuite/gas/nanomips/la.d @@ -0,0 +1,115 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS la using li[48] +#source: la.s + +# Test the la macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 a5a5 0001 li a0,0x1a5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.data +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_data_label +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_common +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.bss +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.data\+0x1 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.data\+0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.data-0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.bss-0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.sbss-0x8000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.data\+0x10000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x10000 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 6080 3456 0012 li a0,0x123456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 6080 0000 0000 li a0,0x0 + [0-9a-f]+: R_NANOMIPS_I32 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/la.s b/gas/testsuite/gas/nanomips/la.s new file mode 100644 index 00000000000..029e3c605e5 --- /dev/null +++ b/gas/testsuite/gas/nanomips/la.s @@ -0,0 +1,82 @@ +# Source file used to test the la macro. + + .ifdef mc_large + .set mcmodel=large + .endif + + .ifdef mc_medium + .set mcmodel=medium + .endif + + .data +data_label: + .extern big_external_data_label,1000 + .extern small_external_data_label,1 + .comm big_external_common,1000 + .comm small_external_common,1 + .lcomm big_local_common,1000 + .lcomm small_local_common,1 + + .text +text_label: + la $4,0 + la $4,1 + la $4,0x8000 + la $4,-0x8000 + la $4,0x10000 + la $4,0x1a5a5 + la $4,0($5) + la $4,1($5) + la $4,0x8000($5) + la $4,-0x8000($5) + la $4,0x10000($5) + la $4,0x1a5a5($5) + la $4,data_label + la $4,big_external_data_label + la $4,small_external_data_label + la $4,big_external_common + la $4,small_external_common + la $4,big_local_common + la $4,small_local_common + la $4,data_label+1 + la $4,big_external_data_label+1 + la $4,small_external_data_label+1 + la $4,big_external_common+1 + la $4,small_external_common+1 + la $4,big_local_common+1 + la $4,small_local_common+1 + la $4,data_label+0x8000 + la $4,big_external_data_label+0x8000 + la $4,small_external_data_label+0x8000 + la $4,big_external_common+0x8000 + la $4,small_external_common+0x8000 + la $4,big_local_common+0x8000 + la $4,small_local_common+0x8000 + la $4,data_label-0x8000 + la $4,big_external_data_label-0x8000 + la $4,small_external_data_label-0x8000 + la $4,big_external_common-0x8000 + la $4,small_external_common-0x8000 + la $4,big_local_common-0x8000 + la $4,small_local_common-0x8000 + la $4,data_label+0x10000 + la $4,big_external_data_label+0x10000 + la $4,small_external_data_label+0x10000 + la $4,big_external_common+0x10000 + la $4,small_external_common+0x10000 + la $4,big_local_common+0x10000 + la $4,small_local_common+0x10000 + la $4,data_label+0x1a5a5 + la $4,big_external_data_label+0x1a5a5 + la $4,small_external_data_label+0x1a5a5 + la $4,big_external_common+0x1a5a5 + la $4,small_external_common+0x1a5a5 + la $4,big_local_common+0x1a5a5 + la $4,small_local_common+0x1a5a5 + la $4,($5) + la $4,(0x123456) + la $4,(0x123456)($5) + la $4,(big_external_data_label) + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/nanomips/lb.d b/gas/testsuite/gas/nanomips/lb.d new file mode 100644 index 00000000000..470bbca36e9 --- /dev/null +++ b/gas/testsuite/gas/nanomips/lb.d @@ -0,0 +1,176 @@ +#objdump: -dr --no-show-raw-insn +#name: nanoMIPS lb + +# Test the lb macro. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 <.text>: + [0-9a-f]+: lb a0,0\(zero\) + [0-9a-f]+: lb a0,1\(zero\) + [0-9a-f]+: li a0,32768 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: lui a0,%hi\(0xffff8000\) + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: lui a0,%hi\(0x10000\) + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: lui a0,%hi\(0x1a000\) + [0-9a-f]+: lb a0,1445\(a0\) + [0-9a-f]+: lb a0,0\(a1\) + [0-9a-f]+: lb a0,1\(a1\) + [0-9a-f]+: addiu a0,a1,32768 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: lui a0,%hi\(0xffff8000\) + [0-9a-f]+: addu a0,a0,a1 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: lui a0,%hi\(0x10000\) + [0-9a-f]+: addu a0,a0,a1 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: lui a0,%hi\(0x1a000\) + [0-9a-f]+: addu a0,a0,a1 + [0-9a-f]+: lb a0,1445\(a0\) + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .data + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .data + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .bss + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .bss + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 .sbss + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .data\+0x1 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .data\+0x1 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x1 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x1 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .bss\+0x1 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .bss\+0x1 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 .sbss\+0x1 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .data\+0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .data\+0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x8000 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x8000 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .bss\+0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .bss\+0x8000 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 .sbss\+0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .data-0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .data-0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label-0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label-0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label-0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label-0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common-0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common-0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 small_external_common-0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 small_external_common-0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .bss-0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .bss-0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .sbss-0x8000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .sbss-0x8000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .data\+0x10000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .data\+0x10000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x10000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x10000 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x10000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x10000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x10000 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x10000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .bss\+0x10000 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .bss\+0x10000 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 .sbss\+0x10000 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .data\+0x1a5a5 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .data\+0x1a5a5 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1a5a5 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1a5a5 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x1a5a5 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1a5a5 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1a5a5 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x1a5a5 + [0-9a-f]+: lui a0,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 .bss\+0x1a5a5 + [0-9a-f]+: lb a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_LO12 .bss\+0x1a5a5 + [0-9a-f]+: lb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 .sbss\+0x1a5a5 + [0-9a-f]+: lbu a0,0\(zero\) + [0-9a-f]+: lh a0,0\(zero\) + [0-9a-f]+: lhu a0,0\(zero\) + [0-9a-f]+: lw a0,0\(zero\) +#pass diff --git a/gas/testsuite/gas/nanomips/lb.s b/gas/testsuite/gas/nanomips/lb.s new file mode 100644 index 00000000000..d1321bb56d2 --- /dev/null +++ b/gas/testsuite/gas/nanomips/lb.s @@ -0,0 +1,72 @@ +# Source file used to test the lb macro. + + .data +data_label: + .extern big_external_data_label,1000 + .extern small_external_data_label,1 + .comm big_external_common,1000 + .comm small_external_common,1 + .lcomm big_local_common,1000 + .lcomm small_local_common,1 + + .text + lb $4,0 + lb $4,1 + lb $4,0x8000 + lb $4,-0x8000 + lb $4,0x10000 + lb $4,0x1a5a5 + lb $4,0($5) + lb $4,1($5) + lb $4,0x8000($5) + lb $4,-0x8000($5) + lb $4,0x10000($5) + lb $4,0x1a5a5($5) + lb $4,data_label + lb $4,big_external_data_label + lb $4,small_external_data_label + lb $4,big_external_common + lb $4,small_external_common + lb $4,big_local_common + lb $4,small_local_common + lb $4,data_label+1 + lb $4,big_external_data_label+1 + lb $4,small_external_data_label+1 + lb $4,big_external_common+1 + lb $4,small_external_common+1 + lb $4,big_local_common+1 + lb $4,small_local_common+1 + lb $4,data_label+0x8000 + lb $4,big_external_data_label+0x8000 + lb $4,small_external_data_label+0x8000 + lb $4,big_external_common+0x8000 + lb $4,small_external_common+0x8000 + lb $4,big_local_common+0x8000 + lb $4,small_local_common+0x8000 + lb $4,data_label-0x8000 + lb $4,big_external_data_label-0x8000 + lb $4,small_external_data_label-0x8000 + lb $4,big_external_common-0x8000 + lb $4,small_external_common-0x8000 + lb $4,big_local_common-0x8000 + lb $4,small_local_common-0x8000 + lb $4,data_label+0x10000 + lb $4,big_external_data_label+0x10000 + lb $4,small_external_data_label+0x10000 + lb $4,big_external_common+0x10000 + lb $4,small_external_common+0x10000 + lb $4,big_local_common+0x10000 + lb $4,small_local_common+0x10000 + lb $4,data_label+0x1a5a5 + lb $4,big_external_data_label+0x1a5a5 + lb $4,small_external_data_label+0x1a5a5 + lb $4,big_external_common+0x1a5a5 + lb $4,small_external_common+0x1a5a5 + lb $4,big_local_common+0x1a5a5 + lb $4,small_local_common+0x1a5a5 + +# Several macros are handled like lb. Sanity check them. + lbu $4,0 + lh $4,0 + lhu $4,0 + lw $4,0 diff --git a/gas/testsuite/gas/nanomips/ld-reloc.d b/gas/testsuite/gas/nanomips/ld-reloc.d new file mode 100644 index 00000000000..4670cc11b61 --- /dev/null +++ b/gas/testsuite/gas/nanomips/ld-reloc.d @@ -0,0 +1,86 @@ +#objdump: -dr +#name: LD with relocation operators for nanoMIPS + +.*file format.* + +Disassembly of section \.text: + +00000000 : + 0: 84a4 8004 lw a1,4\(a0\) + 4: 8484 8000 lw a0,0\(a0\) + 8: 0024 7ffb addiu at,a0,32763 + c: 8481 8000 lw a0,0\(at\) + 10: 84a1 8004 lw a1,4\(at\) + 14: 0024 7ffc addiu at,a0,32764 + 18: 8481 8000 lw a0,0\(at\) + 1c: 84a1 8004 lw a1,4\(at\) + 20: 0024 7fff addiu at,a0,32767 + 24: 8481 8000 lw a0,0\(at\) + 28: 84a1 8004 lw a1,4\(at\) + 2c: 0024 8000 addiu at,a0,32768 + 30: 8481 8000 lw a0,0\(at\) + 34: 84a1 8004 lw a1,4\(at\) + 38: 8485 8000 lw a0,0\(a1\) + 3c: 84a5 8004 lw a1,4\(a1\) + 40: 0025 7ffb addiu at,a1,32763 + 44: 8481 8000 lw a0,0\(at\) + 48: 84a1 8004 lw a1,4\(at\) + 4c: 0025 7ffc addiu at,a1,32764 + 50: 8481 8000 lw a0,0\(at\) + 54: 84a1 8004 lw a1,4\(at\) + 58: 0025 7fff addiu at,a1,32767 + 5c: 8481 8000 lw a0,0\(at\) + 60: 84a1 8004 lw a1,4\(at\) + 64: 0025 8000 addiu at,a1,32768 + 68: 8481 8000 lw a0,0\(at\) + 6c: 84a1 8004 lw a1,4\(at\) + 70: e023 7000 lui at,%hi\(0x37000\) + 74: 2025 0950 addu at,a1,at + 78: 8481 8ffb lw a0,4091\(at\) + 7c: 84a1 8fff lw a1,4095\(at\) + 80: e023 7000 lui at,%hi\(0x37000\) + 84: 8021 0ffc ori at,at,0xffc + 88: 2025 0950 addu at,a1,at + 8c: 8481 8000 lw a0,0\(at\) + 90: 84a1 8004 lw a1,4\(at\) + 94: e023 7000 lui at,%hi\(0x37000\) + 98: 8021 0fff ori at,at,0xfff + 9c: 2025 0950 addu at,a1,at + a0: 8481 8000 lw a0,0\(at\) + a4: 84a1 8004 lw a1,4\(at\) + a8: e023 8000 lui at,%hi\(0x38000\) + ac: 2025 0950 addu at,a1,at + b0: 8481 8000 lw a0,0\(at\) + b4: 84a1 8004 lw a1,4\(at\) + b8: 8480 8000 lw a0,0\(zero\) + b8: R_NANOMIPS_LO12 foo + bc: 84a0 8000 lw a1,0\(zero\) + bc: R_NANOMIPS_LO12 foo\+0x4 + c0: 4080 0002 lw a0,0\(gp\) + c0: R_NANOMIPS_GPREL19_S2 foo + c4: 40a0 0002 lw a1,0\(gp\) + c4: R_NANOMIPS_GPREL19_S2 foo\+0x4 + c8: 8480 8765 lw a0,1893\(zero\) + cc: 84a0 8769 lw a1,1897\(zero\) + d0: e034 8244 lui at,%hi\(0x12348000\) + d4: 8481 8000 lw a0,0\(at\) + d8: 84a1 8004 lw a1,4\(at\) + dc: 84a4 8000 lw a1,0\(a0\) + dc: R_NANOMIPS_LO12 foo\+0x4 + e0: 8484 8000 lw a0,0\(a0\) + e0: R_NANOMIPS_LO12 foo + e4: 8485 8000 lw a0,0\(a1\) + e4: R_NANOMIPS_LO12 foo + e8: 84a5 8000 lw a1,0\(a1\) + e8: R_NANOMIPS_LO12 foo\+0x4 + ec: 8485 8765 lw a0,1893\(a1\) + f0: 84a5 8769 lw a1,1897\(a1\) + f4: e034 8244 lui at,%hi\(0x12348000\) + f8: 2025 0950 addu at,a1,at + fc: 8481 8000 lw a0,0\(at\) + 100: 84a1 8004 lw a1,4\(at\) + 104: 8485 8000 lw a0,0\(a1\) + 104: R_NANOMIPS_LO12 foo\+0x12348765 + 108: 84a5 8000 lw a1,0\(a1\) + 108: R_NANOMIPS_LO12 foo\+0x12348769 +#pass diff --git a/gas/testsuite/gas/nanomips/ld-reloc.s b/gas/testsuite/gas/nanomips/ld-reloc.s new file mode 100644 index 00000000000..e691b4977cd --- /dev/null +++ b/gas/testsuite/gas/nanomips/ld-reloc.s @@ -0,0 +1,34 @@ + .data +data_label: + .comm foo,4 + .text + .ent func +func: + ld $4,($4) + ld $4,0x7ffb($4) + ld $4,0x7ffc($4) + ld $4,0x7fff($4) + ld $4,0x8000($4) + + ld $4,($5) + ld $4,0x7ffb($5) + ld $4,0x7ffc($5) + ld $4,0x7fff($5) + ld $4,0x8000($5) + ld $4,0x37ffb($5) + ld $4,0x37ffc($5) + ld $4,0x37fff($5) + ld $4,0x38000($5) + + ld $4,%lo(foo) + ld $4,%gprel(foo) + ld $4,%lo(0x12348765) + ld $4,%hi(0x12348765) + + ld $4,%lo(foo)($4) + ld $4,%lo(foo)($5) + + ld $4,%lo(0x12348765)($5) + ld $4,%hi(0x12348765)($5) + ld $4,%lo(foo+0x12348765)($5) + .end func diff --git a/gas/testsuite/gas/nanomips/ld.d b/gas/testsuite/gas/nanomips/ld.d new file mode 100644 index 00000000000..93666cf6221 --- /dev/null +++ b/gas/testsuite/gas/nanomips/ld.d @@ -0,0 +1,174 @@ +#objdump: -dr --no-show-raw-insn +#name: nanoMIPS ld +#source: ld.s + +# Test the ld macro on nanoMIPS + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: lwm a0,0\(zero\),2 + 4: lwm a0,1\(zero\),2 + 8: li at,4092 + c: lwm a0,0\(at\),2 + 10: li at,-4092 + 14: lwm a0,0\(at\),2 + 18: li at,4096 + 1c: lwm a0,0\(at\),2 + 20: li at,0x1a5a5 + 26: lwm a0,0\(at\),2 + 2a: lwm a0,0\(a1\),2 + 2e: lwm a0,1\(a1\),2 + 32: addiu at,a1,4092 + 36: lwm a0,0\(at\),2 + 3a: addiu at,a1,-4092 + 3e: lwm a0,0\(at\),2 + 42: addiu at,a1,4096 + 46: lwm a0,0\(at\),2 + 4a: li at,0x1a5a5 + 50: addu at,a1,at + 54: lwm a0,0\(at\),2 + 58: li at,0x0 + 5a: R_NANOMIPS_I32 \.data + 5e: lwm a0,0\(at\),2 + 62: li at,0x0 + 64: R_NANOMIPS_I32 big_external_data_label + 68: lwm a0,0\(at\),2 + 6c: lw a0,0\(gp\) + 6c: R_NANOMIPS_GPREL19_S2 small_external_data_label + 70: lw a1,0\(gp\) + 70: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x4 + 74: li at,0x0 + 76: R_NANOMIPS_I32 big_external_common + 7a: lwm a0,0\(at\),2 + 7e: lw a0,0\(gp\) + 7e: R_NANOMIPS_GPREL19_S2 small_external_common + 82: lw a1,0\(gp\) + 82: R_NANOMIPS_GPREL19_S2 small_external_common\+0x4 + 86: li at,0x0 + 88: R_NANOMIPS_I32 \.bss + 8c: lwm a0,0\(at\),2 + 90: lw a0,0\(gp\) + 90: R_NANOMIPS_GPREL19_S2 \.sbss + 94: lw a1,0\(gp\) + 94: R_NANOMIPS_GPREL19_S2 \.sbss\+0x4 + 98: li at,0x0 + 9a: R_NANOMIPS_I32 \.data\+0x1 + 9e: lwm a0,0\(at\),2 + a2: li at,0x0 + a4: R_NANOMIPS_I32 big_external_data_label\+0x1 + a8: lwm a0,0\(at\),2 + ac: lw a0,0\(gp\) + ac: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1 + b0: lw a1,0\(gp\) + b0: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x5 + b4: li at,0x0 + b6: R_NANOMIPS_I32 big_external_common\+0x1 + ba: lwm a0,0\(at\),2 + be: lw a0,0\(gp\) + be: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1 + c2: lw a1,0\(gp\) + c2: R_NANOMIPS_GPREL19_S2 small_external_common\+0x5 + c6: li at,0x0 + c8: R_NANOMIPS_I32 \.bss\+0x1 + cc: lwm a0,0\(at\),2 + d0: lw a0,0\(gp\) + d0: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1 + d4: lw a1,0\(gp\) + d4: R_NANOMIPS_GPREL19_S2 \.sbss\+0x5 + d8: li at,0x0 + da: R_NANOMIPS_I32 \.data\+0xffc + de: lwm a0,0\(at\),2 + e2: li at,0x0 + e4: R_NANOMIPS_I32 big_external_data_label\+0xffc + e8: lwm a0,0\(at\),2 + ec: lw a0,0\(gp\) + ec: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0xffc + f0: lw a1,0\(gp\) + f0: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1000 + f4: li at,0x0 + f6: R_NANOMIPS_I32 big_external_common\+0xffc + fa: lwm a0,0\(at\),2 + fe: lw a0,0\(gp\) + fe: R_NANOMIPS_GPREL19_S2 small_external_common\+0xffc + 102: lw a1,0\(gp\) + 102: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1000 + 106: li at,0x0 + 108: R_NANOMIPS_I32 \.bss\+0xffc + 10c: lwm a0,0\(at\),2 + 110: lw a0,0\(gp\) + 110: R_NANOMIPS_GPREL19_S2 \.sbss\+0xffc + 114: lw a1,0\(gp\) + 114: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1000 + 118: li at,0x0 + 11a: R_NANOMIPS_I32 \.data-0xffc + 11e: lwm a0,0\(at\),2 + 122: li at,0x0 + 124: R_NANOMIPS_I32 big_external_data_label-0xffc + 128: lwm a0,0\(at\),2 + 12c: li at,0x0 + 12e: R_NANOMIPS_I32 small_external_data_label-0xffc + 132: lwm a0,0\(at\),2 + 136: li at,0x0 + 138: R_NANOMIPS_I32 big_external_common-0xffc + 13c: lwm a0,0\(at\),2 + 140: li at,0x0 + 142: R_NANOMIPS_I32 small_external_common-0xffc + 146: lwm a0,0\(at\),2 + 14a: li at,0x0 + 14c: R_NANOMIPS_I32 \.bss-0xffc + 150: lwm a0,0\(at\),2 + 154: li at,0x0 + 156: R_NANOMIPS_I32 \.sbss-0xffc + 15a: lwm a0,0\(at\),2 + 15e: li at,0x0 + 160: R_NANOMIPS_I32 \.data\+0x1000 + 164: lwm a0,0\(at\),2 + 168: li at,0x0 + 16a: R_NANOMIPS_I32 big_external_data_label\+0x1000 + 16e: lwm a0,0\(at\),2 + 172: lw a0,0\(gp\) + 172: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1000 + 176: lw a1,0\(gp\) + 176: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1004 + 17a: li at,0x0 + 17c: R_NANOMIPS_I32 big_external_common\+0x1000 + 180: lwm a0,0\(at\),2 + 184: lw a0,0\(gp\) + 184: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1000 + 188: lw a1,0\(gp\) + 188: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1004 + 18c: li at,0x0 + 18e: R_NANOMIPS_I32 \.bss\+0x1000 + 192: lwm a0,0\(at\),2 + 196: lw a0,0\(gp\) + 196: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1000 + 19a: lw a1,0\(gp\) + 19a: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1004 + 19e: li at,0x0 + 1a0: R_NANOMIPS_I32 \.data\+0x1a5a5 + 1a4: lwm a0,0\(at\),2 + 1a8: li at,0x0 + 1aa: R_NANOMIPS_I32 big_external_data_label\+0x1a5a5 + 1ae: lwm a0,0\(at\),2 + 1b2: lw a0,0\(gp\) + 1b2: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1a5a5 + 1b6: lw a1,0\(gp\) + 1b6: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1a5a9 + 1ba: li at,0x0 + 1bc: R_NANOMIPS_I32 big_external_common\+0x1a5a5 + 1c0: lwm a0,0\(at\),2 + 1c4: lw a0,0\(gp\) + 1c4: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1a5a5 + 1c8: lw a1,0\(gp\) + 1c8: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1a5a9 + 1cc: li at,0x0 + 1ce: R_NANOMIPS_I32 \.bss\+0x1a5a5 + 1d2: lwm a0,0\(at\),2 + 1d6: lw a0,0\(gp\) + 1d6: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1a5a5 + 1da: lw a1,0\(gp\) + 1da: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1a5a9 +#pass diff --git a/gas/testsuite/gas/nanomips/ld.s b/gas/testsuite/gas/nanomips/ld.s new file mode 100644 index 00000000000..1d68dafa327 --- /dev/null +++ b/gas/testsuite/gas/nanomips/ld.s @@ -0,0 +1,145 @@ +# Source file used to test the doubleword memory access macros +# (ld and friends). + + .ifdef mc_large + .set mcmodel=large + .endif + + .ifdef mc_medium + .set mcmodel=medium + .endif + +# By default test ld. + .set d4, $4 + +# If defined, test sd instead. + .ifdef tsd + .macro ld ops:vararg + sd \ops + .endm + .endif +# If defined, test l.d instead. + .ifdef tl_d + .set d4, $f4 + .macro ld ops:vararg + l.d \ops + .endm + .endif +# If defined, test s.d instead. + .ifdef ts_d + .set d4, $f4 + .macro ld ops:vararg + s.d \ops + .endm + .endif +# If defined, test ldc1 instead. + .ifdef tldc1 + .set d4, $f4 + .macro ld ops:vararg + ldc1 \ops + .endm + .endif +# If defined, test sdc1 instead. + .ifdef tsdc1 + .set d4, $f4 + .macro ld ops:vararg + sdc1 \ops + .endm + .endif +# If defined, test lw instead. + .ifdef tlw + .macro ld ops:vararg + lw \ops + .endm + .endif +# If defined, test sw instead. + .ifdef tsw + .macro ld ops:vararg + sw \ops + .endm + .endif + + .equ lo_max,0xffc + .equ hi_min,0x1000 + + .macro data + .bss + .align 12 + .sbss + .align 12 + .data + .align 12 +data_label: + .extern big_external_data_label,1000 + .extern small_external_data_label,1 + .comm big_external_common,1000 + .comm small_external_common,1 + .lcomm big_local_common,1000 + .lcomm small_local_common,1 + .endm + + .ifndef forward + data + .endif + + .text + .align 12 +text_label: + ld d4,0 + ld d4,1 + ld d4,lo_max + ld d4,-lo_max + ld d4,hi_min + ld d4,0x1a5a5 + ld d4,0($5) + ld d4,1($5) + ld d4,lo_max($5) + ld d4,-lo_max($5) + ld d4,hi_min($5) + ld d4,0x1a5a5($5) + ld d4,data_label + ld d4,big_external_data_label + ld d4,small_external_data_label + ld d4,big_external_common + ld d4,small_external_common + ld d4,big_local_common + ld d4,small_local_common + ld d4,data_label+1 + ld d4,big_external_data_label+1 + ld d4,small_external_data_label+1 + ld d4,big_external_common+1 + ld d4,small_external_common+1 + ld d4,big_local_common+1 + ld d4,small_local_common+1 + ld d4,data_label+lo_max + ld d4,big_external_data_label+lo_max + ld d4,small_external_data_label+lo_max + ld d4,big_external_common+lo_max + ld d4,small_external_common+lo_max + ld d4,big_local_common+lo_max + ld d4,small_local_common+lo_max + ld d4,data_label-lo_max + ld d4,big_external_data_label-lo_max + ld d4,small_external_data_label-lo_max + ld d4,big_external_common-lo_max + ld d4,small_external_common-lo_max + ld d4,big_local_common-lo_max + ld d4,small_local_common-lo_max + ld d4,data_label+hi_min + ld d4,big_external_data_label+hi_min + ld d4,small_external_data_label+hi_min + ld d4,big_external_common+hi_min + ld d4,small_external_common+hi_min + ld d4,big_local_common+hi_min + ld d4,small_local_common+hi_min + ld d4,data_label+0x1a5a5 + ld d4,big_external_data_label+0x1a5a5 + ld d4,small_external_data_label+0x1a5a5 + ld d4,big_external_common+0x1a5a5 + ld d4,small_external_common+0x1a5a5 + ld d4,big_local_common+0x1a5a5 + ld d4,small_local_common+0x1a5a5 + + .ifdef forward + data + .endif diff --git a/gas/testsuite/gas/nanomips/li.d b/gas/testsuite/gas/nanomips/li.d new file mode 100644 index 00000000000..67ab935fc5a --- /dev/null +++ b/gas/testsuite/gas/nanomips/li.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS li + +# Test the li macro (nanoMIPS). + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +0+0000 d200 li a0,0 +0+0002 d201 li a0,1 +0+0004 0080 8000 li a0,32768 +0+0008 e09f 8ffd lui a0,%hi\(0xffff8000\) +0+000c e081 0000 lui a0,%hi\(0x10000\) +0+0010 e081 a000 lui a0,%hi\(0x1a000\) +0+0014 8084 05a5 ori a0,a0,0x5a5 +#pass diff --git a/gas/testsuite/gas/nanomips/li.s b/gas/testsuite/gas/nanomips/li.s new file mode 100644 index 00000000000..7a3848ca4ad --- /dev/null +++ b/gas/testsuite/gas/nanomips/li.s @@ -0,0 +1,9 @@ +# Source file used to test the li macro. + +foo: + li $4,0 + li $4,1 + li $4,0x8000 + li $4,-0x8000 + li $4,0x10000 + li $4,0x1a5a5 diff --git a/gas/testsuite/gas/nanomips/lif-pic.d b/gas/testsuite/gas/nanomips/lif-pic.d new file mode 100644 index 00000000000..4985c3f8615 --- /dev/null +++ b/gas/testsuite/gas/nanomips/lif-pic.d @@ -0,0 +1,16 @@ +#objdump: -dr --no-show-raw-insn +#name: nanoMIPS LI float sysVr4 PIC little endian mode +#as: -mpic -EL +#source: lifloat.s + +# Test loading immediate floating point values in PIC (nanoMIPS) + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: li a1,0x3ff1f9a6 + 6: li a0,0xb50b0f28 + c: li a0,0x3f8fcd36 +#pass diff --git a/gas/testsuite/gas/nanomips/lifloat-mem.d b/gas/testsuite/gas/nanomips/lifloat-mem.d new file mode 100644 index 00000000000..0ebccf63566 --- /dev/null +++ b/gas/testsuite/gas/nanomips/lifloat-mem.d @@ -0,0 +1,20 @@ +#objdump: -dr --no-show-raw-insn +#name: LI float without float construction +#source: lifloat.s +#as: --no-construct-floats + +# Test loading immediate floating point values without float construction + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: li at,0x0 + 2: R_NANOMIPS_I32 .rodata + 6: lwm a0,0\(at\),2 + a: lui a0,0x0 + a: R_NANOMIPS_HI20 .rodata\+0x8 + e: lw a0,0\(a0\) + e: R_NANOMIPS_LO12 .rodata\+0x8 +#pass diff --git a/gas/testsuite/gas/nanomips/lifloat-nms.d b/gas/testsuite/gas/nanomips/lifloat-nms.d new file mode 100644 index 00000000000..ce279c0cdbe --- /dev/null +++ b/gas/testsuite/gas/nanomips/lifloat-nms.d @@ -0,0 +1,20 @@ +#objdump: -dr --no-show-raw-insn +#name: LI float nanoMIPS subset +#source: lifloat.s + +# Test loading immediate floating point values (nanoMIPS subset) + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: lui at,0x0 + 0: R_NANOMIPS_HI20 \.rodata + 4: lw a0,0\(at\) + 4: R_NANOMIPS_LO12 \.rodata + 8: lw a1,0\(at\) + 8: R_NANOMIPS_LO12 \.rodata\+0x4 + c: lui a0,%hi\(0x3f8fc000\) + 10: ori a0,a0,0xd36 +#pass diff --git a/gas/testsuite/gas/nanomips/lifloat.d b/gas/testsuite/gas/nanomips/lifloat.d new file mode 100644 index 00000000000..b58b3f9bc2f --- /dev/null +++ b/gas/testsuite/gas/nanomips/lifloat.d @@ -0,0 +1,15 @@ +#objdump: -dr --no-show-raw-insn +#name: nanoMIPS LI float little endian +#as: -EL + +# Test loading immediate floating point values (nanoMIPS) + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: li a1,0x3ff1f9a6 + 6: li a0,0xb50b0f28 + c: li a0,0x3f8fcd36 +#pass diff --git a/gas/testsuite/gas/nanomips/lifloat.s b/gas/testsuite/gas/nanomips/lifloat.s new file mode 100644 index 00000000000..03610eb4c26 --- /dev/null +++ b/gas/testsuite/gas/nanomips/lifloat.s @@ -0,0 +1,6 @@ +# Source file used to test the li.d and li.s macros. + +foo: + li.d $4,1.12345 + li.s $4,1.12345 + diff --git a/gas/testsuite/gas/nanomips/lineno.d b/gas/testsuite/gas/nanomips/lineno.d new file mode 100644 index 00000000000..a6ef3bca35c --- /dev/null +++ b/gas/testsuite/gas/nanomips/lineno.d @@ -0,0 +1,86 @@ +#objdump: -d -l +#name: assembly line numbers +#as: --gstabs + + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +00000000
: +main\(\): +.*:10 + 0: 83bd 8018 addiu sp,sp,-24 +.*:11 + 4: b7e5 sw ra,20\(sp\) +.*:12 + 6: b7c4 sw fp,16\(sp\) +.*:13 + 8: 13dd move fp,sp +.*:14 + a: 2a00 0000 balc 0 <__main> +.*:15 + e: 0040 0002 li t4,2 +.*:16 + 12: 845e 9000 sw t4,0\(fp\) +.*:17 + 16: 845e 8000 lw t4,0\(fp\) +.*:18 + 1a: 1062 move t5,t4 +.*:19 + 1c: 8083 c001 sll a0,t5,1 +.*:20 + 20: 2044 1150 addu t4,a0,t4 +.*:21 + 24: 845e 9004 sw t4,4\(fp\) +.*:22 + 28: 849e 8004 lw a0,4\(fp\) +.*:23 + 2c: 2a00 0000 balc 44 +.*:24 + 30: 847e 8000 lw t5,0\(fp\) +.*:25 + 34: 1043 move t4,t5 +.*:26 + 36: 1800 bc 38 <\$L1> + +00000038 <\$L1>: +.*:28 + 38: 13be move sp,fp +.*:29 + 3a: 37e5 lw ra,20\(sp\) +.*:30 + 3c: 37c4 lw fp,16\(sp\) +.*:31 + 3e: 03bd 0018 addiu sp,sp,24 +.*:32 + 42: dbe0 jrc ra + +00000044 : +g\(\): +.*:41 + 44: 83bd 8018 addiu sp,sp,-24 +.*:42 + 48: b7c4 sw fp,16\(sp\) +.*:43 + 4a: 13dd move fp,sp +.*:44 + 4c: 849e 9000 sw a0,0\(fp\) +.*:45 + 50: 845e 8000 lw t4,0\(fp\) +.*:46 + 54: 0062 0001 addiu t5,t4,1 +.*:47 + 58: 1043 move t4,t5 +.*:48 + 5a: 1800 bc 5c <\$L2> + +0000005c <\$L2>: +.*:50 + 5c: 13be move sp,fp +.*:51 + 5e: 37c4 lw fp,16\(sp\) +.*:52 + 60: 03bd 0018 addiu sp,sp,24 +.*:53 + 64: dbe0 jrc ra +#pass diff --git a/gas/testsuite/gas/nanomips/lineno.s b/gas/testsuite/gas/nanomips/lineno.s new file mode 100644 index 00000000000..0d651808f1a --- /dev/null +++ b/gas/testsuite/gas/nanomips/lineno.s @@ -0,0 +1,54 @@ + .text + +# some real code, compiled from a toy C program + .globl main + .ent main +main: + .frame $fp,24,$31 # vars= 16, regs= 2/0, args= 0, extra= 0 + .mask 0xc0000000,-8 + .fmask 0x00000000,0 + subu $sp,$sp,24 + sw $31,20($sp) + sw $fp,16($sp) + move $fp,$sp + jal __main + li $2,2 # 0x2 + sw $2,0($fp) + lw $2,0($fp) + move $3,$2 + sll $4,$3,1 + addu $2,$4,$2 + sw $2,4($fp) + lw $4,4($fp) + jal g + lw $3,0($fp) + move $2,$3 + b $L1 +$L1: + move $sp,$fp + lw $31,20($sp) + lw $fp,16($sp) + addu $sp,$sp,24 + j $31 + .end main + .align 2 + .globl g + .ent g +g: + .frame $fp,24,$31 # vars= 16, regs= 1/0, args= 0, extra= 0 + .mask 0x40000000,-16 + .fmask 0x00000000,0 + subu $sp,$sp,24 + sw $fp,16($sp) + move $fp,$sp + sw $4,0($fp) + lw $2,0($fp) + addu $3,$2,1 + move $2,$3 + b $L2 +$L2: + move $sp,$fp + lw $fp,16($sp) + addu $sp,$sp,24 + j $31 + .end g diff --git a/gas/testsuite/gas/nanomips/linkrelax-dis.d b/gas/testsuite/gas/nanomips/linkrelax-dis.d new file mode 100644 index 00000000000..21a788aa644 --- /dev/null +++ b/gas/testsuite/gas/nanomips/linkrelax-dis.d @@ -0,0 +1,30 @@ +#objdump: -dr +#name: nanoMIPS PC-relative disassembly with linkrelax flag + +# Check nanoMIPS PC-relative disassembly with linkrelax + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +[0-9a-f]+ : + 0: 0480 0000 lapc a0,12 + [0-9a-f]+: R_NANOMIPS_PC21_S1 test1 + [0-9a-f]+: R_NANOMIPS_ALIGN __reloc_align_\^B_1 + [0-9a-f]+: R_NANOMIPS_FILL __reloc_fill_\^B_8 + [0-9a-f]+: R_NANOMIPS_MAX __reloc_max_\^B_a + 4: 9a00 beqzc a0,12 + [0-9a-f]+: R_NANOMIPS_PC7_S1 test1 + [0-9a-f]+: R_NANOMIPS_NORELAX \*ABS\* + 6: 9008 nop + 8: 8000 c000 nop + c: 8000 c000 nop + 10: 3800 balc 0 + [0-9a-f]+: R_NANOMIPS_PC10_S1 test + [0-9a-f]+: R_NANOMIPS_RELAX \*ABS\* + +[0-9a-f]+ : + 12: 9008 nop + 14: 8000 c000 nop + 18: 8000 c000 nop + 1c: 8000 c000 nop diff --git a/gas/testsuite/gas/nanomips/linkrelax-dis.s b/gas/testsuite/gas/nanomips/linkrelax-dis.s new file mode 100644 index 00000000000..ffe79abf9b0 --- /dev/null +++ b/gas/testsuite/gas/nanomips/linkrelax-dis.s @@ -0,0 +1,14 @@ +# Check how linker relaxations place-holders affect disassembly +# of PC-relative instructions + +test: + .linkrelax + .balign 8,8,0xa + lapc $a0,test1 + .set nolinkrelax + beqc $a0,$zero,test1 + .set linkrelax + .align 4 + balc test +test1: + nop diff --git a/gas/testsuite/gas/nanomips/linkrelax-relocs.d b/gas/testsuite/gas/nanomips/linkrelax-relocs.d new file mode 100644 index 00000000000..e89adc82cbf --- /dev/null +++ b/gas/testsuite/gas/nanomips/linkrelax-relocs.d @@ -0,0 +1,79 @@ +#name: Relaxation relocations on nanoMIPS +#DUMPPROG: readelf +#readelf: -Wr -Ws +#as: --defsym relaxmode=1 +#source: linkrelax.s + +#... +Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 39 entries: + Offset Info Type Sym. Value Symbol's Name \+ Addend +00000004 [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_1 \+ 0 +00000008 [0-9a-f]+ R_NANOMIPS_PC25_S1 00000030 test2 \+ 0 +00000008 [0-9a-f]+ R_NANOMIPS_INSN32 0 +0000000c [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_2 \+ 0 +00000010 [0-9a-f]+ R_NANOMIPS_PC10_S1 00000030 test2 \+ 0 +00000010 [0-9a-f]+ R_NANOMIPS_INSN16 0 +00000014 [0-9a-f]+ R_NANOMIPS_NORELAX 0 +00000018 [0-9a-f]+ R_NANOMIPS_PC25_S1 00000030 test2 \+ 0 +00000020 [0-9a-f]+ R_NANOMIPS_PC10_S1 00000030 test2 \+ 0 +0000002a [0-9a-f]+ R_NANOMIPS_RELAX 0 +0000002c [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_3 \+ 0 +00000032 [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_4 \+ 0 +00000032 [0-9a-f]+ R_NANOMIPS_FILL 0000000a __reloc_fill_\^B_a \+ 0 +0000003a [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_5 \+ 0 +0000003a [0-9a-f]+ R_NANOMIPS_FILL 000000ab __reloc_fill_\^B_ab \+ 0 +0000003a [0-9a-f]+ R_NANOMIPS_MAX 00000005 __reloc_max_\^B_5 \+ 0 +00000042 [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_6 \+ 0 +00000042 [0-9a-f]+ R_NANOMIPS_FILL 000000cd __reloc_fill_\^B_cd \+ 0 +00000042 [0-9a-f]+ R_NANOMIPS_MAX 00000006 __reloc_max_\^B_6 \+ 0 +0000004c [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_7 \+ 0 +0000004c [0-9a-f]+ R_NANOMIPS_FILL 0000abcd __reloc_fill_\^B_abcd \+ 0 +0000004c [0-9a-f]+ R_NANOMIPS_MAX 00000006 __reloc_max_\^B_6 \+ 0 +00000054 [0-9a-f]+ R_NANOMIPS_ALIGN 00000003 __reloc_align_\^B_8 \+ 0 +00000054 [0-9a-f]+ R_NANOMIPS_FILL abcd1234 __reloc_fill_\^B_abcd1234 \+ 0 +00000054 [0-9a-f]+ R_NANOMIPS_MAX 00000006 __reloc_max_\^B_6 \+ 0 +0000005c [0-9a-f]+ R_NANOMIPS_ALIGN 00000004 __reloc_align_\^B_9 \+ 0 +0000005c [0-9a-f]+ R_NANOMIPS_FILL 0000000b __reloc_fill_\^B_b \+ 0 +00000062 [0-9a-f]+ R_NANOMIPS_ALIGN 00000004 __reloc_align_\^B_10 \+ 0 +00000062 [0-9a-f]+ R_NANOMIPS_FILL 000000ba __reloc_fill_\^B_ba \+ 0 +00000062 [0-9a-f]+ R_NANOMIPS_MAX 00000005 __reloc_max_\^B_5 \+ 0 +00000064 [0-9a-f]+ R_NANOMIPS_ALIGN 00000004 __reloc_align_\^B_11 \+ 0 +00000064 [0-9a-f]+ R_NANOMIPS_FILL 000000ba __reloc_fill_\^B_ba \+ 0 +00000064 [0-9a-f]+ R_NANOMIPS_MAX 0000000c __reloc_max_\^B_c \+ 0 +00000074 [0-9a-f]+ R_NANOMIPS_ALIGN 00000004 __reloc_align_\^B_12 \+ 0 +00000074 [0-9a-f]+ R_NANOMIPS_FILL 0000dcba __reloc_fill_\^B_dcba \+ 0 +00000074 [0-9a-f]+ R_NANOMIPS_MAX 00000010 __reloc_max_\^B_10 \+ 0 +00000084 [0-9a-f]+ R_NANOMIPS_ALIGN 00000004 __reloc_align_\^B_13 \+ 0 +00000084 [0-9a-f]+ R_NANOMIPS_FILL 4321dcba __reloc_fill_\^B_4321dcba \+ 0 +00000084 [0-9a-f]+ R_NANOMIPS_MAX 00000010 __reloc_max_\^B_10 \+ 0 +#... +Symbol table '.symtab' contains [0-9]+ entries: +#... + +[0-9]+: 00000003 4 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_1 +.* + +[0-9]+: 00000003 4 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_2 + +[0-9]+: 00000003 4 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_3 + +[0-9]+: 00000003 6 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_4 + +[0-9]+: 0000000a 1 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_a + +[0-9]+: 00000003 0 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_5 + +[0-9]+: 000000ab 1 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_ab + +[0-9]+: 00000005 0 NOTYPE LOCAL DEFAULT ABS __reloc_max_\^B_5 + +[0-9]+: 00000003 6 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_6 + +[0-9]+: 000000cd 1 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_cd + +[0-9]+: 00000006 0 NOTYPE LOCAL DEFAULT ABS __reloc_max_\^B_6 + +[0-9]+: 00000003 4 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_7 + +[0-9]+: 0000abcd 2 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_abcd + +[0-9]+: 00000003 4 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_8 + +[0-9]+: abcd1234 4 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_abcd1234 + +[0-9]+: 00000004 4 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_9 + +[0-9]+: 0000000b 1 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_b + +[0-9]+: 00000004 0 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_10 + +[0-9]+: 000000ba 1 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_ba + +[0-9]+: 00000004 12 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_11 + +[0-9]+: 0000000c 0 NOTYPE LOCAL DEFAULT ABS __reloc_max_\^B_c + +[0-9]+: 00000004 12 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_12 + +[0-9]+: 0000dcba 2 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_dcba + +[0-9]+: 00000010 0 NOTYPE LOCAL DEFAULT ABS __reloc_max_\^B_10 + +[0-9]+: 00000004 12 NOTYPE LOCAL DEFAULT ABS __reloc_align_\^B_13 + +[0-9]+: 4321dcba 4 NOTYPE LOCAL DEFAULT ABS __reloc_fill_\^B_4321dcba +#pass diff --git a/gas/testsuite/gas/nanomips/linkrelax.d b/gas/testsuite/gas/nanomips/linkrelax.d new file mode 100644 index 00000000000..f2bbd7d93b2 --- /dev/null +++ b/gas/testsuite/gas/nanomips/linkrelax.d @@ -0,0 +1,17 @@ +#name: Relaxation code dump for nanoMIPS little-endian +#objdump: -sj.text +#as: --defsym relaxmode=1 -EL +#source: linkrelax.s + +#... +Contents of section \.text: + 0000 48000400 008000c0 00280000 008000c0 .* + 0010 00180890 43000400 00280000 008000c0 .* + 0020 00180890 008000c0 08900890 008000c0 .* + 0030 4c900a0a 0a0a0a0a 08900080 00c00080 .* + 0040 00c0cdcd cdcdcdcd 008000c0 cdabcdab .* + 0050 008000c0 3412cdab 43000400 0b0b0b0b .* + 0060 08900890 babababa babababa babababa .* + 0070 008000c0 badcbadc badcbadc badcbadc .* + 0080 008000c0 badc2143 badc2143 badc2143 .* + 0090 08900890 00c00080 00c00080 00c00080 .* diff --git a/gas/testsuite/gas/nanomips/linkrelax.s b/gas/testsuite/gas/nanomips/linkrelax.s new file mode 100644 index 00000000000..2204ae1a9cb --- /dev/null +++ b/gas/testsuite/gas/nanomips/linkrelax.s @@ -0,0 +1,54 @@ + .text + .ifdef relaxmode + .linkrelax + .endif + .ent test1 +test1: + addiu $2, $8, 4 + .p2align 3 # no FILL, no MAX + b32 test2 + .align 3 # no FILL + b16 test2 + .balign 2 # no FILL, no MAX + nop + .set nolinkrelax + addiu $2, $3, 4 + .p2align 3 + b32 test2 + .align 3 + b16 test2 + .balign 8 + nop + .set linkrelax + nop + .end test1 + + .ent test2 + .align 3 +test2: + addiu $2, $2, 4 + .p2align 3,0xa # FILL but no MAX + nop + .p2align 3,0xab,5 # FILL and MAX, no padding will be done + nop32 + nop32 + .p2align 3,0xcd,6 # FILL and MAX, padded + nop32 + .p2alignw 3,0xabcd,6 # FILL hword and MAX + nop32 + .p2alignl 3,0xabcd1234,6 # FILL word and MAX + addiu $2, $3, 4 + .balign 16,0xb # FILL but no MAX + nop + .balign 16,0xba,5 # FILL and MAX, no padding will be done + nop + .balign 16,0xba,12 # FILL and MAX, padded + nop32 + .balignw 16,0xdcba,16 # FILL hword and MAX + nop32 + .balignl 16,0x4321dcba,16 # FILL word and MAX + nop + .word 0x8000c000 + .word 0x8000c000 + .word 0x8000c000 + .end test2 diff --git a/gas/testsuite/gas/nanomips/mcmodel-err.l b/gas/testsuite/gas/nanomips/mcmodel-err.l new file mode 100644 index 00000000000..936cf656ffd --- /dev/null +++ b/gas/testsuite/gas/nanomips/mcmodel-err.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*:1: Error: invalid memory model setting mcmodel=small +.*:2: Error: invalid memory model setting mcmodel=any diff --git a/gas/testsuite/gas/nanomips/mcmodel-err.s b/gas/testsuite/gas/nanomips/mcmodel-err.s new file mode 100644 index 00000000000..2584360f7e6 --- /dev/null +++ b/gas/testsuite/gas/nanomips/mcmodel-err.s @@ -0,0 +1,2 @@ +.set mcmodel=small +.set mcmodel=any diff --git a/gas/testsuite/gas/nanomips/mcmodel.l b/gas/testsuite/gas/nanomips/mcmodel.l new file mode 100644 index 00000000000..e69de29bb2d diff --git a/gas/testsuite/gas/nanomips/mcmodel.s b/gas/testsuite/gas/nanomips/mcmodel.s new file mode 100644 index 00000000000..8278bb7c87e --- /dev/null +++ b/gas/testsuite/gas/nanomips/mcmodel.s @@ -0,0 +1,3 @@ +.set mcmodel=medium +.set mcmodel=large +.set mcmodel=auto diff --git a/gas/testsuite/gas/nanomips/move.d b/gas/testsuite/gas/nanomips/move.d new file mode 100644 index 00000000000..073c1a957a8 --- /dev/null +++ b/gas/testsuite/gas/nanomips/move.d @@ -0,0 +1,14 @@ +#objdump: -dr -M reg-names=numeric -mnanomips:isa64r6 +#name: nanoMIPS insn32 move test +#as: -minsn32 + +# Check objdump's disassembly of the move mnenomic for addu and or. + +.*: +file format .*nanomips.* + +Disassembly of section .text: +0+ <[^>]+>: + 0: 201f 6a90 move \$13,\$31 + 4: 201f 6950 move \$13,\$31 + 8: 201f 6a90 move \$13,\$31 +#pass diff --git a/gas/testsuite/gas/nanomips/move.s b/gas/testsuite/gas/nanomips/move.s new file mode 100644 index 00000000000..a72bdca1bd4 --- /dev/null +++ b/gas/testsuite/gas/nanomips/move.s @@ -0,0 +1,3 @@ + move $13, $31 + addu $13, $31, $0 + or $13, $31, $0 diff --git a/gas/testsuite/gas/nanomips/mt-ase.d b/gas/testsuite/gas/nanomips/mt-ase.d new file mode 100644 index 00000000000..556c3afc931 --- /dev/null +++ b/gas/testsuite/gas/nanomips/mt-ase.d @@ -0,0 +1,651 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -M cp0-names=32r6 +#name: MIPS MT ASE for nanoMIPS + +# Check MIPS MT ASE for nanoMIPS Instruction Assembly + +.*: +file format .*nanomips.* + +[0-9A-F]+isassembly of section .text: +[0-9a-f]+ 2001 0ab0 dmt +[0-9a-f]+ 23e1 0ab0 dmt ra +[0-9a-f]+ 2000 0ab0 dvpe +[0-9a-f]+ 2020 0ab0 dvpe at +[0-9a-f]+ 2001 0eb0 emt +[0-9a-f]+ 2041 0eb0 emt t4 +[0-9a-f]+ 2000 0eb0 evpe +[0-9a-f]+ 2060 0eb0 evpe t5 +[0-9a-f]+ 20c5 2228 fork a0,a1,a2 +[0-9a-f]+ 2005 0268 yield a1 +[0-9a-f]+ 20c7 0268 yield a2,a3 +[0-9a-f]+ 20e8 0230 mftc0 a3,badvaddr +[0-9a-f]+ 2100 0230 mftc0 a4,index +[0-9a-f]+ 2100 0a30 mftc0 a4,mvpcontrol +[0-9a-f]+ 2100 1230 mftc0 a4,mvpconf0 +[0-9a-f]+ 2100 1a30 mftc0 a4,mvpconf1 +[0-9a-f]+ 2100 2230 mftc0 a4,vpcontrol +[0-9a-f]+ 2100 2a30 mftc0 a4,\$0,5 +[0-9a-f]+ 2100 3230 mftc0 a4,\$0,6 +[0-9a-f]+ 2100 3a30 mftc0 a4,\$0,7 +[0-9a-f]+ 2101 0230 mftc0 a4,random +[0-9a-f]+ 2101 0a30 mftc0 a4,vpecontrol +[0-9a-f]+ 2101 1230 mftc0 a4,vpeconf0 +[0-9a-f]+ 2101 1a30 mftc0 a4,vpeconf1 +[0-9a-f]+ 2101 2230 mftc0 a4,yqmask +[0-9a-f]+ 2101 2a30 mftc0 a4,vpeschedule +[0-9a-f]+ 2101 3230 mftc0 a4,vpeschefback +[0-9a-f]+ 2101 3a30 mftc0 a4,vpeopt +[0-9a-f]+ 2102 0230 mftc0 a4,entrylo0 +[0-9a-f]+ 2102 0a30 mftc0 a4,tcstatus +[0-9a-f]+ 2102 1230 mftc0 a4,tcbind +[0-9a-f]+ 2102 1a30 mftc0 a4,tcrestart +[0-9a-f]+ 2102 2230 mftc0 a4,tchalt +[0-9a-f]+ 2102 2a30 mftc0 a4,tccontext +[0-9a-f]+ 2102 3230 mftc0 a4,tcschedule +[0-9a-f]+ 2102 3a30 mftc0 a4,tcschefback +[0-9a-f]+ 2103 0230 mftc0 a4,entrylo1 +[0-9a-f]+ 2103 0a30 mftc0 a4,\$3,1 +[0-9a-f]+ 2103 1230 mftc0 a4,\$3,2 +[0-9a-f]+ 2103 1a30 mftc0 a4,\$3,3 +[0-9a-f]+ 2103 2230 mftc0 a4,\$3,4 +[0-9a-f]+ 2103 2a30 mftc0 a4,\$3,5 +[0-9a-f]+ 2103 3230 mftc0 a4,\$3,6 +[0-9a-f]+ 2103 3a30 mftc0 a4,tcopt +[0-9a-f]+ 2104 0230 mftc0 a4,context +[0-9a-f]+ 2104 0a30 mftc0 a4,contextconfig +[0-9a-f]+ 2104 1230 mftc0 a4,userlocal +[0-9a-f]+ 2104 1a30 mftc0 a4,xcontextconfig +[0-9a-f]+ 2104 2230 mftc0 a4,\$4,4 +[0-9a-f]+ 2104 2a30 mftc0 a4,\$4,5 +[0-9a-f]+ 2104 3230 mftc0 a4,\$4,6 +[0-9a-f]+ 2104 3a30 mftc0 a4,\$4,7 +[0-9a-f]+ 2105 0230 mftc0 a4,pagemask +[0-9a-f]+ 2105 0a30 mftc0 a4,pagegrain +[0-9a-f]+ 2105 1230 mftc0 a4,segctl0 +[0-9a-f]+ 2105 1a30 mftc0 a4,segctl1 +[0-9a-f]+ 2105 2230 mftc0 a4,segctl2 +[0-9a-f]+ 2105 2a30 mftc0 a4,pwbase +[0-9a-f]+ 2105 3230 mftc0 a4,pwfield +[0-9a-f]+ 2105 3a30 mftc0 a4,pwsize +[0-9a-f]+ 2106 0230 mftc0 a4,wired +[0-9a-f]+ 2106 0a30 mftc0 a4,srsconf0 +[0-9a-f]+ 2106 1230 mftc0 a4,srsconf1 +[0-9a-f]+ 2106 1a30 mftc0 a4,srsconf2 +[0-9a-f]+ 2106 2230 mftc0 a4,srsconf3 +[0-9a-f]+ 2106 2a30 mftc0 a4,srsconf4 +[0-9a-f]+ 2106 3230 mftc0 a4,pwctl +[0-9a-f]+ 2106 3a30 mftc0 a4,\$6,7 +[0-9a-f]+ 2107 0230 mftc0 a4,hwrena +[0-9a-f]+ 2107 0a30 mftc0 a4,\$7,1 +[0-9a-f]+ 2107 1230 mftc0 a4,\$7,2 +[0-9a-f]+ 2107 1a30 mftc0 a4,\$7,3 +[0-9a-f]+ 2107 2230 mftc0 a4,\$7,4 +[0-9a-f]+ 2107 2a30 mftc0 a4,\$7,5 +[0-9a-f]+ 2107 3230 mftc0 a4,\$7,6 +[0-9a-f]+ 2107 3a30 mftc0 a4,\$7,7 +[0-9a-f]+ 2108 0230 mftc0 a4,badvaddr +[0-9a-f]+ 2108 0a30 mftc0 a4,badinst +[0-9a-f]+ 2108 1230 mftc0 a4,badinstrp +[0-9a-f]+ 2108 1a30 mftc0 a4,\$8,3 +[0-9a-f]+ 2108 2230 mftc0 a4,\$8,4 +[0-9a-f]+ 2108 2a30 mftc0 a4,\$8,5 +[0-9a-f]+ 2108 3230 mftc0 a4,\$8,6 +[0-9a-f]+ 2108 3a30 mftc0 a4,\$8,7 +[0-9a-f]+ 2109 0230 mftc0 a4,count +[0-9a-f]+ 2109 0a30 mftc0 a4,\$9,1 +[0-9a-f]+ 2109 1230 mftc0 a4,\$9,2 +[0-9a-f]+ 2109 1a30 mftc0 a4,\$9,3 +[0-9a-f]+ 2109 2230 mftc0 a4,\$9,4 +[0-9a-f]+ 2109 2a30 mftc0 a4,\$9,5 +[0-9a-f]+ 2109 3230 mftc0 a4,\$9,6 +[0-9a-f]+ 2109 3a30 mftc0 a4,\$9,7 +[0-9a-f]+ 210a 0230 mftc0 a4,entryhi +[0-9a-f]+ 210a 0a30 mftc0 a4,\$10,1 +[0-9a-f]+ 210a 1230 mftc0 a4,\$10,2 +[0-9a-f]+ 210a 1a30 mftc0 a4,\$10,3 +[0-9a-f]+ 210a 2230 mftc0 a4,guestctl1 +[0-9a-f]+ 210a 2a30 mftc0 a4,guestctl2 +[0-9a-f]+ 210a 3230 mftc0 a4,guestctl3 +[0-9a-f]+ 210a 3a30 mftc0 a4,\$10,7 +[0-9a-f]+ 210b 0230 mftc0 a4,compare +[0-9a-f]+ 210b 0a30 mftc0 a4,\$11,1 +[0-9a-f]+ 210b 1230 mftc0 a4,\$11,2 +[0-9a-f]+ 210b 1a30 mftc0 a4,\$11,3 +[0-9a-f]+ 210b 2230 mftc0 a4,guestctl0ext +[0-9a-f]+ 210b 2a30 mftc0 a4,\$11,5 +[0-9a-f]+ 210b 3230 mftc0 a4,\$11,6 +[0-9a-f]+ 210b 3a30 mftc0 a4,\$11,7 +[0-9a-f]+ 210c 0230 mftc0 a4,status +[0-9a-f]+ 210c 0a30 mftc0 a4,intctl +[0-9a-f]+ 210c 1230 mftc0 a4,srsctl +[0-9a-f]+ 210c 1a30 mftc0 a4,srsmap +[0-9a-f]+ 210c 2230 mftc0 a4,view_ipl +[0-9a-f]+ 210c 2a30 mftc0 a4,srsmap2 +[0-9a-f]+ 210c 3230 mftc0 a4,guestctl0 +[0-9a-f]+ 210c 3a30 mftc0 a4,gtoffset +[0-9a-f]+ 210d 0230 mftc0 a4,cause +[0-9a-f]+ 210d 0a30 mftc0 a4,\$13,1 +[0-9a-f]+ 210d 1230 mftc0 a4,\$13,2 +[0-9a-f]+ 210d 1a30 mftc0 a4,\$13,3 +[0-9a-f]+ 210d 2230 mftc0 a4,view_ripl +[0-9a-f]+ 210d 2a30 mftc0 a4,nestedexc +[0-9a-f]+ 210d 3230 mftc0 a4,\$13,6 +[0-9a-f]+ 210d 3a30 mftc0 a4,\$13,7 +[0-9a-f]+ 210e 0230 mftc0 a4,epc +[0-9a-f]+ 210e 0a30 mftc0 a4,\$14,1 +[0-9a-f]+ 210e 1230 mftc0 a4,nestedepc +[0-9a-f]+ 210e 1a30 mftc0 a4,\$14,3 +[0-9a-f]+ 210e 2230 mftc0 a4,\$14,4 +[0-9a-f]+ 210e 2a30 mftc0 a4,\$14,5 +[0-9a-f]+ 210e 3230 mftc0 a4,\$14,6 +[0-9a-f]+ 210e 3a30 mftc0 a4,\$14,7 +[0-9a-f]+ 210f 0230 mftc0 a4,prid +[0-9a-f]+ 210f 0a30 mftc0 a4,ebase +[0-9a-f]+ 210f 1230 mftc0 a4,cdmmbase +[0-9a-f]+ 210f 1a30 mftc0 a4,cmgcrbase +[0-9a-f]+ 210f 2230 mftc0 a4,\$15,4 +[0-9a-f]+ 210f 2a30 mftc0 a4,\$15,5 +[0-9a-f]+ 210f 3230 mftc0 a4,\$15,6 +[0-9a-f]+ 210f 3a30 mftc0 a4,\$15,7 +[0-9a-f]+ 2110 0230 mftc0 a4,config +[0-9a-f]+ 2110 0a30 mftc0 a4,config1 +[0-9a-f]+ 2110 1230 mftc0 a4,config2 +[0-9a-f]+ 2110 1a30 mftc0 a4,config3 +[0-9a-f]+ 2110 2230 mftc0 a4,config4 +[0-9a-f]+ 2110 2a30 mftc0 a4,config5 +[0-9a-f]+ 2110 3230 mftc0 a4,\$16,6 +[0-9a-f]+ 2110 3a30 mftc0 a4,\$16,7 +[0-9a-f]+ 2111 0230 mftc0 a4,lladdr +[0-9a-f]+ 2111 0a30 mftc0 a4,\$17,1 +[0-9a-f]+ 2111 1230 mftc0 a4,\$17,2 +[0-9a-f]+ 2111 1a30 mftc0 a4,\$17,3 +[0-9a-f]+ 2111 2230 mftc0 a4,\$17,4 +[0-9a-f]+ 2111 2a30 mftc0 a4,\$17,5 +[0-9a-f]+ 2111 3230 mftc0 a4,\$17,6 +[0-9a-f]+ 2111 3a30 mftc0 a4,\$17,7 +[0-9a-f]+ 2112 0230 mftc0 a4,watchlo,0 +[0-9a-f]+ 2112 0a30 mftc0 a4,watchlo,1 +[0-9a-f]+ 2112 1230 mftc0 a4,watchlo,2 +[0-9a-f]+ 2112 1a30 mftc0 a4,watchlo,3 +[0-9a-f]+ 2112 2230 mftc0 a4,watchlo,4 +[0-9a-f]+ 2112 2a30 mftc0 a4,watchlo,5 +[0-9a-f]+ 2112 3230 mftc0 a4,watchlo,6 +[0-9a-f]+ 2112 3a30 mftc0 a4,watchlo,7 +[0-9a-f]+ 2113 0230 mftc0 a4,watchhi,0 +[0-9a-f]+ 2113 0a30 mftc0 a4,watchhi,1 +[0-9a-f]+ 2113 1230 mftc0 a4,watchhi,2 +[0-9a-f]+ 2113 1a30 mftc0 a4,watchhi,3 +[0-9a-f]+ 2113 2230 mftc0 a4,watchhi,4 +[0-9a-f]+ 2113 2a30 mftc0 a4,watchhi,5 +[0-9a-f]+ 2113 3230 mftc0 a4,watchhi,6 +[0-9a-f]+ 2113 3a30 mftc0 a4,watchhi,7 +[0-9a-f]+ 2114 0230 mftc0 a4,xcontext +[0-9a-f]+ 2114 0a30 mftc0 a4,\$20,1 +[0-9a-f]+ 2114 1230 mftc0 a4,\$20,2 +[0-9a-f]+ 2114 1a30 mftc0 a4,\$20,3 +[0-9a-f]+ 2114 2230 mftc0 a4,\$20,4 +[0-9a-f]+ 2114 2a30 mftc0 a4,\$20,5 +[0-9a-f]+ 2114 3230 mftc0 a4,\$20,6 +[0-9a-f]+ 2114 3a30 mftc0 a4,\$20,7 +[0-9a-f]+ 2115 0230 mftc0 a4,\$21 +[0-9a-f]+ 2115 0a30 mftc0 a4,\$21,1 +[0-9a-f]+ 2115 1230 mftc0 a4,\$21,2 +[0-9a-f]+ 2115 1a30 mftc0 a4,\$21,3 +[0-9a-f]+ 2115 2230 mftc0 a4,\$21,4 +[0-9a-f]+ 2115 2a30 mftc0 a4,\$21,5 +[0-9a-f]+ 2115 3230 mftc0 a4,\$21,6 +[0-9a-f]+ 2115 3a30 mftc0 a4,\$21,7 +[0-9a-f]+ 2116 0230 mftc0 a4,\$22 +[0-9a-f]+ 2116 0a30 mftc0 a4,\$22,1 +[0-9a-f]+ 2116 1230 mftc0 a4,\$22,2 +[0-9a-f]+ 2116 1a30 mftc0 a4,\$22,3 +[0-9a-f]+ 2116 2230 mftc0 a4,\$22,4 +[0-9a-f]+ 2116 2a30 mftc0 a4,\$22,5 +[0-9a-f]+ 2116 3230 mftc0 a4,\$22,6 +[0-9a-f]+ 2116 3a30 mftc0 a4,\$22,7 +[0-9a-f]+ 2117 0230 mftc0 a4,debug +[0-9a-f]+ 2117 0a30 mftc0 a4,tracecontrol +[0-9a-f]+ 2117 1230 mftc0 a4,tracecontrol2 +[0-9a-f]+ 2117 1a30 mftc0 a4,usertracedata1 +[0-9a-f]+ 2117 2230 mftc0 a4,traceibpc +[0-9a-f]+ 2117 2a30 mftc0 a4,tracedbpc +[0-9a-f]+ 2117 3230 mftc0 a4,debug2 +[0-9a-f]+ 2117 3a30 mftc0 a4,\$23,7 +[0-9a-f]+ 2118 0230 mftc0 a4,depc +[0-9a-f]+ 2118 0a30 mftc0 a4,\$24,1 +[0-9a-f]+ 2118 1230 mftc0 a4,tracecontrol3 +[0-9a-f]+ 2118 1a30 mftc0 a4,usertracedata2 +[0-9a-f]+ 2118 2230 mftc0 a4,\$24,4 +[0-9a-f]+ 2118 2a30 mftc0 a4,\$24,5 +[0-9a-f]+ 2118 3230 mftc0 a4,\$24,6 +[0-9a-f]+ 2118 3a30 mftc0 a4,\$24,7 +[0-9a-f]+ 2119 0230 mftc0 a4,perfctl,0 +[0-9a-f]+ 2119 0a30 mftc0 a4,perfcnt,1 +[0-9a-f]+ 2119 1230 mftc0 a4,perfctl,2 +[0-9a-f]+ 2119 1a30 mftc0 a4,perfcnt,3 +[0-9a-f]+ 2119 2230 mftc0 a4,perfctl,4 +[0-9a-f]+ 2119 2a30 mftc0 a4,perfcnt,5 +[0-9a-f]+ 2119 3230 mftc0 a4,perfctl,6 +[0-9a-f]+ 2119 3a30 mftc0 a4,perfcnt,7 +[0-9a-f]+ 211a 0230 mftc0 a4,errctl +[0-9a-f]+ 211a 0a30 mftc0 a4,\$26,1 +[0-9a-f]+ 211a 1230 mftc0 a4,\$26,2 +[0-9a-f]+ 211a 1a30 mftc0 a4,\$26,3 +[0-9a-f]+ 211a 2230 mftc0 a4,\$26,4 +[0-9a-f]+ 211a 2a30 mftc0 a4,\$26,5 +[0-9a-f]+ 211a 3230 mftc0 a4,\$26,6 +[0-9a-f]+ 211a 3a30 mftc0 a4,\$26,7 +[0-9a-f]+ 211b 0230 mftc0 a4,cacheerr +[0-9a-f]+ 211b 0a30 mftc0 a4,\$27,1 +[0-9a-f]+ 211b 1230 mftc0 a4,\$27,2 +[0-9a-f]+ 211b 1a30 mftc0 a4,\$27,3 +[0-9a-f]+ 211b 2230 mftc0 a4,\$27,4 +[0-9a-f]+ 211b 2a30 mftc0 a4,\$27,5 +[0-9a-f]+ 211b 3230 mftc0 a4,\$27,6 +[0-9a-f]+ 211b 3a30 mftc0 a4,\$27,7 +[0-9a-f]+ 211c 0230 mftc0 a4,taglo,0 +[0-9a-f]+ 211c 0a30 mftc0 a4,datalo,1 +[0-9a-f]+ 211c 1230 mftc0 a4,taglo,2 +[0-9a-f]+ 211c 1a30 mftc0 a4,datalo,3 +[0-9a-f]+ 211c 2230 mftc0 a4,taglo,4 +[0-9a-f]+ 211c 2a30 mftc0 a4,datalo,5 +[0-9a-f]+ 211c 3230 mftc0 a4,taglo,6 +[0-9a-f]+ 211c 3a30 mftc0 a4,datalo,7 +[0-9a-f]+ 211d 0230 mftc0 a4,taghi,0 +[0-9a-f]+ 211d 0a30 mftc0 a4,datahi,1 +[0-9a-f]+ 211d 1230 mftc0 a4,taghi,2 +[0-9a-f]+ 211d 1a30 mftc0 a4,datahi,3 +[0-9a-f]+ 211d 2230 mftc0 a4,taghi,4 +[0-9a-f]+ 211d 2a30 mftc0 a4,datahi,5 +[0-9a-f]+ 211d 3230 mftc0 a4,taghi,6 +[0-9a-f]+ 211d 3a30 mftc0 a4,datahi,7 +[0-9a-f]+ 211e 0230 mftc0 a4,errorepc +[0-9a-f]+ 211e 0a30 mftc0 a4,\$30,1 +[0-9a-f]+ 211e 1230 mftc0 a4,\$30,2 +[0-9a-f]+ 211e 1a30 mftc0 a4,\$30,3 +[0-9a-f]+ 211e 2230 mftc0 a4,\$30,4 +[0-9a-f]+ 211e 2a30 mftc0 a4,\$30,5 +[0-9a-f]+ 211e 3230 mftc0 a4,\$30,6 +[0-9a-f]+ 211e 3a30 mftc0 a4,\$30,7 +[0-9a-f]+ 211f 0230 mftc0 a4,desave +[0-9a-f]+ 211f 0a30 mftc0 a4,\$31,1 +[0-9a-f]+ 211f 1230 mftc0 a4,kscratch1 +[0-9a-f]+ 211f 1a30 mftc0 a4,kscratch2 +[0-9a-f]+ 211f 2230 mftc0 a4,kscratch3 +[0-9a-f]+ 211f 2a30 mftc0 a4,kscratch4 +[0-9a-f]+ 211f 3230 mftc0 a4,kscratch5 +[0-9a-f]+ 211f 3a30 mftc0 a4,kscratch6 +[0-9a-f]+ 212a 0630 mftgpr a5,a6 +[0-9a-f]+ 2140 0e30 mftlo a6 +[0-9a-f]+ 2160 0e30 mftlo a7 +[0-9a-f]+ 2181 0e30 mfthi t0 +[0-9a-f]+ 21a5 0e30 mfthi t1,\$ac1 +#00000444 21c2 0e30 mftacx t2 +#00000448 21ea 0e30 mftacx t3,\$ac2 +[0-9a-f]+ 2210 0e30 mftdsp s0 +[0-9a-f]+ 2232 1630 mftc1 s1,\$f18 +[0-9a-f]+ 2253 1630 mftc1 s2,\$f19 +[0-9a-f]+ 2274 1638 mfthc1 s3,\$f20 +[0-9a-f]+ 2296 1638 mfthc1 s4,\$f22 +[0-9a-f]+ 22b6 1e30 cftc1 s5,\$tcopt +[0-9a-f]+ 22d7 1e30 cftc1 s6,\$context +[0-9a-f]+ 22f8 2630 mftc2 s7,\$24 +[0-9a-f]+ 2319 2638 mfthc2 t8,\$25 +[0-9a-f]+ 233a 2e30 cftc2 t9,\$26 +[0-9a-f]+ 235b 0270 mttc0 k0,cacheerr +[0-9a-f]+ 2360 0270 mttc0 k1,index +[0-9a-f]+ 2360 0a70 mttc0 k1,mvpcontrol +[0-9a-f]+ 2360 1270 mttc0 k1,mvpconf0 +[0-9a-f]+ 2360 1a70 mttc0 k1,mvpconf1 +[0-9a-f]+ 2360 2270 mttc0 k1,vpcontrol +[0-9a-f]+ 2360 2a70 mttc0 k1,\$0,5 +[0-9a-f]+ 2360 3270 mttc0 k1,\$0,6 +[0-9a-f]+ 2360 3a70 mttc0 k1,\$0,7 +[0-9a-f]+ 2361 0270 mttc0 k1,random +[0-9a-f]+ 2361 0a70 mttc0 k1,vpecontrol +[0-9a-f]+ 2361 1270 mttc0 k1,vpeconf0 +[0-9a-f]+ 2361 1a70 mttc0 k1,vpeconf1 +[0-9a-f]+ 2361 2270 mttc0 k1,yqmask +[0-9a-f]+ 2361 2a70 mttc0 k1,vpeschedule +[0-9a-f]+ 2361 3270 mttc0 k1,vpeschefback +[0-9a-f]+ 2361 3a70 mttc0 k1,vpeopt +[0-9a-f]+ 2362 0270 mttc0 k1,entrylo0 +[0-9a-f]+ 2362 0a70 mttc0 k1,tcstatus +[0-9a-f]+ 2362 1270 mttc0 k1,tcbind +[0-9a-f]+ 2362 1a70 mttc0 k1,tcrestart +[0-9a-f]+ 2362 2270 mttc0 k1,tchalt +[0-9a-f]+ 2362 2a70 mttc0 k1,tccontext +[0-9a-f]+ 2362 3270 mttc0 k1,tcschedule +[0-9a-f]+ 2362 3a70 mttc0 k1,tcschefback +[0-9a-f]+ 2363 0270 mttc0 k1,entrylo1 +[0-9a-f]+ 2363 0a70 mttc0 k1,\$3,1 +[0-9a-f]+ 2363 1270 mttc0 k1,\$3,2 +[0-9a-f]+ 2363 1a70 mttc0 k1,\$3,3 +[0-9a-f]+ 2363 2270 mttc0 k1,\$3,4 +[0-9a-f]+ 2363 2a70 mttc0 k1,\$3,5 +[0-9a-f]+ 2363 3270 mttc0 k1,\$3,6 +[0-9a-f]+ 2363 3a70 mttc0 k1,tcopt +[0-9a-f]+ 2364 0270 mttc0 k1,context +[0-9a-f]+ 2364 0a70 mttc0 k1,contextconfig +[0-9a-f]+ 2364 1270 mttc0 k1,userlocal +[0-9a-f]+ 2364 1a70 mttc0 k1,xcontextconfig +[0-9a-f]+ 2364 2270 mttc0 k1,\$4,4 +[0-9a-f]+ 2364 2a70 mttc0 k1,\$4,5 +[0-9a-f]+ 2364 3270 mttc0 k1,\$4,6 +[0-9a-f]+ 2364 3a70 mttc0 k1,\$4,7 +[0-9a-f]+ 2365 0270 mttc0 k1,pagemask +[0-9a-f]+ 2365 0a70 mttc0 k1,pagegrain +[0-9a-f]+ 2365 1270 mttc0 k1,segctl0 +[0-9a-f]+ 2365 1a70 mttc0 k1,segctl1 +[0-9a-f]+ 2365 2270 mttc0 k1,segctl2 +[0-9a-f]+ 2365 2a70 mttc0 k1,pwbase +[0-9a-f]+ 2365 3270 mttc0 k1,pwfield +[0-9a-f]+ 2365 3a70 mttc0 k1,pwsize +[0-9a-f]+ 2366 0270 mttc0 k1,wired +[0-9a-f]+ 2366 0a70 mttc0 k1,srsconf0 +[0-9a-f]+ 2366 1270 mttc0 k1,srsconf1 +[0-9a-f]+ 2366 1a70 mttc0 k1,srsconf2 +[0-9a-f]+ 2366 2270 mttc0 k1,srsconf3 +[0-9a-f]+ 2366 2a70 mttc0 k1,srsconf4 +[0-9a-f]+ 2366 3270 mttc0 k1,pwctl +[0-9a-f]+ 2366 3a70 mttc0 k1,\$6,7 +[0-9a-f]+ 2367 0270 mttc0 k1,hwrena +[0-9a-f]+ 2367 0a70 mttc0 k1,\$7,1 +[0-9a-f]+ 2367 1270 mttc0 k1,\$7,2 +[0-9a-f]+ 2367 1a70 mttc0 k1,\$7,3 +[0-9a-f]+ 2367 2270 mttc0 k1,\$7,4 +[0-9a-f]+ 2367 2a70 mttc0 k1,\$7,5 +[0-9a-f]+ 2367 3270 mttc0 k1,\$7,6 +[0-9a-f]+ 2367 3a70 mttc0 k1,\$7,7 +[0-9a-f]+ 2368 0270 mttc0 k1,badvaddr +[0-9a-f]+ 2368 0a70 mttc0 k1,badinst +[0-9a-f]+ 2368 1270 mttc0 k1,badinstrp +[0-9a-f]+ 2368 1a70 mttc0 k1,\$8,3 +[0-9a-f]+ 2368 2270 mttc0 k1,\$8,4 +[0-9a-f]+ 2368 2a70 mttc0 k1,\$8,5 +[0-9a-f]+ 2368 3270 mttc0 k1,\$8,6 +[0-9a-f]+ 2368 3a70 mttc0 k1,\$8,7 +[0-9a-f]+ 2369 0270 mttc0 k1,count +[0-9a-f]+ 2369 0a70 mttc0 k1,\$9,1 +[0-9a-f]+ 2369 1270 mttc0 k1,\$9,2 +[0-9a-f]+ 2369 1a70 mttc0 k1,\$9,3 +[0-9a-f]+ 2369 2270 mttc0 k1,\$9,4 +[0-9a-f]+ 2369 2a70 mttc0 k1,\$9,5 +[0-9a-f]+ 2369 3270 mttc0 k1,\$9,6 +[0-9a-f]+ 2369 3a70 mttc0 k1,\$9,7 +[0-9a-f]+ 236a 0270 mttc0 k1,entryhi +[0-9a-f]+ 236a 0a70 mttc0 k1,\$10,1 +[0-9a-f]+ 236a 1270 mttc0 k1,\$10,2 +[0-9a-f]+ 236a 1a70 mttc0 k1,\$10,3 +[0-9a-f]+ 236a 2270 mttc0 k1,guestctl1 +[0-9a-f]+ 236a 2a70 mttc0 k1,guestctl2 +[0-9a-f]+ 236a 3270 mttc0 k1,guestctl3 +[0-9a-f]+ 236a 3a70 mttc0 k1,\$10,7 +[0-9a-f]+ 236b 0270 mttc0 k1,compare +[0-9a-f]+ 236b 0a70 mttc0 k1,\$11,1 +[0-9a-f]+ 236b 1270 mttc0 k1,\$11,2 +[0-9a-f]+ 236b 1a70 mttc0 k1,\$11,3 +[0-9a-f]+ 236b 2270 mttc0 k1,guestctl0ext +[0-9a-f]+ 236b 2a70 mttc0 k1,\$11,5 +[0-9a-f]+ 236b 3270 mttc0 k1,\$11,6 +[0-9a-f]+ 236b 3a70 mttc0 k1,\$11,7 +[0-9a-f]+ 236c 0270 mttc0 k1,status +[0-9a-f]+ 236c 0a70 mttc0 k1,intctl +[0-9a-f]+ 236c 1270 mttc0 k1,srsctl +[0-9a-f]+ 236c 1a70 mttc0 k1,srsmap +[0-9a-f]+ 236c 2270 mttc0 k1,view_ipl +[0-9a-f]+ 236c 2a70 mttc0 k1,srsmap2 +[0-9a-f]+ 236c 3270 mttc0 k1,guestctl0 +[0-9a-f]+ 236c 3a70 mttc0 k1,gtoffset +[0-9a-f]+ 236d 0270 mttc0 k1,cause +[0-9a-f]+ 236d 0a70 mttc0 k1,\$13,1 +[0-9a-f]+ 236d 1270 mttc0 k1,\$13,2 +[0-9a-f]+ 236d 1a70 mttc0 k1,\$13,3 +[0-9a-f]+ 236d 2270 mttc0 k1,view_ripl +[0-9a-f]+ 236d 2a70 mttc0 k1,nestedexc +[0-9a-f]+ 236d 3270 mttc0 k1,\$13,6 +[0-9a-f]+ 236d 3a70 mttc0 k1,\$13,7 +[0-9a-f]+ 236e 0270 mttc0 k1,epc +[0-9a-f]+ 236e 0a70 mttc0 k1,\$14,1 +[0-9a-f]+ 236e 1270 mttc0 k1,nestedepc +[0-9a-f]+ 236e 1a70 mttc0 k1,\$14,3 +[0-9a-f]+ 236e 2270 mttc0 k1,\$14,4 +[0-9a-f]+ 236e 2a70 mttc0 k1,\$14,5 +[0-9a-f]+ 236e 3270 mttc0 k1,\$14,6 +[0-9a-f]+ 236e 3a70 mttc0 k1,\$14,7 +[0-9a-f]+ 236f 0270 mttc0 k1,prid +[0-9a-f]+ 236f 0a70 mttc0 k1,ebase +[0-9a-f]+ 236f 1270 mttc0 k1,cdmmbase +[0-9a-f]+ 236f 1a70 mttc0 k1,cmgcrbase +[0-9a-f]+ 236f 2270 mttc0 k1,\$15,4 +[0-9a-f]+ 236f 2a70 mttc0 k1,\$15,5 +[0-9a-f]+ 236f 3270 mttc0 k1,\$15,6 +[0-9a-f]+ 236f 3a70 mttc0 k1,\$15,7 +[0-9a-f]+ 2370 0270 mttc0 k1,config +[0-9a-f]+ 2370 0a70 mttc0 k1,config1 +[0-9a-f]+ 2370 1270 mttc0 k1,config2 +[0-9a-f]+ 2370 1a70 mttc0 k1,config3 +[0-9a-f]+ 2370 2270 mttc0 k1,config4 +[0-9a-f]+ 2370 2a70 mttc0 k1,config5 +[0-9a-f]+ 2370 3270 mttc0 k1,\$16,6 +[0-9a-f]+ 2370 3a70 mttc0 k1,\$16,7 +[0-9a-f]+ 2371 0270 mttc0 k1,lladdr +[0-9a-f]+ 2371 0a70 mttc0 k1,\$17,1 +[0-9a-f]+ 2371 1270 mttc0 k1,\$17,2 +[0-9a-f]+ 2371 1a70 mttc0 k1,\$17,3 +[0-9a-f]+ 2371 2270 mttc0 k1,\$17,4 +[0-9a-f]+ 2371 2a70 mttc0 k1,\$17,5 +[0-9a-f]+ 2371 3270 mttc0 k1,\$17,6 +[0-9a-f]+ 2371 3a70 mttc0 k1,\$17,7 +[0-9a-f]+ 2372 0270 mttc0 k1,watchlo,0 +[0-9a-f]+ 2372 0a70 mttc0 k1,watchlo,1 +[0-9a-f]+ 2372 1270 mttc0 k1,watchlo,2 +[0-9a-f]+ 2372 1a70 mttc0 k1,watchlo,3 +[0-9a-f]+ 2372 2270 mttc0 k1,watchlo,4 +[0-9a-f]+ 2372 2a70 mttc0 k1,watchlo,5 +[0-9a-f]+ 2372 3270 mttc0 k1,watchlo,6 +[0-9a-f]+ 2372 3a70 mttc0 k1,watchlo,7 +[0-9a-f]+ 2373 0270 mttc0 k1,watchhi,0 +[0-9a-f]+ 2373 0a70 mttc0 k1,watchhi,1 +[0-9a-f]+ 2373 1270 mttc0 k1,watchhi,2 +[0-9a-f]+ 2373 1a70 mttc0 k1,watchhi,3 +[0-9a-f]+ 2373 2270 mttc0 k1,watchhi,4 +[0-9a-f]+ 2373 2a70 mttc0 k1,watchhi,5 +[0-9a-f]+ 2373 3270 mttc0 k1,watchhi,6 +[0-9a-f]+ 2373 3a70 mttc0 k1,watchhi,7 +[0-9a-f]+ 2374 0270 mttc0 k1,xcontext +[0-9a-f]+ 2374 0a70 mttc0 k1,\$20,1 +[0-9a-f]+ 2374 1270 mttc0 k1,\$20,2 +[0-9a-f]+ 2374 1a70 mttc0 k1,\$20,3 +[0-9a-f]+ 2374 2270 mttc0 k1,\$20,4 +[0-9a-f]+ 2374 2a70 mttc0 k1,\$20,5 +[0-9a-f]+ 2374 3270 mttc0 k1,\$20,6 +[0-9a-f]+ 2374 3a70 mttc0 k1,\$20,7 +[0-9a-f]+ 2375 0270 mttc0 k1,\$21 +[0-9a-f]+ 2375 0a70 mttc0 k1,\$21,1 +[0-9a-f]+ 2375 1270 mttc0 k1,\$21,2 +[0-9a-f]+ 2375 1a70 mttc0 k1,\$21,3 +[0-9a-f]+ 2375 2270 mttc0 k1,\$21,4 +[0-9a-f]+ 2375 2a70 mttc0 k1,\$21,5 +[0-9a-f]+ 2375 3270 mttc0 k1,\$21,6 +[0-9a-f]+ 2375 3a70 mttc0 k1,\$21,7 +[0-9a-f]+ 2376 0270 mttc0 k1,\$22 +[0-9a-f]+ 2376 0a70 mttc0 k1,\$22,1 +[0-9a-f]+ 2376 1270 mttc0 k1,\$22,2 +[0-9a-f]+ 2376 1a70 mttc0 k1,\$22,3 +[0-9a-f]+ 2376 2270 mttc0 k1,\$22,4 +[0-9a-f]+ 2376 2a70 mttc0 k1,\$22,5 +[0-9a-f]+ 2376 3270 mttc0 k1,\$22,6 +[0-9a-f]+ 2376 3a70 mttc0 k1,\$22,7 +[0-9a-f]+ 2377 0270 mttc0 k1,debug +[0-9a-f]+ 2377 0a70 mttc0 k1,tracecontrol +[0-9a-f]+ 2377 1270 mttc0 k1,tracecontrol2 +[0-9a-f]+ 2377 1a70 mttc0 k1,usertracedata1 +[0-9a-f]+ 2377 2270 mttc0 k1,traceibpc +[0-9a-f]+ 2377 2a70 mttc0 k1,tracedbpc +[0-9a-f]+ 2377 3270 mttc0 k1,debug2 +[0-9a-f]+ 2377 3a70 mttc0 k1,\$23,7 +[0-9a-f]+ 2378 0270 mttc0 k1,depc +[0-9a-f]+ 2378 0a70 mttc0 k1,\$24,1 +[0-9a-f]+ 2378 1270 mttc0 k1,tracecontrol3 +[0-9a-f]+ 2378 1a70 mttc0 k1,usertracedata2 +[0-9a-f]+ 2378 2270 mttc0 k1,\$24,4 +[0-9a-f]+ 2378 2a70 mttc0 k1,\$24,5 +[0-9a-f]+ 2378 3270 mttc0 k1,\$24,6 +[0-9a-f]+ 2378 3a70 mttc0 k1,\$24,7 +[0-9a-f]+ 2379 0270 mttc0 k1,perfctl,0 +[0-9a-f]+ 2379 0a70 mttc0 k1,perfcnt,1 +[0-9a-f]+ 2379 1270 mttc0 k1,perfctl,2 +[0-9a-f]+ 2379 1a70 mttc0 k1,perfcnt,3 +[0-9a-f]+ 2379 2270 mttc0 k1,perfctl,4 +[0-9a-f]+ 2379 2a70 mttc0 k1,perfcnt,5 +[0-9a-f]+ 2379 3270 mttc0 k1,perfctl,6 +[0-9a-f]+ 2379 3a70 mttc0 k1,perfcnt,7 +[0-9a-f]+ 237a 0270 mttc0 k1,errctl +[0-9a-f]+ 237a 0a70 mttc0 k1,\$26,1 +[0-9a-f]+ 237a 1270 mttc0 k1,\$26,2 +[0-9a-f]+ 237a 1a70 mttc0 k1,\$26,3 +[0-9a-f]+ 237a 2270 mttc0 k1,\$26,4 +[0-9a-f]+ 237a 2a70 mttc0 k1,\$26,5 +[0-9a-f]+ 237a 3270 mttc0 k1,\$26,6 +[0-9a-f]+ 237a 3a70 mttc0 k1,\$26,7 +[0-9a-f]+ 237b 0270 mttc0 k1,cacheerr +[0-9a-f]+ 237b 0a70 mttc0 k1,\$27,1 +[0-9a-f]+ 237b 1270 mttc0 k1,\$27,2 +[0-9a-f]+ 237b 1a70 mttc0 k1,\$27,3 +[0-9a-f]+ 237b 2270 mttc0 k1,\$27,4 +[0-9a-f]+ 237b 2a70 mttc0 k1,\$27,5 +[0-9a-f]+ 237b 3270 mttc0 k1,\$27,6 +[0-9a-f]+ 237b 3a70 mttc0 k1,\$27,7 +[0-9a-f]+ 237c 0270 mttc0 k1,taglo,0 +[0-9a-f]+ 237c 0a70 mttc0 k1,datalo,1 +[0-9a-f]+ 237c 1270 mttc0 k1,taglo,2 +[0-9a-f]+ 237c 1a70 mttc0 k1,datalo,3 +[0-9a-f]+ 237c 2270 mttc0 k1,taglo,4 +[0-9a-f]+ 237c 2a70 mttc0 k1,datalo,5 +[0-9a-f]+ 237c 3270 mttc0 k1,taglo,6 +[0-9a-f]+ 237c 3a70 mttc0 k1,datalo,7 +[0-9a-f]+ 237d 0270 mttc0 k1,taghi,0 +[0-9a-f]+ 237d 0a70 mttc0 k1,datahi,1 +[0-9a-f]+ 237d 1270 mttc0 k1,taghi,2 +[0-9a-f]+ 237d 1a70 mttc0 k1,datahi,3 +[0-9a-f]+ 237d 2270 mttc0 k1,taghi,4 +[0-9a-f]+ 237d 2a70 mttc0 k1,datahi,5 +[0-9a-f]+ 237d 3270 mttc0 k1,taghi,6 +[0-9a-f]+ 237d 3a70 mttc0 k1,datahi,7 +[0-9a-f]+ 237e 0270 mttc0 k1,errorepc +[0-9a-f]+ 237e 0a70 mttc0 k1,\$30,1 +[0-9a-f]+ 237e 1270 mttc0 k1,\$30,2 +[0-9a-f]+ 237e 1a70 mttc0 k1,\$30,3 +[0-9a-f]+ 237e 2270 mttc0 k1,\$30,4 +[0-9a-f]+ 237e 2a70 mttc0 k1,\$30,5 +[0-9a-f]+ 237e 3270 mttc0 k1,\$30,6 +[0-9a-f]+ 237e 3a70 mttc0 k1,\$30,7 +[0-9a-f]+ 237f 0270 mttc0 k1,desave +[0-9a-f]+ 237f 0a70 mttc0 k1,\$31,1 +[0-9a-f]+ 237f 1270 mttc0 k1,kscratch1 +[0-9a-f]+ 237f 1a70 mttc0 k1,kscratch2 +[0-9a-f]+ 237f 2270 mttc0 k1,kscratch3 +[0-9a-f]+ 237f 2a70 mttc0 k1,kscratch4 +[0-9a-f]+ 237f 3270 mttc0 k1,kscratch5 +[0-9a-f]+ 237f 3a70 mttc0 k1,kscratch6 +[0-9a-f]+ 239d 0670 mttgpr gp,sp +[0-9a-f]+ 23a0 0e70 mttlo sp +[0-9a-f]+ 23cc 0e70 mttlo fp,\$ac3 +[0-9a-f]+ 23e1 0e70 mtthi ra +[0-9a-f]+ 2001 0e70 mtthi zero +#0000088c 2041 0e70 mttacx at +#00000890 20c2 0e70 mttacx t4,\$ac1 +[0-9a-f]+ 2070 0e70 mttdsp t5 +[0-9a-f]+ 2085 1670 mttc1 a0,\$f5 +[0-9a-f]+ 20a6 1670 mttc1 a1,\$f6 +[0-9a-f]+ 20c8 1678 mtthc1 a2,\$f8 +[0-9a-f]+ 20ea 1678 mtthc1 a3,\$f10 +[0-9a-f]+ 2109 1e70 cttc1 a4,\$yqmask +[0-9a-f]+ 212a 1e70 cttc1 a5,\$vpeschedule +[0-9a-f]+ 214b 2670 mttc2 a6,\$11 +[0-9a-f]+ 216c 2678 mtthc2 a7,\$12 +[0-9a-f]+ 218d 2e70 cttc2 t0,\$13 +[0-9a-f]+ 21ae 0230 mftc0 t1,epc +[0-9a-f]+ 21ae 0a30 mftc0 t1,\$14,1 +[0-9a-f]+ 21ae 1230 mftc0 t1,nestedepc +[0-9a-f]+ 21ae 1a30 mftc0 t1,\$14,3 +[0-9a-f]+ 21ae 2230 mftc0 t1,\$14,4 +[0-9a-f]+ 21ae 2a30 mftc0 t1,\$14,5 +[0-9a-f]+ 21ae 3230 mftc0 t1,\$14,6 +[0-9a-f]+ 21ae 3a30 mftc0 t1,\$14,7 +[0-9a-f]+ 21ae 0238 mfthc0 t1,epc +[0-9a-f]+ 21ae 0a38 mfthc0 t1,\$14,1 +[0-9a-f]+ 21ae 1238 mfthc0 t1,nestedepc +[0-9a-f]+ 21ae 1a38 mfthc0 t1,\$14,3 +[0-9a-f]+ 21ae 2238 mfthc0 t1,\$14,4 +[0-9a-f]+ 21ae 2a38 mfthc0 t1,\$14,5 +[0-9a-f]+ 21ae 3238 mfthc0 t1,\$14,6 +[0-9a-f]+ 21ae 3a38 mfthc0 t1,\$14,7 +[0-9a-f]+ 21ae 0630 mftgpr t1,t2 +[0-9a-f]+ 21ae 0e30 mftr t1,t2,1,1,0 +[0-9a-f]+ 21ae 1630 mftc1 t1,\$f14 +[0-9a-f]+ 21ae 1e30 cftc1 t1,\$tcstatus +[0-9a-f]+ 21ae 2630 mftc2 t1,\$14 +[0-9a-f]+ 21ae 2e30 cftc2 t1,\$14 +[0-9a-f]+ 21ae 3630 mftr t1,t2,1,6,0 +[0-9a-f]+ 21ae 3e30 mftr t1,t2,1,7,0 +[0-9a-f]+ 21ae 0638 mftr t1,t2,1,0,1 +[0-9a-f]+ 21ae 0e38 mftr t1,t2,1,1,1 +[0-9a-f]+ 21ae 1638 mfthc1 t1,\$f14 +[0-9a-f]+ 21ae 1e38 mftr t1,t2,1,3,1 +[0-9a-f]+ 21ae 2638 mfthc2 t1,\$14 +[0-9a-f]+ 21ae 2e38 mftr t1,t2,1,5,1 +[0-9a-f]+ 21ae 3638 mftr t1,t2,1,6,1 +[0-9a-f]+ 21ae 3e38 mftr t1,t2,1,7,1 +[0-9a-f]+ 21ae 0270 mttc0 t1,epc +[0-9a-f]+ 21ae 0a70 mttc0 t1,\$14,1 +[0-9a-f]+ 21ae 1270 mttc0 t1,nestedepc +[0-9a-f]+ 21ae 1a70 mttc0 t1,\$14,3 +[0-9a-f]+ 21ae 2270 mttc0 t1,\$14,4 +[0-9a-f]+ 21ae 2a70 mttc0 t1,\$14,5 +[0-9a-f]+ 21ae 3270 mttc0 t1,\$14,6 +[0-9a-f]+ 21ae 3a70 mttc0 t1,\$14,7 +[0-9a-f]+ 21ae 0278 mtthc0 t1,epc +[0-9a-f]+ 21ae 0a78 mtthc0 t1,\$14,1 +[0-9a-f]+ 21ae 1278 mtthc0 t1,nestedepc +[0-9a-f]+ 21ae 1a78 mtthc0 t1,\$14,3 +[0-9a-f]+ 21ae 2278 mtthc0 t1,\$14,4 +[0-9a-f]+ 21ae 2a78 mtthc0 t1,\$14,5 +[0-9a-f]+ 21ae 3278 mtthc0 t1,\$14,6 +[0-9a-f]+ 21ae 3a78 mtthc0 t1,\$14,7 +[0-9a-f]+ 21ae 0670 mttgpr t1,t2 +[0-9a-f]+ 21ae 0e70 mttr t1,t2,1,1,0 +[0-9a-f]+ 21ae 1670 mttc1 t1,\$f14 +[0-9a-f]+ 21ae 1e70 cttc1 t1,\$tcstatus +[0-9a-f]+ 21ae 2670 mttc2 t1,\$14 +[0-9a-f]+ 21ae 2e70 cttc2 t1,\$14 +[0-9a-f]+ 21ae 3670 mttr t1,t2,1,6,0 +[0-9a-f]+ 21ae 3e70 mttr t1,t2,1,7,0 +[0-9a-f]+ 21ae 0678 mttr t1,t2,1,0,1 +[0-9a-f]+ 21ae 0e78 mttr t1,t2,1,1,1 +[0-9a-f]+ 21ae 1678 mtthc1 t1,\$f14 +[0-9a-f]+ 21ae 1e78 mttr t1,t2,1,3,1 +[0-9a-f]+ 21ae 2678 mtthc2 t1,\$14 +[0-9a-f]+ 21ae 2e78 mttr t1,t2,1,5,1 +[0-9a-f]+ 21ae 3678 mttr t1,t2,1,6,1 +[0-9a-f]+ 21ae 3e78 mttr t1,t2,1,7,1 +[0-9a-f]+ 8000 c005 pause +[0-9a-f]+ 20e8 0238 mfthc0 a3,badvaddr +[0-9a-f]+ 2100 0238 mfthc0 a4,index +[0-9a-f]+ 2100 0a38 mfthc0 a4,mvpcontrol +[0-9a-f]+ 2100 1238 mfthc0 a4,mvpconf0 +[0-9a-f]+ 2100 1a38 mfthc0 a4,mvpconf1 +[0-9a-f]+ 2100 2238 mfthc0 a4,vpcontrol +[0-9a-f]+ 2100 2a38 mfthc0 a4,\$0,5 +[0-9a-f]+ 2100 3238 mfthc0 a4,\$0,6 +[0-9a-f]+ 2100 3a38 mfthc0 a4,\$0,7 +[0-9a-f]+ 235b 0278 mtthc0 k0,cacheerr +[0-9a-f]+ 2360 0278 mtthc0 k1,index +[0-9a-f]+ 2360 0a78 mtthc0 k1,mvpcontrol +[0-9a-f]+ 2360 1278 mtthc0 k1,mvpconf0 +[0-9a-f]+ 2360 1a78 mtthc0 k1,mvpconf1 +[0-9a-f]+ 2360 2278 mtthc0 k1,vpcontrol +[0-9a-f]+ 2360 2a78 mtthc0 k1,\$0,5 +[0-9a-f]+ 2360 3278 mtthc0 k1,\$0,6 +[0-9a-f]+ 2360 3a78 mtthc0 k1,\$0,7 + ... diff --git a/gas/testsuite/gas/nanomips/mt-ase.s b/gas/testsuite/gas/nanomips/mt-ase.s new file mode 100644 index 00000000000..e754b34c504 --- /dev/null +++ b/gas/testsuite/gas/nanomips/mt-ase.s @@ -0,0 +1,656 @@ +# source file to test assembly of MIPS MT ASE for MIPS32 instructions + + .set noreorder + .set noat + + .text +text_label: + + dmt + dmt $31 + dvpe + dvpe $1 + emt + emt $2 + evpe + evpe $3 + fork $4,$5,$6 + yield $5 + yield $6,$7 + mftc0 $7,$8 + mftc0 $8,$0,0 + mftc0 $8,$0,1 + mftc0 $8,$0,2 + mftc0 $8,$0,3 + mftc0 $8,$0,4 + mftc0 $8,$0,5 + mftc0 $8,$0,6 + mftc0 $8,$0,7 + mftc0 $8,$1,0 + mftc0 $8,$1,1 + mftc0 $8,$1,2 + mftc0 $8,$1,3 + mftc0 $8,$1,4 + mftc0 $8,$1,5 + mftc0 $8,$1,6 + mftc0 $8,$1,7 + mftc0 $8,$2,0 + mftc0 $8,$2,1 + mftc0 $8,$2,2 + mftc0 $8,$2,3 + mftc0 $8,$2,4 + mftc0 $8,$2,5 + mftc0 $8,$2,6 + mftc0 $8,$2,7 + mftc0 $8,$3,0 + mftc0 $8,$3,1 + mftc0 $8,$3,2 + mftc0 $8,$3,3 + mftc0 $8,$3,4 + mftc0 $8,$3,5 + mftc0 $8,$3,6 + mftc0 $8,$3,7 + mftc0 $8,$4,0 + mftc0 $8,$4,1 + mftc0 $8,$4,2 + mftc0 $8,$4,3 + mftc0 $8,$4,4 + mftc0 $8,$4,5 + mftc0 $8,$4,6 + mftc0 $8,$4,7 + mftc0 $8,$5,0 + mftc0 $8,$5,1 + mftc0 $8,$5,2 + mftc0 $8,$5,3 + mftc0 $8,$5,4 + mftc0 $8,$5,5 + mftc0 $8,$5,6 + mftc0 $8,$5,7 + mftc0 $8,$6,0 + mftc0 $8,$6,1 + mftc0 $8,$6,2 + mftc0 $8,$6,3 + mftc0 $8,$6,4 + mftc0 $8,$6,5 + mftc0 $8,$6,6 + mftc0 $8,$6,7 + mftc0 $8,$7,0 + mftc0 $8,$7,1 + mftc0 $8,$7,2 + mftc0 $8,$7,3 + mftc0 $8,$7,4 + mftc0 $8,$7,5 + mftc0 $8,$7,6 + mftc0 $8,$7,7 + mftc0 $8,$8,0 + mftc0 $8,$8,1 + mftc0 $8,$8,2 + mftc0 $8,$8,3 + mftc0 $8,$8,4 + mftc0 $8,$8,5 + mftc0 $8,$8,6 + mftc0 $8,$8,7 + mftc0 $8,$9,0 + mftc0 $8,$9,1 + mftc0 $8,$9,2 + mftc0 $8,$9,3 + mftc0 $8,$9,4 + mftc0 $8,$9,5 + mftc0 $8,$9,6 + mftc0 $8,$9,7 + mftc0 $8,$10,0 + mftc0 $8,$10,1 + mftc0 $8,$10,2 + mftc0 $8,$10,3 + mftc0 $8,$10,4 + mftc0 $8,$10,5 + mftc0 $8,$10,6 + mftc0 $8,$10,7 + mftc0 $8,$11,0 + mftc0 $8,$11,1 + mftc0 $8,$11,2 + mftc0 $8,$11,3 + mftc0 $8,$11,4 + mftc0 $8,$11,5 + mftc0 $8,$11,6 + mftc0 $8,$11,7 + mftc0 $8,$12,0 + mftc0 $8,$12,1 + mftc0 $8,$12,2 + mftc0 $8,$12,3 + mftc0 $8,$12,4 + mftc0 $8,$12,5 + mftc0 $8,$12,6 + mftc0 $8,$12,7 + mftc0 $8,$13,0 + mftc0 $8,$13,1 + mftc0 $8,$13,2 + mftc0 $8,$13,3 + mftc0 $8,$13,4 + mftc0 $8,$13,5 + mftc0 $8,$13,6 + mftc0 $8,$13,7 + mftc0 $8,$14,0 + mftc0 $8,$14,1 + mftc0 $8,$14,2 + mftc0 $8,$14,3 + mftc0 $8,$14,4 + mftc0 $8,$14,5 + mftc0 $8,$14,6 + mftc0 $8,$14,7 + mftc0 $8,$15,0 + mftc0 $8,$15,1 + mftc0 $8,$15,2 + mftc0 $8,$15,3 + mftc0 $8,$15,4 + mftc0 $8,$15,5 + mftc0 $8,$15,6 + mftc0 $8,$15,7 + mftc0 $8,$16,0 + mftc0 $8,$16,1 + mftc0 $8,$16,2 + mftc0 $8,$16,3 + mftc0 $8,$16,4 + mftc0 $8,$16,5 + mftc0 $8,$16,6 + mftc0 $8,$16,7 + mftc0 $8,$17,0 + mftc0 $8,$17,1 + mftc0 $8,$17,2 + mftc0 $8,$17,3 + mftc0 $8,$17,4 + mftc0 $8,$17,5 + mftc0 $8,$17,6 + mftc0 $8,$17,7 + mftc0 $8,$18,0 + mftc0 $8,$18,1 + mftc0 $8,$18,2 + mftc0 $8,$18,3 + mftc0 $8,$18,4 + mftc0 $8,$18,5 + mftc0 $8,$18,6 + mftc0 $8,$18,7 + mftc0 $8,$19,0 + mftc0 $8,$19,1 + mftc0 $8,$19,2 + mftc0 $8,$19,3 + mftc0 $8,$19,4 + mftc0 $8,$19,5 + mftc0 $8,$19,6 + mftc0 $8,$19,7 + mftc0 $8,$20,0 + mftc0 $8,$20,1 + mftc0 $8,$20,2 + mftc0 $8,$20,3 + mftc0 $8,$20,4 + mftc0 $8,$20,5 + mftc0 $8,$20,6 + mftc0 $8,$20,7 + mftc0 $8,$21,0 + mftc0 $8,$21,1 + mftc0 $8,$21,2 + mftc0 $8,$21,3 + mftc0 $8,$21,4 + mftc0 $8,$21,5 + mftc0 $8,$21,6 + mftc0 $8,$21,7 + mftc0 $8,$22,0 + mftc0 $8,$22,1 + mftc0 $8,$22,2 + mftc0 $8,$22,3 + mftc0 $8,$22,4 + mftc0 $8,$22,5 + mftc0 $8,$22,6 + mftc0 $8,$22,7 + mftc0 $8,$23,0 + mftc0 $8,$23,1 + mftc0 $8,$23,2 + mftc0 $8,$23,3 + mftc0 $8,$23,4 + mftc0 $8,$23,5 + mftc0 $8,$23,6 + mftc0 $8,$23,7 + mftc0 $8,$24,0 + mftc0 $8,$24,1 + mftc0 $8,$24,2 + mftc0 $8,$24,3 + mftc0 $8,$24,4 + mftc0 $8,$24,5 + mftc0 $8,$24,6 + mftc0 $8,$24,7 + mftc0 $8,$25,0 + mftc0 $8,$25,1 + mftc0 $8,$25,2 + mftc0 $8,$25,3 + mftc0 $8,$25,4 + mftc0 $8,$25,5 + mftc0 $8,$25,6 + mftc0 $8,$25,7 + mftc0 $8,$26,0 + mftc0 $8,$26,1 + mftc0 $8,$26,2 + mftc0 $8,$26,3 + mftc0 $8,$26,4 + mftc0 $8,$26,5 + mftc0 $8,$26,6 + mftc0 $8,$26,7 + mftc0 $8,$27,0 + mftc0 $8,$27,1 + mftc0 $8,$27,2 + mftc0 $8,$27,3 + mftc0 $8,$27,4 + mftc0 $8,$27,5 + mftc0 $8,$27,6 + mftc0 $8,$27,7 + mftc0 $8,$28,0 + mftc0 $8,$28,1 + mftc0 $8,$28,2 + mftc0 $8,$28,3 + mftc0 $8,$28,4 + mftc0 $8,$28,5 + mftc0 $8,$28,6 + mftc0 $8,$28,7 + mftc0 $8,$29,0 + mftc0 $8,$29,1 + mftc0 $8,$29,2 + mftc0 $8,$29,3 + mftc0 $8,$29,4 + mftc0 $8,$29,5 + mftc0 $8,$29,6 + mftc0 $8,$29,7 + mftc0 $8,$30,0 + mftc0 $8,$30,1 + mftc0 $8,$30,2 + mftc0 $8,$30,3 + mftc0 $8,$30,4 + mftc0 $8,$30,5 + mftc0 $8,$30,6 + mftc0 $8,$30,7 + mftc0 $8,$31,0 + mftc0 $8,$31,1 + mftc0 $8,$31,2 + mftc0 $8,$31,3 + mftc0 $8,$31,4 + mftc0 $8,$31,5 + mftc0 $8,$31,6 + mftc0 $8,$31,7 + mftgpr $9,$10 + mftlo $10 + mftlo $11,$ac0 + mfthi $12 + mfthi $13,$ac1 +# mftacx $14 +# mftacx $15,$ac2 + mftdsp $16 + mftc1 $17,$f18 + mftc1 $18,$19 + mfthc1 $19,$f20 + mfthc1 $20,$22 + cftc1 $21,$22 + cftc1 $22,$f23 + mftc2 $23,$24 + mfthc2 $24,$25 + cftc2 $25,$26 + mttc0 $26,$27 + mttc0 $27,$0,0 + mttc0 $27,$0,1 + mttc0 $27,$0,2 + mttc0 $27,$0,3 + mttc0 $27,$0,4 + mttc0 $27,$0,5 + mttc0 $27,$0,6 + mttc0 $27,$0,7 + mttc0 $27,$1,0 + mttc0 $27,$1,1 + mttc0 $27,$1,2 + mttc0 $27,$1,3 + mttc0 $27,$1,4 + mttc0 $27,$1,5 + mttc0 $27,$1,6 + mttc0 $27,$1,7 + mttc0 $27,$2,0 + mttc0 $27,$2,1 + mttc0 $27,$2,2 + mttc0 $27,$2,3 + mttc0 $27,$2,4 + mttc0 $27,$2,5 + mttc0 $27,$2,6 + mttc0 $27,$2,7 + mttc0 $27,$3,0 + mttc0 $27,$3,1 + mttc0 $27,$3,2 + mttc0 $27,$3,3 + mttc0 $27,$3,4 + mttc0 $27,$3,5 + mttc0 $27,$3,6 + mttc0 $27,$3,7 + mttc0 $27,$4,0 + mttc0 $27,$4,1 + mttc0 $27,$4,2 + mttc0 $27,$4,3 + mttc0 $27,$4,4 + mttc0 $27,$4,5 + mttc0 $27,$4,6 + mttc0 $27,$4,7 + mttc0 $27,$5,0 + mttc0 $27,$5,1 + mttc0 $27,$5,2 + mttc0 $27,$5,3 + mttc0 $27,$5,4 + mttc0 $27,$5,5 + mttc0 $27,$5,6 + mttc0 $27,$5,7 + mttc0 $27,$6,0 + mttc0 $27,$6,1 + mttc0 $27,$6,2 + mttc0 $27,$6,3 + mttc0 $27,$6,4 + mttc0 $27,$6,5 + mttc0 $27,$6,6 + mttc0 $27,$6,7 + mttc0 $27,$7,0 + mttc0 $27,$7,1 + mttc0 $27,$7,2 + mttc0 $27,$7,3 + mttc0 $27,$7,4 + mttc0 $27,$7,5 + mttc0 $27,$7,6 + mttc0 $27,$7,7 + mttc0 $27,$8,0 + mttc0 $27,$8,1 + mttc0 $27,$8,2 + mttc0 $27,$8,3 + mttc0 $27,$8,4 + mttc0 $27,$8,5 + mttc0 $27,$8,6 + mttc0 $27,$8,7 + mttc0 $27,$9,0 + mttc0 $27,$9,1 + mttc0 $27,$9,2 + mttc0 $27,$9,3 + mttc0 $27,$9,4 + mttc0 $27,$9,5 + mttc0 $27,$9,6 + mttc0 $27,$9,7 + mttc0 $27,$10,0 + mttc0 $27,$10,1 + mttc0 $27,$10,2 + mttc0 $27,$10,3 + mttc0 $27,$10,4 + mttc0 $27,$10,5 + mttc0 $27,$10,6 + mttc0 $27,$10,7 + mttc0 $27,$11,0 + mttc0 $27,$11,1 + mttc0 $27,$11,2 + mttc0 $27,$11,3 + mttc0 $27,$11,4 + mttc0 $27,$11,5 + mttc0 $27,$11,6 + mttc0 $27,$11,7 + mttc0 $27,$12,0 + mttc0 $27,$12,1 + mttc0 $27,$12,2 + mttc0 $27,$12,3 + mttc0 $27,$12,4 + mttc0 $27,$12,5 + mttc0 $27,$12,6 + mttc0 $27,$12,7 + mttc0 $27,$13,0 + mttc0 $27,$13,1 + mttc0 $27,$13,2 + mttc0 $27,$13,3 + mttc0 $27,$13,4 + mttc0 $27,$13,5 + mttc0 $27,$13,6 + mttc0 $27,$13,7 + mttc0 $27,$14,0 + mttc0 $27,$14,1 + mttc0 $27,$14,2 + mttc0 $27,$14,3 + mttc0 $27,$14,4 + mttc0 $27,$14,5 + mttc0 $27,$14,6 + mttc0 $27,$14,7 + mttc0 $27,$15,0 + mttc0 $27,$15,1 + mttc0 $27,$15,2 + mttc0 $27,$15,3 + mttc0 $27,$15,4 + mttc0 $27,$15,5 + mttc0 $27,$15,6 + mttc0 $27,$15,7 + mttc0 $27,$16,0 + mttc0 $27,$16,1 + mttc0 $27,$16,2 + mttc0 $27,$16,3 + mttc0 $27,$16,4 + mttc0 $27,$16,5 + mttc0 $27,$16,6 + mttc0 $27,$16,7 + mttc0 $27,$17,0 + mttc0 $27,$17,1 + mttc0 $27,$17,2 + mttc0 $27,$17,3 + mttc0 $27,$17,4 + mttc0 $27,$17,5 + mttc0 $27,$17,6 + mttc0 $27,$17,7 + mttc0 $27,$18,0 + mttc0 $27,$18,1 + mttc0 $27,$18,2 + mttc0 $27,$18,3 + mttc0 $27,$18,4 + mttc0 $27,$18,5 + mttc0 $27,$18,6 + mttc0 $27,$18,7 + mttc0 $27,$19,0 + mttc0 $27,$19,1 + mttc0 $27,$19,2 + mttc0 $27,$19,3 + mttc0 $27,$19,4 + mttc0 $27,$19,5 + mttc0 $27,$19,6 + mttc0 $27,$19,7 + mttc0 $27,$20,0 + mttc0 $27,$20,1 + mttc0 $27,$20,2 + mttc0 $27,$20,3 + mttc0 $27,$20,4 + mttc0 $27,$20,5 + mttc0 $27,$20,6 + mttc0 $27,$20,7 + mttc0 $27,$21,0 + mttc0 $27,$21,1 + mttc0 $27,$21,2 + mttc0 $27,$21,3 + mttc0 $27,$21,4 + mttc0 $27,$21,5 + mttc0 $27,$21,6 + mttc0 $27,$21,7 + mttc0 $27,$22,0 + mttc0 $27,$22,1 + mttc0 $27,$22,2 + mttc0 $27,$22,3 + mttc0 $27,$22,4 + mttc0 $27,$22,5 + mttc0 $27,$22,6 + mttc0 $27,$22,7 + mttc0 $27,$23,0 + mttc0 $27,$23,1 + mttc0 $27,$23,2 + mttc0 $27,$23,3 + mttc0 $27,$23,4 + mttc0 $27,$23,5 + mttc0 $27,$23,6 + mttc0 $27,$23,7 + mttc0 $27,$24,0 + mttc0 $27,$24,1 + mttc0 $27,$24,2 + mttc0 $27,$24,3 + mttc0 $27,$24,4 + mttc0 $27,$24,5 + mttc0 $27,$24,6 + mttc0 $27,$24,7 + mttc0 $27,$25,0 + mttc0 $27,$25,1 + mttc0 $27,$25,2 + mttc0 $27,$25,3 + mttc0 $27,$25,4 + mttc0 $27,$25,5 + mttc0 $27,$25,6 + mttc0 $27,$25,7 + mttc0 $27,$26,0 + mttc0 $27,$26,1 + mttc0 $27,$26,2 + mttc0 $27,$26,3 + mttc0 $27,$26,4 + mttc0 $27,$26,5 + mttc0 $27,$26,6 + mttc0 $27,$26,7 + mttc0 $27,$27,0 + mttc0 $27,$27,1 + mttc0 $27,$27,2 + mttc0 $27,$27,3 + mttc0 $27,$27,4 + mttc0 $27,$27,5 + mttc0 $27,$27,6 + mttc0 $27,$27,7 + mttc0 $27,$28,0 + mttc0 $27,$28,1 + mttc0 $27,$28,2 + mttc0 $27,$28,3 + mttc0 $27,$28,4 + mttc0 $27,$28,5 + mttc0 $27,$28,6 + mttc0 $27,$28,7 + mttc0 $27,$29,0 + mttc0 $27,$29,1 + mttc0 $27,$29,2 + mttc0 $27,$29,3 + mttc0 $27,$29,4 + mttc0 $27,$29,5 + mttc0 $27,$29,6 + mttc0 $27,$29,7 + mttc0 $27,$30,0 + mttc0 $27,$30,1 + mttc0 $27,$30,2 + mttc0 $27,$30,3 + mttc0 $27,$30,4 + mttc0 $27,$30,5 + mttc0 $27,$30,6 + mttc0 $27,$30,7 + mttc0 $27,$31,0 + mttc0 $27,$31,1 + mttc0 $27,$31,2 + mttc0 $27,$31,3 + mttc0 $27,$31,4 + mttc0 $27,$31,5 + mttc0 $27,$31,6 + mttc0 $27,$31,7 + mttgpr $28,$29 + mttlo $29 + mttlo $30,$ac3 + mtthi $31 + mtthi $0,$ac0 +# mttacx $1 +# mttacx $2,$ac1 + mttdsp $3 + mttc1 $4,$f5 + mttc1 $5,$6 + mtthc1 $6,$f8 + mtthc1 $7,$10 + cttc1 $8,$9 + cttc1 $9,$f10 + mttc2 $10,$11 + mtthc2 $11,$12 + cttc2 $12,$13 + mftr $13,$14,0,0,0 + mftr $13,$14,0,1,0 + mftr $13,$14,0,2,0 + mftr $13,$14,0,3,0 + mftr $13,$14,0,4,0 + mftr $13,$14,0,5,0 + mftr $13,$14,0,6,0 + mftr $13,$14,0,7,0 + mftr $13,$14,0,0,1 + mftr $13,$14,0,1,1 + mftr $13,$14,0,2,1 + mftr $13,$14,0,3,1 + mftr $13,$14,0,4,1 + mftr $13,$14,0,5,1 + mftr $13,$14,0,6,1 + mftr $13,$14,0,7,1 + mftr $13,$14,1,0,0 + mftr $13,$14,1,1,0 + mftr $13,$14,1,2,0 + mftr $13,$14,1,3,0 + mftr $13,$14,1,4,0 + mftr $13,$14,1,5,0 + mftr $13,$14,1,6,0 + mftr $13,$14,1,7,0 + mftr $13,$14,1,0,1 + mftr $13,$14,1,1,1 + mftr $13,$14,1,2,1 + mftr $13,$14,1,3,1 + mftr $13,$14,1,4,1 + mftr $13,$14,1,5,1 + mftr $13,$14,1,6,1 + mftr $13,$14,1,7,1 + mttr $13,$14,0,0,0 + mttr $13,$14,0,1,0 + mttr $13,$14,0,2,0 + mttr $13,$14,0,3,0 + mttr $13,$14,0,4,0 + mttr $13,$14,0,5,0 + mttr $13,$14,0,6,0 + mttr $13,$14,0,7,0 + mttr $13,$14,0,0,1 + mttr $13,$14,0,1,1 + mttr $13,$14,0,2,1 + mttr $13,$14,0,3,1 + mttr $13,$14,0,4,1 + mttr $13,$14,0,5,1 + mttr $13,$14,0,6,1 + mttr $13,$14,0,7,1 + mttr $13,$14,1,0,0 + mttr $13,$14,1,1,0 + mttr $13,$14,1,2,0 + mttr $13,$14,1,3,0 + mttr $13,$14,1,4,0 + mttr $13,$14,1,5,0 + mttr $13,$14,1,6,0 + mttr $13,$14,1,7,0 + mttr $13,$14,1,0,1 + mttr $13,$14,1,1,1 + mttr $13,$14,1,2,1 + mttr $13,$14,1,3,1 + mttr $13,$14,1,4,1 + mttr $13,$14,1,5,1 + mttr $13,$14,1,6,1 + mttr $13,$14,1,7,1 + pause + + mfthc0 $7,$8 + mfthc0 $8,$0,0 + mfthc0 $8,$0,1 + mfthc0 $8,$0,2 + mfthc0 $8,$0,3 + mfthc0 $8,$0,4 + mfthc0 $8,$0,5 + mfthc0 $8,$0,6 + mfthc0 $8,$0,7 + + mtthc0 $26,$27 + mtthc0 $27,$0,0 + mtthc0 $27,$0,1 + mtthc0 $27,$0,2 + mtthc0 $27,$0,3 + mtthc0 $27,$0,4 + mtthc0 $27,$0,5 + mtthc0 $27,$0,6 + mtthc0 $27,$0,7 + + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 diff --git a/gas/testsuite/gas/nanomips/mvh.d b/gas/testsuite/gas/nanomips/mvh.d new file mode 100644 index 00000000000..01fc39be453 --- /dev/null +++ b/gas/testsuite/gas/nanomips/mvh.d @@ -0,0 +1,16 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mvirt,cp0-names=32r6 +#name: MVH instructions +#as: -mvirt + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 2041 0038 mfhc0 t4,random +[0-9a-f]+ <[^>]+> 2050 0038 mfhc0 t4,config +[0-9a-f]+ <[^>]+> 2040 1038 mfhc0 t4,mvpconf0 +[0-9a-f]+ <[^>]+> 2040 3838 mfhc0 t4,\$0,7 +[0-9a-f]+ <[^>]+> 2041 0078 mthc0 t4,random +[0-9a-f]+ <[^>]+> 2050 0078 mthc0 t4,config +[0-9a-f]+ <[^>]+> 2040 1078 mthc0 t4,mvpconf0 +[0-9a-f]+ <[^>]+> 2040 3878 mthc0 t4,\$0,7 +#pass diff --git a/gas/testsuite/gas/nanomips/mvh.s b/gas/testsuite/gas/nanomips/mvh.s new file mode 100644 index 00000000000..385ffb40ffb --- /dev/null +++ b/gas/testsuite/gas/nanomips/mvh.s @@ -0,0 +1,12 @@ + .text +test_xpa: + + mfhc0 $2, $1 + mfhc0 $2, $16 + mfhc0 $2, $0, 2 + mfhc0 $2, $0, 7 + + mthc0 $2, $1 + mthc0 $2, $16 + mthc0 $2, $0, 2 + mthc0 $2, $0, 7 diff --git a/gas/testsuite/gas/nanomips/nanomips-error.l b/gas/testsuite/gas/nanomips/nanomips-error.l new file mode 100644 index 00000000000..b288b15fde4 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips-error.l @@ -0,0 +1,26 @@ +.*.s: Assembler messages: +.*:9: Error: invalid operands `movep \$a1,\$a1,\$s0,\$zero' +.*:10: Error: invalid operands `movep \$a2,\$a1,\$s1,\$at' +.*:11: Error: invalid operands `movep \$a3,\$a2,\$s2,\$t4' +.*:12: Error: invalid operands `movep \$a3,\$a3,\$s3,\$t5' +.*:13: Error: invalid operands `movep \$a0,\$s4,\$a0,\$a4' +.*:14: Error: invalid operands `movep \$a1,\$s5,\$a1,\$a3' +.*:15: Error: invalid operands `movep \$a2,\$s6,\$a2,\$a4' +.*:16: Error: invalid operands `movep \$a3,\$s7,\$a2,\$a2' +.*:20: Error: the target register must not be \$0 `balrsc \$zero,\$a2' +.*:21: Error: the target register must not be \$0 `move16 \$zero,\$at' +.*:22: Error: the target register must not be \$0 `li \$zero,1' +.*:25: Error: operand 4 out of range `align \$a0,\$t4,\$t5,4' +.*:26: Error: operand 4 out of range `align \$a0,\$t4,\$t5,31' +.*:29: Error: operand 2 out of range `bgeiuc \$t4,-1,test' +.*:30: Error: operand 2 out of range `bgeiuc \$t5,128,test' +.*:31: Error: operand 2 out of range `bltiuc \$a0,-3,test' +.*:32: Error: operand 2 out of range `bltiuc \$a1,256,test' +.*:35: Error: invalid register range `lwm \$16-17,0\(\$4\)' +.*:36: Error: invalid operands `lwm \$17-\$16,0\(\$4\)' +.*:37: Error: invalid operands `lwm \$16-\$f17,0\(\$4\)' +.*:38: Error: invalid operands `lwm \$f16-\$17,0\(\$4\)' +.*:41: Error: floating-point expression required `li\.s \$4,foo' +.*:42: Error: cannot create floating-point number +.*:43: Error: floating-point expression required `li\.s \$4,\$4' +.*:44: Error: invalid operands `li\.s 1.0' diff --git a/gas/testsuite/gas/nanomips/nanomips-error.s b/gas/testsuite/gas/nanomips/nanomips-error.s new file mode 100644 index 00000000000..be0d4147888 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips-error.s @@ -0,0 +1,46 @@ +# nanoMIPS assembly errors + .text + .ent test + .globl test +test: + /* Order between 1st and 2nd operand of movep should be enforced. + 2nd-op = 4 + (( 1st-op + 1 ) % 4). + Likewise for 3rd and 4th operands of movep[REV]. */ + movep $a1,$a1,$s0,$zero + movep $a2,$a1,$s1,$at + movep $a3,$a2,$s2,$t4 + movep $a3,$a3,$s3,$t5 + movep $a0,$s4,$a0,$a4 + movep $a1,$s5,$a1,$a3 + movep $a2,$s6,$a2,$a4 + movep $a3,$s7,$a2,$a2 + + /* Non-zero register check */ + + balrsc $zero, $a2 + move16 $zero, $at + li $zero, 1 + + /* Valid values for ALIGN macro are 0, 1, 2, 3 */ + align $a0, $t4, $t5, 4 + align $a0, $t4, $t5, 31 + + /* Range of immediate operand for branch with compare-immediate */ + bgeiuc $t4, -1, test + bgeiuc $t5, 128, test + bltiuc $a0, -3, test + bltiuc $a1, 256, test + + /* Invalid register range */ + lwm $16-17,0($4) + lwm $17-$16,0($4) + lwm $16-$f17,0($4) + lwm $f16-$17,0($4) + + /* Floating point expression expected */ + li.s $4,foo + li.s $4,2.0e1000 + li.s $4,$4 + li.s 1.0 + + .end test diff --git a/gas/testsuite/gas/nanomips/nanomips-exc-noalias.d b/gas/testsuite/gas/nanomips/nanomips-exc-noalias.d new file mode 100644 index 00000000000..c140a52d51d --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips-exc-noalias.d @@ -0,0 +1,254 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mno-aliases +#name: New nanoMIPS instructions without aliases +#source: nanomips-exc.s + +# Check exclusive nanoMIPS instructions without aliases + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> bc01 movep a0,a1,a5,a4 +[0-9a-f]+ <[^>]+> bd43 movep a1,a2,zero,a6 +[0-9a-f]+ <[^>]+> bc8d movep a2,a3,a1,a0 +[0-9a-f]+ <[^>]+> bdcf movep a3,a4,a3,a2 +[0-9a-f]+ <[^>]+> be30 movep a0,a1,s0,s1 +[0-9a-f]+ <[^>]+> bf72 movep a1,a2,s2,s3 +[0-9a-f]+ <[^>]+> bebc movep a2,a3,s4,s5 +[0-9a-f]+ <[^>]+> bffe movep a3,a4,s6,s7 +[0-9a-f]+ <[^>]+> fce0 movep a4,a3,a0,a1 +[0-9a-f]+ <[^>]+> fdc1 movep a5,a2,a1,a2 +[0-9a-f]+ <[^>]+> fcaa movep a6,a1,a2,a3 +[0-9a-f]+ <[^>]+> fd8b movep a7,a0,a3,a4 +[0-9a-f]+ <[^>]+> fe90 movep s0,s4,a0,a1 +[0-9a-f]+ <[^>]+> ff35 movep s5,s1,a1,a2 +[0-9a-f]+ <[^>]+> feda movep s2,s6,a2,a3 +[0-9a-f]+ <[^>]+> ff7f movep s7,s3,a3,a4 +[0-9a-f]+ <[^>]+> bc01 movep a0,a1,a5,a4 +[0-9a-f]+ <[^>]+> bd43 movep a1,a2,zero,a6 +[0-9a-f]+ <[^>]+> bc8d movep a2,a3,a1,a0 +[0-9a-f]+ <[^>]+> bdcf movep a3,a4,a3,a2 +[0-9a-f]+ <[^>]+> be30 movep a0,a1,s0,s1 +[0-9a-f]+ <[^>]+> bf72 movep a1,a2,s2,s3 +[0-9a-f]+ <[^>]+> bebc movep a2,a3,s4,s5 +[0-9a-f]+ <[^>]+> bffe movep a3,a4,s6,s7 +[0-9a-f]+ <[^>]+> fce0 movep a4,a3,a0,a1 +[0-9a-f]+ <[^>]+> fdc1 movep a5,a2,a1,a2 +[0-9a-f]+ <[^>]+> fcaa movep a6,a1,a2,a3 +[0-9a-f]+ <[^>]+> fd8b movep a7,a0,a3,a4 +[0-9a-f]+ <[^>]+> fe90 movep s0,s4,a0,a1 +[0-9a-f]+ <[^>]+> ff35 movep s5,s1,a1,a2 +[0-9a-f]+ <[^>]+> feda movep s2,s6,a2,a3 +[0-9a-f]+ <[^>]+> ff7f movep s7,s3,a3,a4 +[0-9a-f]+ <[^>]+> 7400 lw a4,0\(a4\) +[0-9a-f]+ <[^>]+> 7521 lw a5,4\(a5\) +[0-9a-f]+ <[^>]+> 744a lw a6,8\(a6\) +[0-9a-f]+ <[^>]+> 756b lw a7,12\(a7\) +[0-9a-f]+ <[^>]+> 7404 lw a4,0\(a0\) +[0-9a-f]+ <[^>]+> 7525 lw a5,4\(a1\) +[0-9a-f]+ <[^>]+> 744e lw a6,8\(a2\) +[0-9a-f]+ <[^>]+> 756f lw a7,12\(a3\) +[0-9a-f]+ <[^>]+> 7410 lw a4,0\(s0\) +[0-9a-f]+ <[^>]+> 7531 lw a5,4\(s1\) +[0-9a-f]+ <[^>]+> 745a lw a6,8\(s2\) +[0-9a-f]+ <[^>]+> 757b lw a7,12\(s3\) +[0-9a-f]+ <[^>]+> 7414 lw a4,0\(s4\) +[0-9a-f]+ <[^>]+> 7535 lw a5,4\(s5\) +[0-9a-f]+ <[^>]+> 745e lw a6,8\(s6\) +[0-9a-f]+ <[^>]+> 757f lw a7,12\(s7\) +[0-9a-f]+ <[^>]+> 7480 lw a0,0\(a4\) +[0-9a-f]+ <[^>]+> 75a1 lw a1,4\(a5\) +[0-9a-f]+ <[^>]+> 74ca lw a2,8\(a6\) +[0-9a-f]+ <[^>]+> 75eb lw a3,12\(a7\) +[0-9a-f]+ <[^>]+> f600 sw s0,0\(a4\) +[0-9a-f]+ <[^>]+> f721 sw s1,4\(a5\) +[0-9a-f]+ <[^>]+> f64a sw s2,8\(a6\) +[0-9a-f]+ <[^>]+> f76b sw s3,12\(a7\) +[0-9a-f]+ <[^>]+> f680 sw s4,0\(a4\) +[0-9a-f]+ <[^>]+> f7a1 sw s5,4\(a5\) +[0-9a-f]+ <[^>]+> f6ca sw s6,8\(a6\) +[0-9a-f]+ <[^>]+> f7eb sw s7,12\(a7\) +[0-9a-f]+ <[^>]+> f684 sw s4,0\(a0\) +[0-9a-f]+ <[^>]+> f7a5 sw s5,4\(a1\) +[0-9a-f]+ <[^>]+> f6ce sw s6,8\(a2\) +[0-9a-f]+ <[^>]+> f7ef sw s7,12\(a3\) +[0-9a-f]+ <[^>]+> f690 sw s4,0\(s0\) +[0-9a-f]+ <[^>]+> f7b1 sw s5,4\(s1\) +[0-9a-f]+ <[^>]+> f6da sw s6,8\(s2\) +[0-9a-f]+ <[^>]+> f7fb sw s7,12\(s3\) +[0-9a-f]+ <[^>]+> f694 sw s4,0\(s4\) +[0-9a-f]+ <[^>]+> f7b5 sw s5,4\(s5\) +[0-9a-f]+ <[^>]+> f6de sw s6,8\(s6\) +[0-9a-f]+ <[^>]+> f7ff sw s7,12\(s7\) +[0-9a-f]+ <[^>]+> f494 sw a0,0\(s4\) +[0-9a-f]+ <[^>]+> f5b5 sw a1,4\(s5\) +[0-9a-f]+ <[^>]+> f4de sw a2,8\(s6\) +[0-9a-f]+ <[^>]+> f5ff sw a3,12\(s7\) +[0-9a-f]+ <[^>]+> f614 sw s0,0\(s4\) +[0-9a-f]+ <[^>]+> f735 sw s1,4\(s5\) +[0-9a-f]+ <[^>]+> f65e sw s2,8\(s6\) +[0-9a-f]+ <[^>]+> f77f sw s3,12\(s7\) +[0-9a-f]+ <[^>]+> 4803 8000 brsc t5 +[0-9a-f]+ <[^>]+> 481f 8000 brsc ra +[0-9a-f]+ <[^>]+> 4a11 8000 balrsc s0,s1 +[0-9a-f]+ <[^>]+> 4bf1 8000 balrsc ra,s1 +[0-9a-f]+ <[^>]+> 446d 2345 addiu t5,gp,74565 +[0-9a-f]+ <[^>]+> 6062 5678 1234 addiu t5,gp,[0-9a-f]+6 +[0-9a-f]+ <[^>]+> 6062 dcbb fffe addiu t5,gp,-74565 +[0-9a-f]+ <[^>]+> 6062 a988 edcb addiu t5,gp,-305419896 +[0-9a-f]+ <[^>]+> 6061 2345 0001 addiu t5,t5,74565 +[0-9a-f]+ <[^>]+> 6061 5678 1234 addiu t5,t5,[0-9a-f]+6 +[0-9a-f]+ <[^>]+> 6061 dcbb fffe addiu t5,t5,-74565 +[0-9a-f]+ <[^>]+> 6061 a988 edcb addiu t5,t5,-305419896 +[0-9a-f]+ <[^>]+> c84c 0800 bgeiuc t4,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c84f f800 bgeiuc t4,127,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c85c 0800 bltiuc t4,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c85f f800 bltiuc t4,127,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 2062 201f extw a0,t4,t5,0 +[0-9a-f]+ <[^>]+> 2062 261f extw a0,t4,t5,24 +[0-9a-f]+ <[^>]+> 2062 241f extw a0,t4,t5,16 +[0-9a-f]+ <[^>]+> 2062 221f extw a0,t4,t5,8 +[0-9a-f]+ <[^>]+> 2062 205f extw a0,t4,t5,1 +[0-9a-f]+ <[^>]+> 2062 209f extw a0,t4,t5,2 +[0-9a-f]+ <[^>]+> 2062 20df extw a0,t4,t5,3 +[0-9a-f]+ <[^>]+> 2062 211f extw a0,t4,t5,4 +[0-9a-f]+ <[^>]+> 1083 move a0,t5 +[0-9a-f]+ <[^>]+> 2003 2290 or a0,t5,zero +[0-9a-f]+ <[^>]+> 2062 261f extw a0,t4,t5,24 +[0-9a-f]+ <[^>]+> 2062 241f extw a0,t4,t5,16 +[0-9a-f]+ <[^>]+> 2062 221f extw a0,t4,t5,8 +[0-9a-f]+ <[^>]+> 5359 lwxs a0,a1\(a2\) +[0-9a-f]+ <[^>]+> 508f lwxs a3,s0\(s1\) +[0-9a-f]+ <[^>]+> 5235 lwxs s2,s3\(a0\) +[0-9a-f]+ <[^>]+> 4200 0003 sw s0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL19_S2 x +[0-9a-f]+ <[^>]+> d484 sw s1,16\(gp\) +[0-9a-f]+ <[^>]+> d484 sw s1,16\(gp\) +[0-9a-f]+ <[^>]+> d480 sw s1,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL7_S2 test +[0-9a-f]+ <[^>]+> 04a0 0000 addiupc a1,4 + [0-9a-f]+: R_NANOMIPS_PC21_S1 test +[0-9a-f]+ <[^>]+> 04a0 0000 addiupc a1,4 + [0-9a-f]+: R_NANOMIPS_PC21_S1 test2 +[0-9a-f]+ <[^>]+> 8483 3fa0 pref 0x4,4000\(t5\) +[0-9a-f]+ <[^>]+> a483 98e2 pref 0x4,-30\(t5\) +[0-9a-f]+ <[^>]+> 8483 3000 pref 0x4,0\(t5\) + [0-9a-f]+: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> c884 c000 bbeqzc a0,24,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c884 0800 bbeqzc a0,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c884 f800 bbeqzc a0,31,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c894 0000 bbnezc a0,0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c894 8000 bbnezc a0,16,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 2083 0000 teq t5,a0,0x0 +[0-9a-f]+ <[^>]+> 20c5 0400 tne a1,a2,0x0 +[0-9a-f]+ <[^>]+> 2083 3000 teq t5,a0,0x6 +[0-9a-f]+ <[^>]+> 20c5 3c00 tne a1,a2,0x7 +[0-9a-f]+ <[^>]+> 606b 0000 0000 lwpc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 \*ABS\*\+0x2710 +[0-9a-f]+ <[^>]+> 606f 0000 0000 swpc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 \*ABS\*\+0x2710 +[0-9a-f]+ <[^>]+> 6063 0000 0000 addiupc t5,6 + [0-9a-f]+: R_NANOMIPS_PC_I32 test +[0-9a-f]+ <[^>]+> 606b 0000 0000 lwpc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 test +[0-9a-f]+ <[^>]+> 606f 0000 0000 swpc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC_I32 test +[0-9a-f]+ <[^>]+> a445 2104 ualh t4,4\(a1\) +[0-9a-f]+ <[^>]+> a445 2904 uash t4,4\(a1\) +[0-9a-f]+ <[^>]+> a445 4504 ualwm t4,4\(a1\),4 +[0-9a-f]+ <[^>]+> a445 6d04 uaswm t4,4\(a1\),6 +[0-9a-f]+ <[^>]+> a445 1504 ualwm t4,4\(a1\),1 +[0-9a-f]+ <[^>]+> a445 1d04 uaswm t4,4\(a1\),1 +[0-9a-f]+ <[^>]+> a445 0504 ualwm t4,4\(a1\),8 +[0-9a-f]+ <[^>]+> a445 7d04 uaswm t4,4\(a1\),7 +[0-9a-f]+ <[^>]+> a445 0404 lwm t4,4\(a1\),8 +[0-9a-f]+ <[^>]+> a445 7c04 swm t4,4\(a1\),7 +[0-9a-f]+ <[^>]+> 8043 d7c5 rotx t4,t5,5,30,1 +[0-9a-f]+ <[^>]+> 8043 d01f rotx t4,t5,31,0,0 +[0-9a-f]+ <[^>]+> 8043 d01f rotx t4,t5,31,0,0 +[0-9a-f]+ <[^>]+> 8043 d247 rotx t4,t5,7,8,1 +[0-9a-f]+ <[^>]+> 8043 d247 rotx t4,t5,7,8,1 +[0-9a-f]+ <[^>]+> 8043 d247 rotx t4,t5,7,8,1 +[0-9a-f]+ <[^>]+> 8043 d40f rotx t4,t5,15,16,0 +[0-9a-f]+ <[^>]+> 8043 d40f rotx t4,t5,15,16,0 +[0-9a-f]+ <[^>]+> 8043 d218 rotx t4,t5,24,8,0 +[0-9a-f]+ <[^>]+> 8043 d218 rotx t4,t5,24,8,0 +[0-9a-f]+ <[^>]+> 8043 d608 rotx t4,t5,8,24,0 +[0-9a-f]+ <[^>]+> 8043 d608 rotx t4,t5,8,24,0 +[0-9a-f]+ <[^>]+> 8043 d608 rotx t4,t5,8,24,0 +[0-9a-f]+ <[^>]+> 04bf fffd addiupc a1,0 +[0-9a-f]+ <[^>]+> 04a0 0000 addiupc a1,4 +[0-9a-f]+ <[^>]+> 04a0 0004 addiupc a1,8 +[0-9a-f]+ <[^>]+> 60a3 fffa ffff addiupc a1,0 +[0-9a-f]+ <[^>]+> 60a3 0000 0000 addiupc a1,6 +[0-9a-f]+ <[^>]+> 60a3 0002 0000 addiupc a1,8 +[0-9a-f]+ <[^>]+> 04bf fffe addiupc a1,2097154 +[0-9a-f]+ <[^>]+> 60a3 fffe 001f addiupc a1,2097156 +[0-9a-f]+ <[^>]+> 04a0 0001 addiupc a1,-2097148 +[0-9a-f]+ <[^>]+> 60a3 fffc ffdf addiupc a1,-2097150 +[0-9a-f]+ <[^>]+> e060 0002 aluipc t5,%pcrel_hi\(00000000 <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 test +[0-9a-f]+ <[^>]+> 0063 0000 addiu t5,t5,0 + [0-9a-f]+: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> e062 5002 aluipc t5,0x25 +[0-9a-f]+ <[^>]+> e062 5002 aluipc t5,0x25 +[0-9a-f]+ <[^>]+> e065 40ef aluipc t5,0x87654 +[0-9a-f]+ <[^>]+> e065 40ef aluipc t5,0x87654 +[0-9a-f]+ <[^>]+> b2c8 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 3c02 addu a4,a4,a6 +[0-9a-f]+ <[^>]+> b100 addu s0,s0,s2 +[0-9a-f]+ <[^>]+> 3e97 addu s4,s4,s7 +[0-9a-f]+ <[^>]+> 3ca3 addu a1,a1,a7 +[0-9a-f]+ <[^>]+> 3c51 addu a6,a6,s1 +[0-9a-f]+ <[^>]+> 3e76 addu s3,s3,s6 +[0-9a-f]+ <[^>]+> 3ea1 addu s5,s5,a5 +[0-9a-f]+ <[^>]+> 3c02 addu a4,a4,a6 +[0-9a-f]+ <[^>]+> 3e97 addu s4,s4,s7 +[0-9a-f]+ <[^>]+> 3ca3 addu a1,a1,a7 +[0-9a-f]+ <[^>]+> 3c51 addu a6,a6,s1 +[0-9a-f]+ <[^>]+> 3e76 addu s3,s3,s6 +[0-9a-f]+ <[^>]+> 3ea1 addu s5,s5,a5 +[0-9a-f]+ <[^>]+> 3ccf mul a2,a2,a3 +[0-9a-f]+ <[^>]+> 3c2b mul a5,a5,a7 +[0-9a-f]+ <[^>]+> 3e3b mul s1,s1,s3 +[0-9a-f]+ <[^>]+> 3edc mul s6,s6,s4 +[0-9a-f]+ <[^>]+> 3ce9 mul a3,a3,a5 +[0-9a-f]+ <[^>]+> 3c78 mul a7,a7,s0 +[0-9a-f]+ <[^>]+> 3e5d mul s2,s2,s5 +[0-9a-f]+ <[^>]+> 3ee8 mul s7,s7,a4 +[0-9a-f]+ <[^>]+> 3ccf mul a2,a2,a3 +[0-9a-f]+ <[^>]+> 3c2b mul a5,a5,a7 +[0-9a-f]+ <[^>]+> 3e3b mul s1,s1,s3 +[0-9a-f]+ <[^>]+> 3edc mul s6,s6,s4 +[0-9a-f]+ <[^>]+> 3ce9 mul a3,a3,a5 +[0-9a-f]+ <[^>]+> 3c78 mul a7,a7,s0 +[0-9a-f]+ <[^>]+> 3e5d mul s2,s2,s5 +[0-9a-f]+ <[^>]+> 3ee8 mul s7,s7,a4 +[0-9a-f]+ <[^>]+> dbef beqc a2,a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC4_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 88c6 0000 beqc a2,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> dbef beqc a2,a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC4_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 9b00 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> db7f bnec a3,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC4_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> db6f bnec a2,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC4_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> db7f bnec a3,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC4_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> bb00 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 2001 f37f eretnc +#pass diff --git a/gas/testsuite/gas/nanomips/nanomips-exc.s b/gas/testsuite/gas/nanomips/nanomips-exc.s new file mode 100644 index 00000000000..925512b7c15 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips-exc.s @@ -0,0 +1,282 @@ + .text + .extern test2 + .ent test + .globl test +test: + .ifndef insn32_broken + .set noat + movep $r4, $r5, $r9, $r8 + movep $r5, $r6, $r0, $r10 + movep $r6, $r7, $r5, $r4 + movep $r7, $r8, $r7, $r6 + + movep $r4, $r5, $r16, $r17 + movep $r5, $r6, $r18, $r19 + movep $r6, $r7, $r20, $r21 + movep $r7, $r8, $r22, $r23 + /* movep[rev] */ + movep[rev] $r8, $r7, $r4, $r5 + movep $r9, $r6, $r5, $r6 + movep $r10, $r5, $r6, $r7 + movep $r11, $r4, $r7, $r8 + + movep $r16, $r20, $r4, $r5 + movep $r21, $r17, $r5, $r6 + movep $r18, $r22, $r6, $r7 + movep $r23, $r19, $r7, $r8 + + /* movep - arg pair reversed */ + movep $r5, $r4, $r8, $r9 + movep $r6, $r5, $r10, $r0 + movep $r7, $r6, $r4, $r5 + movep $r8, $r7, $r6, $r7 + + movep $r5, $r4, $r17, $r16 + movep $r6, $r5, $r19, $r18 + movep $r7, $r6, $r21, $r20 + movep $r8, $r7, $r23, $r22 + /* movep[rev] - arg pair reversed */ + movep[rev] $r7, $r8, $r5, $r4 + movep $r6, $r9, $r6, $r5 + movep $r5, $r10, $r7, $r6 + movep $r4, $r11, $r8, $r7 + + movep $r20, $r16, $r5, $r4 + movep $r17, $r21, $r6, $r5 + movep $r22, $r18, $r7, $r6 + movep $r19, $r23, $r8, $r7 + .endif + + lw $r8, 0($r8) + lw $r9, 4($r9) + lw $r10, 8($r10) + lw $r11, 12($r11) + + lw $r8, 0($r4) + lw $r9, 4($r5) + lw $r10, 8($r6) + lw $r11, 12($r7) + + lw $r8, 0($r16) + lw $r9, 4($r17) + lw $r10, 8($r18) + lw $r11, 12($r19) + + lw $r8, 0($r20) + lw $r9, 4($r21) + lw $r10, 8($r22) + lw $r11, 12($r23) + + lw $r4, 0($r8) + lw $r5, 4($r9) + lw $r6, 8($r10) + lw $r7, 12($r11) + + sw $r16, 0($r8) + sw $r17, 4($r9) + sw $r18, 8($r10) + sw $r19, 12($r11) + + sw $r20, 0($r8) + sw $r21, 4($r9) + sw $r22, 8($r10) + sw $r23, 12($r11) + + sw $r20, 0($r4) + sw $r21, 4($r5) + sw $r22, 8($r6) + sw $r23, 12($r7) + + sw $r20, 0($r16) + sw $r21, 4($r17) + sw $r22, 8($r18) + sw $r23, 12($r19) + + sw $r20, 0($r20) + sw $r21, 4($r21) + sw $r22, 8($r22) + sw $r23, 12($r23) + + sw $r4, 0($r20) + sw $r5, 4($r21) + sw $r6, 8($r22) + sw $r7, 12($r23) + + sw $r16, 0($r20) + sw $r17, 4($r21) + sw $r18, 8($r22) + sw $r19, 12($r23) + + brsc $r3 + brsc $r31 + + balrsc $r16, $r17 + balrsc $r17 + + addiu $r3, $r28, 0x12345 + .ifndef insn32_broken + addiu $r3, $r28, 0x12345678 + addiu $r3, $r28, -0x12345 + addiu $r3, $r28, -0x12345678 + + addiu $r3, $r3, 0x12345 + addiu $r3, 0x12345678 + addiu $r3, $r3, -0x12345 + addiu $r3, -0x12345678 + .endif + + bgeiuc $r2, 1, test + bgeiuc $r2, 127, test + bltiuc $r2, 1, test + bltiuc $r2, 127, test + + extw $r4, $r2, $r3, 0 + extw $r4, $r2, $r3, 24 + extw $r4, $r2, $r3, 16 + extw $r4, $r2, $r3, 8 + extw $r4, $r2, $r3, 1 + extw $r4, $r2, $r3, 2 + extw $r4, $r2, $r3, 3 + extw $r4, $r2, $r3, 4 + + align $r4, $r2, $r3, 0 + align32 $r4, $r2, $r3, 0 + align $r4, $r2, $r3, 1 + align $r4, $r2, $r3, 2 + align $r4, $r2, $r3, 3 + + lwxs $r4, $r5($r6) + lwxs $r7, $r16($r17) + lwxs $r18, $r19($r4) + + sw $r16,%gprel(x)($r28) + sw $r17,16($r28) + .ifndef insn32 + sw16 $r17,16($r28) + sw16 $r17,%gprel(test)($r28) + .endif + lapc $r5,test + lapc $r5,test2 + .set at + pref 4,4000($r3) + pref 4,-30($r3) + pref 4,%lo(test)($r3) + + bbeqzc $r4,24,test + bbeqzc $r4,1,test + bbeqzc $r4,31,test + bbnezc $r4,0,test + bbnezc $r4,16,test + teq $r3,$r4 + tne $r5,$r6 + teq $r3,$r4,6 + tne $r5,$r6,7 + .ifndef insn32 + lwpc $r3, 10000 + swpc $r3, 10000 + lapc48 $r3, test + lwpc $r3, test + swpc $r3, test + .endif + + ualh $r2, 4($r5) + uash $r2, 4($r5) + ualwm $r2, 4($r5),4 + uaswm $r2, 4($r5),6 + ualw $r2, 4($r5) + uasw $r2, 4($r5) + ualwm $r2, 4($r5),8 + uaswm $r2, 4($r5),7 + + lwm $r2, 4($r5),8 + swm $r2, 4($r5),7 + + rotx $r2, $r3, 5, 30, 1 + rotx $r2, $r3, 31, 0 + bitrevw $r2,$r3 + rotx $r2, $r3, 7, 8, 1 + bitswap $r2,$r3 + bitrevb $r2,$r3 + rotx $r2, $r3, 15, 16 + bitrevh $r2,$r3 + rotx $r2, $r3, 24, 8 + byterevw $r2,$r3 + rotx $r2, $r3, 8, 24 + wsbh $r2,$r3 + byterevh $r2,$r3 + + addiupc $r5, 0 + addiupc $r5, 4 + addiupc $r5, 8 + .ifndef insn32 + addiupc48 $r5, 0 + addiupc48 $r5,6 + addiupc48 $r5,8 + .endif + addiupc $r5,2097154 + .ifndef insn32_broken + addiupc $r5,2097156 + .endif + addiupc $r5,-2097148 + .ifndef insn32_broken + addiupc $r5,-2097150 + .endif + + aluipc $r3,%pcrel_hi(test) + addiu $r3, $r3, %pcrel_lo(test) + aluipc $r3,0x25 + aluipc $r3,%hi(0x25000) + aluipc $r3,0x87654 + aluipc $r3,%hi(0x87654000) + + addu $r4, $r4, $r5 + addu $r8, $r8, $r10 + addu $r16, $r16, $r18 + addu $r20, $r20, $r23 + + addu $r5, $r5, $r11 + addu $r10, $r10, $r17 + addu $r19, $r19, $r22 + addu $r21, $r21, $r9 + + addu $r8, $r10, $r8 + addu $r20, $r23, $r20 + addu $r5, $r11, $r5 + addu $r10, $r17, $r10 + addu $r19, $r22, $r19 + addu $r21, $r9, $r21 + + mul $r6, $r6, $r7 + mul $r9, $r9, $r11 + mul $r17, $r17, $r19 + mul $r22, $r22, $r20 + + mul $r7, $r7, $r9 + mul $r11, $r11, $r16 + mul $r18, $r18, $r21 + mul $r23, $r23, $r8 + + mul $r6, $r7, $r6 + mul $r9, $r11, $r9 + mul $r17, $r19, $r17 + mul $r22, $r20, $r22 + + mul $r7, $r9, $r7 + mul $r11, $r16, $r11 + mul $r18, $r21, $r18 + mul $r23, $r8, $r23 + + beqc $r6, $r7, 1f + beqc $r6, $r6, 1f + beqc $r7, $r6, 1f + beqc $r6, $r0, 1f + nop32 +1: + bnec $r6, $r7, 2f + bnec $r6, $r6, 2f + bnec $r7, $r6, 2f + bnec $r6, $r0, 2f + nop32 +2: + eretnc + .end test diff --git a/gas/testsuite/gas/nanomips/nanomips-exc32.d b/gas/testsuite/gas/nanomips/nanomips-exc32.d new file mode 100644 index 00000000000..02daeeaa682 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips-exc32.d @@ -0,0 +1,198 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: New nanoMIPS instructions in 32-bit fixed instruction mode +#as: -minsn32 --defsym insn32= +#source: nanomips-exc.s + +# Check exclusive nanoMIPS 32-bit instructions + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 8508 8000 lw a4,0\(a4\) +[0-9a-f]+ <[^>]+> 8529 8004 lw a5,4\(a5\) +[0-9a-f]+ <[^>]+> 854a 8008 lw a6,8\(a6\) +[0-9a-f]+ <[^>]+> 856b 800c lw a7,12\(a7\) +[0-9a-f]+ <[^>]+> 8504 8000 lw a4,0\(a0\) +[0-9a-f]+ <[^>]+> 8525 8004 lw a5,4\(a1\) +[0-9a-f]+ <[^>]+> 8546 8008 lw a6,8\(a2\) +[0-9a-f]+ <[^>]+> 8567 800c lw a7,12\(a3\) +[0-9a-f]+ <[^>]+> 8510 8000 lw a4,0\(s0\) +[0-9a-f]+ <[^>]+> 8531 8004 lw a5,4\(s1\) +[0-9a-f]+ <[^>]+> 8552 8008 lw a6,8\(s2\) +[0-9a-f]+ <[^>]+> 8573 800c lw a7,12\(s3\) +[0-9a-f]+ <[^>]+> 8514 8000 lw a4,0\(s4\) +[0-9a-f]+ <[^>]+> 8535 8004 lw a5,4\(s5\) +[0-9a-f]+ <[^>]+> 8556 8008 lw a6,8\(s6\) +[0-9a-f]+ <[^>]+> 8577 800c lw a7,12\(s7\) +[0-9a-f]+ <[^>]+> 8488 8000 lw a0,0\(a4\) +[0-9a-f]+ <[^>]+> 84a9 8004 lw a1,4\(a5\) +[0-9a-f]+ <[^>]+> 84ca 8008 lw a2,8\(a6\) +[0-9a-f]+ <[^>]+> 84eb 800c lw a3,12\(a7\) +[0-9a-f]+ <[^>]+> 8608 9000 sw s0,0\(a4\) +[0-9a-f]+ <[^>]+> 8629 9004 sw s1,4\(a5\) +[0-9a-f]+ <[^>]+> 864a 9008 sw s2,8\(a6\) +[0-9a-f]+ <[^>]+> 866b 900c sw s3,12\(a7\) +[0-9a-f]+ <[^>]+> 8688 9000 sw s4,0\(a4\) +[0-9a-f]+ <[^>]+> 86a9 9004 sw s5,4\(a5\) +[0-9a-f]+ <[^>]+> 86ca 9008 sw s6,8\(a6\) +[0-9a-f]+ <[^>]+> 86eb 900c sw s7,12\(a7\) +[0-9a-f]+ <[^>]+> 8684 9000 sw s4,0\(a0\) +[0-9a-f]+ <[^>]+> 86a5 9004 sw s5,4\(a1\) +[0-9a-f]+ <[^>]+> 86c6 9008 sw s6,8\(a2\) +[0-9a-f]+ <[^>]+> 86e7 900c sw s7,12\(a3\) +[0-9a-f]+ <[^>]+> 8690 9000 sw s4,0\(s0\) +[0-9a-f]+ <[^>]+> 86b1 9004 sw s5,4\(s1\) +[0-9a-f]+ <[^>]+> 86d2 9008 sw s6,8\(s2\) +[0-9a-f]+ <[^>]+> 86f3 900c sw s7,12\(s3\) +[0-9a-f]+ <[^>]+> 8694 9000 sw s4,0\(s4\) +[0-9a-f]+ <[^>]+> 86b5 9004 sw s5,4\(s5\) +[0-9a-f]+ <[^>]+> 86d6 9008 sw s6,8\(s6\) +[0-9a-f]+ <[^>]+> 86f7 900c sw s7,12\(s7\) +[0-9a-f]+ <[^>]+> 8494 9000 sw a0,0\(s4\) +[0-9a-f]+ <[^>]+> 84b5 9004 sw a1,4\(s5\) +[0-9a-f]+ <[^>]+> 84d6 9008 sw a2,8\(s6\) +[0-9a-f]+ <[^>]+> 84f7 900c sw a3,12\(s7\) +[0-9a-f]+ <[^>]+> 8614 9000 sw s0,0\(s4\) +[0-9a-f]+ <[^>]+> 8635 9004 sw s1,4\(s5\) +[0-9a-f]+ <[^>]+> 8656 9008 sw s2,8\(s6\) +[0-9a-f]+ <[^>]+> 8677 900c sw s3,12\(s7\) +[0-9a-f]+ <[^>]+> 4803 8000 brsc t5 +[0-9a-f]+ <[^>]+> 481f 8000 brsc ra +[0-9a-f]+ <[^>]+> 4a11 8000 balrsc s0,s1 +[0-9a-f]+ <[^>]+> 4bf1 8000 balrsc ra,s1 +[0-9a-f]+ <[^>]+> 446d 2345 addiu t5,gp,74565 +[0-9a-f]+ <[^>]+> c84c 0800 bgeiuc t4,1,[0-9a-f]+ <[^>]+> + d4: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c84f f800 bgeiuc t4,127,[0-9a-f]+ <[^>]+> + d8: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c85c 0800 bltiuc t4,1,[0-9a-f]+ <[^>]+> + dc: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c85f f800 bltiuc t4,127,[0-9a-f]+ <[^>]+> + e0: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 2062 201f extw a0,t4,t5,0 +[0-9a-f]+ <[^>]+> 2062 261f extw a0,t4,t5,24 +[0-9a-f]+ <[^>]+> 2062 241f extw a0,t4,t5,16 +[0-9a-f]+ <[^>]+> 2062 221f extw a0,t4,t5,8 +[0-9a-f]+ <[^>]+> 2062 205f extw a0,t4,t5,1 +[0-9a-f]+ <[^>]+> 2062 209f extw a0,t4,t5,2 +[0-9a-f]+ <[^>]+> 2062 20df extw a0,t4,t5,3 +[0-9a-f]+ <[^>]+> 2062 211f extw a0,t4,t5,4 +[0-9a-f]+ <[^>]+> 2003 2290 move a0,t5 +[0-9a-f]+ <[^>]+> 2003 2290 move a0,t5 +[0-9a-f]+ <[^>]+> 2062 261f extw a0,t4,t5,24 +[0-9a-f]+ <[^>]+> 2062 241f extw a0,t4,t5,16 +[0-9a-f]+ <[^>]+> 2062 221f extw a0,t4,t5,8 +[0-9a-f]+ <[^>]+> 20c5 2447 lwxs a0,a1\(a2\) +[0-9a-f]+ <[^>]+> 2230 3c47 lwxs a3,s0\(s1\) +[0-9a-f]+ <[^>]+> 2093 9447 lwxs s2,s3\(a0\) +[0-9a-f]+ <[^>]+> 4200 0003 sw s0,0\(gp\) + 124: R_NANOMIPS_GPREL19_S2 x +[0-9a-f]+ <[^>]+> 4220 0013 sw s1,16\(gp\) +[0-9a-f]+ <[^>]+> 04a0 0000 lapc a1,00000000 <[^>]+> + 12c: R_NANOMIPS_PC21_S1 test +[0-9a-f]+ <[^>]+> 04a0 0000 lapc a1,00000000 <[^>]+> + 130: R_NANOMIPS_PC21_S1 test2 +[0-9a-f]+ <[^>]+> 8483 3fa0 pref 0x4,4000\(t5\) +[0-9a-f]+ <[^>]+> a483 98e2 pref 0x4,-30\(t5\) +[0-9a-f]+ <[^>]+> 8483 3000 pref 0x4,0\(t5\) + 13c: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> c884 c000 bbeqzc a0,24,[0-9a-f]+ <[^>]+> + 140: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c884 0800 bbeqzc a0,1,[0-9a-f]+ <[^>]+> + 144: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c884 f800 bbeqzc a0,31,[0-9a-f]+ <[^>]+> + 148: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c894 0000 bbnezc a0,0,[0-9a-f]+ <[^>]+> + 14c: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> c894 8000 bbnezc a0,16,[0-9a-f]+ <[^>]+> + 150: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 2083 0000 teq t5,a0 +[0-9a-f]+ <[^>]+> 20c5 0400 tne a1,a2 +[0-9a-f]+ <[^>]+> 2083 3000 teq t5,a0,0x6 +[0-9a-f]+ <[^>]+> 20c5 3c00 tne a1,a2,0x7 +[0-9a-f]+ <[^>]+> a445 2104 ualh t4,4\(a1\) +[0-9a-f]+ <[^>]+> a445 2904 uash t4,4\(a1\) +[0-9a-f]+ <[^>]+> a445 4504 ualwm t4,4\(a1\),4 +[0-9a-f]+ <[^>]+> a445 6d04 uaswm t4,4\(a1\),6 +[0-9a-f]+ <[^>]+> a445 1504 ualw t4,4\(a1\) +[0-9a-f]+ <[^>]+> a445 1d04 uasw t4,4\(a1\) +[0-9a-f]+ <[^>]+> a445 0504 ualwm t4,4\(a1\),8 +[0-9a-f]+ <[^>]+> a445 7d04 uaswm t4,4\(a1\),7 +[0-9a-f]+ <[^>]+> a445 0404 lwm t4,4\(a1\),8 +[0-9a-f]+ <[^>]+> a445 7c04 swm t4,4\(a1\),7 +[0-9a-f]+ <[^>]+> 8043 d7c5 rotx t4,t5,5,30,1 +[0-9a-f]+ <[^>]+> 8043 d01f bitrevw t4,t5 +[0-9a-f]+ <[^>]+> 8043 d01f bitrevw t4,t5 +[0-9a-f]+ <[^>]+> 8043 d247 bitrevb t4,t5 +[0-9a-f]+ <[^>]+> 8043 d247 bitrevb t4,t5 +[0-9a-f]+ <[^>]+> 8043 d247 bitrevb t4,t5 +[0-9a-f]+ <[^>]+> 8043 d40f bitrevh t4,t5 +[0-9a-f]+ <[^>]+> 8043 d40f bitrevh t4,t5 +[0-9a-f]+ <[^>]+> 8043 d218 byterevw t4,t5 +[0-9a-f]+ <[^>]+> 8043 d218 byterevw t4,t5 +[0-9a-f]+ <[^>]+> 8043 d608 byterevh t4,t5 +[0-9a-f]+ <[^>]+> 8043 d608 byterevh t4,t5 +[0-9a-f]+ <[^>]+> 8043 d608 byterevh t4,t5 +[0-9a-f]+ <[^>]+> 04bf fffd lapc a1,[0-9a-f]+ +[0-9a-f]+ <[^>]+> 04a0 0000 lapc a1,[0-9a-f]+ +[0-9a-f]+ <[^>]+> 04a0 0004 lapc a1,[0-9a-f]+ +[0-9a-f]+ <[^>]+> 04bf fffe lapc a1,[0-9a-f]+ <[^>]+> +[0-9a-f]+ <[^>]+> 04a0 0001 lapc a1,[0-9a-f]+ <[^>]+> +[0-9a-f]+ <[^>]+> e060 0002 aluipc t5,%pcrel_hi\(00000000 <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 test +[0-9a-f]+ <[^>]+> 0063 0000 addiu t5,t5,0 + [0-9a-f]+: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> e062 5002 aluipc t5,0x25 +[0-9a-f]+ <[^>]+> e062 5002 aluipc t5,0x25 +[0-9a-f]+ <[^>]+> e065 40ef aluipc t5,0x87654 +[0-9a-f]+ <[^>]+> e065 40ef aluipc t5,0x87654 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 2148 4150 addu a4,a4,a6 +[0-9a-f]+ <[^>]+> 2250 8150 addu s0,s0,s2 +[0-9a-f]+ <[^>]+> 22f4 a150 addu s4,s4,s7 +[0-9a-f]+ <[^>]+> 2165 2950 addu a1,a1,a7 +[0-9a-f]+ <[^>]+> 222a 5150 addu a6,a6,s1 +[0-9a-f]+ <[^>]+> 22d3 9950 addu s3,s3,s6 +[0-9a-f]+ <[^>]+> 2135 a950 addu s5,s5,a5 +[0-9a-f]+ <[^>]+> 210a 4150 addu a4,a6,a4 +[0-9a-f]+ <[^>]+> 2297 a150 addu s4,s7,s4 +[0-9a-f]+ <[^>]+> 20ab 2950 addu a1,a7,a1 +[0-9a-f]+ <[^>]+> 2151 5150 addu a6,s1,a6 +[0-9a-f]+ <[^>]+> 2276 9950 addu s3,s6,s3 +[0-9a-f]+ <[^>]+> 22a9 a950 addu s5,a5,s5 +[0-9a-f]+ <[^>]+> 20e6 3018 mul a2,a2,a3 +[0-9a-f]+ <[^>]+> 2169 4818 mul a5,a5,a7 +[0-9a-f]+ <[^>]+> 2271 8818 mul s1,s1,s3 +[0-9a-f]+ <[^>]+> 2296 b018 mul s6,s6,s4 +[0-9a-f]+ <[^>]+> 2127 3818 mul a3,a3,a5 +[0-9a-f]+ <[^>]+> 220b 5818 mul a7,a7,s0 +[0-9a-f]+ <[^>]+> 22b2 9018 mul s2,s2,s5 +[0-9a-f]+ <[^>]+> 2117 b818 mul s7,s7,a4 +[0-9a-f]+ <[^>]+> 20c7 3018 mul a2,a3,a2 +[0-9a-f]+ <[^>]+> 212b 4818 mul a5,a7,a5 +[0-9a-f]+ <[^>]+> 2233 8818 mul s1,s3,s1 +[0-9a-f]+ <[^>]+> 22d4 b018 mul s6,s4,s6 +[0-9a-f]+ <[^>]+> 20e9 3818 mul a3,a5,a3 +[0-9a-f]+ <[^>]+> 2170 5818 mul a7,s0,a7 +[0-9a-f]+ <[^>]+> 2255 9018 mul s2,s5,s2 +[0-9a-f]+ <[^>]+> 22e8 b818 mul s7,a4,s7 +[0-9a-f]+ <[^>]+> 88e6 0000 beqc a2,a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 88c6 0000 beqc a2,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 88c7 0000 beqc a3,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 8806 0000 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> a8e6 0000 bnec a2,a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> a8c6 0000 bnec a2,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> a8c7 0000 bnec a3,a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> a806 0000 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L2\^B1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 2001 f37f eretnc +#pass diff --git a/gas/testsuite/gas/nanomips/nanomips-subset.d b/gas/testsuite/gas/nanomips/nanomips-subset.d new file mode 100644 index 00000000000..3da359a0f83 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips-subset.d @@ -0,0 +1,37 @@ +#objdump: -dr --show-raw-insn +#name: nanoMIPS ISA instructions expanded to macros for NMS + +.*: +file format .*nanomips.* + +Disassembly of section .text: +00000000 : + 0: 8043 c011 sll t4,t5,17 + 4: 8042 c056 srl t4,t4,22 + 8: 8043 c001 sll t4,t5,1 + c: 8042 c041 srl t4,t4,1 + 10: 8043 c05f srl t4,t5,31 + 14: 83fe c05f srl ra,fp,31 + 18: 2042 115f extw t4,t4,t4,5 + 1c: 2062 13df extw t4,t4,t5,15 + 20: 2042 131f extw t4,t4,t4,12 + 24: 2042 141f extw t4,t4,t4,16 + 28: 2062 141f extw t4,t4,t5,16 + 2c: 1043 move t4,t5 + 2e: 2062 17df extw t4,t4,t5,31 + 32: 2042 105f extw t4,t4,t4,1 + 36: 2042 17df extw t4,t4,t4,31 + 3a: 2062 105f extw t4,t4,t5,1 + 3e: 2042 105f extw t4,t4,t4,1 + 42: 2062 17df extw t4,t4,t5,31 + 46: 2063 095f extw at,t5,t5,5 + 4a: 2061 1bdf extw t5,at,t5,15 + 4e: 2063 1b1f extw t5,t5,t5,12 + 52: 2063 0c1f extw at,t5,t5,16 + 56: 2061 1c1f extw t5,at,t5,16 + 5a: 9008 nop + 5c: 9008 nop + 5e: 2063 0fdf extw at,t5,t5,31 + 62: 2061 185f extw t5,at,t5,1 + 66: 2063 085f extw at,t5,t5,1 + 6a: 2061 1fdf extw t5,at,t5,31 +#pass diff --git a/gas/testsuite/gas/nanomips/nanomips-subset.s b/gas/testsuite/gas/nanomips/nanomips-subset.s new file mode 100644 index 00000000000..0166f8b68f0 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips-subset.s @@ -0,0 +1,23 @@ + .text + .ent test + .globl test +test: + ext $t4, $t5, 5, 10 + ext $t4, $t5, 0, 31 + ext $t4, $t5, 31, 1 + ext $ra, $fp, 31, 1 + /* INS instruction */ + ins $t4, $t5, 5, 15 + ins $t4, $t5, 16, 16 + ins $t4, $t5, 0, 32 /* MOVE */ + ins $t4, $t5, 0, 31 + ins $t4, $t5, 31, 1 + ins $t4, $t5, 1, 31 + /* INS with same source and destination */ + ins $t5, $t5, 5, 15 + ins $t5, $t5, 16, 16 + ins $t5, $t5, 0, 32 /* NOP */ + ins $t5, $t5, 0, 31 /* NOP */ + ins $t5, $t5, 31, 1 + ins $t5, $t5, 1, 31 + .end test diff --git a/gas/testsuite/gas/nanomips/nanomips.d b/gas/testsuite/gas/nanomips/nanomips.d new file mode 100644 index 00000000000..5f264fb2160 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips.d @@ -0,0 +1,2317 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS instructions +#warning_output: nanomips.l + +# Check nanoMIPS instructions + +.*: +file format .*nanomips.* + +Disassembly of section .text: +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 37ff pref 0x0,2047\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3800 pref 0x0,2048\(zero\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8420 3000 pref 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> 8440 3000 pref 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 3000 pref 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> 8480 3000 pref 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> 84a0 3000 pref 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> 84c0 3000 pref 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 3000 pref 0x7,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 31ff pref 0x7,511\(zero\) +[0-9a-f]+ <[^>]+> 8020 8200 li at,-512 +[0-9a-f]+ <[^>]+> a4e1 1800 pref 0x7,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 0022 7fff addiu at,t4,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2041 0950 addu at,at,t4 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 8000 c003 ehb +[0-9a-f]+ <[^>]+> 8000 c005 pause +[0-9a-f]+ <[^>]+> d17f li s2,-1 +[0-9a-f]+ <[^>]+> d1ff li s3,-1 +[0-9a-f]+ <[^>]+> d27f li a0,-1 +[0-9a-f]+ <[^>]+> d2ff li a1,-1 +[0-9a-f]+ <[^>]+> d37f li a2,-1 +[0-9a-f]+ <[^>]+> d3ff li a3,-1 +[0-9a-f]+ <[^>]+> d07f li s0,-1 +[0-9a-f]+ <[^>]+> d0ff li s1,-1 +[0-9a-f]+ <[^>]+> d080 li s1,0 +[0-9a-f]+ <[^>]+> d0fd li s1,125 +[0-9a-f]+ <[^>]+> d0fe li s1,126 +[0-9a-f]+ <[^>]+> 0220 007f li s1,127 +[0-9a-f]+ <[^>]+> 1180 move t0,zero +[0-9a-f]+ <[^>]+> 1320 move t9,zero +[0-9a-f]+ <[^>]+> 0040 0000 li t4,0 +[0-9a-f]+ <[^>]+> 0040 0001 li t4,1 +[0-9a-f]+ <[^>]+> 0040 7fff li t4,32767 +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 0040 ffff li t4,65535 +[0-9a-f]+ <[^>]+> e041 0000 lui t4,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 6040 8001 ffff li t4,0xffff8001 +[0-9a-f]+ <[^>]+> 8040 8001 li t4,-1 +[0-9a-f]+ <[^>]+> 6040 5678 1234 li t4,0x12345678 +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> d27f li a0,-1 +[0-9a-f]+ <[^>]+> 2016 0290 move zero,s6 +[0-9a-f]+ <[^>]+> 1056 move t4,s6 +[0-9a-f]+ <[^>]+> 1076 move t5,s6 +[0-9a-f]+ <[^>]+> 1096 move a0,s6 +[0-9a-f]+ <[^>]+> 10b6 move a1,s6 +[0-9a-f]+ <[^>]+> 10d6 move a2,s6 +[0-9a-f]+ <[^>]+> 10f6 move a3,s6 +[0-9a-f]+ <[^>]+> 1116 move a4,s6 +[0-9a-f]+ <[^>]+> 1136 move a5,s6 +[0-9a-f]+ <[^>]+> 1156 move a6,s6 +[0-9a-f]+ <[^>]+> 13d6 move fp,s6 +[0-9a-f]+ <[^>]+> 13f6 move ra,s6 +[0-9a-f]+ <[^>]+> 2000 0290 move zero,zero +[0-9a-f]+ <[^>]+> 2002 0290 move zero,t4 +[0-9a-f]+ <[^>]+> 2003 0290 move zero,t5 +[0-9a-f]+ <[^>]+> 2004 0290 move zero,a0 +[0-9a-f]+ <[^>]+> 2005 0290 move zero,a1 +[0-9a-f]+ <[^>]+> 2006 0290 move zero,a2 +[0-9a-f]+ <[^>]+> 2007 0290 move zero,a3 +[0-9a-f]+ <[^>]+> 2008 0290 move zero,a4 +[0-9a-f]+ <[^>]+> 2009 0290 move zero,a5 +[0-9a-f]+ <[^>]+> 200a 0290 move zero,a6 +[0-9a-f]+ <[^>]+> 201e 0290 move zero,fp +[0-9a-f]+ <[^>]+> 201f 0290 move zero,ra +[0-9a-f]+ <[^>]+> 12c2 move s6,t4 +[0-9a-f]+ <[^>]+> 1056 move t4,s6 +[0-9a-f]+ <[^>]+> 12c2 move s6,t4 +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC10_S1 test +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC10_S1 test +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1043 move t4,t5 +[0-9a-f]+ <[^>]+> 8803 8000 bgezc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_0 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 1044 move t4,a0 +[0-9a-f]+ <[^>]+> 8804 8000 bgezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_1 +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_2 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_3 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2083 1110 add t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e910 add sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0064 0000 addiu t5,a0,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 9018 addiu zero,zero,-8 +[0-9a-f]+ <[^>]+> 9058 addiu t4,t4,-8 +[0-9a-f]+ <[^>]+> 9078 addiu t5,t5,-8 +[0-9a-f]+ <[^>]+> 9098 addiu a0,a0,-8 +[0-9a-f]+ <[^>]+> 90b8 addiu a1,a1,-8 +[0-9a-f]+ <[^>]+> 90d8 addiu a2,a2,-8 +[0-9a-f]+ <[^>]+> 90f8 addiu a3,a3,-8 +[0-9a-f]+ <[^>]+> 9118 addiu a4,a4,-8 +[0-9a-f]+ <[^>]+> 9138 addiu a5,a5,-8 +[0-9a-f]+ <[^>]+> 9158 addiu a6,a6,-8 +[0-9a-f]+ <[^>]+> 93d8 addiu fp,fp,-8 +[0-9a-f]+ <[^>]+> 93f8 addiu ra,ra,-8 +[0-9a-f]+ <[^>]+> 93f9 addiu ra,ra,-7 +[0-9a-f]+ <[^>]+> 93e8 addiu ra,ra,0 +[0-9a-f]+ <[^>]+> 93e9 addiu ra,ra,1 +[0-9a-f]+ <[^>]+> 93ee addiu ra,ra,6 +[0-9a-f]+ <[^>]+> 93ef addiu ra,ra,7 +[0-9a-f]+ <[^>]+> 03ff 0008 addiu ra,ra,8 +[0-9a-f]+ <[^>]+> 83bd 8408 addiu sp,sp,-1032 +[0-9a-f]+ <[^>]+> 83bd 8404 addiu sp,sp,-1028 +[0-9a-f]+ <[^>]+> 83bd 8400 addiu sp,sp,-1024 +[0-9a-f]+ <[^>]+> 03bd 03fc addiu sp,sp,1020 +[0-9a-f]+ <[^>]+> 03bd 0400 addiu sp,sp,1024 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0408 addiu sp,sp,1032 +[0-9a-f]+ <[^>]+> 905f addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 8043 8001 addiu t4,t5,-1 +[0-9a-f]+ <[^>]+> 8044 8001 addiu t4,a0,-1 +[0-9a-f]+ <[^>]+> 8045 8001 addiu t4,a1,-1 +[0-9a-f]+ <[^>]+> 8046 8001 addiu t4,a2,-1 +[0-9a-f]+ <[^>]+> 8047 8001 addiu t4,a3,-1 +[0-9a-f]+ <[^>]+> 8050 8001 addiu t4,s0,-1 +[0-9a-f]+ <[^>]+> 8051 8001 addiu t4,s1,-1 +[0-9a-f]+ <[^>]+> 0051 0001 addiu t4,s1,1 +[0-9a-f]+ <[^>]+> 9111 addiu s2,s1,4 +[0-9a-f]+ <[^>]+> 9112 addiu s2,s1,8 +[0-9a-f]+ <[^>]+> 9113 addiu s2,s1,12 +[0-9a-f]+ <[^>]+> 9114 addiu s2,s1,16 +[0-9a-f]+ <[^>]+> 9115 addiu s2,s1,20 +[0-9a-f]+ <[^>]+> 9116 addiu s2,s1,24 +[0-9a-f]+ <[^>]+> 9196 addiu s3,s1,24 +[0-9a-f]+ <[^>]+> 9216 addiu a0,s1,24 +[0-9a-f]+ <[^>]+> 9296 addiu a1,s1,24 +[0-9a-f]+ <[^>]+> 9316 addiu a2,s1,24 +[0-9a-f]+ <[^>]+> 9396 addiu a3,s1,24 +[0-9a-f]+ <[^>]+> 9016 addiu s0,s1,24 +[0-9a-f]+ <[^>]+> 9096 addiu s1,s1,24 +[0-9a-f]+ <[^>]+> 7140 addiu s2,sp,0 +[0-9a-f]+ <[^>]+> 7141 addiu s2,sp,4 +[0-9a-f]+ <[^>]+> 717e addiu s2,sp,248 +[0-9a-f]+ <[^>]+> 717f addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 005d 0100 addiu t4,sp,256 +[0-9a-f]+ <[^>]+> 717f addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 71ff addiu s3,sp,252 +[0-9a-f]+ <[^>]+> 727f addiu a0,sp,252 +[0-9a-f]+ <[^>]+> 72ff addiu a1,sp,252 +[0-9a-f]+ <[^>]+> 737f addiu a2,sp,252 +[0-9a-f]+ <[^>]+> 73ff addiu a3,sp,252 +[0-9a-f]+ <[^>]+> 707f addiu s0,sp,252 +[0-9a-f]+ <[^>]+> 70ff addiu s1,sp,252 +[0-9a-f]+ <[^>]+> 8064 8fff addiu t5,a0,-4095 +[0-9a-f]+ <[^>]+> 91c0 addiu s3,a0,0 +[0-9a-f]+ <[^>]+> 0064 1fff addiu t5,a0,8191 +[0-9a-f]+ <[^>]+> 0064 3fff addiu t5,a0,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 2016 1150 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b150 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1150 addu t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b150 addu s6,zero,t4 +[0-9a-f]+ <[^>]+> b134 addu s2,s3,s2 +[0-9a-f]+ <[^>]+> b1b4 addu s2,s3,s3 +[0-9a-f]+ <[^>]+> b234 addu s2,s3,a0 +[0-9a-f]+ <[^>]+> b2b4 addu s2,s3,a1 +[0-9a-f]+ <[^>]+> b334 addu s2,s3,a2 +[0-9a-f]+ <[^>]+> b3b4 addu s2,s3,a3 +[0-9a-f]+ <[^>]+> b034 addu s2,s3,s0 +[0-9a-f]+ <[^>]+> b0b4 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> b0a4 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0b4 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> b0c4 addu s2,a0,s1 +[0-9a-f]+ <[^>]+> b0d4 addu s2,a1,s1 +[0-9a-f]+ <[^>]+> b0e4 addu s2,a2,s1 +[0-9a-f]+ <[^>]+> b0f4 addu s2,a3,s1 +[0-9a-f]+ <[^>]+> b084 addu s2,s0,s1 +[0-9a-f]+ <[^>]+> b094 addu s2,s1,s1 +[0-9a-f]+ <[^>]+> b0a4 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0a6 addu s3,s2,s1 +[0-9a-f]+ <[^>]+> b0a8 addu a0,s2,s1 +[0-9a-f]+ <[^>]+> b0aa addu a1,s2,s1 +[0-9a-f]+ <[^>]+> b0ac addu a2,s2,s1 +[0-9a-f]+ <[^>]+> b0ae addu a3,s2,s1 +[0-9a-f]+ <[^>]+> b0a0 addu s0,s2,s1 +[0-9a-f]+ <[^>]+> b0a2 addu s1,s2,s1 +[0-9a-f]+ <[^>]+> b17e addu a3,a3,s2 +[0-9a-f]+ <[^>]+> b17e addu a3,a3,s2 +[0-9a-f]+ <[^>]+> b3ae addu a3,s2,a3 +[0-9a-f]+ <[^>]+> 23fe e950 addu sp,fp,ra +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0042 0001 addiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0042 7fff addiu t4,t4,32767 +[0-9a-f]+ <[^>]+> 6041 8000 ffff addiu t4,t4,-32768 +[0-9a-f]+ <[^>]+> 0042 ffff addiu t4,t4,65535 +[0-9a-f]+ <[^>]+> 5128 and s2,s2,s2 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5148 and s2,s2,a0 +[0-9a-f]+ <[^>]+> 5158 and s2,s2,a1 +[0-9a-f]+ <[^>]+> 5168 and s2,s2,a2 +[0-9a-f]+ <[^>]+> 5178 and s2,s2,a3 +[0-9a-f]+ <[^>]+> 5108 and s2,s2,s0 +[0-9a-f]+ <[^>]+> 5118 and s2,s2,s1 +[0-9a-f]+ <[^>]+> 51a8 and s3,s3,s2 +[0-9a-f]+ <[^>]+> 5228 and a0,a0,s2 +[0-9a-f]+ <[^>]+> 52a8 and a1,a1,s2 +[0-9a-f]+ <[^>]+> 5328 and a2,a2,s2 +[0-9a-f]+ <[^>]+> 53a8 and a3,a3,s2 +[0-9a-f]+ <[^>]+> 5028 and s0,s0,s2 +[0-9a-f]+ <[^>]+> 50a8 and s1,s1,s2 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2062 1250 and t4,t4,t5 +[0-9a-f]+ <[^>]+> f121 andi s2,s2,0x1 +[0-9a-f]+ <[^>]+> f122 andi s2,s2,0x2 +[0-9a-f]+ <[^>]+> f123 andi s2,s2,0x3 +[0-9a-f]+ <[^>]+> f124 andi s2,s2,0x4 +[0-9a-f]+ <[^>]+> f127 andi s2,s2,0x7 +[0-9a-f]+ <[^>]+> f128 andi s2,s2,0x8 +[0-9a-f]+ <[^>]+> f12f andi s2,s2,0xf +[0-9a-f]+ <[^>]+> 8042 2010 andi t4,t4,0x10 +[0-9a-f]+ <[^>]+> 8042 201f andi t4,t4,0x1f +[0-9a-f]+ <[^>]+> 8042 2020 andi t4,t4,0x20 +[0-9a-f]+ <[^>]+> 8042 203f andi t4,t4,0x3f +[0-9a-f]+ <[^>]+> 8042 2040 andi t4,t4,0x40 +[0-9a-f]+ <[^>]+> 8042 2080 andi t4,t4,0x80 +[0-9a-f]+ <[^>]+> f12c andi s2,s2,0xff +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> f12d andi s2,s2,0xffff +[0-9a-f]+ <[^>]+> f13d andi s2,s3,0xffff +[0-9a-f]+ <[^>]+> f14d andi s2,a0,0xffff +[0-9a-f]+ <[^>]+> f15d andi s2,a1,0xffff +[0-9a-f]+ <[^>]+> f16d andi s2,a2,0xffff +[0-9a-f]+ <[^>]+> f17d andi s2,a3,0xffff +[0-9a-f]+ <[^>]+> f10d andi s2,s0,0xffff +[0-9a-f]+ <[^>]+> f11d andi s2,s1,0xffff +[0-9a-f]+ <[^>]+> f19d andi s3,s1,0xffff +[0-9a-f]+ <[^>]+> f21d andi a0,s1,0xffff +[0-9a-f]+ <[^>]+> f29d andi a1,s1,0xffff +[0-9a-f]+ <[^>]+> f31d andi a2,s1,0xffff +[0-9a-f]+ <[^>]+> f39d andi a3,s1,0xffff +[0-9a-f]+ <[^>]+> f01d andi s0,s1,0xffff +[0-9a-f]+ <[^>]+> f09d andi s1,s1,0xffff +[0-9a-f]+ <[^>]+> f3fd andi a3,a3,0xffff +[0-9a-f]+ <[^>]+> f3fd andi a3,a3,0xffff +[0-9a-f]+ <[^>]+> f3fd andi a3,a3,0xffff +[0-9a-f]+ <[^>]+> 2083 1250 and t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 2000 andi t4,t5,0x0 +[0-9a-f]+ <[^>]+> 8043 2fff andi t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> 6020 0001 ffff li at,0xffff0001 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> 9900 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9980 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a00 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a80 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b00 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b80 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9900 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9980 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a00 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a80 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b00 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b80 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9900 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9980 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a00 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a80 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b00 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b80 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> ca00 5000 beqic s0,10,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test2 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> b900 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b980 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba00 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba80 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb00 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb80 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b880 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b900 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b980 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba00 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba80 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb00 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb80 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b880 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b900 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b980 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba00 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba80 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb00 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb80 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b880 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 1010 break +[0-9a-f]+ <[^>]+> 1010 break +[0-9a-f]+ <[^>]+> 1011 break 0x1 +[0-9a-f]+ <[^>]+> 1012 break 0x2 +[0-9a-f]+ <[^>]+> 1013 break 0x3 +[0-9a-f]+ <[^>]+> 1014 break 0x4 +[0-9a-f]+ <[^>]+> 1015 break 0x5 +[0-9a-f]+ <[^>]+> 1016 break 0x6 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 0010 0008 break 0x8 +[0-9a-f]+ <[^>]+> 0010 0009 break 0x9 +[0-9a-f]+ <[^>]+> 0010 000a break 0xa +[0-9a-f]+ <[^>]+> 0010 000b break 0xb +[0-9a-f]+ <[^>]+> 0010 000c break 0xc +[0-9a-f]+ <[^>]+> 0010 000d break 0xd +[0-9a-f]+ <[^>]+> 0010 000e break 0xe +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0001 break 0x1 +[0-9a-f]+ <[^>]+> 0010 0002 break 0x2 +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a402 3900 cache 0x0,0\(t4\) +[0-9a-f]+ <[^>]+> 8022 8800 addiu at,t4,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 07ff addiu at,t4,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8022 8801 addiu at,t4,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 0800 addiu at,t4,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a420 3900 cache 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> a440 3900 cache 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> a460 3900 cache 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> a480 3900 cache 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> a4a0 3900 cache 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> a4c0 3900 cache 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> a7e0 3900 cache 0x1f,0\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0023 0800 addiu at,t5,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8023 8801 addiu at,t5,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e3 b9ff cache 0x1f,-1\(t5\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0023 ffff addiu at,t5,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e0 b9ff cache 0x1f,-1\(zero\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 2043 4b3f clo t4,t5 +[0-9a-f]+ <[^>]+> 2062 4b3f clo t5,t4 +[0-9a-f]+ <[^>]+> 2043 5b3f clz t4,t5 +[0-9a-f]+ <[^>]+> 2062 5b3f clz t5,t4 +[0-9a-f]+ <[^>]+> 2000 e37f deret +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2040 477f di t4 +[0-9a-f]+ <[^>]+> 2060 477f di t5 +[0-9a-f]+ <[^>]+> 23c0 477f di fp +[0-9a-f]+ <[^>]+> 23e0 477f di ra +[0-9a-f]+ <[^>]+> 2062 0118 div zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0118 div zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0118 div zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0118 div zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1118 div t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1118 div t4,t5,a0 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 1064 move t5,a0 +[0-9a-f]+ <[^>]+> 2080 1990 neg t5,a0 +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1918 div t5,a0,at +[0-9a-f]+ <[^>]+> 2062 0198 divu zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0198 divu zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0198 divu zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0198 divu zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1198 divu t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1198 divu t4,t5,a0 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 1064 move t5,a0 +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2040 577f ei t4 +[0-9a-f]+ <[^>]+> 2060 577f ei t5 +[0-9a-f]+ <[^>]+> 23c0 577f ei fp +[0-9a-f]+ <[^>]+> 23e0 577f ei ra +[0-9a-f]+ <[^>]+> 2000 f37f eret +[0-9a-f]+ <[^>]+> 8043 f385 ext t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 f7c0 ext t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 f01f ext t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe f01f ext ra,fp,31,1 +[0-9a-f]+ <[^>]+> 8043 e4c5 ins t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 e7c0 ins t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 e7df ins t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe e7df ins ra,fp,31,1 +[0-9a-f]+ <[^>]+> d800 jrc zero +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> d860 jrc t5 +[0-9a-f]+ <[^>]+> d880 jrc a0 +[0-9a-f]+ <[^>]+> d8a0 jrc a1 +[0-9a-f]+ <[^>]+> d8c0 jrc a2 +[0-9a-f]+ <[^>]+> d8e0 jrc a3 +[0-9a-f]+ <[^>]+> d900 jrc a4 +[0-9a-f]+ <[^>]+> dbc0 jrc fp +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> d800 jrc zero +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> d860 jrc t5 +[0-9a-f]+ <[^>]+> d880 jrc a0 +[0-9a-f]+ <[^>]+> d8a0 jrc a1 +[0-9a-f]+ <[^>]+> d8c0 jrc a2 +[0-9a-f]+ <[^>]+> d8e0 jrc a3 +[0-9a-f]+ <[^>]+> d900 jrc a4 +[0-9a-f]+ <[^>]+> dbc0 jrc fp +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 4800 1000 jrc.hb zero +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 4803 1000 jrc.hb t5 +[0-9a-f]+ <[^>]+> 4804 1000 jrc.hb a0 +[0-9a-f]+ <[^>]+> 4805 1000 jrc.hb a1 +[0-9a-f]+ <[^>]+> 4806 1000 jrc.hb a2 +[0-9a-f]+ <[^>]+> 4807 1000 jrc.hb a3 +[0-9a-f]+ <[^>]+> 4808 1000 jrc.hb a4 +[0-9a-f]+ <[^>]+> 481e 1000 jrc.hb fp +[0-9a-f]+ <[^>]+> 481f 1000 jrc.hb ra +[0-9a-f]+ <[^>]+> d800 jrc zero +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> d860 jrc t5 +[0-9a-f]+ <[^>]+> d880 jrc a0 +[0-9a-f]+ <[^>]+> d8a0 jrc a1 +[0-9a-f]+ <[^>]+> d8c0 jrc a2 +[0-9a-f]+ <[^>]+> d8e0 jrc a3 +[0-9a-f]+ <[^>]+> d900 jrc a4 +[0-9a-f]+ <[^>]+> dbc0 jrc fp +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> d810 jalrc zero +[0-9a-f]+ <[^>]+> d850 jalrc t4 +[0-9a-f]+ <[^>]+> d870 jalrc t5 +[0-9a-f]+ <[^>]+> d890 jalrc a0 +[0-9a-f]+ <[^>]+> d8b0 jalrc a1 +[0-9a-f]+ <[^>]+> d8d0 jalrc a2 +[0-9a-f]+ <[^>]+> d8f0 jalrc a3 +[0-9a-f]+ <[^>]+> d910 jalrc a4 +[0-9a-f]+ <[^>]+> dbd0 jalrc fp +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> d810 jalrc zero +[0-9a-f]+ <[^>]+> d850 jalrc t4 +[0-9a-f]+ <[^>]+> d870 jalrc t5 +[0-9a-f]+ <[^>]+> d890 jalrc a0 +[0-9a-f]+ <[^>]+> d8b0 jalrc a1 +[0-9a-f]+ <[^>]+> d8d0 jalrc a2 +[0-9a-f]+ <[^>]+> d8f0 jalrc a3 +[0-9a-f]+ <[^>]+> d910 jalrc a4 +[0-9a-f]+ <[^>]+> dbd0 jalrc fp +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> 4840 0000 jalrc t4,zero +[0-9a-f]+ <[^>]+> 4862 0000 jalrc t5,t4 +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4844 0000 jalrc t4,a0 +[0-9a-f]+ <[^>]+> 4845 0000 jalrc t4,a1 +[0-9a-f]+ <[^>]+> 4846 0000 jalrc t4,a2 +[0-9a-f]+ <[^>]+> 4847 0000 jalrc t4,a3 +[0-9a-f]+ <[^>]+> 4848 0000 jalrc t4,a4 +[0-9a-f]+ <[^>]+> 485e 0000 jalrc t4,fp +[0-9a-f]+ <[^>]+> 485f 0000 jalrc t4,ra +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4bdf 1000 jalrc.hb fp,ra +[0-9a-f]+ <[^>]+> 4840 1000 jalrc.hb t4,zero +[0-9a-f]+ <[^>]+> 4862 1000 jalrc.hb t5,t4 +[0-9a-f]+ <[^>]+> 4843 1000 jalrc.hb t4,t5 +[0-9a-f]+ <[^>]+> 4844 1000 jalrc.hb t4,a0 +[0-9a-f]+ <[^>]+> 4845 1000 jalrc.hb t4,a1 +[0-9a-f]+ <[^>]+> 4846 1000 jalrc.hb t4,a2 +[0-9a-f]+ <[^>]+> 4847 1000 jalrc.hb t4,a3 +[0-9a-f]+ <[^>]+> 4848 1000 jalrc.hb t4,a4 +[0-9a-f]+ <[^>]+> 485e 1000 jalrc.hb t4,fp +[0-9a-f]+ <[^>]+> 485f 1000 jalrc.hb t4,ra +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> d870 jalrc t5 +[0-9a-f]+ <[^>]+> dbf0 jalrc ra +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 test2 +[0-9a-f]+ <[^>]+> 6040 0000 0000 li t4,0x0 + [0-9a-f]+: R_NANOMIPS_I32 test +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 80ff lb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 5dc0 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 5dc0 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 0004 lb t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 80ff lb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a443 90ff lbu t4,-1\(t5\) +[0-9a-f]+ <[^>]+> 5d38 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 5d38 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 5d39 lbu s2,1\(s3\) +[0-9a-f]+ <[^>]+> 5d3a lbu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 5d3b lbu s2,3\(s3\) +[0-9a-f]+ <[^>]+> 8443 2004 lbu t4,4\(t5\) +[0-9a-f]+ <[^>]+> 8443 2005 lbu t4,5\(t5\) +[0-9a-f]+ <[^>]+> 8443 2006 lbu t4,6\(t5\) +[0-9a-f]+ <[^>]+> 8443 2007 lbu t4,7\(t5\) +[0-9a-f]+ <[^>]+> 8443 2008 lbu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 2009 lbu t4,9\(t5\) +[0-9a-f]+ <[^>]+> 8443 200a lbu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 200b lbu t4,11\(t5\) +[0-9a-f]+ <[^>]+> 8443 200c lbu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 200d lbu t4,13\(t5\) +[0-9a-f]+ <[^>]+> 8443 200e lbu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8442 200e lbu t4,14\(t4\) +[0-9a-f]+ <[^>]+> 8444 200e lbu t4,14\(a0\) +[0-9a-f]+ <[^>]+> 8445 200e lbu t4,14\(a1\) +[0-9a-f]+ <[^>]+> 8446 200e lbu t4,14\(a2\) +[0-9a-f]+ <[^>]+> 8447 200e lbu t4,14\(a3\) +[0-9a-f]+ <[^>]+> 8450 200e lbu t4,14\(s0\) +[0-9a-f]+ <[^>]+> 8451 200e lbu t4,14\(s1\) +[0-9a-f]+ <[^>]+> 8471 200e lbu t5,14\(s1\) +[0-9a-f]+ <[^>]+> 8491 200e lbu a0,14\(s1\) +[0-9a-f]+ <[^>]+> 84b1 200e lbu a1,14\(s1\) +[0-9a-f]+ <[^>]+> 84d1 200e lbu a2,14\(s1\) +[0-9a-f]+ <[^>]+> 84f1 200e lbu a3,14\(s1\) +[0-9a-f]+ <[^>]+> 8611 200e lbu s0,14\(s1\) +[0-9a-f]+ <[^>]+> 8631 200e lbu s1,14\(s1\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 90ff lbu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 5dc8 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 5dc8 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 2004 lbu t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 90ff lbu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 a0ff lh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 7dc0 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dc0 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dc4 lh s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 a0ff lh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 7d38 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d38 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d3a lhu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 7d3c lhu s2,4\(s3\) +[0-9a-f]+ <[^>]+> 7d3e lhu s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 6008 lhu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 600a lhu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 600c lhu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 600e lhu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 6010 lhu t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 6012 lhu t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 6014 lhu t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 6016 lhu t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 6018 lhu t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 601a lhu t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 601c lhu t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 601e lhu t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 601e lhu t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 601e lhu t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 601e lhu t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 601e lhu t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 601e lhu t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 601e lhu t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 601e lhu t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 601e lhu t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 601e lhu a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 601e lhu a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 601e lhu a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 601e lhu a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8611 601e lhu s0,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 601e lhu s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 b0ff lhu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 7dc8 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dc8 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dcc lhu s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 b0ff lhu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 6060 5678 1234 li t5,0x12345678 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5104 ll t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8064 8001 addiu t5,a0,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 6060 5678 1234 li t5,0x12345678 +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e060 0000 lui t5,0x0 +[0-9a-f]+ <[^>]+> e07f 0ffc lui t5,%hi\(0x7fff0000\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 1540 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 1540 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 1541 lw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 1542 lw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 1543 lw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 1544 lw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 1545 lw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 1546 lw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 1547 lw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 1548 lw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 1549 lw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 154a lw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 154b lw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 154c lw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 154d lw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 154e lw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 154f lw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 155f lw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 156f lw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 157f lw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 152f lw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 153f lw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 150f lw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 151f lw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 159f lw s3,60\(s1\) +[0-9a-f]+ <[^>]+> 161f lw a0,60\(s1\) +[0-9a-f]+ <[^>]+> 169f lw a1,60\(s1\) +[0-9a-f]+ <[^>]+> 171f lw a2,60\(s1\) +[0-9a-f]+ <[^>]+> 179f lw a3,60\(s1\) +[0-9a-f]+ <[^>]+> 141f lw s0,60\(s1\) +[0-9a-f]+ <[^>]+> 149f lw s1,60\(s1\) +[0-9a-f]+ <[^>]+> 3480 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 3480 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 3481 lw a0,4\(sp\) +[0-9a-f]+ <[^>]+> 3482 lw a0,8\(sp\) +[0-9a-f]+ <[^>]+> 3483 lw a0,12\(sp\) +[0-9a-f]+ <[^>]+> 3484 lw a0,16\(sp\) +[0-9a-f]+ <[^>]+> 3485 lw a0,20\(sp\) +[0-9a-f]+ <[^>]+> 349f lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 345f lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 345f lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 347f lw t5,124\(sp\) +[0-9a-f]+ <[^>]+> 349f lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 34bf lw a1,124\(sp\) +[0-9a-f]+ <[^>]+> 34df lw a2,124\(sp\) +[0-9a-f]+ <[^>]+> 34ff lw a3,124\(sp\) +[0-9a-f]+ <[^>]+> 351f lw a4,124\(sp\) +[0-9a-f]+ <[^>]+> 353f lw a5,124\(sp\) +[0-9a-f]+ <[^>]+> 355f lw a6,124\(sp\) +[0-9a-f]+ <[^>]+> 37df lw fp,124\(sp\) +[0-9a-f]+ <[^>]+> 37ff lw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 81f8 lw a0,504\(sp\) +[0-9a-f]+ <[^>]+> 849d 81fc lw a0,508\(sp\) +[0-9a-f]+ <[^>]+> 861d 81fc lw s0,508\(sp\) +[0-9a-f]+ <[^>]+> 863d 81fc lw s1,508\(sp\) +[0-9a-f]+ <[^>]+> 865d 81fc lw s2,508\(sp\) +[0-9a-f]+ <[^>]+> 867d 81fc lw s3,508\(sp\) +[0-9a-f]+ <[^>]+> 869d 81fc lw s4,508\(sp\) +[0-9a-f]+ <[^>]+> 86bd 81fc lw s5,508\(sp\) +[0-9a-f]+ <[^>]+> 87fd 81fc lw ra,508\(sp\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 c0ff lw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 15c0 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 15c0 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 15c1 lw s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 c0ff lw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 52c7 lwxs s3,a0\(a1\) +[0-9a-f]+ <[^>]+> 2040 0030 mfc0 t4,index +[0-9a-f]+ <[^>]+> 2041 0030 mfc0 t4,random +[0-9a-f]+ <[^>]+> 2042 0830 mfc0 t4,tcstatus +[0-9a-f]+ <[^>]+> 2042 1030 mfc0 t4,tcbind +[0-9a-f]+ <[^>]+> 2043 0070 mtc0 t4,entrylo1 +[0-9a-f]+ <[^>]+> 2044 0070 mtc0 t4,context +[0-9a-f]+ <[^>]+> 2045 3070 mtc0 t4,pwfield +[0-9a-f]+ <[^>]+> 2045 3870 mtc0 t4,pwsize +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1610 movn t4,t5,a0 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1210 movz t4,t5,a0 +[0-9a-f]+ <[^>]+> 2083 1018 mul t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e818 mul sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 2060 1190 neg t4,t5 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 5120 not s2,s2 +[0-9a-f]+ <[^>]+> 5120 not s2,s2 +[0-9a-f]+ <[^>]+> 5130 not s2,s3 +[0-9a-f]+ <[^>]+> 5140 not s2,a0 +[0-9a-f]+ <[^>]+> 5150 not s2,a1 +[0-9a-f]+ <[^>]+> 5160 not s2,a2 +[0-9a-f]+ <[^>]+> 5170 not s2,a3 +[0-9a-f]+ <[^>]+> 5100 not s2,s0 +[0-9a-f]+ <[^>]+> 5110 not s2,s1 +[0-9a-f]+ <[^>]+> 5190 not s3,s1 +[0-9a-f]+ <[^>]+> 5210 not a0,s1 +[0-9a-f]+ <[^>]+> 5290 not a1,s1 +[0-9a-f]+ <[^>]+> 5310 not a2,s1 +[0-9a-f]+ <[^>]+> 5390 not a3,s1 +[0-9a-f]+ <[^>]+> 5010 not s0,s1 +[0-9a-f]+ <[^>]+> 5090 not s1,s1 +[0-9a-f]+ <[^>]+> 2007 12d0 not t4,a3 +[0-9a-f]+ <[^>]+> 20e0 12d0 nor t4,zero,a3 +[0-9a-f]+ <[^>]+> 2083 12d0 nor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ead0 nor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1290 or t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b290 or s6,zero,t4 +[0-9a-f]+ <[^>]+> 512c or s2,s2,s2 +[0-9a-f]+ <[^>]+> 513c or s2,s2,s3 +[0-9a-f]+ <[^>]+> 514c or s2,s2,a0 +[0-9a-f]+ <[^>]+> 515c or s2,s2,a1 +[0-9a-f]+ <[^>]+> 516c or s2,s2,a2 +[0-9a-f]+ <[^>]+> 517c or s2,s2,a3 +[0-9a-f]+ <[^>]+> 510c or s2,s2,s0 +[0-9a-f]+ <[^>]+> 511c or s2,s2,s1 +[0-9a-f]+ <[^>]+> 51ac or s3,s3,s2 +[0-9a-f]+ <[^>]+> 522c or a0,a0,s2 +[0-9a-f]+ <[^>]+> 52ac or a1,a1,s2 +[0-9a-f]+ <[^>]+> 532c or a2,a2,s2 +[0-9a-f]+ <[^>]+> 53ac or a3,a3,s2 +[0-9a-f]+ <[^>]+> 502c or s0,s0,s2 +[0-9a-f]+ <[^>]+> 50ac or s1,s1,s2 +[0-9a-f]+ <[^>]+> 512c or s2,s2,s2 +[0-9a-f]+ <[^>]+> 513c or s2,s2,s3 +[0-9a-f]+ <[^>]+> 513c or s2,s2,s3 +[0-9a-f]+ <[^>]+> 2083 1290 or t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ea90 or sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8043 0fff ori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8064 0000 ori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8064 0fff ori t5,a0,0xfff +[0-9a-f]+ <[^>]+> 2040 01c0 rdhwr t4,hwr_cpunum +[0-9a-f]+ <[^>]+> 2041 01c0 rdhwr t4,hwr_synci_step +[0-9a-f]+ <[^>]+> 2042 01c0 rdhwr t4,hwr_cc +[0-9a-f]+ <[^>]+> 2043 01c0 rdhwr t4,hwr_ccres +[0-9a-f]+ <[^>]+> 2044 01c0 rdhwr t4,hwr_perfcnt +[0-9a-f]+ <[^>]+> 2045 01c0 rdhwr t4,hwr_xnp +[0-9a-f]+ <[^>]+> 2046 01c0 rdhwr t4,\$6 +[0-9a-f]+ <[^>]+> 2047 01c0 rdhwr t4,\$7 +[0-9a-f]+ <[^>]+> 2048 01c0 rdhwr t4,\$8 +[0-9a-f]+ <[^>]+> 2049 01c0 rdhwr t4,\$9 +[0-9a-f]+ <[^>]+> 204a 01c0 rdhwr t4,\$10 +[0-9a-f]+ <[^>]+> 2043 e17f rdpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2042 e17f rdpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2062 0158 mod zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0158 mod zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0158 mod zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0158 mod zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1158 mod t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1158 mod t4,t5,a0 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 1060 move t5,zero +[0-9a-f]+ <[^>]+> 1060 move t5,zero +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1958 mod t5,a0,at +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2080 09d0 negu at,a0 +[0-9a-f]+ <[^>]+> 2022 10d0 rotrv t4,t4,at +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 5c34 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 5c34 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 5c35 sb zero,1\(s3\) +[0-9a-f]+ <[^>]+> 5c36 sb zero,2\(s3\) +[0-9a-f]+ <[^>]+> 5c37 sb zero,3\(s3\) +[0-9a-f]+ <[^>]+> 8403 1004 sb zero,4\(t5\) +[0-9a-f]+ <[^>]+> 8403 1005 sb zero,5\(t5\) +[0-9a-f]+ <[^>]+> 8403 1006 sb zero,6\(t5\) +[0-9a-f]+ <[^>]+> 8403 1007 sb zero,7\(t5\) +[0-9a-f]+ <[^>]+> 8403 1008 sb zero,8\(t5\) +[0-9a-f]+ <[^>]+> 8403 1009 sb zero,9\(t5\) +[0-9a-f]+ <[^>]+> 8403 100a sb zero,10\(t5\) +[0-9a-f]+ <[^>]+> 8403 100b sb zero,11\(t5\) +[0-9a-f]+ <[^>]+> 8403 100c sb zero,12\(t5\) +[0-9a-f]+ <[^>]+> 8403 100d sb zero,13\(t5\) +[0-9a-f]+ <[^>]+> 8403 100e sb zero,14\(t5\) +[0-9a-f]+ <[^>]+> 8403 100f sb zero,15\(t5\) +[0-9a-f]+ <[^>]+> 8443 100f sb t4,15\(t5\) +[0-9a-f]+ <[^>]+> 8463 100f sb t5,15\(t5\) +[0-9a-f]+ <[^>]+> 8483 100f sb a0,15\(t5\) +[0-9a-f]+ <[^>]+> 84a3 100f sb a1,15\(t5\) +[0-9a-f]+ <[^>]+> 84c3 100f sb a2,15\(t5\) +[0-9a-f]+ <[^>]+> 84e3 100f sb a3,15\(t5\) +[0-9a-f]+ <[^>]+> 8623 100f sb s1,15\(t5\) +[0-9a-f]+ <[^>]+> 8624 100f sb s1,15\(a0\) +[0-9a-f]+ <[^>]+> 8625 100f sb s1,15\(a1\) +[0-9a-f]+ <[^>]+> 8626 100f sb s1,15\(a2\) +[0-9a-f]+ <[^>]+> 8627 100f sb s1,15\(a3\) +[0-9a-f]+ <[^>]+> 8622 100f sb s1,15\(t4\) +[0-9a-f]+ <[^>]+> 8630 100f sb s1,15\(s0\) +[0-9a-f]+ <[^>]+> 8631 100f sb s1,15\(s1\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1fff sb t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 88ff sb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1fff sb t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 88ff sb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 6020 5678 1234 li at,0x12345678 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> 0024 07ff addiu at,a0,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8800 addiu at,a0,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 7fff addiu at,a0,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8001 addiu at,a0,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 6020 5678 1234 li at,0x12345678 +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 1018 sdbbp +[0-9a-f]+ <[^>]+> 1018 sdbbp +[0-9a-f]+ <[^>]+> 1019 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 101a sdbbp 0x2 +[0-9a-f]+ <[^>]+> 101b sdbbp 0x3 +[0-9a-f]+ <[^>]+> 101c sdbbp 0x4 +[0-9a-f]+ <[^>]+> 101d sdbbp 0x5 +[0-9a-f]+ <[^>]+> 101e sdbbp 0x6 +[0-9a-f]+ <[^>]+> 101f sdbbp 0x7 +[0-9a-f]+ <[^>]+> 0018 0008 sdbbp 0x8 +[0-9a-f]+ <[^>]+> 0018 0009 sdbbp 0x9 +[0-9a-f]+ <[^>]+> 0018 000a sdbbp 0xa +[0-9a-f]+ <[^>]+> 0018 000b sdbbp 0xb +[0-9a-f]+ <[^>]+> 0018 000c sdbbp 0xc +[0-9a-f]+ <[^>]+> 0018 000d sdbbp 0xd +[0-9a-f]+ <[^>]+> 0018 000e sdbbp 0xe +[0-9a-f]+ <[^>]+> 0018 000f sdbbp 0xf +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0001 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 0018 0002 sdbbp 0x2 +[0-9a-f]+ <[^>]+> 0018 00ff sdbbp 0xff +[0-9a-f]+ <[^>]+> 2043 0008 seb t4,t5 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2043 0048 seh t4,t5 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8044 5001 sltiu t4,a0,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 6001 seqi t4,t5,1 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 7d31 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d31 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d33 sh s2,2\(s3\) +[0-9a-f]+ <[^>]+> 7d35 sh s2,4\(s3\) +[0-9a-f]+ <[^>]+> 7d37 sh s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 5008 sh t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 500a sh t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 500c sh t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 500e sh t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 5010 sh t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 5012 sh t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 5014 sh t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 5016 sh t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 5018 sh t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 501a sh t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 501c sh t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 501e sh t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 501e sh t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 501e sh t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 501e sh t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 501e sh t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 501e sh t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 501e sh t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 501e sh t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 501e sh t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 501e sh a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 501e sh a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 501e sh a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 501e sh a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 501e sh s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8411 501e sh zero,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5fff sh t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 a8ff sh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5fff sh t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 a8ff sh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 3121 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 3122 sll s2,s2,2 +[0-9a-f]+ <[^>]+> 3123 sll s2,s2,3 +[0-9a-f]+ <[^>]+> 3124 sll s2,s2,4 +[0-9a-f]+ <[^>]+> 3125 sll s2,s2,5 +[0-9a-f]+ <[^>]+> 3126 sll s2,s2,6 +[0-9a-f]+ <[^>]+> 3127 sll s2,s2,7 +[0-9a-f]+ <[^>]+> 3120 sll s2,s2,8 +[0-9a-f]+ <[^>]+> 3130 sll s2,s3,8 +[0-9a-f]+ <[^>]+> 3140 sll s2,a0,8 +[0-9a-f]+ <[^>]+> 3150 sll s2,a1,8 +[0-9a-f]+ <[^>]+> 3160 sll s2,a2,8 +[0-9a-f]+ <[^>]+> 3170 sll s2,a3,8 +[0-9a-f]+ <[^>]+> 3100 sll s2,s0,8 +[0-9a-f]+ <[^>]+> 3110 sll s2,s1,8 +[0-9a-f]+ <[^>]+> 31a0 sll s3,s2,8 +[0-9a-f]+ <[^>]+> 3220 sll a0,s2,8 +[0-9a-f]+ <[^>]+> 32a0 sll a1,s2,8 +[0-9a-f]+ <[^>]+> 3320 sll a2,s2,8 +[0-9a-f]+ <[^>]+> 33a0 sll a3,s2,8 +[0-9a-f]+ <[^>]+> 3020 sll s0,s2,8 +[0-9a-f]+ <[^>]+> 30a0 sll s1,s2,8 +[0-9a-f]+ <[^>]+> 3121 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 31b1 sll s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1010 sllv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c000 sll t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c001 sll t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c01f sll t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8064 4000 slti t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 4fff slti t5,a0,4095 +[0-9a-f]+ <[^>]+> 8064 5000 sltiu t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 5fff sltiu t5,a0,4095 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2080 1390 sltu t4,zero,a0 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 8043 1001 xori t4,t5,0x1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2083 1090 srav t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c080 sra t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c081 sra t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c09f sra t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1050 srlv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c040 srl t4,a0,0 +[0-9a-f]+ <[^>]+> 3149 srl s2,a0,1 +[0-9a-f]+ <[^>]+> 8044 c05f srl t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 3129 srl s2,s2,1 +[0-9a-f]+ <[^>]+> 312a srl s2,s2,2 +[0-9a-f]+ <[^>]+> 312b srl s2,s2,3 +[0-9a-f]+ <[^>]+> 312c srl s2,s2,4 +[0-9a-f]+ <[^>]+> 312d srl s2,s2,5 +[0-9a-f]+ <[^>]+> 312e srl s2,s2,6 +[0-9a-f]+ <[^>]+> 312f srl s2,s2,7 +[0-9a-f]+ <[^>]+> 3128 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 3138 srl s2,s3,8 +[0-9a-f]+ <[^>]+> 3148 srl s2,a0,8 +[0-9a-f]+ <[^>]+> 3158 srl s2,a1,8 +[0-9a-f]+ <[^>]+> 3168 srl s2,a2,8 +[0-9a-f]+ <[^>]+> 3178 srl s2,a3,8 +[0-9a-f]+ <[^>]+> 3108 srl s2,s0,8 +[0-9a-f]+ <[^>]+> 3118 srl s2,s1,8 +[0-9a-f]+ <[^>]+> 3128 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 31a8 srl s3,s2,8 +[0-9a-f]+ <[^>]+> 3228 srl a0,s2,8 +[0-9a-f]+ <[^>]+> 32a8 srl a1,s2,8 +[0-9a-f]+ <[^>]+> 3328 srl a2,s2,8 +[0-9a-f]+ <[^>]+> 33a8 srl a3,s2,8 +[0-9a-f]+ <[^>]+> 3028 srl s0,s2,8 +[0-9a-f]+ <[^>]+> 30a8 srl s1,s2,8 +[0-9a-f]+ <[^>]+> 31b9 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 31b9 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1190 sub t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e990 sub sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> b135 subu s2,s3,s2 +[0-9a-f]+ <[^>]+> b1b5 subu s2,s3,s3 +[0-9a-f]+ <[^>]+> b235 subu s2,s3,a0 +[0-9a-f]+ <[^>]+> b2b5 subu s2,s3,a1 +[0-9a-f]+ <[^>]+> b335 subu s2,s3,a2 +[0-9a-f]+ <[^>]+> b3b5 subu s2,s3,a3 +[0-9a-f]+ <[^>]+> b035 subu s2,s3,s0 +[0-9a-f]+ <[^>]+> b0b5 subu s2,s3,s1 +[0-9a-f]+ <[^>]+> b0a5 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0c5 subu s2,a0,s1 +[0-9a-f]+ <[^>]+> b0d5 subu s2,a1,s1 +[0-9a-f]+ <[^>]+> b0e5 subu s2,a2,s1 +[0-9a-f]+ <[^>]+> b0f5 subu s2,a3,s1 +[0-9a-f]+ <[^>]+> b085 subu s2,s0,s1 +[0-9a-f]+ <[^>]+> b095 subu s2,s1,s1 +[0-9a-f]+ <[^>]+> b0a5 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0a7 subu s3,s2,s1 +[0-9a-f]+ <[^>]+> b0a9 subu a0,s2,s1 +[0-9a-f]+ <[^>]+> b0ab subu a1,s2,s1 +[0-9a-f]+ <[^>]+> b0ad subu a2,s2,s1 +[0-9a-f]+ <[^>]+> b0af subu a3,s2,s1 +[0-9a-f]+ <[^>]+> b0a1 subu s0,s2,s1 +[0-9a-f]+ <[^>]+> b0a3 subu s1,s2,s1 +[0-9a-f]+ <[^>]+> b17f subu a3,a3,s2 +[0-9a-f]+ <[^>]+> b17f subu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2083 11d0 subu t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e9d0 subu sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 8042 8001 addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 6041 8001 ffff addiu t4,t4,-32767 +[0-9a-f]+ <[^>]+> 0042 8000 addiu t4,t4,32768 +[0-9a-f]+ <[^>]+> 6041 0001 ffff addiu t4,t4,-65535 +[0-9a-f]+ <[^>]+> 9540 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 9540 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 9541 sw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 9542 sw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 9543 sw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 9544 sw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 9545 sw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 9546 sw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 9547 sw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 9548 sw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 9549 sw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 954a sw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 954b sw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 954c sw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 954d sw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 954e sw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 954f sw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 955f sw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 956f sw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 957f sw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 950f sw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 951f sw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 952f sw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 953f sw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 95bf sw s3,60\(s3\) +[0-9a-f]+ <[^>]+> 963f sw a0,60\(s3\) +[0-9a-f]+ <[^>]+> 96bf sw a1,60\(s3\) +[0-9a-f]+ <[^>]+> 973f sw a2,60\(s3\) +[0-9a-f]+ <[^>]+> 97bf sw a3,60\(s3\) +[0-9a-f]+ <[^>]+> 94bf sw s1,60\(s3\) +[0-9a-f]+ <[^>]+> 943f sw zero,60\(s3\) +[0-9a-f]+ <[^>]+> b400 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> b400 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> b401 sw zero,4\(sp\) +[0-9a-f]+ <[^>]+> b402 sw zero,8\(sp\) +[0-9a-f]+ <[^>]+> b403 sw zero,12\(sp\) +[0-9a-f]+ <[^>]+> b404 sw zero,16\(sp\) +[0-9a-f]+ <[^>]+> b405 sw zero,20\(sp\) +[0-9a-f]+ <[^>]+> b41e sw zero,120\(sp\) +[0-9a-f]+ <[^>]+> b41f sw zero,124\(sp\) +[0-9a-f]+ <[^>]+> b45f sw t4,124\(sp\) +[0-9a-f]+ <[^>]+> b63f sw s1,124\(sp\) +[0-9a-f]+ <[^>]+> b47f sw t5,124\(sp\) +[0-9a-f]+ <[^>]+> b49f sw a0,124\(sp\) +[0-9a-f]+ <[^>]+> b4bf sw a1,124\(sp\) +[0-9a-f]+ <[^>]+> b4df sw a2,124\(sp\) +[0-9a-f]+ <[^>]+> b4ff sw a3,124\(sp\) +[0-9a-f]+ <[^>]+> b7ff sw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9fff sw t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 c8ff sw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9fff sw t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 c8ff sw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8001 c006 sync 0x1 +[0-9a-f]+ <[^>]+> 8002 c006 sync 0x2 +[0-9a-f]+ <[^>]+> 8003 c006 sync 0x3 +[0-9a-f]+ <[^>]+> 8005 c006 sync 0x5 +[0-9a-f]+ <[^>]+> 801e c006 sync 0x1e +[0-9a-f]+ <[^>]+> 801f c006 sync 0x1f +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 37ff synci 2047\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3800 synci 2048\(zero\) +[0-9a-f]+ <[^>]+> 87e2 3000 synci 0\(t4\) +[0-9a-f]+ <[^>]+> 87e3 3000 synci 0\(t5\) +[0-9a-f]+ <[^>]+> 87e3 30ff synci 255\(t5\) +[0-9a-f]+ <[^>]+> a7e3 9800 synci -256\(t5\) +[0-9a-f]+ <[^>]+> 87e3 3800 synci 2048\(t5\) +[0-9a-f]+ <[^>]+> 1008 syscall +[0-9a-f]+ <[^>]+> 1008 syscall +[0-9a-f]+ <[^>]+> 1009 syscall 0x1 +[0-9a-f]+ <[^>]+> 100a syscall 0x2 +[0-9a-f]+ <[^>]+> 0008 00ff syscall 0xff +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2001 c37f wait 0x1 +[0-9a-f]+ <[^>]+> 20ff c37f wait 0xff +[0-9a-f]+ <[^>]+> 2043 f17f wrpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2044 f17f wrpgpr t4,a0 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 8043 d608 byterevh t4,t5 +[0-9a-f]+ <[^>]+> 8044 d608 byterevh t4,a0 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 5124 xor s2,s2,s2 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 5144 xor s2,s2,a0 +[0-9a-f]+ <[^>]+> 5154 xor s2,s2,a1 +[0-9a-f]+ <[^>]+> 5164 xor s2,s2,a2 +[0-9a-f]+ <[^>]+> 5174 xor s2,s2,a3 +[0-9a-f]+ <[^>]+> 5104 xor s2,s2,s0 +[0-9a-f]+ <[^>]+> 5114 xor s2,s2,s1 +[0-9a-f]+ <[^>]+> 5194 xor s3,s3,s1 +[0-9a-f]+ <[^>]+> 5214 xor a0,a0,s1 +[0-9a-f]+ <[^>]+> 5294 xor a1,a1,s1 +[0-9a-f]+ <[^>]+> 5314 xor a2,a2,s1 +[0-9a-f]+ <[^>]+> 5394 xor a3,a3,s1 +[0-9a-f]+ <[^>]+> 5014 xor s0,s0,s1 +[0-9a-f]+ <[^>]+> 5094 xor s1,s1,s1 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe eb10 xor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8043 1fff xori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8064 1000 xori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8063 1fff xori t5,t5,0xfff +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8949 0000 beqc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c920 0800 beqic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8940 8000 blezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 896a 8000 bgec a6,a7,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c948 1000 bgeic a6,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 c000 bgeuc t4,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8840 c000 bgeuc zero,t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8862 c000 bgeuc t4,t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 0000 bnezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c84c 1000 bgeiuc t4,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 8000 bgtzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a802 8000 bltzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8809 8000 bgezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c928 1000 bgeic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 6020 0001 8000 li at,0x80000001 +[0-9a-f]+ <[^>]+> 2029 0b50 slt at,a5,at +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c92c 1000 bgeiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 8000 bltc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 c000 bltuc a5,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 c000 bltuc zero,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 c000 bltuc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 0000 bnec a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c930 0800 bneic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 1d00 restore.jrc 0 +[0-9a-f]+ <[^>]+> 8000 300b restore.jrc 8 +[0-9a-f]+ <[^>]+> 1d10 restore.jrc 16 +[0-9a-f]+ <[^>]+> 8000 301b restore.jrc 24 +[0-9a-f]+ <[^>]+> 1d20 restore.jrc 32 +[0-9a-f]+ <[^>]+> 8000 302b restore.jrc 40 +[0-9a-f]+ <[^>]+> 03bd 0004 addiu sp,sp,4 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 000c addiu sp,sp,12 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0014 addiu sp,sp,20 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 001c addiu sp,sp,28 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0024 addiu sp,sp,36 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 8000 307b restore.jrc 120 +[0-9a-f]+ <[^>]+> 03bd 007c addiu sp,sp,124 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 0018 03ff sdbbp 0x3ff +[0-9a-f]+ <[^>]+> 23ff c37f wait 0x3ff +[0-9a-f]+ <[^>]+> 0008 03ff syscall 0x3ff +[0-9a-f]+ <[^>]+> 3800 balc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 test_delay_slot +[0-9a-f]+ <[^>]+> d850 jalrc t4 +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 557f lw s2,508\(gp\) +[0-9a-f]+ <[^>]+> 55ff lw s3,508\(gp\) +[0-9a-f]+ <[^>]+> 567f lw a0,508\(gp\) +[0-9a-f]+ <[^>]+> 56ff lw a1,508\(gp\) +[0-9a-f]+ <[^>]+> 577f lw a2,508\(gp\) +[0-9a-f]+ <[^>]+> 57ff lw a3,508\(gp\) +[0-9a-f]+ <[^>]+> 547f lw s0,508\(gp\) +[0-9a-f]+ <[^>]+> 54ff lw s1,508\(gp\) +[0-9a-f]+ <[^>]+> 54fe lw s1,504\(gp\) +[0-9a-f]+ <[^>]+> 54fd lw s1,500\(gp\) +[0-9a-f]+ <[^>]+> 5480 lw s1,0\(gp\) +[0-9a-f]+ <[^>]+> 5481 lw s1,4\(gp\) +[0-9a-f]+ <[^>]+> 54be lw s1,248\(gp\) +[0-9a-f]+ <[^>]+> 54bf lw s1,252\(gp\) +[0-9a-f]+ <[^>]+> 54c0 lw s1,256\(gp\) +[0-9a-f]+ <[^>]+> 823c 8104 addiu s1,gp,-260 +[0-9a-f]+ <[^>]+> 8631 8000 lw s1,0\(s1\) +[0-9a-f]+ <[^>]+> 863c 8001 lw s1,1\(gp\) +[0-9a-f]+ <[^>]+> 863c 8002 lw s1,2\(gp\) +[0-9a-f]+ <[^>]+> 863c 8003 lw s1,3\(gp\) +[0-9a-f]+ <[^>]+> a63c c0ff lw s1,-1\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fe lw s1,-2\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fd lw s1,-3\(gp\) +[0-9a-f]+ <[^>]+> 863b 8000 lw s1,0\(k1\) +[0-9a-f]+ <[^>]+> bd63 movep a1,a2,zero,zero +[0-9a-f]+ <[^>]+> bc6b movep a2,a3,zero,zero +[0-9a-f]+ <[^>]+> bc63 movep a0,a1,zero,zero +[0-9a-f]+ <[^>]+> bd63 movep a1,a2,zero,zero +[0-9a-f]+ <[^>]+> bc6b movep a2,a3,zero,zero +[0-9a-f]+ <[^>]+> bc79 movep a2,a3,s1,zero +[0-9a-f]+ <[^>]+> bc69 movep a2,a3,a5,zero +[0-9a-f]+ <[^>]+> bc6a movep a2,a3,a6,zero +[0-9a-f]+ <[^>]+> bc78 movep a2,a3,s0,zero +[0-9a-f]+ <[^>]+> bc7a movep a2,a3,s2,zero +[0-9a-f]+ <[^>]+> bc7b movep a2,a3,s3,zero +[0-9a-f]+ <[^>]+> bc7c movep a2,a3,s4,zero +[0-9a-f]+ <[^>]+> be3c movep a2,a3,s4,s1 +[0-9a-f]+ <[^>]+> bc3c movep a2,a3,s4,a5 +[0-9a-f]+ <[^>]+> bc5c movep a2,a3,s4,a6 +[0-9a-f]+ <[^>]+> be1c movep a2,a3,s4,s0 +[0-9a-f]+ <[^>]+> be5c movep a2,a3,s4,s2 +[0-9a-f]+ <[^>]+> be7c movep a2,a3,s4,s3 +[0-9a-f]+ <[^>]+> be9c movep a2,a3,s4,s4 +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> 8043 f300 ext t4,t5,0,13 +[0-9a-f]+ <[^>]+> 8044 f340 ext t4,a0,0,14 +[0-9a-f]+ <[^>]+> 8045 f380 ext t4,a1,0,15 +[0-9a-f]+ <[^>]+> 8046 f3c0 ext t4,a2,0,16 +[0-9a-f]+ <[^>]+> 8047 f500 ext t4,a3,0,21 +[0-9a-f]+ <[^>]+> 8048 f540 ext t4,a4,0,22 +[0-9a-f]+ <[^>]+> 8049 f580 ext t4,a5,0,23 +[0-9a-f]+ <[^>]+> 8050 f5c0 ext t4,s0,0,24 +[0-9a-f]+ <[^>]+> 6040 0000 0000 li t4,0x0 + [0-9a-f]+: R_NANOMIPS_I32 test +[0-9a-f]+ <[^>]+> 2000 0390 dvp +[0-9a-f]+ <[^>]+> 20a0 0390 dvp a1 +[0-9a-f]+ <[^>]+> 2000 0790 evp +[0-9a-f]+ <[^>]+> 20c0 0790 evp a2 +#pass diff --git a/gas/testsuite/gas/nanomips/nanomips.exp b/gas/testsuite/gas/nanomips/nanomips.exp new file mode 100644 index 00000000000..8f43014ef32 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips.exp @@ -0,0 +1,557 @@ +# Copyright (C) 2018-2026 Free Software Foundation, CIP United Inc. +# Contributed by MIPS Tech LLC. +# Written by Faraz Shahbazker + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + +# +# Some generic nanoMIPS tests +# + +# When adding a new test to this file, try to do the following things: +# +# * If testing assembly and disassembly of code, don't forget to test +# the actual bit encodings of the instructions (using the +# --show-raw-insn flag to objdump). +# +# * Try to run the test for as many architectures as appropriate, +# using the "run_dump_test_arches" or "run_list_test_arches" functions, +# along with the output from a call to "arch_list_matching." +# +# * Be sure to compare the test output before and after your testsuite +# changes, to verify that existing and new tests were run as expected. +# Look for expect ERROR messages in the testsuite .log file to make sure +# the new expect code did not contain errors. + +# To add support for a new CPU to this file, add an appropriate entry +# to the sequence of "arch_create" function calls below, and test +# the result. The new CPU should automatically be used when running +# various tests. If the new CPU is the default CPU for any tool +# targets, make sure the call to "arch_create" reflects that fact. + + +# The functions below create and manipulate an "architecture data +# array" which contains entries for each nanoMIPS architecture (or CPU) +# known to these tests. The array contains the following information +# for each architecture, indexed by the name of the architecture +# described by the entry: +# +# displayname: The name of the entry to be used for pretty-printing. +# +# gprsize: The size in bits of General Purpose Registers provided by +# the architecture (must be 32 or 64). +# +# props: A list of text strings which are associated with the +# architecture. These include the architecture name as well as +# information about what instructions the CPU supports. When matching +# based on properties, an additional property is added to the normal +# property list, "gpr" so that tests can match CPUs which +# have GPRs of a specific size. +# +# as_flags: The assembler flags used when assembling tests for this +# architecture. +# +# objdump_flags: The objdump flags used when disassembling tests for +# this architecture. +# +# Most entries in the architecture array will have values in all of +# the fields above. One entry, "default" represents the default CPU +# based on the target of the assembler being built. If always has +# empty "as_flags" and "objdump_flags." + +# arch_init +# +# This function initializes the architecture data array ("mips_arches") +# to be empty. +proc arch_init {} { + global nanomips_arches + + # Catch because the variable won't be set the first time through. + catch {unset nanomips_arches} +} + +# arch_create ARCH GPRSIZE EXTENDS PROPS AS_FLAGS OBJDUMP_FLAGS \ +# (optional:) DEFAULT_FOR_TARGETS +# +# This function creates a new entry in the architecture data array, +# for the architecture or CPU named ARCH, and fills in the entry +# according to the rest of the arguments. +# +# The new entry's property list is initialized to contain ARCH, any +# properties specified by PROPS, and the properties associated with +# the entry specified by EXTENDS. (The new architecture is considered +# to extend the capabilities provided by that architecture.) +# +# If DEFAULT_FOR_TARGETS is specified, it is a list of targets for which +# this architecture is the default architecture. If "istarget" returns +# true for any of the targets in the list, a "default" entry will be +# added to the architecture array which indicates that ARCH is the default +# architecture. +proc arch_create {arch gprsize extends props as_flags objdump_flags + {default_for_targets {}}} { + global nanomips_arches + + if { [info exists nanomips_arches($arch)] } { + error "arch_create: arch \"$arch\" already exists" + } + if { $gprsize != 32 && $gprsize != 64 } { + error "arch_create: invalid GPR size $gprsize" + } + + set archdata(displayname) $arch + set archdata(gprsize) $gprsize + set archdata(as_flags) $as_flags + set archdata(objdump_flags) $objdump_flags + set archdata(props) $arch + eval lappend archdata(props) $props + if { [string length $extends] != 0 } { + eval lappend archdata(props) [nanomips_arch_properties $extends] + } + + set nanomips_arches($arch) [array get archdata] + + # Set as default if appropriate. + foreach target $default_for_targets { + if { [istarget $target] } { + if { [info exists nanomips_arches(default)] } { + error "arch_create: default arch already exists" + } + + set archdata(displayname) "default = $arch" + set archdata(as_flags) "" + set archdata(objdump_flags) "" + + set nanomips_arches(default) [array get archdata] + break + } + } +} + +# nanomips_arch_destroy ARCH +# +# The opposite of the above. This function removes an entry from +# the architecture data array, for the architecture or CPU named ARCH. + +proc nanomips_arch_destroy {arch} { + global nanomips_arches + + if { [info exists nanomips_arches($arch)] } { + unset nanomips_arches($arch) + } +} + +# nanomips_arch_list_all +# +# This function returns the list of all names of entries in the +# architecture data array (including the default entry, if a default +# is known). +proc nanomips_arch_list_all {} { + global nanomips_arches + return [lsort -dictionary [array names nanomips_arches]] +} + +# nanomips_arch_data ARCH +# +# This function returns the information associated with ARCH +# in the architecture data array, in "array get" form. +proc nanomips_arch_data {arch} { + global nanomips_arches + + if { ! [info exists nanomips_arches($arch)] } { + error "nanomips_arch_data: unknown arch \"$arch\"" + } + return $nanomips_arches($arch) +} + +# nanomips_arch_displayname ARCH +# +# This function returns the printable name associated with ARCH in +# the architecture data array. +proc nanomips_arch_displayname {arch} { + array set archdata [nanomips_arch_data $arch] + return $archdata(displayname) +} + +# nanomips_arch_properties ARCH (optional:) INCLUDE_GPRSIZE +# +# This function returns the property list associated with ARCH in the +# architecture data array, including the "canonical" target name as the +# first element. + +proc nanomips_arch_properties {arch} { + array set archdata [nanomips_arch_data $arch] + set props $archdata(props) + return $props +} + +# nanomips_arch_as_flags ARCH +# +# This function returns the assembler flags associated with ARCH in +# the architecture data array. +proc nanomips_arch_as_flags {arch} { + array set archdata [nanomips_arch_data $arch] + return $archdata(as_flags) +} + +# nanomips_arch_objdump_flags ARCH +# +# This function returns the objdump disassembly flags associated with +# ARCH in the architecture data array. +proc nanomips_arch_objdump_flags {arch} { + array set archdata [nanomips_arch_data $arch] + return $archdata(objdump_flags) +} + +# nanomips_arch_matches ARCH PROPMATCHLIST +# +# This function returns non-zero if ARCH matches the set of properties +# described by PROPMATCHLIST. Each entry in PROPMATCHLIST can either +# be the name of a property which must be matched, or "!" followed by +# the name of a property which must not be matched. ARCH matches +# PROPMATCHLIST if and only if all of the conditions specified by +# PROPMATCHLIST are satisfied. +proc nanomips_arch_matches {arch propmatchlist} { + foreach pm $propmatchlist { + if { [string match {!*} $pm] } { + # fail if present. + set inverted 1 + set p [string range $pm 1 end] + } { + # fail if not present. + set inverted 0 + set p $pm + } + + set loc [lsearch -exact [nanomips_arch_properties $arch] $p] + + # required-absent and found, or required-present and not found: fail. + if { ($inverted && $loc != -1) || (! $inverted && $loc == -1) } { + return 0 + } + } + return 1 +} + +# arch_list_matching ARGS +# +# This function returns a list of all architectures which match +# the conditions described by its arguments. Its arguments are +# taken as a list and used as the PROPMATCHLIST in a call to +# "mips_arch_matches" for each known architecture. +proc arch_list_matching {args} { + set l "" + foreach arch [nanomips_arch_list_all] { + # For now, don't match default arch until we know what its + # properties actually are. + if { [string compare $arch default] == 0 + && [string length [nanomips_arch_properties default]] == 0} { + continue + } + if { [nanomips_arch_matches $arch $args] } { + lappend l $arch + } + } + return $l +} + + +# The functions below facilitate running various types of tests. + +# run_dump_test_arch NAME OPTS ARCH +# +# Invoke "run_dump_test" for test NAME with additional assembler options OPTS. +# Add the assembler and disassembler flags that are associated with +# architecture ARCH. +# +# You can override the expected output for particular architectures. +# The possible test names are, in order of preference: +# +# 1. CARCH@NAME.d +# 2. NAME.d +# +# where CARCH is the "canonical" name of architecture ARCH as recorded +# in its associated property list. +proc run_dump_test_arch { name opts arch } { + global subdir srcdir + + set proparch [lindex [nanomips_arch_properties $arch] 0] + set prefixes [list ${proparch}@ ] + + if { [ string match "nanomips32s" $arch ] + || [ string match "nanomips32r6s" $arch ] } { + lappend prefixes nms@ + } + + foreach prefix ${prefixes} { + set archname ${prefix}${name} + if { [file exists "$srcdir/$subdir/${archname}.d"] } { + set name $archname + break + } + } + + if [catch {run_dump_test $name \ + "{name {([concat $opts [nanomips_arch_displayname $arch]])}} + {objdump {[nanomips_arch_objdump_flags $arch]}} + {as {[concat $opts [nanomips_arch_as_flags $arch]]}}"} rv] { + perror "$rv" + untested "$subdir/$name ($arch)" + } +} + +# run_dump_test_arches NAME [OPTS] ARCH_LIST +# +# Invoke "run_dump_test_arch" for test NAME, for each architecture +# listed in ARCH_LIST. OPTS, if specified, is a list of additional +# assembler options that should be used for all architectures. +proc run_dump_test_arches { name args } { + set opts "" + if { [llength $args] > 1 } { + set opts [lindex $args 0] + set args [lrange $args 1 end] + } + set arch_list [lindex $args 0] + foreach arch $arch_list { + run_dump_test_arch $name $opts $arch + } +} + +# run_list_test_arch NAME OPTS ARCH +# +# Invoke "run_list_test" for test NAME with additional assembler options OPTS. +# Add the assembler flags that are associated with architecture ARCH. +proc run_list_test_arch { name opts arch } { + global subdir srcdir + + set testname "nanoMIPS $name ([concat $opts [nanomips_arch_displayname $arch]])" + set proparch [lindex [nanomips_arch_properties $arch] 0] + set prefixes [list ${proparch}@ ] + if { [ string match "nanomips32s" $arch ] + || [ string match "nanomips32r6s" $arch] } { + lappend prefixes nms@ + } + + verbose "run_list_test_arch $prefixes" + foreach prefix ${prefixes} { + set archname ${prefix}${name} + verbose "Checking $archname" + if { [file exists "$srcdir/$subdir/${archname}.l"] } { + set name $archname + break + } + } + + if [catch {run_list_test \ + $name \ + [concat $opts [nanomips_arch_as_flags $arch]] \ + $testname} rv] { + perror "$rv" + untested "$testname" + } +} + +# run_list_test_arches NAME [OPTS] ARCH_LIST +# +# Invoke "run_list_test_arch" for test NAME, for each architecture listed +# in ARCH_LIST. OPTS, if specified, is a list of additional assembler +# options that should be used for all architectures. +proc run_list_test_arches { name args } { + set opts "" + if { [llength $args] > 1 } { + set opts [lindex $args 0] + set args [lrange $args 1 end] + } + set arch_list [lindex $args 0] + foreach arch $arch_list { + run_list_test_arch "$name" "$opts" "$arch" + } +} + +# run_dump_test_opts NAME OPTS_LIST ARCH_LIST +# +# Invoke "run_dump_test_arch" for test NAME, for each architecture +# listed in ARCH_LIST and each option listed in OPTS_LIST. +proc run_dump_test_opts { name opts_list arch_list } { + foreach opts $opts_list { + foreach arch $arch_list { + run_dump_test_arch $name $opts $arch + } + } +} + +# run_list_test_opts NAME OPTS_LIST ARCH_LIST +# +# Invoke "run_list_test_arch" for test NAME, for each architecture +# listed in ARCH_LIST and each option listed in OPTS_LIST. +proc run_list_test_opts { name opts_list arch_list } { + foreach opts $opts_list { + foreach arch $arch_list { + run_list_test_arch "$name" "$opts" "$arch" + } + } +} + +# Create the architecture data array by providing data for all +# known architectures. +# +# Note that several targets pick default CPU based on ABI. We +# can't easily handle that; do NOT list those targets as defaulting +# to any architecture. +arch_init +arch_create nanomips32r6 32 {} \ + { nanomipsr6 } \ + { -march=32r6 --defsym nanomips= -mlegacyregs } {} +arch_create nanomips32r6s 32 {} \ + {} \ + { -march=32r6s --defsym nanomips= -mlegacyregs } {} +arch_create nanomips64r6 64 {} \ + { nanomips32r6 nanomipsr6 } \ + { -march=64r6 --defsym nanomips= -mlegacyregs } {} +arch_create nanomips32 32 {} \ + { nanomips xnms } \ + { -march=32r6 --defsym nanomips= } {} +arch_create nanomips32s 32 {} \ + { nanomips } \ + { -march=32r6s --defsym nanomips= } {} +arch_create nanomips64 64 {} \ + { nanomips xnms } \ + { -march=64r6 --defsym nanomips= } {} +# +# And now begin the actual tests! VxWorks uses RELA rather than REL +# relocations, so most of the generic dump tests will not work there. +# +if { [istarget nanomips*-*-*] } { + set addr32 0 + set has_newabi [expr [istarget nanomips*-*-linux*] \ + || [istarget nanomips*-*-elf*]] + + if { [istarget "nanomips*-*-*linux*"] + || [istarget "nanomips*-*-elf*"] + || [istarget "nanomips*-*-*bsd*"] } then { + set tmips "t" + } else { + set tmips "" + } + if {[istarget "nanomips-*-*"] || [istarget "nanomipsel*-*-*"] } { + set el "el" + } { + set el "" + } + + run_dump_test_arch "abi32" "-mlegacyregs" nanomips32s + run_dump_test_arches "abs" [arch_list_matching nanomipsr6] + run_dump_test_arches "add" [arch_list_matching nanomipsr6] + run_dump_test_arch "addu" "" nanomips32r6s + + run_dump_test_arches "aent" [arch_list_matching nanomipsr6] + + run_dump_test_arch "and" "" nanomips32r6s + + run_list_test_arches "baddata1" "" [arch_list_matching nanomips] + run_dump_test_arch "beq" "" nanomips32r6s + run_dump_test_arch "bge" "" nanomips32r6s + run_dump_test_arch "bgeu" "" nanomips32r6s + run_dump_test_arch "blt" "" nanomips32r6s + run_dump_test_arch "bltu" "" nanomips32r6s + + run_dump_test_arch "cp0-names-numeric" "" nanomips32r6 + run_dump_test_arch "cp0-names" "" nanomips32r6 + + run_dump_test_arch "cp0sel-names-numeric" "" nanomips32r6 + run_dump_test_arch "cp0sel-names" "" nanomips32r6 + + run_dump_test_arch "ctc" "" nanomips32 + + run_dump_test_arches "debug-dis" [arch_list_matching nanomips] + run_dump_test_arch "div" "" nanomips32r6 + + run_dump_test_arch "expr1" "" nanomips32r6 + run_dump_test_arch "expr-const" "-EB" nanomips32r6 + run_dump_test_arch "expr-sym" "-EB" nanomips32r6 + run_list_test_arches "expr-ill" [arch_list_matching nanomips] + run_dump_test_arches "expr-vol" [arch_list_matching nanomips] + + run_dump_test_arch "gpr-names-numeric" "" nanomips32r6 + run_dump_test_arch "gpr-names" "" nanomips32r6 + + run_list_test_arch "insn-suffix-error" "" nanomips32 + run_list_test_arches "isa-errors" "" [arch_list_matching nanomips] + + run_dump_test_arches "jal" [arch_list_matching nanomipsr6] + + run_dump_test_arch "la-pic" "" nanomips32r6s + run_dump_test_arches "la-pic-mclarge" "-mlegacyregs" \ + [arch_list_matching nanomips] + run_dump_test_arches "la-lpic-mclarge" "-mlegacyregs" \ + [arch_list_matching nanomips] + run_dump_test_arches "la-lpic-mcmedium" "-mlegacyregs" \ + [arch_list_matching nanomips] + run_dump_test_opts "la" \ + {"-mlegacyregs" "-mlegacyregs --defsym mc_medium="} \ + [arch_list_matching nanomips] + run_dump_test_opts "la-pcrel" {"" "--defsym mc_medium="} \ + [arch_list_matching nanomips] + run_dump_test_arches "la-mclarge" "-mlegacyregs --defsym mc_large=" \ + [arch_list_matching nanomips] + run_dump_test_arches "la-mclarge-pcrel" "--defsym mc_large=" \ + [arch_list_matching nanomips] + + run_dump_test_arches "lb" [arch_list_matching nanomipsr6] + + run_dump_test_arch "ld" "" nanomips32r6 + run_dump_test_arch "ld-reloc" "-mlegacyregs" nanomips32s + + run_dump_test_arch "li" "-mlegacyregs" nanomips32s + run_dump_test_arch "lifloat" "" nanomips32r6 + run_dump_test_arch "lifloat-nms" "" nanomips32r6s + run_dump_test_arch "lifloat-mem" "" nanomips32r6 + + run_dump_test_arch "lif-pic" "" nanomips32r6 + run_dump_test_arch "lif-pic" "" nanomips32r6s + run_dump_test_arch "lineno" "" nanomips32r6 + run_dump_test_arches "linkrelax" "-mlegacyregs" [arch_list_matching nanomips] + run_dump_test_arches "linkrelax-relocs" "-mlegacyregs" [arch_list_matching nanomips] + run_dump_test_arch "linkrelax-dis" "" nanomips32 + + run_list_test_arch "mcmodel" "" nanomips32 + run_list_test_arch "mcmodel-err" "" nanomips32 + + # tests of objdump's ability to disassemble the move mnemonic + run_dump_test_arches "move" [arch_list_matching nanomipsr6] + run_dump_test_arches "mt-ase" "-mmt" [arch_list_matching nanomipsr6] + + run_dump_test_arches "mvh" [arch_list_matching nanomipsr6] + + # FIXME: repeat with traps, insn32, noinsn32 + run_dump_test_arches "nanomips" [arch_list_matching xnms] + run_dump_test_arches "nanomips32" [arch_list_matching xnms] + run_list_test_arches "nanomips-error" "-mlegacyregs" [arch_list_matching xnms] + run_dump_test_arch "nanomips-exc32" "--defsym insn32_broken=" nanomips32 + run_dump_test_arch "nanomips-exc-noalias" "" nanomips32 + run_dump_test_arch "nanomips-subset" "" nanomips32s + + run_dump_test_arches "nolinkrelax" "-mlegacyregs" \ + [arch_list_matching nanomips] + run_dump_test_arches "nolinkrelax-relocs" "-mlegacyregs" \ + [arch_list_matching nanomips] + + run_dump_test_arches "rol" [arch_list_matching nanomipsr6] + + run_dump_test_arch "save" "" nanomips32 + run_list_test_arch "save-error" "" nanomips32 + run_list_test_arch "save-error" "" nanomips32s + run_dump_test_arch "save-relocs" "" nanomips32 + run_dump_test_arch "sb" "" nanomips32r6 +} diff --git a/gas/testsuite/gas/nanomips/nanomips.l b/gas/testsuite/gas/nanomips/nanomips.l new file mode 100644 index 00000000000..4c68abab824 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips.l @@ -0,0 +1,10 @@ +.*.s: Assembler messages: +.*.s:493: Warning: divide by zero +.*.s:506: Warning: divide by zero +.*.s:1103: Warning: divide by zero +.*.s:1763: Warning: branch bge is always true +.*.s:1775: Warning: branch bgeu is always true +.*.s:1847: Warning: branch ble is always true +.*.s:1862: Warning: branch bleu is always true +.*.s:1868: Warning: branch bleu is always true +.*.s:1871: Warning: branch bleu is always true diff --git a/gas/testsuite/gas/nanomips/nanomips.s b/gas/testsuite/gas/nanomips/nanomips.s new file mode 100644 index 00000000000..5fa026ea7c5 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips.s @@ -0,0 +1,2034 @@ + .text + .align 3 + .ent test + .globl test +test: + pref 0, 0 + pref 0, 2047 + pref 0, -2048 + pref 0, 2048 + pref 0, -2049 + pref 0, ($zero) + pref 0, 0($zero) + pref 1, 0($zero) + pref 2, 0($zero) + pref 3, 0($zero) + pref 4, 0($zero) + pref 5, 0($zero) + pref 6, 0($zero) + pref 7, 0($zero) + pref 7, 511($zero) + pref 7, -512($zero) + pref 3, 32767($zero) + pref 3, -32768($zero) + + pref 3, 32767($t4) + pref 3, -32768($t4) + + nop + .ifndef insn32 + nop16 + .endif + nop32 + ehb + pause + + li $s2, -1 + li $s3, -1 + li $a0, -1 + li $a1, -1 + li $a2, -1 + li $a3, -1 + li $s0, -1 + li $s1, -1 + li $s1, 0 + li $s1, 125 + li $s1, 126 + li $s1, 127 + li $t0, 0 + li $t9, 0 + + li32 $t4, 0 + li32 $t4, 1 + li $t4, 32767 + li $t4, -32768 + li $t4, 65535 + + li $t4, 65536 + li $t4, 0xffff8000 + li $t4, 0xffff8001 + li $t4, 0xffffffff + li $t4, 0x12345678 + li $t5, 0xffffffff + li $a0, 0xffffffff + + move $zero, $s6 + move $t4, $s6 + move $t5, $s6 + move $a0, $s6 + move $a1, $s6 + move $a2, $s6 + move $a3, $s6 + move $a4, $s6 + move $a5, $s6 + move $a6, $s6 + move $fp, $s6 + move $ra, $s6 + move $zero, $zero + move $zero, $t4 + move $zero, $t5 + move $zero, $a0 + move $zero, $a1 + move $zero, $a2 + move $zero, $a3 + move $zero, $a4 + move $zero, $a5 + move $zero, $a6 + move $zero, $fp + move $zero, $ra + + move $s6, $t4 + .ifndef insn32 + move16 $t4, $s6 + move16 $s6, $t4 + .endif + + move32 $t4, $s6 + move32 $s6, $t4 + + b test + .ifndef insn32 + b16 test + .endif + b32 test + b 1f + .ifndef insn32 + b16 1f + .endif + b32 1f +1: + b 1b + .ifndef insn32 + b16 1b + .endif + b32 1b + + abs $t4, $t5 + abs $t4, $a0 + abs $t4, $t4 + abs $t4 + + add $t4, $t5, $a0 + add $sp, $fp, $ra + add $t4, $t4, $a0 + add $t4, $a0 + + add $t4, $t4, 0 + add $t4, $t4, 1 + add $t4, $t4, 32767 + add $t4, $t4, -32768 + add $t4, $t4, 65535 + + addi $t5, $a0, -32768 + addi $t5, $a0, 0 + addi $t5, $a0, 32767 + addi $t5, $a0, 65535 + addi $t5, $t5, 65535 + addi $t5, 65535 + + addiu $zero, -8 + addiu $t4, -8 + addiu $t5, -8 + addiu $a0, -8 + addiu $a1, -8 + addiu $a2, -8 + addiu $a3, -8 + addiu $a4, -8 + addiu $a5, -8 + addiu $a6, -8 + addiu $fp, -8 + addiu $ra, -8 + addiu $ra, -7 + addiu $ra, 0 + addiu $ra, 1 + addiu $ra, 6 + addiu $ra, 7 + addiu $ra, 8 + addiu $sp, -258 << 2 + addiu $sp, -257 << 2 + addiu $sp, -256 << 2 + addiu $sp, 255 << 2 + addiu $sp, 256 << 2 + addiu $sp, 257 << 2 + addiu $sp, $sp, 257 << 2 + addiu $sp, $sp, 258 << 2 + + addiu $t4, $t4, -1 + addiu $t4, $t5, -1 + addiu $t4, $a0, -1 + addiu $t4, $a1, -1 + addiu $t4, $a2, -1 + addiu $t4, $a3, -1 + addiu $t4, $s0, -1 + addiu $t4, $s1, -1 + addiu $t4, $s1, 1 + addiu $s2, $s1, 4 + addiu $s2, $s1, 8 + addiu $s2, $s1, 12 + addiu $s2, $s1, 16 + addiu $s2, $s1, 20 + addiu $s2, $s1, 24 + addiu $s3, $s1, 24 + addiu $a0, $s1, 24 + addiu $a1, $s1, 24 + addiu $a2, $s1, 24 + addiu $a3, $s1, 24 + addiu $s0, $s1, 24 + addiu $s1, $s1, 24 + + addiu $s2, $sp, 0 << 2 + addiu $s2, $sp, 1 << 2 + addiu $s2, $sp, 62 << 2 + addiu $s2, $sp, 63 << 2 + addiu $t4, $sp, 64 << 2 + addiu $s2, $sp, 63 << 2 + addiu $s3, $sp, 63 << 2 + addiu $a0, $sp, 63 << 2 + addiu $a1, $sp, 63 << 2 + addiu $a2, $sp, 63 << 2 + addiu $a3, $sp, 63 << 2 + addiu $s0, $sp, 63 << 2 + addiu $s1, $sp, 63 << 2 + + addiu $t5, $a0, -4095 + addiu $s3, $a0, 0 + addiu $t5, $a0, 8191 + + addiu $t5, $a0, 16383 + addiu $t5, $t5, 16383 + addiu $t5, 16383 + + addu $t4, $s6, $zero + addu $s6, $t4, $zero + addu $t4, $zero, $s6 + addu $s6, $zero, $t4 + + addu $s2, $s3, $s2 + addu $s2, $s3, $s3 + addu $s2, $s3, $a0 + addu $s2, $s3, $a1 + addu $s2, $s3, $a2 + addu $s2, $s3, $a3 + addu $s2, $s3, $s0 + addu $s2, $s3, $s1 + + addu $s2, $s2, $s1 + addu $s2, $s3, $s1 + addu $s2, $a0, $s1 + addu $s2, $a1, $s1 + addu $s2, $a2, $s1 + addu $s2, $a3, $s1 + addu $s2, $s0, $s1 + addu $s2, $s1, $s1 + + addu $s2, $s2, $s1 + addu $s3, $s2, $s1 + addu $a0, $s2, $s1 + addu $a1, $s2, $s1 + addu $a2, $s2, $s1 + addu $a3, $s2, $s1 + addu $s0, $s2, $s1 + addu $s1, $s2, $s1 + + addu $a3, $a3, $s2 + addu $a3, $s2 + addu $a3, $s2, $a3 + + addu $sp, $fp, $ra + addu $t4, $t4, 0 + addu $t4, $t4, 1 + addu $t4, $t4, 32767 + addu $t4, $t4, -32768 + addu $t4, $t4, 65535 + + and $s2, $s2 + and $s2, $s3 + and $s2, $a0 + and $s2, $a1 + and $s2, $a2 + and $s2, $a3 + and $s2, $s0 + and $s2, $s1 + and $s3, $s2 + and $a0, $s2 + and $a1, $s2 + and $a2, $s2 + and $a3, $s2 + and $s0, $s2 + and $s1, $s2 + + and $s2, $s3 + and $s2, $s2, $s3 + and $s2, $s3, $s2 + .ifndef insn32 + and16 $s2, $s2, $s3 + .endif + and32 $t4, $t4, $t5 + + andi $s2,$s2,1 + andi $s2,$s2,2 + andi $s2,$s2,3 + andi $s2,$s2,4 + andi $s2,$s2,7 + andi $s2,$s2,8 + andi $s2,$s2,15 + andi $t4,$t4,16 + andi $t4,$t4,31 + andi $t4,$t4,32 + andi $t4,$t4,63 + andi $t4,$t4,64 + andi $t4,$t4,128 + andi $s2,$s2,255 + andi $t4,$t4,4095 + andi $s2,$s2,65535 + andi $s2,$s3,65535 + andi $s2,$a0,65535 + andi $s2,$a1,65535 + andi $s2,$a2,65535 + andi $s2,$a3,65535 + andi $s2,$s0,65535 + andi $s2,$s1,65535 + andi $s3,$s1,65535 + andi $a0,$s1,65535 + andi $a1,$s1,65535 + andi $a2,$s1,65535 + andi $a3,$s1,65535 + andi $s0,$s1,65535 + andi $s1,$s1,65535 + + andi $a3,$a3,65535 + + andi $a3,65535 + .ifndef insn32 + andi16 $a3,65535 + .endif + + and32 $t4, $t5, $a0 + and32 $t4, $t4, $a0 + and32 $t4, $a0 + and $t4, $t5, 0 + and $t4, $t5, 4095 + and $t4, $t5, 4096 + and $t4, $t5, 0xffff0001 + +test2: + beqz $s2, test2 + beqz $s3, test2 + beqz $a0, test2 + beqz $a1, test2 + beqz $a2, test2 + beqz $a3, test2 + beqz $s0, test2 + beqz $s1, test2 + beq $s2, $zero, test2 + beq $s3, $zero, test2 + beq $a0, $zero, test2 + beq $a1, $zero, test2 + beq $a2, $zero, test2 + beq $a3, $zero, test2 + beq $s0, $zero, test2 + beq $s1, $zero, test2 + beq $zero, $s2, test2 + beq $zero, $s3, test2 + beq $zero, $a0, test2 + beq $zero, $a1, test2 + beq $zero, $a2, test2 + beq $zero, $a3, test2 + beq $zero, $s0, test2 + beq $zero, $s1, test2 + + .ifndef insn32 + beqz16 $s0, test2 + .endif + beqz32 $s0, test2 + beqz $s1, test2 + beqz32 $s1, test2 + + beqzc $s1, test2 + + beq $s0, 0, test2 + beq $s0, 10, test2 + beq $s0, 32767, test2 + beq $s0, 65536, test2 + + bnez $s2, test3 + bnez $s3, test3 + bnez $a0, test3 + bnez $a1, test3 + bnez $a2, test3 + bnez $a3, test3 + bnez $s0, test3 + bnez $s1, test3 + bne $s2, $zero, test3 + bne $s3, $zero, test3 + bne $a0, $zero, test3 + bne $a1, $zero, test3 + bne $a2, $zero, test3 + bne $a3, $zero, test3 + bne $s0, $zero, test3 + bne $s1, $zero, test3 + bne $zero, $s2, test3 + bne $zero, $s3, test3 + bne $zero, $a0, test3 + bne $zero, $a1, test3 + bne $zero, $a2, test3 + bne $zero, $a3, test3 + bne $zero, $s0, test3 + bne $zero, $s1, test3 + + .ifndef insn32 + bnez16 $s0, test3 + .endif + bnez32 $s0, test3 + bnez $s1, test2 + bnez32 $s1, test2 +test3: + bnezc $s1, test2 + + break + break 0 + break 1 + break 2 + break 3 + break 4 + break 5 + break 6 + break 7 + break 8 + break 9 + break 10 + break 11 + break 12 + break 13 + break 14 + break 15 + break 63 + break 64 + break 1023 + break32 + + break32 0 + break32 1 + break32 2 + break32 15 + break32 63 + break32 64 + break32 1023 + cache 0, 0 + cache 0, -2048 + cache 0, 2047 + cache 0, -2049 + cache 0, 2048 + cache 0, 0($t4) + cache 0, -2048($t4) + cache 0, 2047($t4) + cache 0, -2049($t4) + cache 0, 2048($t4) + + cache 0, ($zero) + cache 0, 0($zero) + cache 1, 0($zero) + cache 2, 0($zero) + cache 3, 0($zero) + cache 4, 0($zero) + cache 5, 0($zero) + cache 6, 0($zero) + cache 31, 0($zero) + cache 31, 2047($zero) + cache 31, -2048($zero) + cache 0, 2047($zero) + cache 0, -2048($zero) + + cache 31, 65536($t5) + cache 31, 2048($t5) + cache 31, -2049($t5) + cache 31, 65537($t5) + cache 31, 0xffffffff($t5) + cache 31, 0xffff0000($t5) + cache 31, 0xffff0001($t5) + cache 31, 0xffff($t5) + + cache 31, 65536($zero) + cache 31, 2048($zero) + cache 31, -2049($zero) + cache 31, 65537($zero) + cache 31, 0xffffffff($zero) + cache 31, 0xffff0000($zero) + cache 31, 0xffff0001($zero) + cache 31, 0xffff($zero) + + + clo $t4, $t5 + clo $t5, $t4 + clz $t4, $t5 + clz $t5, $t4 + + deret + di + + di $zero + di $t4 + di $t5 + di $fp + di $ra + + div $zero, $t4, $t5 + div $zero, $fp, $ra + div $zero, $t5 + div $zero, $ra + + div $t4, $t5, $zero + div $t4, $t5, $a0 + + div $t5, $a0, 0 + div $t5, $a0, 1 + div $t5, $a0, -1 + div $t5, $a0, 2 + + divu $zero, $t4, $t5 + divu $zero, $fp, $ra + divu $zero, $t5 + divu $zero, $ra + + divu $t4, $t5, $zero + divu $t4, $t5, $a0 + + divu $t5, $a0, 0 + divu $t5, $a0, 1 + divu $t5, $a0, -1 + divu $t5, $a0, 2 + + ei + ei $zero + ei $t4 + ei $t5 + ei $fp + ei $ra + + eret + + ext $t4, $t5, 5, 15 + ext $t4, $t5, 0, 32 + ext $t4, $t5, 31, 1 + ext $ra, $fp, 31, 1 + + ins $t4, $t5, 5, 15 + ins $t4, $t5, 0, 32 + ins $t4, $t5, 31, 1 + ins $ra, $fp, 31, 1 + + jr $zero + jr $t4 + jr $t5 + jr $a0 + jr $a1 + jr $a2 + jr $a3 + jr $a4 + jr $fp + jr $ra + + jr32 $zero + jr32 $t4 + jr32 $t5 + jr32 $a0 + jr32 $a1 + jr32 $a2 + jr32 $a3 + jr32 $a4 + jr32 $fp + jr32 $ra + + jrc $zero + jrc $t4 + jrc $t5 + jrc $a0 + jrc $a1 + jrc $a2 + jrc $a3 + jrc $a4 + jrc $fp + jrc $ra + + jr.hb $zero + jr.hb $t4 + jr.hb $t5 + jr.hb $a0 + jr.hb $a1 + jr.hb $a2 + jr.hb $a3 + jr.hb $a4 + jr.hb $fp + jr.hb $ra + + j $zero + j $t4 + j $t5 + j $a0 + j $a1 + j $a2 + j $a3 + j $a4 + j $fp + j $ra + + jalrc $ra, $zero + jalrc $t4 + jalrc $t5 + jalrc $a0 + jalrc $a1 + jalrc $a2 + jalrc $a3 + jalrc $a4 + jalrc $fp + + jalrc32 $ra, $zero + + jalrc32 $t4 + jalrc32 $t5 + jalrc32 $a0 + jalrc32 $a1 + jalrc32 $a2 + jalrc32 $a3 + jalrc32 $a4 + jalrc32 $fp + + jalrc $ra, $zero + jalrc $ra, $t4 + jalrc $ra, $t5 + jalrc $ra, $a0 + jalrc $ra, $a1 + jalrc $ra, $a2 + jalrc $ra, $a3 + jalrc $ra, $a4 + jalrc $ra, $fp + jalrc $fp, $ra + + jalrc $t4, $zero + jalrc $t5, $t4 + jalrc $t4, $t5 + jalrc $t4, $a0 + jalrc $t4, $a1 + jalrc $t4, $a2 + jalrc $t4, $a3 + jalrc $t4, $a4 + jalrc $t4, $fp + jalrc $t4, $ra + + jalrc.hb $ra, $zero + jalrc.hb $t4 + jalrc.hb $t5 + jalrc.hb $a0 + jalrc.hb $a1 + jalrc.hb $a2 + jalrc.hb $a3 + jalrc.hb $a4 + jalrc.hb $fp + + jalrc.hb $ra, $zero + jalrc.hb $ra, $t4 + jalrc.hb $ra, $t5 + jalrc.hb $ra, $a0 + jalrc.hb $ra, $a1 + jalrc.hb $ra, $a2 + jalrc.hb $ra, $a3 + jalrc.hb $ra, $a4 + jalrc.hb $ra, $fp + jalrc.hb $fp, $ra + + jalrc.hb $t4, $zero + jalrc.hb $t5, $t4 + jalrc.hb $t4, $t5 + jalrc.hb $t4, $a0 + jalrc.hb $t4, $a1 + jalrc.hb $t4, $a2 + jalrc.hb $t4, $a3 + jalrc.hb $t4, $a4 + jalrc.hb $t4, $fp + jalrc.hb $t4, $ra + + jal $t4, $t5 + jal $fp, $ra + + jal $t5 + jal $ra + + jal test + jal test2 + la $t4, test + lb $t5, 0 + lb $t5, 4 + lb $t5, 0($zero) + lb $t5, 4($zero) + lb $t5, 32767($zero) + lb $t5, -32768($zero) + lb $t5, 65535($zero) + lb $t5, 0xffff0000($zero) + lb $t5, 0xffff8000($zero) + lb $t5, 0xffff0001($zero) + lb $t5, 0xffff8001($zero) + lb $t5, 0xf0000000($zero) + lb $t5, 0xffffffff($zero) + lb $t5, 0x12345678($zero) + lb $s3, ($a0) + lb $s3, 0($a0) + lb $t5, 4($a0) + lb $t5, 32767($a0) + lb $t5, -32768($a0) + lb $t5, 65535($a0) + lb $t5, 0xffff0000($a0) + lb $t5, 0xffff8000($a0) + lb $t5, 0xffff0001($a0) + lb $t5, 0xffff8001($a0) + lb $t5, 0xf0000000($a0) + lb $t5, 0xffffffff($a0) + lb $t5, 0x12345678($a0) + + lbu $t4, -1($t5) + lbu $s2, 0($s3) + lbu $s2, ($s3) + lbu $s2, 1($s3) + lbu $s2, 2($s3) + lbu $s2, 3($s3) + lbu $t4, 4($t5) + lbu $t4, 5($t5) + lbu $t4, 6($t5) + lbu $t4, 7($t5) + lbu $t4, 8($t5) + lbu $t4, 9($t5) + lbu $t4, 10($t5) + lbu $t4, 11($t5) + lbu $t4, 12($t5) + lbu $t4, 13($t5) + lbu $t4, 14($t5) + lbu $t4, 14($t4) + lbu $t4, 14($a0) + lbu $t4, 14($a1) + lbu $t4, 14($a2) + lbu $t4, 14($a3) + lbu $t4, 14($s0) + lbu $t4, 14($s1) + lbu $t5, 14($s1) + lbu $a0, 14($s1) + lbu $a1, 14($s1) + lbu $a2, 14($s1) + lbu $a3, 14($s1) + lbu $s0, 14($s1) + lbu $s1, 14($s1) + + lbu $t5, 0 + lbu $t5, 4 + lbu $t5, 0($zero) + lbu $t5, 4($zero) + lbu $t5, 32767($zero) + lbu $t5, -32768($zero) + lbu $t5, 65535($zero) + lbu $t5, 0xffff0000($zero) + lbu $t5, 0xffff8000($zero) + lbu $t5, 0xffff0001($zero) + lbu $t5, 0xffff8001($zero) + lbu $t5, 0xf0000000($zero) + lbu $t5, 0xffffffff($zero) + lbu $t5, 0x12345678($zero) + + lbu $s3, ($a0) + lbu $s3, 0($a0) + lbu $t5, 4($a0) + lbu $t5, 32767($a0) + lbu $t5, -32768($a0) + lbu $t5, 65535($a0) + lbu $t5, 0xffff0000($a0) + lbu $t5, 0xffff8000($a0) + lbu $t5, 0xffff0001($a0) + lbu $t5, 0xffff8001($a0) + lbu $t5, 0xf0000000($a0) + lbu $t5, 0xffffffff($a0) + lbu $t5, 0x12345678($a0) + + lh $t5, 0 + lh $t5, 4 + lh $t5, 0($zero) + lh $t5, 4($zero) + lh $t5, 32767($zero) + lh $t5, -32768($zero) + lh $t5, 65535($zero) + lh $t5, 0xffff0000($zero) + lh $t5, 0xffff8000($zero) + lh $t5, 0xffff0001($zero) + lh $t5, 0xffff8001($zero) + lh $t5, 0xf0000000($zero) + lh $t5, 0xffffffff($zero) + lh $t5, 0x12345678($zero) + lh $s3, ($a0) + lh $s3, 0($a0) + lh $s3, 4($a0) + lh $t5, 32767($a0) + lh $t5, -32768($a0) + lh $t5, 65535($a0) + lh $t5, 0xffff0000($a0) + lh $t5, 0xffff8000($a0) + lh $t5, 0xffff0001($a0) + lh $t5, 0xffff8001($a0) + lh $t5, 0xf0000000($a0) + lh $t5, 0xffffffff($a0) + lh $t5, 0x12345678($a0) + + lhu $s2, ($s3) + lhu $s2, 0<<1($s3) + lhu $s2, 1<<1($s3) + lhu $s2, 2<<1($s3) + lhu $s2, 3<<1($s3) + lhu $t4, 4<<1($t5) + lhu $t4, 5<<1($t5) + lhu $t4, 6<<1($t5) + lhu $t4, 7<<1($t5) + lhu $t4, 8<<1($t5) + lhu $t4, 9<<1($t5) + lhu $t4, 10<<1($t5) + lhu $t4, 11<<1($t5) + lhu $t4, 12<<1($t5) + lhu $t4, 13<<1($t5) + lhu $t4, 14<<1($t5) + lhu $t4, 15<<1($t5) + lhu $t4, 15<<1($a0) + lhu $t4, 15<<1($a1) + lhu $t4, 15<<1($a2) + lhu $t4, 15<<1($a3) + lhu $t4, 15<<1($t4) + lhu $t4, 15<<1($s0) + lhu $t4, 15<<1($s1) + lhu $t5, 15<<1($s1) + lhu $a0, 15<<1($s1) + lhu $a1, 15<<1($s1) + lhu $a2, 15<<1($s1) + lhu $a3, 15<<1($s1) + lhu $s0, 15<<1($s1) + lhu $s1, 15<<1($s1) + + lhu $t5, 0 + lhu $t5, 4 + lhu $t5, 0($zero) + lhu $t5, 4($zero) + lhu $t5, 32767($zero) + lhu $t5, -32768($zero) + lhu $t5, 65535($zero) + lhu $t5, 0xffff0000($zero) + lhu $t5, 0xffff8000($zero) + lhu $t5, 0xffff0001($zero) + lhu $t5, 0xffff8001($zero) + lhu $t5, 0xf0000000($zero) + lhu $t5, 0xffffffff($zero) + lhu $t5, 0x12345678($zero) + lhu $s3, ($a0) + lhu $s3, 0($a0) + lhu $s3, 4($a0) + lhu $t5, 32767($a0) + lhu $t5, -32768($a0) + lhu $t5, 65535($a0) + lhu $t5, 0xffff0000($a0) + lhu $t5, 0xffff8000($a0) + lhu $t5, 0xffff0001($a0) + lhu $t5, 0xffff8001($a0) + lhu $t5, 0xf0000000($a0) + lhu $t5, 0xffffffff($a0) + lhu $t5, 0x12345678($a0) + + ll $t5, 0 + ll $t5, 0($zero) + ll $t5, 4 + ll $t5, 4($zero) + ll $t5, 32767($zero) + ll $t5, -32768($zero) + ll $t5, 65535($zero) + ll $t5, 0xffff0000($zero) + ll $t5, 0xffff8000($zero) + ll $t5, 0xffff0001($zero) + ll $t5, 0xffff8001($zero) + ll $t5, 0xf0000000($zero) + ll $t5, 0xffffffff($zero) + ll $t5, 0x12345678($zero) + ll $t5, ($a0) + ll $t5, 0($a0) + ll $t5, 4($a0) + ll $t5, 32767($a0) + ll $t5, -32768($a0) + ll $t5, 65535($a0) + ll $t5, 0xffff0000($a0) + ll $t5, 0xffff8000($a0) + ll $t5, 0xffff0001($a0) + ll $t5, 0xffff8001($a0) + ll $t5, 0xf0000000($a0) + ll $t5, 0xffffffff($a0) + ll $t5, 0x12345678($a0) + + lui $t5, 0 + lui $t5, 32767 + lui $t5, 65535 + + lw $s2, ($a0) + lw $s2, 0($a0) + lw $s2, 1<<2($a0) + lw $s2, 2<<2($a0) + lw $s2, 3<<2($a0) + lw $s2, 4<<2($a0) + lw $s2, 5<<2($a0) + lw $s2, 6<<2($a0) + lw $s2, 7<<2($a0) + lw $s2, 8<<2($a0) + lw $s2, 9<<2($a0) + lw $s2, 10<<2($a0) + lw $s2, 11<<2($a0) + lw $s2, 12<<2($a0) + lw $s2, 13<<2($a0) + lw $s2, 14<<2($a0) + lw $s2, 15<<2($a0) + lw $s2, 15<<2($a1) + lw $s2, 15<<2($a2) + lw $s2, 15<<2($a3) + lw $s2, 15<<2($s2) + lw $s2, 15<<2($s3) + lw $s2, 15<<2($s0) + lw $s2, 15<<2($s1) + lw $s3, 15<<2($s1) + lw $a0, 15<<2($s1) + lw $a1, 15<<2($s1) + lw $a2, 15<<2($s1) + lw $a3, 15<<2($s1) + lw $s0, 15<<2($s1) + lw $s1, 15<<2($s1) + + lw $a0, ($sp) + lw $a0, 0($sp) + lw $a0, 1<<2($sp) + lw $a0, 2<<2($sp) + lw $a0, 3<<2($sp) + lw $a0, 4<<2($sp) + lw $a0, 5<<2($sp) + lw $a0, 31<<2($sp) + lw $t4, 31<<2($sp) + lw $t4, 31<<2($sp) + lw $t5, 31<<2($sp) + lw $a0, 31<<2($sp) + lw $a1, 31<<2($sp) + lw $a2, 31<<2($sp) + lw $a3, 31<<2($sp) + lw $a4, 31<<2($sp) + lw $a5, 31<<2($sp) + lw $a6, 31<<2($sp) + lw $fp, 31<<2($sp) + lw $ra, 31<<2($sp) + + lw $a0, 126<<2($sp) + lw $a0, 127<<2($sp) + lw $s0, 127<<2($sp) + lw $s1, 127<<2($sp) + lw $s2, 127<<2($sp) + lw $s3, 127<<2($sp) + lw $s4, 127<<2($sp) + lw $s5, 127<<2($sp) + lw $ra, 127<<2($sp) + + lw $t5, 0 + lw $t5, 4 + lw $t5, ($zero) + lw $t5, 0($zero) + lw $t5, 0($zero) + lw $t5, 4($zero) + lw $t5, 32767($zero) + lw $t5, -32768($zero) + lw $t5, 65535($zero) + lw $t5, 0xffff0000($zero) + lw $t5, 0xffff8000($zero) + lw $t5, 0xffff0001($zero) + lw $t5, 0xffff8001($zero) + lw $t5, 0xf0000000($zero) + lw $t5, 0xffffffff($zero) + lw $t5, 0x12345678($zero) + lw $s3, ($a0) + lw $s3, 0($a0) + lw $s3, 4($a0) + lw $t5, 32767($a0) + lw $t5, -32768($a0) + lw $t5, 65535($a0) + lw $t5, 0xffff0000($a0) + lw $t5, 0xffff8000($a0) + lw $t5, 0xffff0001($a0) + lw $t5, 0xffff8001($a0) + lw $t5, 0xf0000000($a0) + lw $t5, 0xffffffff($a0) + lw $t5, 0x12345678($a0) + .set push + lwxs $s3, $a0($a1) + .set pop + + mfc0 $t4, $0 + mfc0 $t4, $1 + mfc0 $t4, $2, 1 + mfc0 $t4, $2, 2 + mtc0 $t4, $3 + mtc0 $t4, $4 + mtc0 $t4, $5, 6 + mtc0 $t4, $5, 7 + + movn $t4, $t5 + movn $t4, $t4, $t5 + movn $t4, $t5, $a0 + + movz $t4, $t5 + movz $t4, $t4, $t5 + movz $t4, $t5, $a0 + + mul $t4, $t5, $a0 + mul $sp, $fp, $ra + mul $t4, $t4, $a0 + mul $t4, $a0 + mul $t4, $t4, 0 + mul $t4, $t4, 1 + mul $t4, $t4, 32767 + mul $t4, $t4, -32768 + mul $t4, $t4, 65535 + + neg $t4, $t5 + neg $t4, $t4 + neg $t4 + negu $t4, $t5 + negu $t4, $t4 + negu $t4 + negu32 $t4, $t5 + negu32 $t4, $t4 + negu32 $t4 + + not $s2, $s2 + not $s2, $s2 + not $s2, $s3 + not $s2, $a0 + not $s2, $a1 + not $s2, $a2 + not $s2, $a3 + not $s2, $s0 + not $s2, $s1 + not $s3, $s1 + not $a0, $s1 + not $a1, $s1 + not $a2, $s1 + not $a3, $s1 + not $s0, $s1 + not $s1, $s1 + + nor $t4, $a3, $zero + nor $t4, $zero, $a3 + + nor32 $t4, $t5, $a0 + nor32 $sp, $fp, $ra + nor32 $t4, $t4, $a0 + nor32 $t4, $a0 + + nor $t4, $t5, 32768 + nor $t4, $t5, 65535 + nor $t4, $t5, 65536 + nor $t4, $t5, -32768 + nor $t4, $t5, -32769 + + or $t4, $s6, $zero + or $s6, $t4, $zero + or $t4, $zero, $s6 + or $s6, $zero, $t4 + + or $s2, $s2 + or $s2, $s3 + or $s2, $a0 + or $s2, $a1 + or $s2, $a2 + or $s2, $a3 + or $s2, $s0 + or $s2, $s1 + or $s3, $s2 + or $a0, $s2 + or $a1, $s2 + or $a2, $s2 + or $a3, $s2 + or $s0, $s2 + or $s1, $s2 + or $s2, $s2 + or $s2, $s2, $s3 + or $s2, $s3, $s2 + + or32 $t4, $t5, $a0 + or32 $sp, $fp, $ra + or32 $t4, $t4, $a0 + or32 $t4, $a0 + + or $t4, $t5, 32768 + or $t4, $t5, 4095 + or $t4, $t5, 4096 + or $t4, $t5, -32768 + or $t4, $t5, -32769 + + ori $t5, $a0, 0 + ori $t5, $a0, 4095 + + rdhwr $t4, $0 + rdhwr $t4, $1 + rdhwr $t4, $2 + rdhwr $t4, $3 + rdhwr $t4, $4 + rdhwr $t4, $5 + rdhwr $t4, $6 + rdhwr $t4, $7 + rdhwr $t4, $8 + rdhwr $t4, $9 + rdhwr $t4, $10 + + rdpgpr $t4, $t5 + rdpgpr $t4, $t4 + + rem $zero, $t4, $t5 + rem $zero, $fp, $ra + rem $zero, $t5 + rem $zero, $ra + + rem $t4, $t5, $zero + rem $t4, $t5, $a0 + + rem $t5, $a0, 0 + rem $t5, $a0, 1 + rem $t5, $a0, -1 + rem $t5, $a0, 2 + + rol $t4, $t5, $a0 + rol $t4, $t4, $a0 + rol $t4, $t5, $t5 + rol $t4, $t5, $t4 + + rol $t4, $t5, 0 + rol $t4, $t5, 1 + rol $t4, $t5, 31 + rol $t4, $t4, 31 + rol $t4, 31 + + ror $t4, $t5, 0 + ror $t4, $t5, 1 + ror $t4, $t5, 31 + ror $t4, $t4, 31 + ror $t4, 31 + + ror $t4, $t5, $a0 + ror $t4, $t4, $a0 + + rotr $t4, $t5, $a0 + rotr $t4, $t4, $a0 + + rorv $t4, $t5, $a0 + rorv $t4, $t4, $a0 + + rotrv $t4, $t5, $a0 + rotrv $t4, $t4, $a0 + + sb $zero, ($s3) + sb $zero, 0($s3) + sb $zero, 1($s3) + sb $zero, 2($s3) + sb $zero, 3($s3) + sb $zero, 4($t5) + sb $zero, 5($t5) + sb $zero, 6($t5) + sb $zero, 7($t5) + sb $zero, 8($t5) + sb $zero, 9($t5) + sb $zero, 10($t5) + sb $zero, 11($t5) + sb $zero, 12($t5) + sb $zero, 13($t5) + sb $zero, 14($t5) + sb $zero, 15($t5) + sb $t4, 15($t5) + sb $t5, 15($t5) + sb $a0, 15($t5) + sb $a1, 15($t5) + sb $a2, 15($t5) + sb $a3, 15($t5) + sb $s1, 15($t5) + sb $s1, 15($a0) + sb $s1, 15($a1) + sb $s1, 15($a2) + sb $s1, 15($a3) + sb $s1, 15($t4) + sb $s1, 15($s0) + sb $s1, 15($s1) + + sb32 $t5, 4 + sb32 $t5, 4($zero) + + sb32 $t5, 4095($zero) + + sb $t5, 65535($zero) + sb $t5, 0xffff0000($zero) + sb $t5, 0xffff8000($zero) + sb $t5, 0xffff0001($zero) + sb $t5, 0xffff8001($zero) + sb $t5, 0xf0000000($zero) + sb $t5, 0xffffffff($zero) + sb $t5, 0x12345678($zero) + sb32 $t5, ($a0) + sb32 $t5, 0($a0) + sb32 $t5, 4095($a0) + + sb $t5, 65535($a0) + sb $t5, 0xffff0000($a0) + sb $t5, 0xffff8000($a0) + sb $t5, 0xffff0001($a0) + sb $t5, 0xffff8001($a0) + sb $t5, 0xf0000000($a0) + sb $t5, 0xffffffff($a0) + sb $t5, 0x12345678($a0) + + sc $t5, 4 + sc $t5, 4($zero) + sc $t5, 2047($zero) + sc $t5, -2048($zero) + sc $t5, 32767($zero) + sc $t5, -32768($zero) + sc $t5, 65535($zero) + sc $t5, 0xffff0000($zero) + sc $t5, 0xffff8000($zero) + sc $t5, 0xffff0001($zero) + sc $t5, 0xffff8001($zero) + sc $t5, 0xf0000000($zero) + sc $t5, 0xffffffff($zero) + sc $t5, 0x12345678($zero) + sc $t5, ($a0) + sc $t5, 0($a0) + sc $t5, 2047($a0) + sc $t5, -2048($a0) + sc $t5, 32767($a0) + sc $t5, -32768($a0) + sc $t5, 65535($a0) + sc $t5, 0xffff0000($a0) + sc $t5, 0xffff8000($a0) + sc $t5, 0xffff0001($a0) + sc $t5, 0xffff8001($a0) + sc $t5, 0xf0000000($a0) + sc $t5, 0xffffffff($a0) + sc $t5, 0x12345678($a0) + + sdbbp + sdbbp 0 + sdbbp 1 + sdbbp 2 + sdbbp 3 + sdbbp 4 + sdbbp 5 + sdbbp 6 + sdbbp 7 + sdbbp 8 + sdbbp 9 + sdbbp 10 + sdbbp 11 + sdbbp 12 + sdbbp 13 + sdbbp 14 + sdbbp 15 + + + sdbbp32 + + sdbbp32 0 + sdbbp32 1 + sdbbp32 2 + sdbbp32 255 + + seb $t4, $t5 + seb $t4, $t4 + seb $t4 + seh $t4, $t5 + seh $t4, $t4 + seh $t4 + + seq $t4, $t5, $a0 + seq $t4, $t5, $zero + seq $t4, $zero, $a0 + + seq $t4, $t5, 0 + seq $t4, $t5, 1 + seq $t4, $t5, -1 + seq $t4, $t5, -32769 + + sge $t4, $t5, $a0 + sge $t4, $t4, $a0 + sge $t4, $a0 + sge $t4, $t5, 0 + sge $t4, $t5, -32768 + sge $t4, $t5, 0 + sge $t4, $t5, 32767 + sge $t4, $t5, 65535 + sge $t4, $t5, 65536 + sge $t4, $t5, -32769 + + sgeu $t4, $t5, $a0 + sgeu $t4, $t4, $a0 + sgeu $t4, $a0 + sgeu $t4, $t5, 0 + sgeu $t4, $t5, -32768 + sgeu $t4, $t5, 0 + sgeu $t4, $t5, 32767 + sgeu $t4, $t5, 65535 + sgeu $t4, $t5, 65536 + sgeu $t4, $t5, -32769 + + sgt $t4, $t5, $a0 + sgt $t4, $t4, $a0 + sgt $t4, $a0 + sgt $t4, $t5, 0 + sgt $t4, $t5, -32768 + sgt $t4, $t5, 0 + sgt $t4, $t5, 32767 + sgt $t4, $t5, 65535 + sgt $t4, $t5, 65536 + sgt $t4, $t5, -32769 + + sgtu $t4, $t5, $a0 + sgtu $t4, $t4, $a0 + sgtu $t4, $a0 + sgtu $t4, $t5, 0 + sgtu $t4, $t5, -32768 + sgtu $t4, $t5, 0 + sgtu $t4, $t5, 32767 + sgtu $t4, $t5, 65535 + sgtu $t4, $t5, 65536 + sgtu $t4, $t5, -32769 + + sh $s2, ($s3) + sh $s2, 0<<1($s3) + sh $s2, 1<<1($s3) + sh $s2, 2<<1($s3) + sh $s2, 3<<1($s3) + sh $t4, 4<<1($t5) + sh $t4, 5<<1($t5) + sh $t4, 6<<1($t5) + sh $t4, 7<<1($t5) + sh $t4, 8<<1($t5) + sh $t4, 9<<1($t5) + sh $t4, 10<<1($t5) + sh $t4, 11<<1($t5) + sh $t4, 12<<1($t5) + sh $t4, 13<<1($t5) + sh $t4, 14<<1($t5) + sh $t4, 15<<1($t5) + sh $t4, 15<<1($a0) + sh $t4, 15<<1($a1) + sh $t4, 15<<1($a2) + sh $t4, 15<<1($a3) + sh $t4, 15<<1($t4) + sh $t4, 15<<1($s0) + sh $t4, 15<<1($s1) + sh $t5, 15<<1($s1) + sh $a0, 15<<1($s1) + sh $a1, 15<<1($s1) + sh $a2, 15<<1($s1) + sh $a3, 15<<1($s1) + sh $s1, 15<<1($s1) + sh $zero, 15<<1($s1) + + sh32 $t5, 4 + sh32 $t5, 4($zero) + sh32 $t5, 4095($zero) + + sh $t5, 65535($zero) + sh $t5, 0xffff0000($zero) + sh $t5, 0xffff8000($zero) + sh $t5, 0xffff0001($zero) + sh $t5, 0xffff8001($zero) + sh $t5, 0xf0000000($zero) + sh $t5, 0xffffffff($zero) + sh $t5, 0x12345678($zero) + sh32 $t5, ($a0) + sh32 $t5, 0($a0) + sh32 $t5, 4095($a0) + + sh $t5, 65535($a0) + sh $t5, 0xffff0000($a0) + sh $t5, 0xffff8000($a0) + sh $t5, 0xffff0001($a0) + sh $t5, 0xffff8001($a0) + sh $t5, 0xf0000000($a0) + sh $t5, 0xffffffff($a0) + sh $t5, 0x12345678($a0) + + sle $t4, $t5, $a0 + sle $t4, $t4, $a0 + sle $t4, $a0 + sle $t4, $t5, 0 + sle $t4, $t5, -32768 + sle $t4, $t5, 0 + sle $t4, $t5, 32767 + sle $t4, $t5, 65535 + sle $t4, $t5, 65536 + sle $t4, $t5, -32769 + + sleu $t4, $t5, $a0 + sleu $t4, $t4, $a0 + sleu $t4, $a0 + sleu $t4, $t5, 0 + sleu $t4, $t5, -32768 + sleu $t4, $t5, 0 + sleu $t4, $t5, 32767 + sleu $t4, $t5, 65535 + sleu $t4, $t5, 65536 + sleu $t4, $t5, -32769 + + sll $s2, $s2, 1 + sll $s2, $s2, 2 + sll $s2, $s2, 3 + sll $s2, $s2, 4 + sll $s2, $s2, 5 + sll $s2, $s2, 6 + sll $s2, $s2, 7 + sll $s2, $s2, 8 + sll $s2, $s3, 8 + sll $s2, $a0, 8 + sll $s2, $a1, 8 + sll $s2, $a2, 8 + sll $s2, $a3, 8 + sll $s2, $s0, 8 + sll $s2, $s1, 8 + sll $s3, $s2, 8 + sll $a0, $s2, 8 + sll $a1, $s2, 8 + sll $a2, $s2, 8 + sll $a3, $s2, 8 + sll $s0, $s2, 8 + sll $s1, $s2, 8 + sll $s2, $s2, 1 + sll $s3, 1 + + sllv $t4, $t5, $a0 + sllv $t4, $t4, $a0 + sll $t4, $t4, $a0 + sll $t4, $a0 + + sll32 $t4, $a0, 0 + sll32 $t4, $a0, 1 + sll32 $t4, $a0, 31 + sll32 $t4, $t4, 31 + sll32 $t4, 31 + + slt $t4, $t5, $a0 + slt $t4, $t4, $a0 + slt $t4, $a0 + slt $t4, $t5, 0 + slt $t4, $t5, -32768 + slt $t4, $t5, 0 + slt $t4, $t5, 32767 + slt $t4, $t5, 65535 + slt $t4, $t5, 65536 + slt $t4, $t5, -32769 + + slti $t5, $a0, 0 + slti $t5, $a0, 4095 + + sltiu $t5, $a0, 0 + sltiu $t5, $a0, 4095 + + sltu $t4, $t5, $a0 + sltu $t4, $t4, $a0 + sltu $t4, $a0 + sltu $t4, $t5, 0 + sltu $t4, $t5, -32768 + sltu $t4, $t5, 0 + sltu $t4, $t5, 32767 + sltu $t4, $t5, 65535 + sltu $t4, $t5, 65536 + sltu $t4, $t5, -32769 + + sne $t4, $t5, $a0 + sne $t4, $zero, $a0 + sne $t4, $t5, $zero + + sne $t4, $t5, 0 + sne $t4, $t5, 1 + sne $t4, $t5, -1 + sne $t4, $t5, -32769 + + srav $t4, $t5, $a0 + srav $t4, $t4, $a0 + sra $t4, $t4, $a0 + sra $t4, $a0 + sra $t4, $a0, 0 + sra $t4, $a0, 1 + sra $t4, $a0, 31 + sra $t4, $t4, 31 + sra $t4, 31 + + srlv $t4, $t5, $a0 + srlv $t4, $t4, $a0 + srl $t4, $t4, $a0 + srl $t4, $a0 + srl $t4, $a0, 0 + srl $s2, $a0, 1 + srl $t4, $a0, 31 + srl $t4, $t4, 31 + srl $t4, 31 + + srl $s2, $s2, 1 + srl $s2, $s2, 2 + srl $s2, $s2, 3 + srl $s2, $s2, 4 + srl $s2, $s2, 5 + srl $s2, $s2, 6 + srl $s2, $s2, 7 + srl $s2, $s2, 8 + srl $s2, $s3, 8 + srl $s2, $a0, 8 + srl $s2, $a1, 8 + srl $s2, $a2, 8 + srl $s2, $a3, 8 + srl $s2, $s0, 8 + srl $s2, $s1, 8 + srl $s2, $s2, 8 + srl $s3, $s2, 8 + srl $a0, $s2, 8 + srl $a1, $s2, 8 + srl $a2, $s2, 8 + srl $a3, $s2, 8 + srl $s0, $s2, 8 + srl $s1, $s2, 8 + srl $s3, $s3, 1 + srl $s3, 1 + + sub $t4, $t5, $a0 + sub $sp, $fp, $ra + sub $t4, $t4, $a0 + sub $t4, $a0 + sub $t4, $t4, 0 + sub $t4, $t4, 1 + sub $t4, $t4, 32767 + sub $t4, $t4, -32768 + sub $t4, $t4, 65535 + subu $s2, $s3, $s2 + subu $s2, $s3, $s3 + subu $s2, $s3, $a0 + subu $s2, $s3, $a1 + subu $s2, $s3, $a2 + subu $s2, $s3, $a3 + subu $s2, $s3, $s0 + subu $s2, $s3, $s1 + subu $s2, $s2, $s1 + subu $s2, $a0, $s1 + subu $s2, $a1, $s1 + subu $s2, $a2, $s1 + subu $s2, $a3, $s1 + subu $s2, $s0, $s1 + subu $s2, $s1, $s1 + subu $s2, $s2, $s1 + subu $s3, $s2, $s1 + subu $a0, $s2, $s1 + subu $a1, $s2, $s1 + subu $a2, $s2, $s1 + subu $a3, $s2, $s1 + subu $s0, $s2, $s1 + subu $s1, $s2, $s1 + subu $a3, $a3, $s2 + subu $a3, $s2 + + subu32 $t4, $t5, $a0 + subu32 $sp, $fp, $ra + subu32 $t4, $t4, $a0 + subu32 $t4, $a0 + subu $t4, $t4, 0 + subu $t4, $t4, 1 + subu $t4, $t4, 32767 + subu $t4, $t4, -32768 + subu $t4, $t4, 65535 + + sw $s2, ($a0) + sw $s2, 0($a0) + sw $s2, 1<<2($a0) + sw $s2, 2<<2($a0) + sw $s2, 3<<2($a0) + sw $s2, 4<<2($a0) + sw $s2, 5<<2($a0) + sw $s2, 6<<2($a0) + sw $s2, 7<<2($a0) + sw $s2, 8<<2($a0) + sw $s2, 9<<2($a0) + sw $s2, 10<<2($a0) + sw $s2, 11<<2($a0) + sw $s2, 12<<2($a0) + sw $s2, 13<<2($a0) + sw $s2, 14<<2($a0) + sw $s2, 15<<2($a0) + sw $s2, 15<<2($a1) + sw $s2, 15<<2($a2) + sw $s2, 15<<2($a3) + sw $s2, 15<<2($s0) + sw $s2, 15<<2($s1) + sw $s2, 15<<2($s2) + sw $s2, 15<<2($s3) + sw $s3, 15<<2($s3) + sw $a0, 15<<2($s3) + sw $a1, 15<<2($s3) + sw $a2, 15<<2($s3) + sw $a3, 15<<2($s3) + sw $s1, 15<<2($s3) + sw $zero, 15<<2($s3) + + sw $zero, ($sp) + sw $zero, 0($sp) + sw $zero, 1<<2($sp) + sw $zero, 2<<2($sp) + sw $zero, 3<<2($sp) + sw $zero, 4<<2($sp) + sw $zero, 5<<2($sp) + sw $zero, 30<<2($sp) + sw $zero, 31<<2($sp) + sw $t4, 31<<2($sp) + sw $s1, 31<<2($sp) + sw $t5, 31<<2($sp) + sw $a0, 31<<2($sp) + sw $a1, 31<<2($sp) + sw $a2, 31<<2($sp) + sw $a3, 31<<2($sp) + sw $ra, 31<<2($sp) + + sw32 $t5, 4 + sw32 $t5, 4($zero) + sw32 $t5, 4095($zero) + + sw $t5, 65535($zero) + sw $t5, 0xffff0000($zero) + sw $t5, 0xffff8000($zero) + sw $t5, 0xffff0001($zero) + sw $t5, 0xffff8001($zero) + sw $t5, 0xf0000000($zero) + sw $t5, 0xffffffff($zero) + sw $t5, 0x12345678($zero) + sw32 $t5, ($a0) + sw32 $t5, 0($a0) + sw32 $t5, 4095($a0) + + sw $t5, 65535($a0) + sw $t5, 0xffff0000($a0) + sw $t5, 0xffff8000($a0) + sw $t5, 0xffff0001($a0) + sw $t5, 0xffff8001($a0) + sw $t5, 0xf0000000($a0) + sw $t5, 0xffffffff($a0) + sw $t5, 0x12345678($a0) + + sync + sync 0 + sync 1 + sync 2 + sync 3 + sync 5 + sync 30 + sync 31 + + synci 0 + synci ($zero) + synci 0($zero) + synci 2047($zero) + synci 2048($zero) + + synci 0($t4) + synci 0($t5) + synci 255($t5) + synci -256($t5) + synci 2048($t5) + + syscall + syscall 0 + syscall 1 + syscall 2 + syscall 255 +/* + teq $t4, $t5 + teq $t5, $t4 + teq $t4, $t5, 0 + teq $t4, $t5, 1 + teq $t4, $t5, 15 + teq $t4, 0 + teq $t4, -32768 + teq $t4, 32767 + teq $t4, 65535 + + tlbp + tlbr + tlbwi + tlbwr + + tne $t4, $t5 + tne $t5, $t4 + tne $t4, $t5, 0 + tne $t4, $t5, 1 + tne $t4, $t5, 15 + tne $t4, 0 + tne $t4, -32768 + tne $t4, 32767 + tne $t4, 65535 + tne $t4, 65536 + tne $t4, 0xffffffff +*/ + wait + wait 0 + wait 1 + wait 255 + + wrpgpr $t4, $t5 + wrpgpr $t4, $a0 + wrpgpr $t4, $t4 + wrpgpr $t4 + + wsbh $t4, $t5 + wsbh $t4, $a0 + wsbh $t4, $t4 + wsbh $t4 + + xor $s2, $s2 + xor $s2, $s3 + xor $s2, $a0 + xor $s2, $a1 + xor $s2, $a2 + xor $s2, $a3 + xor $s2, $s0 + xor $s2, $s1 + xor $s3, $s1 + xor $a0, $s1 + xor $a1, $s1 + xor $a2, $s1 + xor $a3, $s1 + xor $s0, $s1 + xor $s1, $s1 + xor $s2, $s3 + xor $s2, $s2, $s3 + xor $s2, $s3, $s2 + + xor32 $t4, $t5, $a0 + xor32 $sp, $fp, $ra + xor32 $t4, $t4, $a0 + xor32 $t4, $a0 + + xor $t4, $t5, 32768 + xor $t4, $t5, 4095 + xor $t4, $t5, 4096 + xor $t4, $t5, -32768 + xor $t4, $t5, -32769 + + xori $t5, $a0, 0 + xori $t5, $t5, 4095 + + beqz $a5, test + addu $s3, $a0, $a1 + + beq $a5, $a6, test + addu $s3, $a0, $a1 + + beq $a5, 0, test + addu $s3, $a0, $a1 + + beq $a5, 1, test + addu $s3, $a0, $a1 + + bge $a6, $zero, test + addu $s3, $a0, $a1 + + bge $a6, $zero, test + addu $s3, $a0, $a1 + + bge $zero, $a6, test + addu $s3, $a0, $a1 + + bge $a6, $a7, test + addu $s3, $a0, $a1 + + bge $a6, 0, test + addu $s3, $a0, $a1 + + bge $a6, 1, test + addu $s3, $a0, $a1 + + bge $a6, 2, test + addu $s3, $a0, $a1 + + bge $a6, 0x80000000, test + addu $s3, $a0, $a1 + + bgeu $t4, $zero, test + addu $s3, $a0, $a1 + + bgeu $zero, $t4, test + addu $s3, $a0, $a1 + + bgeu $t4, $t5, test + addu $s3, $a0, $a1 + + bgeu $t4, 0, test + addu $s3, $a0, $a1 + + bgeu $t4, 1, test + addu $s3, $a0, $a1 + + bgeu $t4, 2, test + addu $s3, $a0, $a1 + + bgez $t4, test + addu $s3, $a0, $a1 + + bgt $t4, $zero, test + addu $s3, $a0, $a1 + + bgt $zero, $t4, test + addu $s3, $a0, $a1 + + bgt $a5, $a6, test + addu $s3, $a0, $a1 + + bgt $a5, 0x7fffffff, test + addu $s3, $a0, $a1 + + bgt $a5, -1, test + addu $s3, $a0, $a1 + + bgt $a5, 0, test + addu $s3, $a0, $a1 + + bgt $a5, 1, test + addu $s3, $a0, $a1 + + bgt $a5, 0x80000000, test + addu $s3, $a0, $a1 + + bgtu $a5, $zero, test + addu $s3, $a0, $a1 + + bgtu $zero, $a5, test + addu $s3, $a0, $a1 + + bgtu $a5, $a6, test + addu $s3, $a0, $a1 + + bgtu $zero, 0, test + addu $s3, $a0, $a1 + + bgtu $a5, 0xffffffff, test + addu $s3, $a0, $a1 + + bgtu $a5, -1, test + addu $s3, $a0, $a1 + + bgtu $a5, 0, test + addu $s3, $a0, $a1 + + bgtu $a5, 1, test + addu $s3, $a0, $a1 + + bgtz $a5, test + addu $s3, $a0, $a1 + + ble $a5, $zero, test + addu $s3, $a0, $a1 + + ble $zero, $a6, test + addu $s3, $a0, $a1 + + ble $a5, $a6, test + addu $s3, $a0, $a1 + + ble $a5, 0x7fffffff, test + addu $s3, $a0, $a1 + + ble $a5, -1, test + addu $s3, $a0, $a1 + + ble $a5, 0, test + addu $s3, $a0, $a1 + + ble $a5, 1, test + addu $s3, $a0, $a1 + + bleu $a5, $zero, test + addu $s3, $a0, $a1 + + bleu $zero, $a6, test + addu $s3, $a0, $a1 + + bleu $a5, $a6, test + addu $s3, $a0, $a1 + + bleu $zero, $a6, test + addu $s3, $a0, $a1 + + bleu $a5, 0xffffffff, test + addu $s3, $a0, $a1 + + bleu $a5, 0, test + addu $s3, $a0, $a1 + + bleu $a5, 1, test + addu $s3, $a0, $a1 + + blez $a5, test + addu $s3, $a0, $a1 + + blt $a5, $zero, test + addu $s3, $a0, $a1 + + blt $zero, $a6, test + addu $s3, $a0, $a1 + + blt $a5, $a6, test + addu $s3, $a0, $a1 + + blt $a5, 0, test + addu $s3, $a0, $a1 + + blt $a5, 1, test + addu $s3, $a0, $a1 + + blt $a5, 2, test + addu $s3, $a0, $a1 + + bltu $a5, $zero, test + addu $s3, $a0, $a1 + + bltu $zero, $a6, test + addu $s3, $a0, $a1 + + bltu $a5, $a6, test + addu $s3, $a0, $a1 + + bltu $a5, 0, test + addu $s3, $a0, $a1 + + bltu $a5, 1, test + addu $s3, $a0, $a1 + + bltu $a5, 2, test + addu $s3, $a0, $a1 + + bltz $a5, test + addu $s3, $a0, $a1 + + bnez $a5, test + addu $s3, $a0, $a1 + + bne $a5, $a6, test + addu $s3, $a0, $a1 + + bne $a5, 0, test + addu $s3, $a0, $a1 + + bne $a5, 1, test + addu $s3, $a0, $a1 + + jraddiusp 0 << 2 + jraddiusp 2 << 2 + jraddiusp 4 << 2 + jraddiusp 6 << 2 + jraddiusp 8 << 2 + jraddiusp 10 << 2 + jraddiusp (1 << 2) + jraddiusp 3 << 2 + jraddiusp 5 << 2 + jraddiusp 7 << 2 + jraddiusp 9 << 2 + jraddiusp 30 << 2 + jraddiusp 31 << 2 + + sdbbp 1023 + wait 1023 + syscall 1023 + .end test + + .ent test_delay_slot +test_delay_slot: + bal test_delay_slot + .ifndef insn32 + jalr16 $t4 + .endif + jalr32 $t4 + .ifndef insn32 + jr16 $t4 + .endif + jr32 $t4 + jalr.hb $t4 + + jr.hb $t4 + .end test_delay_slot + + .ent test_spec102 +test_spec102: + lw $s2, 127<<2 ($gp) + lw $s3, 127<<2 ($gp) + lw $a0, 127<<2 ($gp) + lw $a1, 127<<2 ($gp) + lw $a2, 127<<2 ($gp) + lw $a3, 127<<2 ($gp) + lw $s0, 127<<2 ($gp) + lw $s1, 127<<2 ($gp) + lw $s1, 126<<2 ($gp) + lw $s1, 125<<2 ($gp) + lw $s1, 0<<2 ($gp) + lw $s1, 1<<2 ($gp) + lw $s1, 62<<2 ($gp) + lw $s1, 63<<2 ($gp) + lw $s1, 64<<2 ($gp) + lw $s1, -65<<2 ($gp) + lw $s1, 1 ($gp) + lw $s1, 2 ($gp) + lw $s1, 3 ($gp) + lw $s1, -1 ($gp) + lw $s1, -2 ($gp) + lw $s1, -3 ($gp) + lw $s1, 0 ($k1) + .end test_spec102 + + .ent test_spec107 +test_spec107: + .ifndef insn32 + movep $a1, $a2, $zero, $zero + movep $a2, $a3, $zero, $zero + movep $a0, $a1, $zero, $zero + movep $a1, $a2, $zero, $zero + movep $a2, $a3, $zero, $zero + movep $a2, $a3, $s1, $zero + movep $a2, $a3, $a5, $zero + movep $a2, $a3, $a6, $zero + movep $a2, $a3, $s0, $zero + movep $a2, $a3, $s2, $zero + movep $a2, $a3, $s3, $zero + movep $a2, $a3, $s4, $zero + movep $a2, $a3, $s4, $s1 + movep $a2, $a3, $s4, $a5 + movep $a2, $a3, $s4, $a6 + movep $a2, $a3, $s4, $s0 + movep $a2, $a3, $s4, $s2 + movep $a2, $a3, $s4, $s3 + movep $a2, $a3, $s4, $s4 + .endif + + andi $t4, $t4, 0xfff + andi $t4, $t5, 0x1fff + andi $t4, $a0, 0x3fff + andi $t4, $a1, 0x7fff + andi $t4, $a2, 0xffff + andi $t4, $a3, 0x1fffff + andi $t4, $a4, 0x3fffff + andi $t4, $a5, 0x7fffff + andi $t4, $s0, 0xffffff + li $t4, test + dvp + dvp $a1 + evp + evp $a2 + .end test_spec107 diff --git a/gas/testsuite/gas/nanomips/nanomips32.d b/gas/testsuite/gas/nanomips/nanomips32.d new file mode 100644 index 00000000000..5f410744952 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips32.d @@ -0,0 +1,2309 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS 32-bit instruction mode +#as: -minsn32 --defsym insn32= +#warning_output: nanomips.l +#source: nanomips.s + +# Check nanoMIPS32 fixed-size instructions + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 37ff pref 0x0,2047\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3800 pref 0x0,2048\(zero\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8420 3000 pref 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> 8440 3000 pref 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 3000 pref 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> 8480 3000 pref 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> 84a0 3000 pref 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> 84c0 3000 pref 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 3000 pref 0x7,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 31ff pref 0x7,511\(zero\) +[0-9a-f]+ <[^>]+> 8020 8200 li at,-512 +[0-9a-f]+ <[^>]+> a4e1 1800 pref 0x7,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 0022 7fff addiu at,t4,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2041 0950 addu at,at,t4 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 8000 c003 ehb +[0-9a-f]+ <[^>]+> 8000 c005 pause +[0-9a-f]+ <[^>]+> 8240 8001 li s2,-1 +[0-9a-f]+ <[^>]+> 8260 8001 li s3,-1 +[0-9a-f]+ <[^>]+> 8080 8001 li a0,-1 +[0-9a-f]+ <[^>]+> 80a0 8001 li a1,-1 +[0-9a-f]+ <[^>]+> 80c0 8001 li a2,-1 +[0-9a-f]+ <[^>]+> 80e0 8001 li a3,-1 +[0-9a-f]+ <[^>]+> 8200 8001 li s0,-1 +[0-9a-f]+ <[^>]+> 8220 8001 li s1,-1 +[0-9a-f]+ <[^>]+> 0220 0000 li s1,0 +[0-9a-f]+ <[^>]+> 0220 007d li s1,125 +[0-9a-f]+ <[^>]+> 0220 007e li s1,126 +[0-9a-f]+ <[^>]+> 0220 007f li s1,127 +[0-9a-f]+ <[^>]+> 0180 0000 li t0,0 +[0-9a-f]+ <[^>]+> 0320 0000 li t9,0 +[0-9a-f]+ <[^>]+> 0040 0000 li t4,0 +[0-9a-f]+ <[^>]+> 0040 0001 li t4,1 +[0-9a-f]+ <[^>]+> 0040 7fff li t4,32767 +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 0040 ffff li t4,65535 +[0-9a-f]+ <[^>]+> e041 0000 lui t4,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8042 0001 ori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8040 8001 li t4,-1 +[0-9a-f]+ <[^>]+> e054 5244 lui t4,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8042 0678 ori t4,t4,0x678 +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> 8080 8001 li a0,-1 +[0-9a-f]+ <[^>]+> 2016 0290 move zero,s6 +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2016 1a90 move t5,s6 +[0-9a-f]+ <[^>]+> 2016 2290 move a0,s6 +[0-9a-f]+ <[^>]+> 2016 2a90 move a1,s6 +[0-9a-f]+ <[^>]+> 2016 3290 move a2,s6 +[0-9a-f]+ <[^>]+> 2016 3a90 move a3,s6 +[0-9a-f]+ <[^>]+> 2016 4290 move a4,s6 +[0-9a-f]+ <[^>]+> 2016 4a90 move a5,s6 +[0-9a-f]+ <[^>]+> 2016 5290 move a6,s6 +[0-9a-f]+ <[^>]+> 2016 f290 move fp,s6 +[0-9a-f]+ <[^>]+> 2016 fa90 move ra,s6 +[0-9a-f]+ <[^>]+> 2000 0290 move zero,zero +[0-9a-f]+ <[^>]+> 2002 0290 move zero,t4 +[0-9a-f]+ <[^>]+> 2003 0290 move zero,t5 +[0-9a-f]+ <[^>]+> 2004 0290 move zero,a0 +[0-9a-f]+ <[^>]+> 2005 0290 move zero,a1 +[0-9a-f]+ <[^>]+> 2006 0290 move zero,a2 +[0-9a-f]+ <[^>]+> 2007 0290 move zero,a3 +[0-9a-f]+ <[^>]+> 2008 0290 move zero,a4 +[0-9a-f]+ <[^>]+> 2009 0290 move zero,a5 +[0-9a-f]+ <[^>]+> 200a 0290 move zero,a6 +[0-9a-f]+ <[^>]+> 201e 0290 move zero,fp +[0-9a-f]+ <[^>]+> 201f 0290 move zero,ra +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2003 1290 move t4,t5 +[0-9a-f]+ <[^>]+> 8803 8000 bgezc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_0 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2004 1290 move t4,a0 +[0-9a-f]+ <[^>]+> 8804 8000 bgezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_1 +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_2 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_3 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2083 1110 add t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e910 add sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0064 0000 addiu t5,a0,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 8000 8008 li zero,-8 +[0-9a-f]+ <[^>]+> 8042 8008 addiu t4,t4,-8 +[0-9a-f]+ <[^>]+> 8063 8008 addiu t5,t5,-8 +[0-9a-f]+ <[^>]+> 8084 8008 addiu a0,a0,-8 +[0-9a-f]+ <[^>]+> 80a5 8008 addiu a1,a1,-8 +[0-9a-f]+ <[^>]+> 80c6 8008 addiu a2,a2,-8 +[0-9a-f]+ <[^>]+> 80e7 8008 addiu a3,a3,-8 +[0-9a-f]+ <[^>]+> 8108 8008 addiu a4,a4,-8 +[0-9a-f]+ <[^>]+> 8129 8008 addiu a5,a5,-8 +[0-9a-f]+ <[^>]+> 814a 8008 addiu a6,a6,-8 +[0-9a-f]+ <[^>]+> 83de 8008 addiu fp,fp,-8 +[0-9a-f]+ <[^>]+> 83ff 8008 addiu ra,ra,-8 +[0-9a-f]+ <[^>]+> 83ff 8007 addiu ra,ra,-7 +[0-9a-f]+ <[^>]+> 03ff 0000 addiu ra,ra,0 +[0-9a-f]+ <[^>]+> 03ff 0001 addiu ra,ra,1 +[0-9a-f]+ <[^>]+> 03ff 0006 addiu ra,ra,6 +[0-9a-f]+ <[^>]+> 03ff 0007 addiu ra,ra,7 +[0-9a-f]+ <[^>]+> 03ff 0008 addiu ra,ra,8 +[0-9a-f]+ <[^>]+> 83bd 8408 addiu sp,sp,-1032 +[0-9a-f]+ <[^>]+> 83bd 8404 addiu sp,sp,-1028 +[0-9a-f]+ <[^>]+> 83bd 8400 addiu sp,sp,-1024 +[0-9a-f]+ <[^>]+> 03bd 03fc addiu sp,sp,1020 +[0-9a-f]+ <[^>]+> 03bd 0400 addiu sp,sp,1024 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0408 addiu sp,sp,1032 +[0-9a-f]+ <[^>]+> 8042 8001 addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 8043 8001 addiu t4,t5,-1 +[0-9a-f]+ <[^>]+> 8044 8001 addiu t4,a0,-1 +[0-9a-f]+ <[^>]+> 8045 8001 addiu t4,a1,-1 +[0-9a-f]+ <[^>]+> 8046 8001 addiu t4,a2,-1 +[0-9a-f]+ <[^>]+> 8047 8001 addiu t4,a3,-1 +[0-9a-f]+ <[^>]+> 8050 8001 addiu t4,s0,-1 +[0-9a-f]+ <[^>]+> 8051 8001 addiu t4,s1,-1 +[0-9a-f]+ <[^>]+> 0051 0001 addiu t4,s1,1 +[0-9a-f]+ <[^>]+> 0251 0004 addiu s2,s1,4 +[0-9a-f]+ <[^>]+> 0251 0008 addiu s2,s1,8 +[0-9a-f]+ <[^>]+> 0251 000c addiu s2,s1,12 +[0-9a-f]+ <[^>]+> 0251 0010 addiu s2,s1,16 +[0-9a-f]+ <[^>]+> 0251 0014 addiu s2,s1,20 +[0-9a-f]+ <[^>]+> 0251 0018 addiu s2,s1,24 +[0-9a-f]+ <[^>]+> 0271 0018 addiu s3,s1,24 +[0-9a-f]+ <[^>]+> 0091 0018 addiu a0,s1,24 +[0-9a-f]+ <[^>]+> 00b1 0018 addiu a1,s1,24 +[0-9a-f]+ <[^>]+> 00d1 0018 addiu a2,s1,24 +[0-9a-f]+ <[^>]+> 00f1 0018 addiu a3,s1,24 +[0-9a-f]+ <[^>]+> 0211 0018 addiu s0,s1,24 +[0-9a-f]+ <[^>]+> 0231 0018 addiu s1,s1,24 +[0-9a-f]+ <[^>]+> 025d 0000 addiu s2,sp,0 +[0-9a-f]+ <[^>]+> 025d 0004 addiu s2,sp,4 +[0-9a-f]+ <[^>]+> 025d 00f8 addiu s2,sp,248 +[0-9a-f]+ <[^>]+> 025d 00fc addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 005d 0100 addiu t4,sp,256 +[0-9a-f]+ <[^>]+> 025d 00fc addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 027d 00fc addiu s3,sp,252 +[0-9a-f]+ <[^>]+> 009d 00fc addiu a0,sp,252 +[0-9a-f]+ <[^>]+> 00bd 00fc addiu a1,sp,252 +[0-9a-f]+ <[^>]+> 00dd 00fc addiu a2,sp,252 +[0-9a-f]+ <[^>]+> 00fd 00fc addiu a3,sp,252 +[0-9a-f]+ <[^>]+> 021d 00fc addiu s0,sp,252 +[0-9a-f]+ <[^>]+> 023d 00fc addiu s1,sp,252 +[0-9a-f]+ <[^>]+> 8064 8fff addiu t5,a0,-4095 +[0-9a-f]+ <[^>]+> 0264 0000 addiu s3,a0,0 +[0-9a-f]+ <[^>]+> 0064 1fff addiu t5,a0,8191 +[0-9a-f]+ <[^>]+> 0064 3fff addiu t5,a0,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 2016 1150 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b150 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1150 addu t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b150 addu s6,zero,t4 +[0-9a-f]+ <[^>]+> 2253 9150 addu s2,s3,s2 +[0-9a-f]+ <[^>]+> 2273 9150 addu s2,s3,s3 +[0-9a-f]+ <[^>]+> 2093 9150 addu s2,s3,a0 +[0-9a-f]+ <[^>]+> 20b3 9150 addu s2,s3,a1 +[0-9a-f]+ <[^>]+> 20d3 9150 addu s2,s3,a2 +[0-9a-f]+ <[^>]+> 20f3 9150 addu s2,s3,a3 +[0-9a-f]+ <[^>]+> 2213 9150 addu s2,s3,s0 +[0-9a-f]+ <[^>]+> 2233 9150 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> 2232 9150 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2233 9150 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> 2224 9150 addu s2,a0,s1 +[0-9a-f]+ <[^>]+> 2225 9150 addu s2,a1,s1 +[0-9a-f]+ <[^>]+> 2226 9150 addu s2,a2,s1 +[0-9a-f]+ <[^>]+> 2227 9150 addu s2,a3,s1 +[0-9a-f]+ <[^>]+> 2230 9150 addu s2,s0,s1 +[0-9a-f]+ <[^>]+> 2231 9150 addu s2,s1,s1 +[0-9a-f]+ <[^>]+> 2232 9150 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 9950 addu s3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 2150 addu a0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 2950 addu a1,s2,s1 +[0-9a-f]+ <[^>]+> 2232 3150 addu a2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 3950 addu a3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 8150 addu s0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 8950 addu s1,s2,s1 +[0-9a-f]+ <[^>]+> 2247 3950 addu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2247 3950 addu a3,a3,s2 +[0-9a-f]+ <[^>]+> 20f2 3950 addu a3,s2,a3 +[0-9a-f]+ <[^>]+> 23fe e950 addu sp,fp,ra +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0042 0001 addiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0042 7fff addiu t4,t4,32767 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1150 addu t4,t4,at +[0-9a-f]+ <[^>]+> 0042 ffff addiu t4,t4,65535 +[0-9a-f]+ <[^>]+> 2252 9250 and s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9250 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2092 9250 and s2,s2,a0 +[0-9a-f]+ <[^>]+> 20b2 9250 and s2,s2,a1 +[0-9a-f]+ <[^>]+> 20d2 9250 and s2,s2,a2 +[0-9a-f]+ <[^>]+> 20f2 9250 and s2,s2,a3 +[0-9a-f]+ <[^>]+> 2212 9250 and s2,s2,s0 +[0-9a-f]+ <[^>]+> 2232 9250 and s2,s2,s1 +[0-9a-f]+ <[^>]+> 2253 9a50 and s3,s3,s2 +[0-9a-f]+ <[^>]+> 2244 2250 and a0,a0,s2 +[0-9a-f]+ <[^>]+> 2245 2a50 and a1,a1,s2 +[0-9a-f]+ <[^>]+> 2246 3250 and a2,a2,s2 +[0-9a-f]+ <[^>]+> 2247 3a50 and a3,a3,s2 +[0-9a-f]+ <[^>]+> 2250 8250 and s0,s0,s2 +[0-9a-f]+ <[^>]+> 2251 8a50 and s1,s1,s2 +[0-9a-f]+ <[^>]+> 2272 9250 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2272 9250 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2253 9250 and s2,s3,s2 +[0-9a-f]+ <[^>]+> 2062 1250 and t4,t4,t5 +[0-9a-f]+ <[^>]+> 8252 2001 andi s2,s2,0x1 +[0-9a-f]+ <[^>]+> 8252 2002 andi s2,s2,0x2 +[0-9a-f]+ <[^>]+> 8252 2003 andi s2,s2,0x3 +[0-9a-f]+ <[^>]+> 8252 2004 andi s2,s2,0x4 +[0-9a-f]+ <[^>]+> 8252 2007 andi s2,s2,0x7 +[0-9a-f]+ <[^>]+> 8252 2008 andi s2,s2,0x8 +[0-9a-f]+ <[^>]+> 8252 200f andi s2,s2,0xf +[0-9a-f]+ <[^>]+> 8042 2010 andi t4,t4,0x10 +[0-9a-f]+ <[^>]+> 8042 201f andi t4,t4,0x1f +[0-9a-f]+ <[^>]+> 8042 2020 andi t4,t4,0x20 +[0-9a-f]+ <[^>]+> 8042 203f andi t4,t4,0x3f +[0-9a-f]+ <[^>]+> 8042 2040 andi t4,t4,0x40 +[0-9a-f]+ <[^>]+> 8042 2080 andi t4,t4,0x80 +[0-9a-f]+ <[^>]+> 8252 20ff andi s2,s2,0xff +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> 8252 f3c0 ext s2,s2,0,16 +[0-9a-f]+ <[^>]+> 8253 f3c0 ext s2,s3,0,16 +[0-9a-f]+ <[^>]+> 8244 f3c0 ext s2,a0,0,16 +[0-9a-f]+ <[^>]+> 8245 f3c0 ext s2,a1,0,16 +[0-9a-f]+ <[^>]+> 8246 f3c0 ext s2,a2,0,16 +[0-9a-f]+ <[^>]+> 8247 f3c0 ext s2,a3,0,16 +[0-9a-f]+ <[^>]+> 8250 f3c0 ext s2,s0,0,16 +[0-9a-f]+ <[^>]+> 8251 f3c0 ext s2,s1,0,16 +[0-9a-f]+ <[^>]+> 8271 f3c0 ext s3,s1,0,16 +[0-9a-f]+ <[^>]+> 8091 f3c0 ext a0,s1,0,16 +[0-9a-f]+ <[^>]+> 80b1 f3c0 ext a1,s1,0,16 +[0-9a-f]+ <[^>]+> 80d1 f3c0 ext a2,s1,0,16 +[0-9a-f]+ <[^>]+> 80f1 f3c0 ext a3,s1,0,16 +[0-9a-f]+ <[^>]+> 8211 f3c0 ext s0,s1,0,16 +[0-9a-f]+ <[^>]+> 8231 f3c0 ext s1,s1,0,16 +[0-9a-f]+ <[^>]+> 80e7 f3c0 ext a3,a3,0,16 +[0-9a-f]+ <[^>]+> 80e7 f3c0 ext a3,a3,0,16 +[0-9a-f]+ <[^>]+> 2083 1250 and t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 2000 andi t4,t5,0x0 +[0-9a-f]+ <[^>]+> 8043 2fff andi t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8021 0001 ori at,at,0x1 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> 8a40 0000 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a60 0000 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8880 0000 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88a0 0000 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88c0 0000 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88e0 0000 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8812 0000 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8813 0000 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8804 0000 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8805 0000 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8806 0000 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8807 0000 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8810 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8811 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a40 0000 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a60 0000 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8880 0000 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88a0 0000 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88c0 0000 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88e0 0000 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> ca00 5000 beqic s0,10,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test2 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa40 0000 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa60 0000 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a880 0000 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8a0 0000 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8c0 0000 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8e0 0000 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a812 0000 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a813 0000 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a804 0000 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a805 0000 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a806 0000 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a807 0000 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a810 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a811 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa40 0000 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa60 0000 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a880 0000 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8a0 0000 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8c0 0000 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8e0 0000 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0001 break 0x1 +[0-9a-f]+ <[^>]+> 0010 0002 break 0x2 +[0-9a-f]+ <[^>]+> 0010 0003 break 0x3 +[0-9a-f]+ <[^>]+> 0010 0004 break 0x4 +[0-9a-f]+ <[^>]+> 0010 0005 break 0x5 +[0-9a-f]+ <[^>]+> 0010 0006 break 0x6 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 0010 0008 break 0x8 +[0-9a-f]+ <[^>]+> 0010 0009 break 0x9 +[0-9a-f]+ <[^>]+> 0010 000a break 0xa +[0-9a-f]+ <[^>]+> 0010 000b break 0xb +[0-9a-f]+ <[^>]+> 0010 000c break 0xc +[0-9a-f]+ <[^>]+> 0010 000d break 0xd +[0-9a-f]+ <[^>]+> 0010 000e break 0xe +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0001 break 0x1 +[0-9a-f]+ <[^>]+> 0010 0002 break 0x2 +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a402 3900 cache 0x0,0\(t4\) +[0-9a-f]+ <[^>]+> 8022 8800 addiu at,t4,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 07ff addiu at,t4,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8022 8801 addiu at,t4,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 0800 addiu at,t4,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a420 3900 cache 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> a440 3900 cache 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> a460 3900 cache 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> a480 3900 cache 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> a4a0 3900 cache 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> a4c0 3900 cache 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> a7e0 3900 cache 0x1f,0\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0023 0800 addiu at,t5,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8023 8801 addiu at,t5,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e3 b9ff cache 0x1f,-1\(t5\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0023 ffff addiu at,t5,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e0 b9ff cache 0x1f,-1\(zero\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 2043 4b3f clo t4,t5 +[0-9a-f]+ <[^>]+> 2062 4b3f clo t5,t4 +[0-9a-f]+ <[^>]+> 2043 5b3f clz t4,t5 +[0-9a-f]+ <[^>]+> 2062 5b3f clz t5,t4 +[0-9a-f]+ <[^>]+> 2000 e37f deret +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2040 477f di t4 +[0-9a-f]+ <[^>]+> 2060 477f di t5 +[0-9a-f]+ <[^>]+> 23c0 477f di fp +[0-9a-f]+ <[^>]+> 23e0 477f di ra +[0-9a-f]+ <[^>]+> 2062 0118 div zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0118 div zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0118 div zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0118 div zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1118 div t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1118 div t4,t5,a0 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 2004 1a90 move t5,a0 +[0-9a-f]+ <[^>]+> 2080 1990 neg t5,a0 +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1918 div t5,a0,at +[0-9a-f]+ <[^>]+> 2062 0198 divu zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0198 divu zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0198 divu zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0198 divu zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1198 divu t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1198 divu t4,t5,a0 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 2004 1a90 move t5,a0 +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2040 577f ei t4 +[0-9a-f]+ <[^>]+> 2060 577f ei t5 +[0-9a-f]+ <[^>]+> 23c0 577f ei fp +[0-9a-f]+ <[^>]+> 23e0 577f ei ra +[0-9a-f]+ <[^>]+> 2000 f37f eret +[0-9a-f]+ <[^>]+> 8043 f385 ext t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 f7c0 ext t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 f01f ext t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe f01f ext ra,fp,31,1 +[0-9a-f]+ <[^>]+> 8043 e4c5 ins t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 e7c0 ins t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 e7df ins t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe e7df ins ra,fp,31,1 +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4800 1000 jrc.hb zero +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 4803 1000 jrc.hb t5 +[0-9a-f]+ <[^>]+> 4804 1000 jrc.hb a0 +[0-9a-f]+ <[^>]+> 4805 1000 jrc.hb a1 +[0-9a-f]+ <[^>]+> 4806 1000 jrc.hb a2 +[0-9a-f]+ <[^>]+> 4807 1000 jrc.hb a3 +[0-9a-f]+ <[^>]+> 4808 1000 jrc.hb a4 +[0-9a-f]+ <[^>]+> 481e 1000 jrc.hb fp +[0-9a-f]+ <[^>]+> 481f 1000 jrc.hb ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> 4840 0000 jalrc t4,zero +[0-9a-f]+ <[^>]+> 4862 0000 jalrc t5,t4 +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4844 0000 jalrc t4,a0 +[0-9a-f]+ <[^>]+> 4845 0000 jalrc t4,a1 +[0-9a-f]+ <[^>]+> 4846 0000 jalrc t4,a2 +[0-9a-f]+ <[^>]+> 4847 0000 jalrc t4,a3 +[0-9a-f]+ <[^>]+> 4848 0000 jalrc t4,a4 +[0-9a-f]+ <[^>]+> 485e 0000 jalrc t4,fp +[0-9a-f]+ <[^>]+> 485f 0000 jalrc t4,ra +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4bdf 1000 jalrc.hb fp,ra +[0-9a-f]+ <[^>]+> 4840 1000 jalrc.hb t4,zero +[0-9a-f]+ <[^>]+> 4862 1000 jalrc.hb t5,t4 +[0-9a-f]+ <[^>]+> 4843 1000 jalrc.hb t4,t5 +[0-9a-f]+ <[^>]+> 4844 1000 jalrc.hb t4,a0 +[0-9a-f]+ <[^>]+> 4845 1000 jalrc.hb t4,a1 +[0-9a-f]+ <[^>]+> 4846 1000 jalrc.hb t4,a2 +[0-9a-f]+ <[^>]+> 4847 1000 jalrc.hb t4,a3 +[0-9a-f]+ <[^>]+> 4848 1000 jalrc.hb t4,a4 +[0-9a-f]+ <[^>]+> 485e 1000 jalrc.hb t4,fp +[0-9a-f]+ <[^>]+> 485f 1000 jalrc.hb t4,ra +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4bff 0000 jalrc ra +[0-9a-f]+ <[^>]+> 2a00 0000 balc 00000000 + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 test2 +[0-9a-f]+ <[^>]+> e040 0000 lui t4,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 test +[0-9a-f]+ <[^>]+> 8042 0000 ori t4,t4,0x0 + [0-9a-f]+: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 80ff lb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 0000 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 0000 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 0004 lb t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 80ff lb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a443 90ff lbu t4,-1\(t5\) +[0-9a-f]+ <[^>]+> 8653 2000 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 2000 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 2001 lbu s2,1\(s3\) +[0-9a-f]+ <[^>]+> 8653 2002 lbu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 8653 2003 lbu s2,3\(s3\) +[0-9a-f]+ <[^>]+> 8443 2004 lbu t4,4\(t5\) +[0-9a-f]+ <[^>]+> 8443 2005 lbu t4,5\(t5\) +[0-9a-f]+ <[^>]+> 8443 2006 lbu t4,6\(t5\) +[0-9a-f]+ <[^>]+> 8443 2007 lbu t4,7\(t5\) +[0-9a-f]+ <[^>]+> 8443 2008 lbu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 2009 lbu t4,9\(t5\) +[0-9a-f]+ <[^>]+> 8443 200a lbu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 200b lbu t4,11\(t5\) +[0-9a-f]+ <[^>]+> 8443 200c lbu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 200d lbu t4,13\(t5\) +[0-9a-f]+ <[^>]+> 8443 200e lbu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8442 200e lbu t4,14\(t4\) +[0-9a-f]+ <[^>]+> 8444 200e lbu t4,14\(a0\) +[0-9a-f]+ <[^>]+> 8445 200e lbu t4,14\(a1\) +[0-9a-f]+ <[^>]+> 8446 200e lbu t4,14\(a2\) +[0-9a-f]+ <[^>]+> 8447 200e lbu t4,14\(a3\) +[0-9a-f]+ <[^>]+> 8450 200e lbu t4,14\(s0\) +[0-9a-f]+ <[^>]+> 8451 200e lbu t4,14\(s1\) +[0-9a-f]+ <[^>]+> 8471 200e lbu t5,14\(s1\) +[0-9a-f]+ <[^>]+> 8491 200e lbu a0,14\(s1\) +[0-9a-f]+ <[^>]+> 84b1 200e lbu a1,14\(s1\) +[0-9a-f]+ <[^>]+> 84d1 200e lbu a2,14\(s1\) +[0-9a-f]+ <[^>]+> 84f1 200e lbu a3,14\(s1\) +[0-9a-f]+ <[^>]+> 8611 200e lbu s0,14\(s1\) +[0-9a-f]+ <[^>]+> 8631 200e lbu s1,14\(s1\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 90ff lbu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 2000 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 2000 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 2004 lbu t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 90ff lbu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 a0ff lh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 4000 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 4000 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 4004 lh s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 a0ff lh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8653 6000 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 6000 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 6002 lhu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 8653 6004 lhu s2,4\(s3\) +[0-9a-f]+ <[^>]+> 8653 6006 lhu s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 6008 lhu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 600a lhu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 600c lhu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 600e lhu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 6010 lhu t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 6012 lhu t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 6014 lhu t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 6016 lhu t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 6018 lhu t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 601a lhu t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 601c lhu t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 601e lhu t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 601e lhu t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 601e lhu t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 601e lhu t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 601e lhu t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 601e lhu t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 601e lhu t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 601e lhu t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 601e lhu t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 601e lhu a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 601e lhu a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 601e lhu a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 601e lhu a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8611 601e lhu s0,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 601e lhu s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 b0ff lhu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 6000 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 6000 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 6004 lhu s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 b0ff lhu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8063 0678 ori t5,t5,0x678 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5104 ll t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8064 8001 addiu t5,a0,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8063 0678 ori t5,t5,0x678 +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e060 0000 lui t5,0x0 +[0-9a-f]+ <[^>]+> e07f 0ffc lui t5,%hi\(0x7fff0000\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8644 8000 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 8000 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 8004 lw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 8644 8008 lw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 8644 800c lw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 8644 8010 lw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 8644 8014 lw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 8644 8018 lw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 8644 801c lw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 8644 8020 lw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 8644 8024 lw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 8644 8028 lw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 8644 802c lw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 8644 8030 lw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 8644 8034 lw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 8644 8038 lw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 8644 803c lw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 8645 803c lw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 8646 803c lw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 8647 803c lw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 8652 803c lw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 8653 803c lw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 8650 803c lw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 8651 803c lw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 8671 803c lw s3,60\(s1\) +[0-9a-f]+ <[^>]+> 8491 803c lw a0,60\(s1\) +[0-9a-f]+ <[^>]+> 84b1 803c lw a1,60\(s1\) +[0-9a-f]+ <[^>]+> 84d1 803c lw a2,60\(s1\) +[0-9a-f]+ <[^>]+> 84f1 803c lw a3,60\(s1\) +[0-9a-f]+ <[^>]+> 8611 803c lw s0,60\(s1\) +[0-9a-f]+ <[^>]+> 8631 803c lw s1,60\(s1\) +[0-9a-f]+ <[^>]+> 849d 8000 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 849d 8000 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 849d 8004 lw a0,4\(sp\) +[0-9a-f]+ <[^>]+> 849d 8008 lw a0,8\(sp\) +[0-9a-f]+ <[^>]+> 849d 800c lw a0,12\(sp\) +[0-9a-f]+ <[^>]+> 849d 8010 lw a0,16\(sp\) +[0-9a-f]+ <[^>]+> 849d 8014 lw a0,20\(sp\) +[0-9a-f]+ <[^>]+> 849d 807c lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 845d 807c lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 845d 807c lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 847d 807c lw t5,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 807c lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 84bd 807c lw a1,124\(sp\) +[0-9a-f]+ <[^>]+> 84dd 807c lw a2,124\(sp\) +[0-9a-f]+ <[^>]+> 84fd 807c lw a3,124\(sp\) +[0-9a-f]+ <[^>]+> 851d 807c lw a4,124\(sp\) +[0-9a-f]+ <[^>]+> 853d 807c lw a5,124\(sp\) +[0-9a-f]+ <[^>]+> 855d 807c lw a6,124\(sp\) +[0-9a-f]+ <[^>]+> 87dd 807c lw fp,124\(sp\) +[0-9a-f]+ <[^>]+> 87fd 807c lw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 81f8 lw a0,504\(sp\) +[0-9a-f]+ <[^>]+> 849d 81fc lw a0,508\(sp\) +[0-9a-f]+ <[^>]+> 861d 81fc lw s0,508\(sp\) +[0-9a-f]+ <[^>]+> 863d 81fc lw s1,508\(sp\) +[0-9a-f]+ <[^>]+> 865d 81fc lw s2,508\(sp\) +[0-9a-f]+ <[^>]+> 867d 81fc lw s3,508\(sp\) +[0-9a-f]+ <[^>]+> 869d 81fc lw s4,508\(sp\) +[0-9a-f]+ <[^>]+> 86bd 81fc lw s5,508\(sp\) +[0-9a-f]+ <[^>]+> 87fd 81fc lw ra,508\(sp\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 c0ff lw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 8000 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 8000 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 8004 lw s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 c0ff lw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 20a4 9c47 lwxs s3,a0\(a1\) +[0-9a-f]+ <[^>]+> 2040 0030 mfc0 t4,index +[0-9a-f]+ <[^>]+> 2041 0030 mfc0 t4,random +[0-9a-f]+ <[^>]+> 2042 0830 mfc0 t4,tcstatus +[0-9a-f]+ <[^>]+> 2042 1030 mfc0 t4,tcbind +[0-9a-f]+ <[^>]+> 2043 0070 mtc0 t4,entrylo1 +[0-9a-f]+ <[^>]+> 2044 0070 mtc0 t4,context +[0-9a-f]+ <[^>]+> 2045 3070 mtc0 t4,pwfield +[0-9a-f]+ <[^>]+> 2045 3870 mtc0 t4,pwsize +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1610 movn t4,t5,a0 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1210 movz t4,t5,a0 +[0-9a-f]+ <[^>]+> 2083 1018 mul t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e818 mul sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 2060 1190 neg t4,t5 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2012 92d0 not s2,s2 +[0-9a-f]+ <[^>]+> 2012 92d0 not s2,s2 +[0-9a-f]+ <[^>]+> 2013 92d0 not s2,s3 +[0-9a-f]+ <[^>]+> 2004 92d0 not s2,a0 +[0-9a-f]+ <[^>]+> 2005 92d0 not s2,a1 +[0-9a-f]+ <[^>]+> 2006 92d0 not s2,a2 +[0-9a-f]+ <[^>]+> 2007 92d0 not s2,a3 +[0-9a-f]+ <[^>]+> 2010 92d0 not s2,s0 +[0-9a-f]+ <[^>]+> 2011 92d0 not s2,s1 +[0-9a-f]+ <[^>]+> 2011 9ad0 not s3,s1 +[0-9a-f]+ <[^>]+> 2011 22d0 not a0,s1 +[0-9a-f]+ <[^>]+> 2011 2ad0 not a1,s1 +[0-9a-f]+ <[^>]+> 2011 32d0 not a2,s1 +[0-9a-f]+ <[^>]+> 2011 3ad0 not a3,s1 +[0-9a-f]+ <[^>]+> 2011 82d0 not s0,s1 +[0-9a-f]+ <[^>]+> 2011 8ad0 not s1,s1 +[0-9a-f]+ <[^>]+> 2007 12d0 not t4,a3 +[0-9a-f]+ <[^>]+> 20e0 12d0 nor t4,zero,a3 +[0-9a-f]+ <[^>]+> 2083 12d0 nor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ead0 nor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1290 or t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b290 or s6,zero,t4 +[0-9a-f]+ <[^>]+> 2252 9290 or s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9290 or s2,s2,s3 +[0-9a-f]+ <[^>]+> 2092 9290 or s2,s2,a0 +[0-9a-f]+ <[^>]+> 20b2 9290 or s2,s2,a1 +[0-9a-f]+ <[^>]+> 20d2 9290 or s2,s2,a2 +[0-9a-f]+ <[^>]+> 20f2 9290 or s2,s2,a3 +[0-9a-f]+ <[^>]+> 2212 9290 or s2,s2,s0 +[0-9a-f]+ <[^>]+> 2232 9290 or s2,s2,s1 +[0-9a-f]+ <[^>]+> 2253 9a90 or s3,s3,s2 +[0-9a-f]+ <[^>]+> 2244 2290 or a0,a0,s2 +[0-9a-f]+ <[^>]+> 2245 2a90 or a1,a1,s2 +[0-9a-f]+ <[^>]+> 2246 3290 or a2,a2,s2 +[0-9a-f]+ <[^>]+> 2247 3a90 or a3,a3,s2 +[0-9a-f]+ <[^>]+> 2250 8290 or s0,s0,s2 +[0-9a-f]+ <[^>]+> 2251 8a90 or s1,s1,s2 +[0-9a-f]+ <[^>]+> 2252 9290 or s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9290 or s2,s2,s3 +[0-9a-f]+ <[^>]+> 2253 9290 or s2,s3,s2 +[0-9a-f]+ <[^>]+> 2083 1290 or t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ea90 or sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8043 0fff ori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8064 0000 ori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8064 0fff ori t5,a0,0xfff +[0-9a-f]+ <[^>]+> 2040 01c0 rdhwr t4,hwr_cpunum +[0-9a-f]+ <[^>]+> 2041 01c0 rdhwr t4,hwr_synci_step +[0-9a-f]+ <[^>]+> 2042 01c0 rdhwr t4,hwr_cc +[0-9a-f]+ <[^>]+> 2043 01c0 rdhwr t4,hwr_ccres +[0-9a-f]+ <[^>]+> 2044 01c0 rdhwr t4,hwr_perfcnt +[0-9a-f]+ <[^>]+> 2045 01c0 rdhwr t4,hwr_xnp +[0-9a-f]+ <[^>]+> 2046 01c0 rdhwr t4,\$6 +[0-9a-f]+ <[^>]+> 2047 01c0 rdhwr t4,\$7 +[0-9a-f]+ <[^>]+> 2048 01c0 rdhwr t4,\$8 +[0-9a-f]+ <[^>]+> 2049 01c0 rdhwr t4,\$9 +[0-9a-f]+ <[^>]+> 204a 01c0 rdhwr t4,\$10 +[0-9a-f]+ <[^>]+> 2043 e17f rdpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2042 e17f rdpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2062 0158 mod zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0158 mod zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0158 mod zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0158 mod zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1158 mod t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1158 mod t4,t5,a0 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 2000 1a90 move t5,zero +[0-9a-f]+ <[^>]+> 2000 1a90 move t5,zero +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1958 mod t5,a0,at +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2080 09d0 negu at,a0 +[0-9a-f]+ <[^>]+> 2022 10d0 rotrv t4,t4,at +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8413 1000 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 8413 1000 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 8413 1001 sb zero,1\(s3\) +[0-9a-f]+ <[^>]+> 8413 1002 sb zero,2\(s3\) +[0-9a-f]+ <[^>]+> 8413 1003 sb zero,3\(s3\) +[0-9a-f]+ <[^>]+> 8403 1004 sb zero,4\(t5\) +[0-9a-f]+ <[^>]+> 8403 1005 sb zero,5\(t5\) +[0-9a-f]+ <[^>]+> 8403 1006 sb zero,6\(t5\) +[0-9a-f]+ <[^>]+> 8403 1007 sb zero,7\(t5\) +[0-9a-f]+ <[^>]+> 8403 1008 sb zero,8\(t5\) +[0-9a-f]+ <[^>]+> 8403 1009 sb zero,9\(t5\) +[0-9a-f]+ <[^>]+> 8403 100a sb zero,10\(t5\) +[0-9a-f]+ <[^>]+> 8403 100b sb zero,11\(t5\) +[0-9a-f]+ <[^>]+> 8403 100c sb zero,12\(t5\) +[0-9a-f]+ <[^>]+> 8403 100d sb zero,13\(t5\) +[0-9a-f]+ <[^>]+> 8403 100e sb zero,14\(t5\) +[0-9a-f]+ <[^>]+> 8403 100f sb zero,15\(t5\) +[0-9a-f]+ <[^>]+> 8443 100f sb t4,15\(t5\) +[0-9a-f]+ <[^>]+> 8463 100f sb t5,15\(t5\) +[0-9a-f]+ <[^>]+> 8483 100f sb a0,15\(t5\) +[0-9a-f]+ <[^>]+> 84a3 100f sb a1,15\(t5\) +[0-9a-f]+ <[^>]+> 84c3 100f sb a2,15\(t5\) +[0-9a-f]+ <[^>]+> 84e3 100f sb a3,15\(t5\) +[0-9a-f]+ <[^>]+> 8623 100f sb s1,15\(t5\) +[0-9a-f]+ <[^>]+> 8624 100f sb s1,15\(a0\) +[0-9a-f]+ <[^>]+> 8625 100f sb s1,15\(a1\) +[0-9a-f]+ <[^>]+> 8626 100f sb s1,15\(a2\) +[0-9a-f]+ <[^>]+> 8627 100f sb s1,15\(a3\) +[0-9a-f]+ <[^>]+> 8622 100f sb s1,15\(t4\) +[0-9a-f]+ <[^>]+> 8630 100f sb s1,15\(s0\) +[0-9a-f]+ <[^>]+> 8631 100f sb s1,15\(s1\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1fff sb t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 88ff sb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1fff sb t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 88ff sb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8021 0678 ori at,at,0x678 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> 0024 07ff addiu at,a0,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8800 addiu at,a0,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 7fff addiu at,a0,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8001 addiu at,a0,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8021 0678 ori at,at,0x678 +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0001 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 0018 0002 sdbbp 0x2 +[0-9a-f]+ <[^>]+> 0018 0003 sdbbp 0x3 +[0-9a-f]+ <[^>]+> 0018 0004 sdbbp 0x4 +[0-9a-f]+ <[^>]+> 0018 0005 sdbbp 0x5 +[0-9a-f]+ <[^>]+> 0018 0006 sdbbp 0x6 +[0-9a-f]+ <[^>]+> 0018 0007 sdbbp 0x7 +[0-9a-f]+ <[^>]+> 0018 0008 sdbbp 0x8 +[0-9a-f]+ <[^>]+> 0018 0009 sdbbp 0x9 +[0-9a-f]+ <[^>]+> 0018 000a sdbbp 0xa +[0-9a-f]+ <[^>]+> 0018 000b sdbbp 0xb +[0-9a-f]+ <[^>]+> 0018 000c sdbbp 0xc +[0-9a-f]+ <[^>]+> 0018 000d sdbbp 0xd +[0-9a-f]+ <[^>]+> 0018 000e sdbbp 0xe +[0-9a-f]+ <[^>]+> 0018 000f sdbbp 0xf +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0001 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 0018 0002 sdbbp 0x2 +[0-9a-f]+ <[^>]+> 0018 00ff sdbbp 0xff +[0-9a-f]+ <[^>]+> 2043 0008 seb t4,t5 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2043 0048 seh t4,t5 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8044 5001 sltiu t4,a0,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 6001 seqi t4,t5,1 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8653 5000 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 5000 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 5002 sh s2,2\(s3\) +[0-9a-f]+ <[^>]+> 8653 5004 sh s2,4\(s3\) +[0-9a-f]+ <[^>]+> 8653 5006 sh s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 5008 sh t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 500a sh t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 500c sh t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 500e sh t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 5010 sh t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 5012 sh t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 5014 sh t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 5016 sh t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 5018 sh t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 501a sh t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 501c sh t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 501e sh t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 501e sh t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 501e sh t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 501e sh t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 501e sh t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 501e sh t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 501e sh t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 501e sh t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 501e sh t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 501e sh a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 501e sh a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 501e sh a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 501e sh a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 501e sh s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8411 501e sh zero,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5fff sh t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 a8ff sh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5fff sh t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 a8ff sh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8252 c001 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 8252 c002 sll s2,s2,2 +[0-9a-f]+ <[^>]+> 8252 c003 sll s2,s2,3 +[0-9a-f]+ <[^>]+> 8252 c004 sll s2,s2,4 +[0-9a-f]+ <[^>]+> 8252 c005 sll s2,s2,5 +[0-9a-f]+ <[^>]+> 8252 c006 sll s2,s2,6 +[0-9a-f]+ <[^>]+> 8252 c007 sll s2,s2,7 +[0-9a-f]+ <[^>]+> 8252 c008 sll s2,s2,8 +[0-9a-f]+ <[^>]+> 8253 c008 sll s2,s3,8 +[0-9a-f]+ <[^>]+> 8244 c008 sll s2,a0,8 +[0-9a-f]+ <[^>]+> 8245 c008 sll s2,a1,8 +[0-9a-f]+ <[^>]+> 8246 c008 sll s2,a2,8 +[0-9a-f]+ <[^>]+> 8247 c008 sll s2,a3,8 +[0-9a-f]+ <[^>]+> 8250 c008 sll s2,s0,8 +[0-9a-f]+ <[^>]+> 8251 c008 sll s2,s1,8 +[0-9a-f]+ <[^>]+> 8272 c008 sll s3,s2,8 +[0-9a-f]+ <[^>]+> 8092 c008 sll a0,s2,8 +[0-9a-f]+ <[^>]+> 80b2 c008 sll a1,s2,8 +[0-9a-f]+ <[^>]+> 80d2 c008 sll a2,s2,8 +[0-9a-f]+ <[^>]+> 80f2 c008 sll a3,s2,8 +[0-9a-f]+ <[^>]+> 8212 c008 sll s0,s2,8 +[0-9a-f]+ <[^>]+> 8232 c008 sll s1,s2,8 +[0-9a-f]+ <[^>]+> 8252 c001 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 8273 c001 sll s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1010 sllv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c000 sll t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c001 sll t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c01f sll t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8064 4000 slti t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 4fff slti t5,a0,4095 +[0-9a-f]+ <[^>]+> 8064 5000 sltiu t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 5fff sltiu t5,a0,4095 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2080 1390 sltu t4,zero,a0 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 8043 1001 xori t4,t5,0x1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2083 1090 srav t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c080 sra t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c081 sra t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c09f sra t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1050 srlv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c040 srl t4,a0,0 +[0-9a-f]+ <[^>]+> 8244 c041 srl s2,a0,1 +[0-9a-f]+ <[^>]+> 8044 c05f srl t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 8252 c041 srl s2,s2,1 +[0-9a-f]+ <[^>]+> 8252 c042 srl s2,s2,2 +[0-9a-f]+ <[^>]+> 8252 c043 srl s2,s2,3 +[0-9a-f]+ <[^>]+> 8252 c044 srl s2,s2,4 +[0-9a-f]+ <[^>]+> 8252 c045 srl s2,s2,5 +[0-9a-f]+ <[^>]+> 8252 c046 srl s2,s2,6 +[0-9a-f]+ <[^>]+> 8252 c047 srl s2,s2,7 +[0-9a-f]+ <[^>]+> 8252 c048 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 8253 c048 srl s2,s3,8 +[0-9a-f]+ <[^>]+> 8244 c048 srl s2,a0,8 +[0-9a-f]+ <[^>]+> 8245 c048 srl s2,a1,8 +[0-9a-f]+ <[^>]+> 8246 c048 srl s2,a2,8 +[0-9a-f]+ <[^>]+> 8247 c048 srl s2,a3,8 +[0-9a-f]+ <[^>]+> 8250 c048 srl s2,s0,8 +[0-9a-f]+ <[^>]+> 8251 c048 srl s2,s1,8 +[0-9a-f]+ <[^>]+> 8252 c048 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 8272 c048 srl s3,s2,8 +[0-9a-f]+ <[^>]+> 8092 c048 srl a0,s2,8 +[0-9a-f]+ <[^>]+> 80b2 c048 srl a1,s2,8 +[0-9a-f]+ <[^>]+> 80d2 c048 srl a2,s2,8 +[0-9a-f]+ <[^>]+> 80f2 c048 srl a3,s2,8 +[0-9a-f]+ <[^>]+> 8212 c048 srl s0,s2,8 +[0-9a-f]+ <[^>]+> 8232 c048 srl s1,s2,8 +[0-9a-f]+ <[^>]+> 8273 c041 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 8273 c041 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1190 sub t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e990 sub sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 2253 91d0 subu s2,s3,s2 +[0-9a-f]+ <[^>]+> 2273 91d0 subu s2,s3,s3 +[0-9a-f]+ <[^>]+> 2093 91d0 subu s2,s3,a0 +[0-9a-f]+ <[^>]+> 20b3 91d0 subu s2,s3,a1 +[0-9a-f]+ <[^>]+> 20d3 91d0 subu s2,s3,a2 +[0-9a-f]+ <[^>]+> 20f3 91d0 subu s2,s3,a3 +[0-9a-f]+ <[^>]+> 2213 91d0 subu s2,s3,s0 +[0-9a-f]+ <[^>]+> 2233 91d0 subu s2,s3,s1 +[0-9a-f]+ <[^>]+> 2232 91d0 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2224 91d0 subu s2,a0,s1 +[0-9a-f]+ <[^>]+> 2225 91d0 subu s2,a1,s1 +[0-9a-f]+ <[^>]+> 2226 91d0 subu s2,a2,s1 +[0-9a-f]+ <[^>]+> 2227 91d0 subu s2,a3,s1 +[0-9a-f]+ <[^>]+> 2230 91d0 subu s2,s0,s1 +[0-9a-f]+ <[^>]+> 2231 91d0 subu s2,s1,s1 +[0-9a-f]+ <[^>]+> 2232 91d0 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 99d0 subu s3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 21d0 subu a0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 29d0 subu a1,s2,s1 +[0-9a-f]+ <[^>]+> 2232 31d0 subu a2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 39d0 subu a3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 81d0 subu s0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 89d0 subu s1,s2,s1 +[0-9a-f]+ <[^>]+> 2247 39d0 subu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2247 39d0 subu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2083 11d0 subu t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e9d0 subu sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 8042 8001 addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 11d0 subu t4,t4,at +[0-9a-f]+ <[^>]+> 0042 8000 addiu t4,t4,32768 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 11d0 subu t4,t4,at +[0-9a-f]+ <[^>]+> 8644 9000 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 9000 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 9004 sw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 8644 9008 sw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 8644 900c sw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 8644 9010 sw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 8644 9014 sw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 8644 9018 sw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 8644 901c sw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 8644 9020 sw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 8644 9024 sw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 8644 9028 sw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 8644 902c sw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 8644 9030 sw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 8644 9034 sw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 8644 9038 sw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 8644 903c sw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 8645 903c sw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 8646 903c sw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 8647 903c sw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 8650 903c sw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 8651 903c sw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 8652 903c sw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 8653 903c sw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 8673 903c sw s3,60\(s3\) +[0-9a-f]+ <[^>]+> 8493 903c sw a0,60\(s3\) +[0-9a-f]+ <[^>]+> 84b3 903c sw a1,60\(s3\) +[0-9a-f]+ <[^>]+> 84d3 903c sw a2,60\(s3\) +[0-9a-f]+ <[^>]+> 84f3 903c sw a3,60\(s3\) +[0-9a-f]+ <[^>]+> 8633 903c sw s1,60\(s3\) +[0-9a-f]+ <[^>]+> 8413 903c sw zero,60\(s3\) +[0-9a-f]+ <[^>]+> 841d 9000 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> 841d 9000 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> 841d 9004 sw zero,4\(sp\) +[0-9a-f]+ <[^>]+> 841d 9008 sw zero,8\(sp\) +[0-9a-f]+ <[^>]+> 841d 900c sw zero,12\(sp\) +[0-9a-f]+ <[^>]+> 841d 9010 sw zero,16\(sp\) +[0-9a-f]+ <[^>]+> 841d 9014 sw zero,20\(sp\) +[0-9a-f]+ <[^>]+> 841d 9078 sw zero,120\(sp\) +[0-9a-f]+ <[^>]+> 841d 907c sw zero,124\(sp\) +[0-9a-f]+ <[^>]+> 845d 907c sw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 863d 907c sw s1,124\(sp\) +[0-9a-f]+ <[^>]+> 847d 907c sw t5,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 907c sw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 84bd 907c sw a1,124\(sp\) +[0-9a-f]+ <[^>]+> 84dd 907c sw a2,124\(sp\) +[0-9a-f]+ <[^>]+> 84fd 907c sw a3,124\(sp\) +[0-9a-f]+ <[^>]+> 87fd 907c sw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9fff sw t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 c8ff sw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9fff sw t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 c8ff sw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8001 c006 sync 0x1 +[0-9a-f]+ <[^>]+> 8002 c006 sync 0x2 +[0-9a-f]+ <[^>]+> 8003 c006 sync 0x3 +[0-9a-f]+ <[^>]+> 8005 c006 sync 0x5 +[0-9a-f]+ <[^>]+> 801e c006 sync 0x1e +[0-9a-f]+ <[^>]+> 801f c006 sync 0x1f +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 37ff synci 2047\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3800 synci 2048\(zero\) +[0-9a-f]+ <[^>]+> 87e2 3000 synci 0\(t4\) +[0-9a-f]+ <[^>]+> 87e3 3000 synci 0\(t5\) +[0-9a-f]+ <[^>]+> 87e3 30ff synci 255\(t5\) +[0-9a-f]+ <[^>]+> a7e3 9800 synci -256\(t5\) +[0-9a-f]+ <[^>]+> 87e3 3800 synci 2048\(t5\) +[0-9a-f]+ <[^>]+> 0008 0000 syscall +[0-9a-f]+ <[^>]+> 0008 0000 syscall +[0-9a-f]+ <[^>]+> 0008 0001 syscall 0x1 +[0-9a-f]+ <[^>]+> 0008 0002 syscall 0x2 +[0-9a-f]+ <[^>]+> 0008 00ff syscall 0xff +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2001 c37f wait 0x1 +[0-9a-f]+ <[^>]+> 20ff c37f wait 0xff +[0-9a-f]+ <[^>]+> 2043 f17f wrpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2044 f17f wrpgpr t4,a0 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 8043 d608 byterevh t4,t5 +[0-9a-f]+ <[^>]+> 8044 d608 byterevh t4,a0 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 2252 9310 xor s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9310 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2092 9310 xor s2,s2,a0 +[0-9a-f]+ <[^>]+> 20b2 9310 xor s2,s2,a1 +[0-9a-f]+ <[^>]+> 20d2 9310 xor s2,s2,a2 +[0-9a-f]+ <[^>]+> 20f2 9310 xor s2,s2,a3 +[0-9a-f]+ <[^>]+> 2212 9310 xor s2,s2,s0 +[0-9a-f]+ <[^>]+> 2232 9310 xor s2,s2,s1 +[0-9a-f]+ <[^>]+> 2233 9b10 xor s3,s3,s1 +[0-9a-f]+ <[^>]+> 2224 2310 xor a0,a0,s1 +[0-9a-f]+ <[^>]+> 2225 2b10 xor a1,a1,s1 +[0-9a-f]+ <[^>]+> 2226 3310 xor a2,a2,s1 +[0-9a-f]+ <[^>]+> 2227 3b10 xor a3,a3,s1 +[0-9a-f]+ <[^>]+> 2230 8310 xor s0,s0,s1 +[0-9a-f]+ <[^>]+> 2231 8b10 xor s1,s1,s1 +[0-9a-f]+ <[^>]+> 2272 9310 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2272 9310 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2253 9310 xor s2,s3,s2 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe eb10 xor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8043 1fff xori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8064 1000 xori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8063 1fff xori t5,t5,0xfff +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8949 0000 beqc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c920 0800 beqic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8940 8000 blezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 896a 8000 bgec a6,a7,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c948 1000 bgeic a6,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 c000 bgeuc t4,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8840 c000 bgeuc zero,t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8862 c000 bgeuc t4,t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 0000 bnezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c84c 1000 bgeiuc t4,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 8000 bgtzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a802 8000 bltzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8809 8000 bgezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c928 1000 bgeic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> e020 0001 lui at,%hi\(0x80000000\) +[0-9a-f]+ <[^>]+> 8021 0001 ori at,at,0x1 +[0-9a-f]+ <[^>]+> 2029 0b50 slt at,a5,at +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c92c 1000 bgeiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 8000 bltc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 c000 bltuc a5,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 c000 bltuc zero,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 c000 bltuc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 0000 bnec a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c930 0800 bneic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 3003 restore.jrc 0 +[0-9a-f]+ <[^>]+> 8000 300b restore.jrc 8 +[0-9a-f]+ <[^>]+> 8000 3013 restore.jrc 16 +[0-9a-f]+ <[^>]+> 8000 301b restore.jrc 24 +[0-9a-f]+ <[^>]+> 8000 3023 restore.jrc 32 +[0-9a-f]+ <[^>]+> 8000 302b restore.jrc 40 +[0-9a-f]+ <[^>]+> 03bd 0004 addiu sp,sp,4 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 000c addiu sp,sp,12 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0014 addiu sp,sp,20 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 001c addiu sp,sp,28 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0024 addiu sp,sp,36 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 8000 307b restore.jrc 120 +[0-9a-f]+ <[^>]+> 03bd 007c addiu sp,sp,124 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 0018 03ff sdbbp 0x3ff +[0-9a-f]+ <[^>]+> 23ff c37f wait 0x3ff +[0-9a-f]+ <[^>]+> 0008 03ff syscall 0x3ff +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 test_delay_slot +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 4240 01fe lw s2,508\(gp\) +[0-9a-f]+ <[^>]+> 4260 01fe lw s3,508\(gp\) +[0-9a-f]+ <[^>]+> 4080 01fe lw a0,508\(gp\) +[0-9a-f]+ <[^>]+> 40a0 01fe lw a1,508\(gp\) +[0-9a-f]+ <[^>]+> 40c0 01fe lw a2,508\(gp\) +[0-9a-f]+ <[^>]+> 40e0 01fe lw a3,508\(gp\) +[0-9a-f]+ <[^>]+> 4200 01fe lw s0,508\(gp\) +[0-9a-f]+ <[^>]+> 4220 01fe lw s1,508\(gp\) +[0-9a-f]+ <[^>]+> 4220 01fa lw s1,504\(gp\) +[0-9a-f]+ <[^>]+> 4220 01f6 lw s1,500\(gp\) +[0-9a-f]+ <[^>]+> 4220 0002 lw s1,0\(gp\) +[0-9a-f]+ <[^>]+> 4220 0006 lw s1,4\(gp\) +[0-9a-f]+ <[^>]+> 4220 00fa lw s1,248\(gp\) +[0-9a-f]+ <[^>]+> 4220 00fe lw s1,252\(gp\) +[0-9a-f]+ <[^>]+> 4220 0102 lw s1,256\(gp\) +[0-9a-f]+ <[^>]+> 823c 8104 addiu s1,gp,-260 +[0-9a-f]+ <[^>]+> 8631 8000 lw s1,0\(s1\) +[0-9a-f]+ <[^>]+> 863c 8001 lw s1,1\(gp\) +[0-9a-f]+ <[^>]+> 863c 8002 lw s1,2\(gp\) +[0-9a-f]+ <[^>]+> 863c 8003 lw s1,3\(gp\) +[0-9a-f]+ <[^>]+> a63c c0ff lw s1,-1\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fe lw s1,-2\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fd lw s1,-3\(gp\) +[0-9a-f]+ <[^>]+> 863b 8000 lw s1,0\(k1\) +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> 8043 f300 ext t4,t5,0,13 +[0-9a-f]+ <[^>]+> 8044 f340 ext t4,a0,0,14 +[0-9a-f]+ <[^>]+> 8045 f380 ext t4,a1,0,15 +[0-9a-f]+ <[^>]+> 8046 f3c0 ext t4,a2,0,16 +[0-9a-f]+ <[^>]+> 8047 f500 ext t4,a3,0,21 +[0-9a-f]+ <[^>]+> 8048 f540 ext t4,a4,0,22 +[0-9a-f]+ <[^>]+> 8049 f580 ext t4,a5,0,23 +[0-9a-f]+ <[^>]+> 8050 f5c0 ext t4,s0,0,24 +[0-9a-f]+ <[^>]+> e040 0000 lui t4,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 test +[0-9a-f]+ <[^>]+> 8042 0000 ori t4,t4,0x0 + [0-9a-f]+: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> 2000 0390 dvp +[0-9a-f]+ <[^>]+> 20a0 0390 dvp a1 +[0-9a-f]+ <[^>]+> 2000 0790 evp +[0-9a-f]+ <[^>]+> 20c0 0790 evp a2 +#pass diff --git a/gas/testsuite/gas/nanomips/nanomips64@nanomips.d b/gas/testsuite/gas/nanomips/nanomips64@nanomips.d new file mode 100644 index 00000000000..cc122336ab9 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips64@nanomips.d @@ -0,0 +1,2318 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS instructions +#warning_output: nanomips.l +#source: nanomips.s + +# Check nanoMIPS32 instructions + +.*: +file format .*nanomips.* + +Disassembly of section .text: +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 37ff pref 0x0,2047\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3800 pref 0x0,2048\(zero\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8420 3000 pref 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> 8440 3000 pref 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 3000 pref 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> 8480 3000 pref 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> 84a0 3000 pref 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> 84c0 3000 pref 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 3000 pref 0x7,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 31ff pref 0x7,511\(zero\) +[0-9a-f]+ <[^>]+> 8020 8200 li at,-512 +[0-9a-f]+ <[^>]+> a4e1 1800 pref 0x7,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 0022 7fff addiu at,t4,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2041 0950 addu at,at,t4 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 8000 c003 ehb +[0-9a-f]+ <[^>]+> 8000 c005 pause +[0-9a-f]+ <[^>]+> d17f li s2,-1 +[0-9a-f]+ <[^>]+> d1ff li s3,-1 +[0-9a-f]+ <[^>]+> d27f li a0,-1 +[0-9a-f]+ <[^>]+> d2ff li a1,-1 +[0-9a-f]+ <[^>]+> d37f li a2,-1 +[0-9a-f]+ <[^>]+> d3ff li a3,-1 +[0-9a-f]+ <[^>]+> d07f li s0,-1 +[0-9a-f]+ <[^>]+> d0ff li s1,-1 +[0-9a-f]+ <[^>]+> d080 li s1,0 +[0-9a-f]+ <[^>]+> d0fd li s1,125 +[0-9a-f]+ <[^>]+> d0fe li s1,126 +[0-9a-f]+ <[^>]+> 0220 007f li s1,127 +[0-9a-f]+ <[^>]+> 1180 move t0,zero +[0-9a-f]+ <[^>]+> 1320 move t9,zero +[0-9a-f]+ <[^>]+> 0040 0000 li t4,0 +[0-9a-f]+ <[^>]+> 0040 0001 li t4,1 +[0-9a-f]+ <[^>]+> 0040 7fff li t4,32767 +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 0040 ffff li t4,65535 +[0-9a-f]+ <[^>]+> e041 0000 lui t4,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 6040 8001 ffff li t4,0xffff8001 +[0-9a-f]+ <[^>]+> 8040 8001 li t4,-1 +[0-9a-f]+ <[^>]+> 6040 5678 1234 li t4,0x12345678 +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> d27f li a0,-1 +[0-9a-f]+ <[^>]+> 2016 0290 move zero,s6 +[0-9a-f]+ <[^>]+> 1056 move t4,s6 +[0-9a-f]+ <[^>]+> 1076 move t5,s6 +[0-9a-f]+ <[^>]+> 1096 move a0,s6 +[0-9a-f]+ <[^>]+> 10b6 move a1,s6 +[0-9a-f]+ <[^>]+> 10d6 move a2,s6 +[0-9a-f]+ <[^>]+> 10f6 move a3,s6 +[0-9a-f]+ <[^>]+> 1116 move a4,s6 +[0-9a-f]+ <[^>]+> 1136 move a5,s6 +[0-9a-f]+ <[^>]+> 1156 move a6,s6 +[0-9a-f]+ <[^>]+> 13d6 move fp,s6 +[0-9a-f]+ <[^>]+> 13f6 move ra,s6 +[0-9a-f]+ <[^>]+> 2000 0290 move zero,zero +[0-9a-f]+ <[^>]+> 2002 0290 move zero,t4 +[0-9a-f]+ <[^>]+> 2003 0290 move zero,t5 +[0-9a-f]+ <[^>]+> 2004 0290 move zero,a0 +[0-9a-f]+ <[^>]+> 2005 0290 move zero,a1 +[0-9a-f]+ <[^>]+> 2006 0290 move zero,a2 +[0-9a-f]+ <[^>]+> 2007 0290 move zero,a3 +[0-9a-f]+ <[^>]+> 2008 0290 move zero,a4 +[0-9a-f]+ <[^>]+> 2009 0290 move zero,a5 +[0-9a-f]+ <[^>]+> 200a 0290 move zero,a6 +[0-9a-f]+ <[^>]+> 201e 0290 move zero,fp +[0-9a-f]+ <[^>]+> 201f 0290 move zero,ra +[0-9a-f]+ <[^>]+> 12c2 move s6,t4 +[0-9a-f]+ <[^>]+> 1056 move t4,s6 +[0-9a-f]+ <[^>]+> 12c2 move s6,t4 +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 test +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 test +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1800 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 1043 move t4,t5 +[0-9a-f]+ <[^>]+> 8803 8000 bgezc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_0 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 1044 move t4,a0 +[0-9a-f]+ <[^>]+> 8804 8000 bgezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_1 +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_2 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_3 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2083 1110 add t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e910 add sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0064 0000 addiu t5,a0,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 9018 addiu zero,zero,-8 +[0-9a-f]+ <[^>]+> 9058 addiu t4,t4,-8 +[0-9a-f]+ <[^>]+> 9078 addiu t5,t5,-8 +[0-9a-f]+ <[^>]+> 9098 addiu a0,a0,-8 +[0-9a-f]+ <[^>]+> 90b8 addiu a1,a1,-8 +[0-9a-f]+ <[^>]+> 90d8 addiu a2,a2,-8 +[0-9a-f]+ <[^>]+> 90f8 addiu a3,a3,-8 +[0-9a-f]+ <[^>]+> 9118 addiu a4,a4,-8 +[0-9a-f]+ <[^>]+> 9138 addiu a5,a5,-8 +[0-9a-f]+ <[^>]+> 9158 addiu a6,a6,-8 +[0-9a-f]+ <[^>]+> 93d8 addiu fp,fp,-8 +[0-9a-f]+ <[^>]+> 93f8 addiu ra,ra,-8 +[0-9a-f]+ <[^>]+> 93f9 addiu ra,ra,-7 +[0-9a-f]+ <[^>]+> 93e8 addiu ra,ra,0 +[0-9a-f]+ <[^>]+> 93e9 addiu ra,ra,1 +[0-9a-f]+ <[^>]+> 93ee addiu ra,ra,6 +[0-9a-f]+ <[^>]+> 93ef addiu ra,ra,7 +[0-9a-f]+ <[^>]+> 03ff 0008 addiu ra,ra,8 +[0-9a-f]+ <[^>]+> 83bd 8408 addiu sp,sp,-1032 +[0-9a-f]+ <[^>]+> 83bd 8404 addiu sp,sp,-1028 +[0-9a-f]+ <[^>]+> 83bd 8400 addiu sp,sp,-1024 +[0-9a-f]+ <[^>]+> 03bd 03fc addiu sp,sp,1020 +[0-9a-f]+ <[^>]+> 03bd 0400 addiu sp,sp,1024 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0408 addiu sp,sp,1032 +[0-9a-f]+ <[^>]+> 905f addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 8043 8001 addiu t4,t5,-1 +[0-9a-f]+ <[^>]+> 8044 8001 addiu t4,a0,-1 +[0-9a-f]+ <[^>]+> 8045 8001 addiu t4,a1,-1 +[0-9a-f]+ <[^>]+> 8046 8001 addiu t4,a2,-1 +[0-9a-f]+ <[^>]+> 8047 8001 addiu t4,a3,-1 +[0-9a-f]+ <[^>]+> 8050 8001 addiu t4,s0,-1 +[0-9a-f]+ <[^>]+> 8051 8001 addiu t4,s1,-1 +[0-9a-f]+ <[^>]+> 0051 0001 addiu t4,s1,1 +[0-9a-f]+ <[^>]+> 9111 addiu s2,s1,4 +[0-9a-f]+ <[^>]+> 9112 addiu s2,s1,8 +[0-9a-f]+ <[^>]+> 9113 addiu s2,s1,12 +[0-9a-f]+ <[^>]+> 9114 addiu s2,s1,16 +[0-9a-f]+ <[^>]+> 9115 addiu s2,s1,20 +[0-9a-f]+ <[^>]+> 9116 addiu s2,s1,24 +[0-9a-f]+ <[^>]+> 9196 addiu s3,s1,24 +[0-9a-f]+ <[^>]+> 9216 addiu a0,s1,24 +[0-9a-f]+ <[^>]+> 9296 addiu a1,s1,24 +[0-9a-f]+ <[^>]+> 9316 addiu a2,s1,24 +[0-9a-f]+ <[^>]+> 9396 addiu a3,s1,24 +[0-9a-f]+ <[^>]+> 9016 addiu s0,s1,24 +[0-9a-f]+ <[^>]+> 9096 addiu s1,s1,24 +[0-9a-f]+ <[^>]+> 7140 addiu s2,sp,0 +[0-9a-f]+ <[^>]+> 7141 addiu s2,sp,4 +[0-9a-f]+ <[^>]+> 717e addiu s2,sp,248 +[0-9a-f]+ <[^>]+> 717f addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 005d 0100 addiu t4,sp,256 +[0-9a-f]+ <[^>]+> 717f addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 71ff addiu s3,sp,252 +[0-9a-f]+ <[^>]+> 727f addiu a0,sp,252 +[0-9a-f]+ <[^>]+> 72ff addiu a1,sp,252 +[0-9a-f]+ <[^>]+> 737f addiu a2,sp,252 +[0-9a-f]+ <[^>]+> 73ff addiu a3,sp,252 +[0-9a-f]+ <[^>]+> 707f addiu s0,sp,252 +[0-9a-f]+ <[^>]+> 70ff addiu s1,sp,252 +[0-9a-f]+ <[^>]+> 8064 8fff addiu t5,a0,-4095 +[0-9a-f]+ <[^>]+> 91c0 addiu s3,a0,0 +[0-9a-f]+ <[^>]+> 0064 1fff addiu t5,a0,8191 +[0-9a-f]+ <[^>]+> 0064 3fff addiu t5,a0,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 2016 1150 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b150 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1150 addu t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b150 addu s6,zero,t4 +[0-9a-f]+ <[^>]+> b134 addu s2,s3,s2 +[0-9a-f]+ <[^>]+> b1b4 addu s2,s3,s3 +[0-9a-f]+ <[^>]+> b234 addu s2,s3,a0 +[0-9a-f]+ <[^>]+> b2b4 addu s2,s3,a1 +[0-9a-f]+ <[^>]+> b334 addu s2,s3,a2 +[0-9a-f]+ <[^>]+> b3b4 addu s2,s3,a3 +[0-9a-f]+ <[^>]+> b034 addu s2,s3,s0 +[0-9a-f]+ <[^>]+> b0b4 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> b0a4 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0b4 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> b0c4 addu s2,a0,s1 +[0-9a-f]+ <[^>]+> b0d4 addu s2,a1,s1 +[0-9a-f]+ <[^>]+> b0e4 addu s2,a2,s1 +[0-9a-f]+ <[^>]+> b0f4 addu s2,a3,s1 +[0-9a-f]+ <[^>]+> b084 addu s2,s0,s1 +[0-9a-f]+ <[^>]+> b094 addu s2,s1,s1 +[0-9a-f]+ <[^>]+> b0a4 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0a6 addu s3,s2,s1 +[0-9a-f]+ <[^>]+> b0a8 addu a0,s2,s1 +[0-9a-f]+ <[^>]+> b0aa addu a1,s2,s1 +[0-9a-f]+ <[^>]+> b0ac addu a2,s2,s1 +[0-9a-f]+ <[^>]+> b0ae addu a3,s2,s1 +[0-9a-f]+ <[^>]+> b0a0 addu s0,s2,s1 +[0-9a-f]+ <[^>]+> b0a2 addu s1,s2,s1 +[0-9a-f]+ <[^>]+> b17e addu a3,a3,s2 +[0-9a-f]+ <[^>]+> b17e addu a3,a3,s2 +[0-9a-f]+ <[^>]+> b3ae addu a3,s2,a3 +[0-9a-f]+ <[^>]+> 23fe e950 addu sp,fp,ra +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0042 0001 addiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0042 7fff addiu t4,t4,32767 +[0-9a-f]+ <[^>]+> 6041 8000 ffff addiu t4,t4,-32768 +[0-9a-f]+ <[^>]+> 0042 ffff addiu t4,t4,65535 +[0-9a-f]+ <[^>]+> 5128 and s2,s2,s2 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5148 and s2,s2,a0 +[0-9a-f]+ <[^>]+> 5158 and s2,s2,a1 +[0-9a-f]+ <[^>]+> 5168 and s2,s2,a2 +[0-9a-f]+ <[^>]+> 5178 and s2,s2,a3 +[0-9a-f]+ <[^>]+> 5108 and s2,s2,s0 +[0-9a-f]+ <[^>]+> 5118 and s2,s2,s1 +[0-9a-f]+ <[^>]+> 51a8 and s3,s3,s2 +[0-9a-f]+ <[^>]+> 5228 and a0,a0,s2 +[0-9a-f]+ <[^>]+> 52a8 and a1,a1,s2 +[0-9a-f]+ <[^>]+> 5328 and a2,a2,s2 +[0-9a-f]+ <[^>]+> 53a8 and a3,a3,s2 +[0-9a-f]+ <[^>]+> 5028 and s0,s0,s2 +[0-9a-f]+ <[^>]+> 50a8 and s1,s1,s2 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 5138 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2062 1250 and t4,t4,t5 +[0-9a-f]+ <[^>]+> f121 andi s2,s2,0x1 +[0-9a-f]+ <[^>]+> f122 andi s2,s2,0x2 +[0-9a-f]+ <[^>]+> f123 andi s2,s2,0x3 +[0-9a-f]+ <[^>]+> f124 andi s2,s2,0x4 +[0-9a-f]+ <[^>]+> f127 andi s2,s2,0x7 +[0-9a-f]+ <[^>]+> f128 andi s2,s2,0x8 +[0-9a-f]+ <[^>]+> f12f andi s2,s2,0xf +[0-9a-f]+ <[^>]+> 8042 2010 andi t4,t4,0x10 +[0-9a-f]+ <[^>]+> 8042 201f andi t4,t4,0x1f +[0-9a-f]+ <[^>]+> 8042 2020 andi t4,t4,0x20 +[0-9a-f]+ <[^>]+> 8042 203f andi t4,t4,0x3f +[0-9a-f]+ <[^>]+> 8042 2040 andi t4,t4,0x40 +[0-9a-f]+ <[^>]+> 8042 2080 andi t4,t4,0x80 +[0-9a-f]+ <[^>]+> f12c andi s2,s2,0xff +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> f12d andi s2,s2,0xffff +[0-9a-f]+ <[^>]+> f13d andi s2,s3,0xffff +[0-9a-f]+ <[^>]+> f14d andi s2,a0,0xffff +[0-9a-f]+ <[^>]+> f15d andi s2,a1,0xffff +[0-9a-f]+ <[^>]+> f16d andi s2,a2,0xffff +[0-9a-f]+ <[^>]+> f17d andi s2,a3,0xffff +[0-9a-f]+ <[^>]+> f10d andi s2,s0,0xffff +[0-9a-f]+ <[^>]+> f11d andi s2,s1,0xffff +[0-9a-f]+ <[^>]+> f19d andi s3,s1,0xffff +[0-9a-f]+ <[^>]+> f21d andi a0,s1,0xffff +[0-9a-f]+ <[^>]+> f29d andi a1,s1,0xffff +[0-9a-f]+ <[^>]+> f31d andi a2,s1,0xffff +[0-9a-f]+ <[^>]+> f39d andi a3,s1,0xffff +[0-9a-f]+ <[^>]+> f01d andi s0,s1,0xffff +[0-9a-f]+ <[^>]+> f09d andi s1,s1,0xffff +[0-9a-f]+ <[^>]+> f3fd andi a3,a3,0xffff +[0-9a-f]+ <[^>]+> f3fd andi a3,a3,0xffff +[0-9a-f]+ <[^>]+> f3fd andi a3,a3,0xffff +[0-9a-f]+ <[^>]+> 2083 1250 and t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 2000 andi t4,t5,0x0 +[0-9a-f]+ <[^>]+> 8043 2fff andi t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> 6020 0001 ffff li at,0xffff0001 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> 9900 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9980 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a00 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a80 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b00 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b80 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9900 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9980 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a00 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a80 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b00 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b80 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9900 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9980 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a00 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9a80 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b00 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9b80 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 9800 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 9880 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> ca00 5000 beqic s0,10,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test2 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> b900 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b980 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba00 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba80 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb00 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb80 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b880 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b900 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b980 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba00 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba80 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb00 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb80 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b880 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b900 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b980 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba00 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> ba80 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb00 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> bb80 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b880 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> b800 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC7_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 1010 break +[0-9a-f]+ <[^>]+> 1010 break +[0-9a-f]+ <[^>]+> 1011 break 0x1 +[0-9a-f]+ <[^>]+> 1012 break 0x2 +[0-9a-f]+ <[^>]+> 1013 break 0x3 +[0-9a-f]+ <[^>]+> 1014 break 0x4 +[0-9a-f]+ <[^>]+> 1015 break 0x5 +[0-9a-f]+ <[^>]+> 1016 break 0x6 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 0010 0008 break 0x8 +[0-9a-f]+ <[^>]+> 0010 0009 break 0x9 +[0-9a-f]+ <[^>]+> 0010 000a break 0xa +[0-9a-f]+ <[^>]+> 0010 000b break 0xb +[0-9a-f]+ <[^>]+> 0010 000c break 0xc +[0-9a-f]+ <[^>]+> 0010 000d break 0xd +[0-9a-f]+ <[^>]+> 0010 000e break 0xe +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0001 break 0x1 +[0-9a-f]+ <[^>]+> 0010 0002 break 0x2 +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a402 3900 cache 0x0,0\(t4\) +[0-9a-f]+ <[^>]+> 8022 8800 addiu at,t4,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 07ff addiu at,t4,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8022 8801 addiu at,t4,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 0800 addiu at,t4,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a420 3900 cache 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> a440 3900 cache 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> a460 3900 cache 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> a480 3900 cache 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> a4a0 3900 cache 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> a4c0 3900 cache 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> a7e0 3900 cache 0x1f,0\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0023 0800 addiu at,t5,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8023 8801 addiu at,t5,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e3 b9ff cache 0x1f,-1\(t5\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0023 ffff addiu at,t5,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e0 b9ff cache 0x1f,-1\(zero\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 2043 4b3f clo t4,t5 +[0-9a-f]+ <[^>]+> 2062 4b3f clo t5,t4 +[0-9a-f]+ <[^>]+> 2043 5b3f clz t4,t5 +[0-9a-f]+ <[^>]+> 2062 5b3f clz t5,t4 +[0-9a-f]+ <[^>]+> 2000 e37f deret +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2040 477f di t4 +[0-9a-f]+ <[^>]+> 2060 477f di t5 +[0-9a-f]+ <[^>]+> 23c0 477f di fp +[0-9a-f]+ <[^>]+> 23e0 477f di ra +[0-9a-f]+ <[^>]+> 2062 0118 div zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0118 div zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0118 div zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0118 div zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1118 div t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1118 div t4,t5,a0 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 1064 move t5,a0 +[0-9a-f]+ <[^>]+> 2080 1990 neg t5,a0 +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1918 div t5,a0,at +[0-9a-f]+ <[^>]+> 2062 0198 divu zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0198 divu zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0198 divu zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0198 divu zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1198 divu t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1198 divu t4,t5,a0 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 1064 move t5,a0 +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2040 577f ei t4 +[0-9a-f]+ <[^>]+> 2060 577f ei t5 +[0-9a-f]+ <[^>]+> 23c0 577f ei fp +[0-9a-f]+ <[^>]+> 23e0 577f ei ra +[0-9a-f]+ <[^>]+> 2000 f37f eret +[0-9a-f]+ <[^>]+> 8043 f385 ext t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 f7c0 ext t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 f01f ext t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe f01f ext ra,fp,31,1 +[0-9a-f]+ <[^>]+> 8043 e4c5 ins t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 e7c0 ins t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 e7df ins t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe e7df ins ra,fp,31,1 +[0-9a-f]+ <[^>]+> d800 jrc zero +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> d860 jrc t5 +[0-9a-f]+ <[^>]+> d880 jrc a0 +[0-9a-f]+ <[^>]+> d8a0 jrc a1 +[0-9a-f]+ <[^>]+> d8c0 jrc a2 +[0-9a-f]+ <[^>]+> d8e0 jrc a3 +[0-9a-f]+ <[^>]+> d900 jrc a4 +[0-9a-f]+ <[^>]+> dbc0 jrc fp +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> d800 jrc zero +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> d860 jrc t5 +[0-9a-f]+ <[^>]+> d880 jrc a0 +[0-9a-f]+ <[^>]+> d8a0 jrc a1 +[0-9a-f]+ <[^>]+> d8c0 jrc a2 +[0-9a-f]+ <[^>]+> d8e0 jrc a3 +[0-9a-f]+ <[^>]+> d900 jrc a4 +[0-9a-f]+ <[^>]+> dbc0 jrc fp +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 4800 1000 jrc.hb zero +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 4803 1000 jrc.hb t5 +[0-9a-f]+ <[^>]+> 4804 1000 jrc.hb a0 +[0-9a-f]+ <[^>]+> 4805 1000 jrc.hb a1 +[0-9a-f]+ <[^>]+> 4806 1000 jrc.hb a2 +[0-9a-f]+ <[^>]+> 4807 1000 jrc.hb a3 +[0-9a-f]+ <[^>]+> 4808 1000 jrc.hb a4 +[0-9a-f]+ <[^>]+> 481e 1000 jrc.hb fp +[0-9a-f]+ <[^>]+> 481f 1000 jrc.hb ra +[0-9a-f]+ <[^>]+> d800 jrc zero +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> d860 jrc t5 +[0-9a-f]+ <[^>]+> d880 jrc a0 +[0-9a-f]+ <[^>]+> d8a0 jrc a1 +[0-9a-f]+ <[^>]+> d8c0 jrc a2 +[0-9a-f]+ <[^>]+> d8e0 jrc a3 +[0-9a-f]+ <[^>]+> d900 jrc a4 +[0-9a-f]+ <[^>]+> dbc0 jrc fp +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> d810 jalrc zero +[0-9a-f]+ <[^>]+> d850 jalrc t4 +[0-9a-f]+ <[^>]+> d870 jalrc t5 +[0-9a-f]+ <[^>]+> d890 jalrc a0 +[0-9a-f]+ <[^>]+> d8b0 jalrc a1 +[0-9a-f]+ <[^>]+> d8d0 jalrc a2 +[0-9a-f]+ <[^>]+> d8f0 jalrc a3 +[0-9a-f]+ <[^>]+> d910 jalrc a4 +[0-9a-f]+ <[^>]+> dbd0 jalrc fp +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> d810 jalrc zero +[0-9a-f]+ <[^>]+> d850 jalrc t4 +[0-9a-f]+ <[^>]+> d870 jalrc t5 +[0-9a-f]+ <[^>]+> d890 jalrc a0 +[0-9a-f]+ <[^>]+> d8b0 jalrc a1 +[0-9a-f]+ <[^>]+> d8d0 jalrc a2 +[0-9a-f]+ <[^>]+> d8f0 jalrc a3 +[0-9a-f]+ <[^>]+> d910 jalrc a4 +[0-9a-f]+ <[^>]+> dbd0 jalrc fp +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> 4840 0000 jalrc t4,zero +[0-9a-f]+ <[^>]+> 4862 0000 jalrc t5,t4 +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4844 0000 jalrc t4,a0 +[0-9a-f]+ <[^>]+> 4845 0000 jalrc t4,a1 +[0-9a-f]+ <[^>]+> 4846 0000 jalrc t4,a2 +[0-9a-f]+ <[^>]+> 4847 0000 jalrc t4,a3 +[0-9a-f]+ <[^>]+> 4848 0000 jalrc t4,a4 +[0-9a-f]+ <[^>]+> 485e 0000 jalrc t4,fp +[0-9a-f]+ <[^>]+> 485f 0000 jalrc t4,ra +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4bdf 1000 jalrc.hb fp,ra +[0-9a-f]+ <[^>]+> 4840 1000 jalrc.hb t4,zero +[0-9a-f]+ <[^>]+> 4862 1000 jalrc.hb t5,t4 +[0-9a-f]+ <[^>]+> 4843 1000 jalrc.hb t4,t5 +[0-9a-f]+ <[^>]+> 4844 1000 jalrc.hb t4,a0 +[0-9a-f]+ <[^>]+> 4845 1000 jalrc.hb t4,a1 +[0-9a-f]+ <[^>]+> 4846 1000 jalrc.hb t4,a2 +[0-9a-f]+ <[^>]+> 4847 1000 jalrc.hb t4,a3 +[0-9a-f]+ <[^>]+> 4848 1000 jalrc.hb t4,a4 +[0-9a-f]+ <[^>]+> 485e 1000 jalrc.hb t4,fp +[0-9a-f]+ <[^>]+> 485f 1000 jalrc.hb t4,ra +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> d870 jalrc t5 +[0-9a-f]+ <[^>]+> dbf0 jalrc ra +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test2 +[0-9a-f]+ <[^>]+> 6040 0000 0000 li t4,0x0 + [0-9a-f]+: R_NANOMIPS_I32 test +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 80ff lb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 5dc0 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 5dc0 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 0004 lb t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 80ff lb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a443 90ff lbu t4,-1\(t5\) +[0-9a-f]+ <[^>]+> 5d38 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 5d38 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 5d39 lbu s2,1\(s3\) +[0-9a-f]+ <[^>]+> 5d3a lbu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 5d3b lbu s2,3\(s3\) +[0-9a-f]+ <[^>]+> 8443 2004 lbu t4,4\(t5\) +[0-9a-f]+ <[^>]+> 8443 2005 lbu t4,5\(t5\) +[0-9a-f]+ <[^>]+> 8443 2006 lbu t4,6\(t5\) +[0-9a-f]+ <[^>]+> 8443 2007 lbu t4,7\(t5\) +[0-9a-f]+ <[^>]+> 8443 2008 lbu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 2009 lbu t4,9\(t5\) +[0-9a-f]+ <[^>]+> 8443 200a lbu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 200b lbu t4,11\(t5\) +[0-9a-f]+ <[^>]+> 8443 200c lbu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 200d lbu t4,13\(t5\) +[0-9a-f]+ <[^>]+> 8443 200e lbu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8442 200e lbu t4,14\(t4\) +[0-9a-f]+ <[^>]+> 8444 200e lbu t4,14\(a0\) +[0-9a-f]+ <[^>]+> 8445 200e lbu t4,14\(a1\) +[0-9a-f]+ <[^>]+> 8446 200e lbu t4,14\(a2\) +[0-9a-f]+ <[^>]+> 8447 200e lbu t4,14\(a3\) +[0-9a-f]+ <[^>]+> 8450 200e lbu t4,14\(s0\) +[0-9a-f]+ <[^>]+> 8451 200e lbu t4,14\(s1\) +[0-9a-f]+ <[^>]+> 8471 200e lbu t5,14\(s1\) +[0-9a-f]+ <[^>]+> 8491 200e lbu a0,14\(s1\) +[0-9a-f]+ <[^>]+> 84b1 200e lbu a1,14\(s1\) +[0-9a-f]+ <[^>]+> 84d1 200e lbu a2,14\(s1\) +[0-9a-f]+ <[^>]+> 84f1 200e lbu a3,14\(s1\) +[0-9a-f]+ <[^>]+> 8611 200e lbu s0,14\(s1\) +[0-9a-f]+ <[^>]+> 8631 200e lbu s1,14\(s1\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 90ff lbu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 5dc8 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 5dc8 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 2004 lbu t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 90ff lbu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 a0ff lh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 7dc0 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dc0 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dc4 lh s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 a0ff lh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 7d38 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d38 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d3a lhu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 7d3c lhu s2,4\(s3\) +[0-9a-f]+ <[^>]+> 7d3e lhu s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 6008 lhu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 600a lhu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 600c lhu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 600e lhu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 6010 lhu t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 6012 lhu t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 6014 lhu t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 6016 lhu t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 6018 lhu t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 601a lhu t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 601c lhu t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 601e lhu t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 601e lhu t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 601e lhu t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 601e lhu t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 601e lhu t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 601e lhu t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 601e lhu t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 601e lhu t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 601e lhu t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 601e lhu a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 601e lhu a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 601e lhu a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 601e lhu a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8611 601e lhu s0,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 601e lhu s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 b0ff lhu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 7dc8 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dc8 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 7dcc lhu s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 b0ff lhu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 6060 5678 1234 li t5,0x12345678 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5104 ll t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8064 8001 addiu t5,a0,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 6060 5678 1234 li t5,0x12345678 +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e060 0000 lui t5,0x0 +[0-9a-f]+ <[^>]+> e07f 0ffc lui t5,%hi\(0x7fff0000\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 1540 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 1540 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 1541 lw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 1542 lw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 1543 lw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 1544 lw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 1545 lw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 1546 lw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 1547 lw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 1548 lw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 1549 lw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 154a lw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 154b lw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 154c lw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 154d lw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 154e lw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 154f lw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 155f lw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 156f lw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 157f lw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 152f lw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 153f lw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 150f lw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 151f lw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 159f lw s3,60\(s1\) +[0-9a-f]+ <[^>]+> 161f lw a0,60\(s1\) +[0-9a-f]+ <[^>]+> 169f lw a1,60\(s1\) +[0-9a-f]+ <[^>]+> 171f lw a2,60\(s1\) +[0-9a-f]+ <[^>]+> 179f lw a3,60\(s1\) +[0-9a-f]+ <[^>]+> 141f lw s0,60\(s1\) +[0-9a-f]+ <[^>]+> 149f lw s1,60\(s1\) +[0-9a-f]+ <[^>]+> 3480 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 3480 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 3481 lw a0,4\(sp\) +[0-9a-f]+ <[^>]+> 3482 lw a0,8\(sp\) +[0-9a-f]+ <[^>]+> 3483 lw a0,12\(sp\) +[0-9a-f]+ <[^>]+> 3484 lw a0,16\(sp\) +[0-9a-f]+ <[^>]+> 3485 lw a0,20\(sp\) +[0-9a-f]+ <[^>]+> 349f lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 345f lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 345f lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 347f lw t5,124\(sp\) +[0-9a-f]+ <[^>]+> 349f lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 34bf lw a1,124\(sp\) +[0-9a-f]+ <[^>]+> 34df lw a2,124\(sp\) +[0-9a-f]+ <[^>]+> 34ff lw a3,124\(sp\) +[0-9a-f]+ <[^>]+> 351f lw a4,124\(sp\) +[0-9a-f]+ <[^>]+> 353f lw a5,124\(sp\) +[0-9a-f]+ <[^>]+> 355f lw a6,124\(sp\) +[0-9a-f]+ <[^>]+> 37df lw fp,124\(sp\) +[0-9a-f]+ <[^>]+> 37ff lw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 81f8 lw a0,504\(sp\) +[0-9a-f]+ <[^>]+> 849d 81fc lw a0,508\(sp\) +[0-9a-f]+ <[^>]+> 861d 81fc lw s0,508\(sp\) +[0-9a-f]+ <[^>]+> 863d 81fc lw s1,508\(sp\) +[0-9a-f]+ <[^>]+> 865d 81fc lw s2,508\(sp\) +[0-9a-f]+ <[^>]+> 867d 81fc lw s3,508\(sp\) +[0-9a-f]+ <[^>]+> 869d 81fc lw s4,508\(sp\) +[0-9a-f]+ <[^>]+> 86bd 81fc lw s5,508\(sp\) +[0-9a-f]+ <[^>]+> 87fd 81fc lw ra,508\(sp\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 c0ff lw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 15c0 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 15c0 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 15c1 lw s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 c0ff lw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 52c7 lwxs s3,a0\(a1\) +[0-9a-f]+ <[^>]+> 2040 0030 mfc0 t4,index +[0-9a-f]+ <[^>]+> 2041 0030 mfc0 t4,random +[0-9a-f]+ <[^>]+> 2042 0830 mfc0 t4,tcstatus +[0-9a-f]+ <[^>]+> 2042 1030 mfc0 t4,tcbind +[0-9a-f]+ <[^>]+> 2043 0070 mtc0 t4,entrylo1 +[0-9a-f]+ <[^>]+> 2044 0070 mtc0 t4,context +[0-9a-f]+ <[^>]+> 2045 3070 mtc0 t4,pwfield +[0-9a-f]+ <[^>]+> 2045 3870 mtc0 t4,pwsize +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1610 movn t4,t5,a0 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1210 movz t4,t5,a0 +[0-9a-f]+ <[^>]+> 2083 1018 mul t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e818 mul sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 2060 1190 neg t4,t5 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 5120 not s2,s2 +[0-9a-f]+ <[^>]+> 5120 not s2,s2 +[0-9a-f]+ <[^>]+> 5130 not s2,s3 +[0-9a-f]+ <[^>]+> 5140 not s2,a0 +[0-9a-f]+ <[^>]+> 5150 not s2,a1 +[0-9a-f]+ <[^>]+> 5160 not s2,a2 +[0-9a-f]+ <[^>]+> 5170 not s2,a3 +[0-9a-f]+ <[^>]+> 5100 not s2,s0 +[0-9a-f]+ <[^>]+> 5110 not s2,s1 +[0-9a-f]+ <[^>]+> 5190 not s3,s1 +[0-9a-f]+ <[^>]+> 5210 not a0,s1 +[0-9a-f]+ <[^>]+> 5290 not a1,s1 +[0-9a-f]+ <[^>]+> 5310 not a2,s1 +[0-9a-f]+ <[^>]+> 5390 not a3,s1 +[0-9a-f]+ <[^>]+> 5010 not s0,s1 +[0-9a-f]+ <[^>]+> 5090 not s1,s1 +[0-9a-f]+ <[^>]+> 2007 12d0 not t4,a3 +[0-9a-f]+ <[^>]+> 20e0 12d0 nor t4,zero,a3 +[0-9a-f]+ <[^>]+> 2083 12d0 nor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ead0 nor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1290 or t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b290 or s6,zero,t4 +[0-9a-f]+ <[^>]+> 512c or s2,s2,s2 +[0-9a-f]+ <[^>]+> 513c or s2,s2,s3 +[0-9a-f]+ <[^>]+> 514c or s2,s2,a0 +[0-9a-f]+ <[^>]+> 515c or s2,s2,a1 +[0-9a-f]+ <[^>]+> 516c or s2,s2,a2 +[0-9a-f]+ <[^>]+> 517c or s2,s2,a3 +[0-9a-f]+ <[^>]+> 510c or s2,s2,s0 +[0-9a-f]+ <[^>]+> 511c or s2,s2,s1 +[0-9a-f]+ <[^>]+> 51ac or s3,s3,s2 +[0-9a-f]+ <[^>]+> 522c or a0,a0,s2 +[0-9a-f]+ <[^>]+> 52ac or a1,a1,s2 +[0-9a-f]+ <[^>]+> 532c or a2,a2,s2 +[0-9a-f]+ <[^>]+> 53ac or a3,a3,s2 +[0-9a-f]+ <[^>]+> 502c or s0,s0,s2 +[0-9a-f]+ <[^>]+> 50ac or s1,s1,s2 +[0-9a-f]+ <[^>]+> 512c or s2,s2,s2 +[0-9a-f]+ <[^>]+> 513c or s2,s2,s3 +[0-9a-f]+ <[^>]+> 513c or s2,s2,s3 +[0-9a-f]+ <[^>]+> 2083 1290 or t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ea90 or sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8043 0fff ori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8064 0000 ori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8064 0fff ori t5,a0,0xfff +[0-9a-f]+ <[^>]+> 2040 01c0 rdhwr t4,hwr_cpunum +[0-9a-f]+ <[^>]+> 2041 01c0 rdhwr t4,hwr_synci_step +[0-9a-f]+ <[^>]+> 2042 01c0 rdhwr t4,hwr_cc +[0-9a-f]+ <[^>]+> 2043 01c0 rdhwr t4,hwr_ccres +[0-9a-f]+ <[^>]+> 2044 01c0 rdhwr t4,hwr_perfcnt +[0-9a-f]+ <[^>]+> 2045 01c0 rdhwr t4,hwr_xnp +[0-9a-f]+ <[^>]+> 2046 01c0 rdhwr t4,\$6 +[0-9a-f]+ <[^>]+> 2047 01c0 rdhwr t4,\$7 +[0-9a-f]+ <[^>]+> 2048 01c0 rdhwr t4,\$8 +[0-9a-f]+ <[^>]+> 2049 01c0 rdhwr t4,\$9 +[0-9a-f]+ <[^>]+> 204a 01c0 rdhwr t4,\$10 +[0-9a-f]+ <[^>]+> 2043 e17f rdpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2042 e17f rdpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2062 0158 mod zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0158 mod zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0158 mod zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0158 mod zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1158 mod t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1158 mod t4,t5,a0 +[0-9a-f]+ <[^>]+> 1017 break 0x7 +[0-9a-f]+ <[^>]+> 1060 move t5,zero +[0-9a-f]+ <[^>]+> 1060 move t5,zero +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1958 mod t5,a0,at +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2080 09d0 negu at,a0 +[0-9a-f]+ <[^>]+> 2022 10d0 rotrv t4,t4,at +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 5c34 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 5c34 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 5c35 sb zero,1\(s3\) +[0-9a-f]+ <[^>]+> 5c36 sb zero,2\(s3\) +[0-9a-f]+ <[^>]+> 5c37 sb zero,3\(s3\) +[0-9a-f]+ <[^>]+> 8403 1004 sb zero,4\(t5\) +[0-9a-f]+ <[^>]+> 8403 1005 sb zero,5\(t5\) +[0-9a-f]+ <[^>]+> 8403 1006 sb zero,6\(t5\) +[0-9a-f]+ <[^>]+> 8403 1007 sb zero,7\(t5\) +[0-9a-f]+ <[^>]+> 8403 1008 sb zero,8\(t5\) +[0-9a-f]+ <[^>]+> 8403 1009 sb zero,9\(t5\) +[0-9a-f]+ <[^>]+> 8403 100a sb zero,10\(t5\) +[0-9a-f]+ <[^>]+> 8403 100b sb zero,11\(t5\) +[0-9a-f]+ <[^>]+> 8403 100c sb zero,12\(t5\) +[0-9a-f]+ <[^>]+> 8403 100d sb zero,13\(t5\) +[0-9a-f]+ <[^>]+> 8403 100e sb zero,14\(t5\) +[0-9a-f]+ <[^>]+> 8403 100f sb zero,15\(t5\) +[0-9a-f]+ <[^>]+> 8443 100f sb t4,15\(t5\) +[0-9a-f]+ <[^>]+> 8463 100f sb t5,15\(t5\) +[0-9a-f]+ <[^>]+> 8483 100f sb a0,15\(t5\) +[0-9a-f]+ <[^>]+> 84a3 100f sb a1,15\(t5\) +[0-9a-f]+ <[^>]+> 84c3 100f sb a2,15\(t5\) +[0-9a-f]+ <[^>]+> 84e3 100f sb a3,15\(t5\) +[0-9a-f]+ <[^>]+> 8623 100f sb s1,15\(t5\) +[0-9a-f]+ <[^>]+> 8624 100f sb s1,15\(a0\) +[0-9a-f]+ <[^>]+> 8625 100f sb s1,15\(a1\) +[0-9a-f]+ <[^>]+> 8626 100f sb s1,15\(a2\) +[0-9a-f]+ <[^>]+> 8627 100f sb s1,15\(a3\) +[0-9a-f]+ <[^>]+> 8622 100f sb s1,15\(t4\) +[0-9a-f]+ <[^>]+> 8630 100f sb s1,15\(s0\) +[0-9a-f]+ <[^>]+> 8631 100f sb s1,15\(s1\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1fff sb t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 88ff sb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1fff sb t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 88ff sb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 6020 5678 1234 li at,0x12345678 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> 0024 07ff addiu at,a0,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8800 addiu at,a0,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 7fff addiu at,a0,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8001 addiu at,a0,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 6020 5678 1234 li at,0x12345678 +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 1018 sdbbp +[0-9a-f]+ <[^>]+> 1018 sdbbp +[0-9a-f]+ <[^>]+> 1019 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 101a sdbbp 0x2 +[0-9a-f]+ <[^>]+> 101b sdbbp 0x3 +[0-9a-f]+ <[^>]+> 101c sdbbp 0x4 +[0-9a-f]+ <[^>]+> 101d sdbbp 0x5 +[0-9a-f]+ <[^>]+> 101e sdbbp 0x6 +[0-9a-f]+ <[^>]+> 101f sdbbp 0x7 +[0-9a-f]+ <[^>]+> 0018 0008 sdbbp 0x8 +[0-9a-f]+ <[^>]+> 0018 0009 sdbbp 0x9 +[0-9a-f]+ <[^>]+> 0018 000a sdbbp 0xa +[0-9a-f]+ <[^>]+> 0018 000b sdbbp 0xb +[0-9a-f]+ <[^>]+> 0018 000c sdbbp 0xc +[0-9a-f]+ <[^>]+> 0018 000d sdbbp 0xd +[0-9a-f]+ <[^>]+> 0018 000e sdbbp 0xe +[0-9a-f]+ <[^>]+> 0018 000f sdbbp 0xf +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0001 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 0018 0002 sdbbp 0x2 +[0-9a-f]+ <[^>]+> 0018 00ff sdbbp 0xff +[0-9a-f]+ <[^>]+> 2043 0008 seb t4,t5 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2043 0048 seh t4,t5 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8044 5001 sltiu t4,a0,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 6001 seqi t4,t5,1 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 7d31 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d31 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 7d33 sh s2,2\(s3\) +[0-9a-f]+ <[^>]+> 7d35 sh s2,4\(s3\) +[0-9a-f]+ <[^>]+> 7d37 sh s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 5008 sh t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 500a sh t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 500c sh t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 500e sh t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 5010 sh t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 5012 sh t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 5014 sh t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 5016 sh t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 5018 sh t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 501a sh t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 501c sh t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 501e sh t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 501e sh t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 501e sh t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 501e sh t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 501e sh t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 501e sh t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 501e sh t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 501e sh t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 501e sh t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 501e sh a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 501e sh a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 501e sh a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 501e sh a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 501e sh s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8411 501e sh zero,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5fff sh t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 a8ff sh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5fff sh t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 a8ff sh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 3121 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 3122 sll s2,s2,2 +[0-9a-f]+ <[^>]+> 3123 sll s2,s2,3 +[0-9a-f]+ <[^>]+> 3124 sll s2,s2,4 +[0-9a-f]+ <[^>]+> 3125 sll s2,s2,5 +[0-9a-f]+ <[^>]+> 3126 sll s2,s2,6 +[0-9a-f]+ <[^>]+> 3127 sll s2,s2,7 +[0-9a-f]+ <[^>]+> 3120 sll s2,s2,8 +[0-9a-f]+ <[^>]+> 3130 sll s2,s3,8 +[0-9a-f]+ <[^>]+> 3140 sll s2,a0,8 +[0-9a-f]+ <[^>]+> 3150 sll s2,a1,8 +[0-9a-f]+ <[^>]+> 3160 sll s2,a2,8 +[0-9a-f]+ <[^>]+> 3170 sll s2,a3,8 +[0-9a-f]+ <[^>]+> 3100 sll s2,s0,8 +[0-9a-f]+ <[^>]+> 3110 sll s2,s1,8 +[0-9a-f]+ <[^>]+> 31a0 sll s3,s2,8 +[0-9a-f]+ <[^>]+> 3220 sll a0,s2,8 +[0-9a-f]+ <[^>]+> 32a0 sll a1,s2,8 +[0-9a-f]+ <[^>]+> 3320 sll a2,s2,8 +[0-9a-f]+ <[^>]+> 33a0 sll a3,s2,8 +[0-9a-f]+ <[^>]+> 3020 sll s0,s2,8 +[0-9a-f]+ <[^>]+> 30a0 sll s1,s2,8 +[0-9a-f]+ <[^>]+> 3121 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 31b1 sll s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1010 sllv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c000 sll t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c001 sll t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c01f sll t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8064 4000 slti t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 4fff slti t5,a0,4095 +[0-9a-f]+ <[^>]+> 8064 5000 sltiu t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 5fff sltiu t5,a0,4095 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2080 1390 sltu t4,zero,a0 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 8043 1001 xori t4,t5,0x1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2083 1090 srav t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c080 sra t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c081 sra t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c09f sra t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1050 srlv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c040 srl t4,a0,0 +[0-9a-f]+ <[^>]+> 3149 srl s2,a0,1 +[0-9a-f]+ <[^>]+> 8044 c05f srl t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 3129 srl s2,s2,1 +[0-9a-f]+ <[^>]+> 312a srl s2,s2,2 +[0-9a-f]+ <[^>]+> 312b srl s2,s2,3 +[0-9a-f]+ <[^>]+> 312c srl s2,s2,4 +[0-9a-f]+ <[^>]+> 312d srl s2,s2,5 +[0-9a-f]+ <[^>]+> 312e srl s2,s2,6 +[0-9a-f]+ <[^>]+> 312f srl s2,s2,7 +[0-9a-f]+ <[^>]+> 3128 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 3138 srl s2,s3,8 +[0-9a-f]+ <[^>]+> 3148 srl s2,a0,8 +[0-9a-f]+ <[^>]+> 3158 srl s2,a1,8 +[0-9a-f]+ <[^>]+> 3168 srl s2,a2,8 +[0-9a-f]+ <[^>]+> 3178 srl s2,a3,8 +[0-9a-f]+ <[^>]+> 3108 srl s2,s0,8 +[0-9a-f]+ <[^>]+> 3118 srl s2,s1,8 +[0-9a-f]+ <[^>]+> 3128 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 31a8 srl s3,s2,8 +[0-9a-f]+ <[^>]+> 3228 srl a0,s2,8 +[0-9a-f]+ <[^>]+> 32a8 srl a1,s2,8 +[0-9a-f]+ <[^>]+> 3328 srl a2,s2,8 +[0-9a-f]+ <[^>]+> 33a8 srl a3,s2,8 +[0-9a-f]+ <[^>]+> 3028 srl s0,s2,8 +[0-9a-f]+ <[^>]+> 30a8 srl s1,s2,8 +[0-9a-f]+ <[^>]+> 31b9 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 31b9 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1190 sub t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e990 sub sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> b135 subu s2,s3,s2 +[0-9a-f]+ <[^>]+> b1b5 subu s2,s3,s3 +[0-9a-f]+ <[^>]+> b235 subu s2,s3,a0 +[0-9a-f]+ <[^>]+> b2b5 subu s2,s3,a1 +[0-9a-f]+ <[^>]+> b335 subu s2,s3,a2 +[0-9a-f]+ <[^>]+> b3b5 subu s2,s3,a3 +[0-9a-f]+ <[^>]+> b035 subu s2,s3,s0 +[0-9a-f]+ <[^>]+> b0b5 subu s2,s3,s1 +[0-9a-f]+ <[^>]+> b0a5 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0c5 subu s2,a0,s1 +[0-9a-f]+ <[^>]+> b0d5 subu s2,a1,s1 +[0-9a-f]+ <[^>]+> b0e5 subu s2,a2,s1 +[0-9a-f]+ <[^>]+> b0f5 subu s2,a3,s1 +[0-9a-f]+ <[^>]+> b085 subu s2,s0,s1 +[0-9a-f]+ <[^>]+> b095 subu s2,s1,s1 +[0-9a-f]+ <[^>]+> b0a5 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> b0a7 subu s3,s2,s1 +[0-9a-f]+ <[^>]+> b0a9 subu a0,s2,s1 +[0-9a-f]+ <[^>]+> b0ab subu a1,s2,s1 +[0-9a-f]+ <[^>]+> b0ad subu a2,s2,s1 +[0-9a-f]+ <[^>]+> b0af subu a3,s2,s1 +[0-9a-f]+ <[^>]+> b0a1 subu s0,s2,s1 +[0-9a-f]+ <[^>]+> b0a3 subu s1,s2,s1 +[0-9a-f]+ <[^>]+> b17f subu a3,a3,s2 +[0-9a-f]+ <[^>]+> b17f subu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2083 11d0 subu t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e9d0 subu sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 8042 8001 addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 6041 8001 ffff addiu t4,t4,-32767 +[0-9a-f]+ <[^>]+> 0042 8000 addiu t4,t4,32768 +[0-9a-f]+ <[^>]+> 6041 0001 ffff addiu t4,t4,-65535 +[0-9a-f]+ <[^>]+> 9540 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 9540 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 9541 sw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 9542 sw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 9543 sw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 9544 sw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 9545 sw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 9546 sw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 9547 sw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 9548 sw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 9549 sw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 954a sw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 954b sw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 954c sw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 954d sw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 954e sw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 954f sw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 955f sw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 956f sw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 957f sw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 950f sw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 951f sw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 952f sw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 953f sw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 95bf sw s3,60\(s3\) +[0-9a-f]+ <[^>]+> 963f sw a0,60\(s3\) +[0-9a-f]+ <[^>]+> 96bf sw a1,60\(s3\) +[0-9a-f]+ <[^>]+> 973f sw a2,60\(s3\) +[0-9a-f]+ <[^>]+> 97bf sw a3,60\(s3\) +[0-9a-f]+ <[^>]+> 94bf sw s1,60\(s3\) +[0-9a-f]+ <[^>]+> 943f sw zero,60\(s3\) +[0-9a-f]+ <[^>]+> b400 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> b400 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> b401 sw zero,4\(sp\) +[0-9a-f]+ <[^>]+> b402 sw zero,8\(sp\) +[0-9a-f]+ <[^>]+> b403 sw zero,12\(sp\) +[0-9a-f]+ <[^>]+> b404 sw zero,16\(sp\) +[0-9a-f]+ <[^>]+> b405 sw zero,20\(sp\) +[0-9a-f]+ <[^>]+> b41e sw zero,120\(sp\) +[0-9a-f]+ <[^>]+> b41f sw zero,124\(sp\) +[0-9a-f]+ <[^>]+> b45f sw t4,124\(sp\) +[0-9a-f]+ <[^>]+> b63f sw s1,124\(sp\) +[0-9a-f]+ <[^>]+> b47f sw t5,124\(sp\) +[0-9a-f]+ <[^>]+> b49f sw a0,124\(sp\) +[0-9a-f]+ <[^>]+> b4bf sw a1,124\(sp\) +[0-9a-f]+ <[^>]+> b4df sw a2,124\(sp\) +[0-9a-f]+ <[^>]+> b4ff sw a3,124\(sp\) +[0-9a-f]+ <[^>]+> b7ff sw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9fff sw t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 c8ff sw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9fff sw t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 c8ff sw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8001 c006 sync 0x1 +[0-9a-f]+ <[^>]+> 8002 c006 sync 0x2 +[0-9a-f]+ <[^>]+> 8003 c006 sync 0x3 +[0-9a-f]+ <[^>]+> 8005 c006 sync 0x5 +[0-9a-f]+ <[^>]+> 801e c006 sync 0x1e +[0-9a-f]+ <[^>]+> 801f c006 sync 0x1f +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 37ff synci 2047\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3800 synci 2048\(zero\) +[0-9a-f]+ <[^>]+> 87e2 3000 synci 0\(t4\) +[0-9a-f]+ <[^>]+> 87e3 3000 synci 0\(t5\) +[0-9a-f]+ <[^>]+> 87e3 30ff synci 255\(t5\) +[0-9a-f]+ <[^>]+> a7e3 9800 synci -256\(t5\) +[0-9a-f]+ <[^>]+> 87e3 3800 synci 2048\(t5\) +[0-9a-f]+ <[^>]+> 1008 syscall +[0-9a-f]+ <[^>]+> 1008 syscall +[0-9a-f]+ <[^>]+> 1009 syscall 0x1 +[0-9a-f]+ <[^>]+> 100a syscall 0x2 +[0-9a-f]+ <[^>]+> 0008 00ff syscall 0xff +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2001 c37f wait 0x1 +[0-9a-f]+ <[^>]+> 20ff c37f wait 0xff +[0-9a-f]+ <[^>]+> 2043 f17f wrpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2044 f17f wrpgpr t4,a0 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 8043 d608 byterevh t4,t5 +[0-9a-f]+ <[^>]+> 8044 d608 byterevh t4,a0 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 5124 xor s2,s2,s2 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 5144 xor s2,s2,a0 +[0-9a-f]+ <[^>]+> 5154 xor s2,s2,a1 +[0-9a-f]+ <[^>]+> 5164 xor s2,s2,a2 +[0-9a-f]+ <[^>]+> 5174 xor s2,s2,a3 +[0-9a-f]+ <[^>]+> 5104 xor s2,s2,s0 +[0-9a-f]+ <[^>]+> 5114 xor s2,s2,s1 +[0-9a-f]+ <[^>]+> 5194 xor s3,s3,s1 +[0-9a-f]+ <[^>]+> 5214 xor a0,a0,s1 +[0-9a-f]+ <[^>]+> 5294 xor a1,a1,s1 +[0-9a-f]+ <[^>]+> 5314 xor a2,a2,s1 +[0-9a-f]+ <[^>]+> 5394 xor a3,a3,s1 +[0-9a-f]+ <[^>]+> 5014 xor s0,s0,s1 +[0-9a-f]+ <[^>]+> 5094 xor s1,s1,s1 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 5134 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe eb10 xor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8043 1fff xori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 6020 7fff ffff li at,0xffff7fff +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8064 1000 xori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8063 1fff xori t5,t5,0xfff +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8949 0000 beqc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c920 0800 beqic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8940 8000 blezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 896a 8000 bgec a6,a7,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c948 1000 bgeic a6,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 c000 bgeuc t4,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8840 c000 bgeuc zero,t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8862 c000 bgeuc t4,t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 0000 bnezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c84c 1000 bgeiuc t4,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 8000 bgtzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a802 8000 bltzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8809 8000 bgezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c928 1000 bgeic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 6020 0001 8000 li at,0x80000001 +[0-9a-f]+ <[^>]+> 2029 0b50 slt at,a5,at +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c92c 1000 bgeiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 8000 bltc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 c000 bltuc a5,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 c000 bltuc zero,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 c000 bltuc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 9008 nop +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 0000 bnec a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c930 0800 bneic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> b2c6 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 1d00 restore.jrc 0 +[0-9a-f]+ <[^>]+> 8000 300b restore.jrc 8 +[0-9a-f]+ <[^>]+> 1d10 restore.jrc 16 +[0-9a-f]+ <[^>]+> 8000 301b restore.jrc 24 +[0-9a-f]+ <[^>]+> 1d20 restore.jrc 32 +[0-9a-f]+ <[^>]+> 8000 302b restore.jrc 40 +[0-9a-f]+ <[^>]+> 03bd 0004 addiu sp,sp,4 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 000c addiu sp,sp,12 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0014 addiu sp,sp,20 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 001c addiu sp,sp,28 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0024 addiu sp,sp,36 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 8000 307b restore.jrc 120 +[0-9a-f]+ <[^>]+> 03bd 007c addiu sp,sp,124 +[0-9a-f]+ <[^>]+> dbe0 jrc ra +[0-9a-f]+ <[^>]+> 0018 03ff sdbbp 0x3ff +[0-9a-f]+ <[^>]+> 23ff c37f wait 0x3ff +[0-9a-f]+ <[^>]+> 0008 03ff syscall 0x3ff +[0-9a-f]+ <[^>]+> 3800 balc [0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC10_S1 test_delay_slot +[0-9a-f]+ <[^>]+> d850 jalrc t4 +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> d840 jrc t4 +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 557f lw s2,508\(gp\) +[0-9a-f]+ <[^>]+> 55ff lw s3,508\(gp\) +[0-9a-f]+ <[^>]+> 567f lw a0,508\(gp\) +[0-9a-f]+ <[^>]+> 56ff lw a1,508\(gp\) +[0-9a-f]+ <[^>]+> 577f lw a2,508\(gp\) +[0-9a-f]+ <[^>]+> 57ff lw a3,508\(gp\) +[0-9a-f]+ <[^>]+> 547f lw s0,508\(gp\) +[0-9a-f]+ <[^>]+> 54ff lw s1,508\(gp\) +[0-9a-f]+ <[^>]+> 54fe lw s1,504\(gp\) +[0-9a-f]+ <[^>]+> 54fd lw s1,500\(gp\) +[0-9a-f]+ <[^>]+> 5480 lw s1,0\(gp\) +[0-9a-f]+ <[^>]+> 5481 lw s1,4\(gp\) +[0-9a-f]+ <[^>]+> 54be lw s1,248\(gp\) +[0-9a-f]+ <[^>]+> 54bf lw s1,252\(gp\) +[0-9a-f]+ <[^>]+> 54c0 lw s1,256\(gp\) +[0-9a-f]+ <[^>]+> 823c 8104 addiu s1,gp,-260 +[0-9a-f]+ <[^>]+> 8631 8000 lw s1,0\(s1\) +[0-9a-f]+ <[^>]+> 863c 8001 lw s1,1\(gp\) +[0-9a-f]+ <[^>]+> 863c 8002 lw s1,2\(gp\) +[0-9a-f]+ <[^>]+> 863c 8003 lw s1,3\(gp\) +[0-9a-f]+ <[^>]+> a63c c0ff lw s1,-1\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fe lw s1,-2\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fd lw s1,-3\(gp\) +[0-9a-f]+ <[^>]+> 863b 8000 lw s1,0\(k1\) +[0-9a-f]+ <[^>]+> bd63 movep a1,a2,zero,zero +[0-9a-f]+ <[^>]+> bc6b movep a2,a3,zero,zero +[0-9a-f]+ <[^>]+> bc63 movep a0,a1,zero,zero +[0-9a-f]+ <[^>]+> bd63 movep a1,a2,zero,zero +[0-9a-f]+ <[^>]+> bc6b movep a2,a3,zero,zero +[0-9a-f]+ <[^>]+> bc79 movep a2,a3,s1,zero +[0-9a-f]+ <[^>]+> bc69 movep a2,a3,a5,zero +[0-9a-f]+ <[^>]+> bc6a movep a2,a3,a6,zero +[0-9a-f]+ <[^>]+> bc78 movep a2,a3,s0,zero +[0-9a-f]+ <[^>]+> bc7a movep a2,a3,s2,zero +[0-9a-f]+ <[^>]+> bc7b movep a2,a3,s3,zero +[0-9a-f]+ <[^>]+> bc7c movep a2,a3,s4,zero +[0-9a-f]+ <[^>]+> be3c movep a2,a3,s4,s1 +[0-9a-f]+ <[^>]+> bc3c movep a2,a3,s4,a5 +[0-9a-f]+ <[^>]+> bc5c movep a2,a3,s4,a6 +[0-9a-f]+ <[^>]+> be1c movep a2,a3,s4,s0 +[0-9a-f]+ <[^>]+> be5c movep a2,a3,s4,s2 +[0-9a-f]+ <[^>]+> be7c movep a2,a3,s4,s3 +[0-9a-f]+ <[^>]+> be9c movep a2,a3,s4,s4 +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> 8043 f300 ext t4,t5,0,13 +[0-9a-f]+ <[^>]+> 8044 f340 ext t4,a0,0,14 +[0-9a-f]+ <[^>]+> 8045 f380 ext t4,a1,0,15 +[0-9a-f]+ <[^>]+> 8046 f3c0 ext t4,a2,0,16 +[0-9a-f]+ <[^>]+> 8047 f500 ext t4,a3,0,21 +[0-9a-f]+ <[^>]+> 8048 f540 ext t4,a4,0,22 +[0-9a-f]+ <[^>]+> 8049 f580 ext t4,a5,0,23 +[0-9a-f]+ <[^>]+> 8050 f5c0 ext t4,s0,0,24 +[0-9a-f]+ <[^>]+> 6040 0000 0000 li t4,0x0 + [0-9a-f]+: R_NANOMIPS_I32 test +[0-9a-f]+ <[^>]+> 2000 0390 dvp +[0-9a-f]+ <[^>]+> 20a0 0390 dvp a1 +[0-9a-f]+ <[^>]+> 2000 0790 evp +[0-9a-f]+ <[^>]+> 20c0 0790 evp a2 +#pass diff --git a/gas/testsuite/gas/nanomips/nanomips64@nanomips32.d b/gas/testsuite/gas/nanomips/nanomips64@nanomips32.d new file mode 100644 index 00000000000..ceacbb8ad8d --- /dev/null +++ b/gas/testsuite/gas/nanomips/nanomips64@nanomips32.d @@ -0,0 +1,2309 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS64 32-bit instruction mode +#as: -minsn32 --defsym insn32= +#warning_output: nanomips.l +#source: nanomips.s + +# Check nanoMIPS32 fixed-size instructions + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 37ff pref 0x0,2047\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3800 pref 0x0,2048\(zero\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 1800 pref 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8400 3000 pref 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8420 3000 pref 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> 8440 3000 pref 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 3000 pref 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> 8480 3000 pref 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> 84a0 3000 pref 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> 84c0 3000 pref 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 3000 pref 0x7,0\(zero\) +[0-9a-f]+ <[^>]+> 84e0 31ff pref 0x7,511\(zero\) +[0-9a-f]+ <[^>]+> 8020 8200 li at,-512 +[0-9a-f]+ <[^>]+> a4e1 1800 pref 0x7,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 0022 7fff addiu at,t4,32767 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2041 0950 addu at,at,t4 +[0-9a-f]+ <[^>]+> a461 1800 pref 0x3,0\(at\) +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 8000 c003 ehb +[0-9a-f]+ <[^>]+> 8000 c005 pause +[0-9a-f]+ <[^>]+> 8240 8001 li s2,-1 +[0-9a-f]+ <[^>]+> 8260 8001 li s3,-1 +[0-9a-f]+ <[^>]+> 8080 8001 li a0,-1 +[0-9a-f]+ <[^>]+> 80a0 8001 li a1,-1 +[0-9a-f]+ <[^>]+> 80c0 8001 li a2,-1 +[0-9a-f]+ <[^>]+> 80e0 8001 li a3,-1 +[0-9a-f]+ <[^>]+> 8200 8001 li s0,-1 +[0-9a-f]+ <[^>]+> 8220 8001 li s1,-1 +[0-9a-f]+ <[^>]+> 0220 0000 li s1,0 +[0-9a-f]+ <[^>]+> 0220 007d li s1,125 +[0-9a-f]+ <[^>]+> 0220 007e li s1,126 +[0-9a-f]+ <[^>]+> 0220 007f li s1,127 +[0-9a-f]+ <[^>]+> 0180 0000 li t0,0 +[0-9a-f]+ <[^>]+> 0320 0000 li t9,0 +[0-9a-f]+ <[^>]+> 0040 0000 li t4,0 +[0-9a-f]+ <[^>]+> 0040 0001 li t4,1 +[0-9a-f]+ <[^>]+> 0040 7fff li t4,32767 +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 0040 ffff li t4,65535 +[0-9a-f]+ <[^>]+> e041 0000 lui t4,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e05f 8ffd lui t4,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8042 0001 ori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8040 8001 li t4,-1 +[0-9a-f]+ <[^>]+> e054 5244 lui t4,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8042 0678 ori t4,t4,0x678 +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> 8080 8001 li a0,-1 +[0-9a-f]+ <[^>]+> 2016 0290 move zero,s6 +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2016 1a90 move t5,s6 +[0-9a-f]+ <[^>]+> 2016 2290 move a0,s6 +[0-9a-f]+ <[^>]+> 2016 2a90 move a1,s6 +[0-9a-f]+ <[^>]+> 2016 3290 move a2,s6 +[0-9a-f]+ <[^>]+> 2016 3a90 move a3,s6 +[0-9a-f]+ <[^>]+> 2016 4290 move a4,s6 +[0-9a-f]+ <[^>]+> 2016 4a90 move a5,s6 +[0-9a-f]+ <[^>]+> 2016 5290 move a6,s6 +[0-9a-f]+ <[^>]+> 2016 f290 move fp,s6 +[0-9a-f]+ <[^>]+> 2016 fa90 move ra,s6 +[0-9a-f]+ <[^>]+> 2000 0290 move zero,zero +[0-9a-f]+ <[^>]+> 2002 0290 move zero,t4 +[0-9a-f]+ <[^>]+> 2003 0290 move zero,t5 +[0-9a-f]+ <[^>]+> 2004 0290 move zero,a0 +[0-9a-f]+ <[^>]+> 2005 0290 move zero,a1 +[0-9a-f]+ <[^>]+> 2006 0290 move zero,a2 +[0-9a-f]+ <[^>]+> 2007 0290 move zero,a3 +[0-9a-f]+ <[^>]+> 2008 0290 move zero,a4 +[0-9a-f]+ <[^>]+> 2009 0290 move zero,a5 +[0-9a-f]+ <[^>]+> 200a 0290 move zero,a6 +[0-9a-f]+ <[^>]+> 201e 0290 move zero,fp +[0-9a-f]+ <[^>]+> 201f 0290 move zero,ra +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 0000016c <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 .L1\^B1 +[0-9a-f]+ <[^>]+> 2003 1290 move t4,t5 +[0-9a-f]+ <[^>]+> 8803 8000 bgezc t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_0 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2004 1290 move t4,a0 +[0-9a-f]+ <[^>]+> 8804 8000 bgezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_1 +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_2 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 .L\^_3 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2083 1110 add t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e910 add sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1110 add t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1110 add t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0064 0000 addiu t5,a0,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2024 1910 add t5,a0,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1910 add t5,t5,at +[0-9a-f]+ <[^>]+> 8000 8008 li zero,-8 +[0-9a-f]+ <[^>]+> 8042 8008 addiu t4,t4,-8 +[0-9a-f]+ <[^>]+> 8063 8008 addiu t5,t5,-8 +[0-9a-f]+ <[^>]+> 8084 8008 addiu a0,a0,-8 +[0-9a-f]+ <[^>]+> 80a5 8008 addiu a1,a1,-8 +[0-9a-f]+ <[^>]+> 80c6 8008 addiu a2,a2,-8 +[0-9a-f]+ <[^>]+> 80e7 8008 addiu a3,a3,-8 +[0-9a-f]+ <[^>]+> 8108 8008 addiu a4,a4,-8 +[0-9a-f]+ <[^>]+> 8129 8008 addiu a5,a5,-8 +[0-9a-f]+ <[^>]+> 814a 8008 addiu a6,a6,-8 +[0-9a-f]+ <[^>]+> 83de 8008 addiu fp,fp,-8 +[0-9a-f]+ <[^>]+> 83ff 8008 addiu ra,ra,-8 +[0-9a-f]+ <[^>]+> 83ff 8007 addiu ra,ra,-7 +[0-9a-f]+ <[^>]+> 03ff 0000 addiu ra,ra,0 +[0-9a-f]+ <[^>]+> 03ff 0001 addiu ra,ra,1 +[0-9a-f]+ <[^>]+> 03ff 0006 addiu ra,ra,6 +[0-9a-f]+ <[^>]+> 03ff 0007 addiu ra,ra,7 +[0-9a-f]+ <[^>]+> 03ff 0008 addiu ra,ra,8 +[0-9a-f]+ <[^>]+> 83bd 8408 addiu sp,sp,-1032 +[0-9a-f]+ <[^>]+> 83bd 8404 addiu sp,sp,-1028 +[0-9a-f]+ <[^>]+> 83bd 8400 addiu sp,sp,-1024 +[0-9a-f]+ <[^>]+> 03bd 03fc addiu sp,sp,1020 +[0-9a-f]+ <[^>]+> 03bd 0400 addiu sp,sp,1024 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0404 addiu sp,sp,1028 +[0-9a-f]+ <[^>]+> 03bd 0408 addiu sp,sp,1032 +[0-9a-f]+ <[^>]+> 8042 8001 addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 8043 8001 addiu t4,t5,-1 +[0-9a-f]+ <[^>]+> 8044 8001 addiu t4,a0,-1 +[0-9a-f]+ <[^>]+> 8045 8001 addiu t4,a1,-1 +[0-9a-f]+ <[^>]+> 8046 8001 addiu t4,a2,-1 +[0-9a-f]+ <[^>]+> 8047 8001 addiu t4,a3,-1 +[0-9a-f]+ <[^>]+> 8050 8001 addiu t4,s0,-1 +[0-9a-f]+ <[^>]+> 8051 8001 addiu t4,s1,-1 +[0-9a-f]+ <[^>]+> 0051 0001 addiu t4,s1,1 +[0-9a-f]+ <[^>]+> 0251 0004 addiu s2,s1,4 +[0-9a-f]+ <[^>]+> 0251 0008 addiu s2,s1,8 +[0-9a-f]+ <[^>]+> 0251 000c addiu s2,s1,12 +[0-9a-f]+ <[^>]+> 0251 0010 addiu s2,s1,16 +[0-9a-f]+ <[^>]+> 0251 0014 addiu s2,s1,20 +[0-9a-f]+ <[^>]+> 0251 0018 addiu s2,s1,24 +[0-9a-f]+ <[^>]+> 0271 0018 addiu s3,s1,24 +[0-9a-f]+ <[^>]+> 0091 0018 addiu a0,s1,24 +[0-9a-f]+ <[^>]+> 00b1 0018 addiu a1,s1,24 +[0-9a-f]+ <[^>]+> 00d1 0018 addiu a2,s1,24 +[0-9a-f]+ <[^>]+> 00f1 0018 addiu a3,s1,24 +[0-9a-f]+ <[^>]+> 0211 0018 addiu s0,s1,24 +[0-9a-f]+ <[^>]+> 0231 0018 addiu s1,s1,24 +[0-9a-f]+ <[^>]+> 025d 0000 addiu s2,sp,0 +[0-9a-f]+ <[^>]+> 025d 0004 addiu s2,sp,4 +[0-9a-f]+ <[^>]+> 025d 00f8 addiu s2,sp,248 +[0-9a-f]+ <[^>]+> 025d 00fc addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 005d 0100 addiu t4,sp,256 +[0-9a-f]+ <[^>]+> 025d 00fc addiu s2,sp,252 +[0-9a-f]+ <[^>]+> 027d 00fc addiu s3,sp,252 +[0-9a-f]+ <[^>]+> 009d 00fc addiu a0,sp,252 +[0-9a-f]+ <[^>]+> 00bd 00fc addiu a1,sp,252 +[0-9a-f]+ <[^>]+> 00dd 00fc addiu a2,sp,252 +[0-9a-f]+ <[^>]+> 00fd 00fc addiu a3,sp,252 +[0-9a-f]+ <[^>]+> 021d 00fc addiu s0,sp,252 +[0-9a-f]+ <[^>]+> 023d 00fc addiu s1,sp,252 +[0-9a-f]+ <[^>]+> 8064 8fff addiu t5,a0,-4095 +[0-9a-f]+ <[^>]+> 0264 0000 addiu s3,a0,0 +[0-9a-f]+ <[^>]+> 0064 1fff addiu t5,a0,8191 +[0-9a-f]+ <[^>]+> 0064 3fff addiu t5,a0,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 0063 3fff addiu t5,t5,16383 +[0-9a-f]+ <[^>]+> 2016 1150 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b150 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1150 addu t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b150 addu s6,zero,t4 +[0-9a-f]+ <[^>]+> 2253 9150 addu s2,s3,s2 +[0-9a-f]+ <[^>]+> 2273 9150 addu s2,s3,s3 +[0-9a-f]+ <[^>]+> 2093 9150 addu s2,s3,a0 +[0-9a-f]+ <[^>]+> 20b3 9150 addu s2,s3,a1 +[0-9a-f]+ <[^>]+> 20d3 9150 addu s2,s3,a2 +[0-9a-f]+ <[^>]+> 20f3 9150 addu s2,s3,a3 +[0-9a-f]+ <[^>]+> 2213 9150 addu s2,s3,s0 +[0-9a-f]+ <[^>]+> 2233 9150 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> 2232 9150 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2233 9150 addu s2,s3,s1 +[0-9a-f]+ <[^>]+> 2224 9150 addu s2,a0,s1 +[0-9a-f]+ <[^>]+> 2225 9150 addu s2,a1,s1 +[0-9a-f]+ <[^>]+> 2226 9150 addu s2,a2,s1 +[0-9a-f]+ <[^>]+> 2227 9150 addu s2,a3,s1 +[0-9a-f]+ <[^>]+> 2230 9150 addu s2,s0,s1 +[0-9a-f]+ <[^>]+> 2231 9150 addu s2,s1,s1 +[0-9a-f]+ <[^>]+> 2232 9150 addu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 9950 addu s3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 2150 addu a0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 2950 addu a1,s2,s1 +[0-9a-f]+ <[^>]+> 2232 3150 addu a2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 3950 addu a3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 8150 addu s0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 8950 addu s1,s2,s1 +[0-9a-f]+ <[^>]+> 2247 3950 addu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2247 3950 addu a3,a3,s2 +[0-9a-f]+ <[^>]+> 20f2 3950 addu a3,s2,a3 +[0-9a-f]+ <[^>]+> 23fe e950 addu sp,fp,ra +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 0042 0001 addiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0042 7fff addiu t4,t4,32767 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1150 addu t4,t4,at +[0-9a-f]+ <[^>]+> 0042 ffff addiu t4,t4,65535 +[0-9a-f]+ <[^>]+> 2252 9250 and s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9250 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2092 9250 and s2,s2,a0 +[0-9a-f]+ <[^>]+> 20b2 9250 and s2,s2,a1 +[0-9a-f]+ <[^>]+> 20d2 9250 and s2,s2,a2 +[0-9a-f]+ <[^>]+> 20f2 9250 and s2,s2,a3 +[0-9a-f]+ <[^>]+> 2212 9250 and s2,s2,s0 +[0-9a-f]+ <[^>]+> 2232 9250 and s2,s2,s1 +[0-9a-f]+ <[^>]+> 2253 9a50 and s3,s3,s2 +[0-9a-f]+ <[^>]+> 2244 2250 and a0,a0,s2 +[0-9a-f]+ <[^>]+> 2245 2a50 and a1,a1,s2 +[0-9a-f]+ <[^>]+> 2246 3250 and a2,a2,s2 +[0-9a-f]+ <[^>]+> 2247 3a50 and a3,a3,s2 +[0-9a-f]+ <[^>]+> 2250 8250 and s0,s0,s2 +[0-9a-f]+ <[^>]+> 2251 8a50 and s1,s1,s2 +[0-9a-f]+ <[^>]+> 2272 9250 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2272 9250 and s2,s2,s3 +[0-9a-f]+ <[^>]+> 2253 9250 and s2,s3,s2 +[0-9a-f]+ <[^>]+> 2062 1250 and t4,t4,t5 +[0-9a-f]+ <[^>]+> 8252 2001 andi s2,s2,0x1 +[0-9a-f]+ <[^>]+> 8252 2002 andi s2,s2,0x2 +[0-9a-f]+ <[^>]+> 8252 2003 andi s2,s2,0x3 +[0-9a-f]+ <[^>]+> 8252 2004 andi s2,s2,0x4 +[0-9a-f]+ <[^>]+> 8252 2007 andi s2,s2,0x7 +[0-9a-f]+ <[^>]+> 8252 2008 andi s2,s2,0x8 +[0-9a-f]+ <[^>]+> 8252 200f andi s2,s2,0xf +[0-9a-f]+ <[^>]+> 8042 2010 andi t4,t4,0x10 +[0-9a-f]+ <[^>]+> 8042 201f andi t4,t4,0x1f +[0-9a-f]+ <[^>]+> 8042 2020 andi t4,t4,0x20 +[0-9a-f]+ <[^>]+> 8042 203f andi t4,t4,0x3f +[0-9a-f]+ <[^>]+> 8042 2040 andi t4,t4,0x40 +[0-9a-f]+ <[^>]+> 8042 2080 andi t4,t4,0x80 +[0-9a-f]+ <[^>]+> 8252 20ff andi s2,s2,0xff +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> 8252 f3c0 ext s2,s2,0,16 +[0-9a-f]+ <[^>]+> 8253 f3c0 ext s2,s3,0,16 +[0-9a-f]+ <[^>]+> 8244 f3c0 ext s2,a0,0,16 +[0-9a-f]+ <[^>]+> 8245 f3c0 ext s2,a1,0,16 +[0-9a-f]+ <[^>]+> 8246 f3c0 ext s2,a2,0,16 +[0-9a-f]+ <[^>]+> 8247 f3c0 ext s2,a3,0,16 +[0-9a-f]+ <[^>]+> 8250 f3c0 ext s2,s0,0,16 +[0-9a-f]+ <[^>]+> 8251 f3c0 ext s2,s1,0,16 +[0-9a-f]+ <[^>]+> 8271 f3c0 ext s3,s1,0,16 +[0-9a-f]+ <[^>]+> 8091 f3c0 ext a0,s1,0,16 +[0-9a-f]+ <[^>]+> 80b1 f3c0 ext a1,s1,0,16 +[0-9a-f]+ <[^>]+> 80d1 f3c0 ext a2,s1,0,16 +[0-9a-f]+ <[^>]+> 80f1 f3c0 ext a3,s1,0,16 +[0-9a-f]+ <[^>]+> 8211 f3c0 ext s0,s1,0,16 +[0-9a-f]+ <[^>]+> 8231 f3c0 ext s1,s1,0,16 +[0-9a-f]+ <[^>]+> 80e7 f3c0 ext a3,a3,0,16 +[0-9a-f]+ <[^>]+> 80e7 f3c0 ext a3,a3,0,16 +[0-9a-f]+ <[^>]+> 2083 1250 and t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1250 and t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 2000 andi t4,t5,0x0 +[0-9a-f]+ <[^>]+> 8043 2fff andi t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8021 0001 ori at,at,0x1 +[0-9a-f]+ <[^>]+> 2023 1250 and t4,t5,at +[0-9a-f]+ <[^>]+> 8a40 0000 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a60 0000 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8880 0000 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88a0 0000 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88c0 0000 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88e0 0000 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8812 0000 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8813 0000 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8804 0000 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8805 0000 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8806 0000 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8807 0000 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8810 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8811 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a40 0000 beqzc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a60 0000 beqzc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8880 0000 beqzc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88a0 0000 beqzc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88c0 0000 beqzc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 88e0 0000 beqzc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a20 0000 beqzc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 8a00 0000 beqzc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> ca00 5000 beqic s0,10,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test2 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 8830 0000 beqc s0,at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa40 0000 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa60 0000 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a880 0000 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8a0 0000 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8c0 0000 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8e0 0000 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a812 0000 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a813 0000 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a804 0000 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a805 0000 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a806 0000 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a807 0000 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a810 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a811 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa40 0000 bnezc s2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa60 0000 bnezc s3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a880 0000 bnezc a0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8a0 0000 bnezc a1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8c0 0000 bnezc a2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> a8e0 0000 bnezc a3,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa00 0000 bnezc s0,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test3 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> aa20 0000 bnezc s1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test2 +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0001 break 0x1 +[0-9a-f]+ <[^>]+> 0010 0002 break 0x2 +[0-9a-f]+ <[^>]+> 0010 0003 break 0x3 +[0-9a-f]+ <[^>]+> 0010 0004 break 0x4 +[0-9a-f]+ <[^>]+> 0010 0005 break 0x5 +[0-9a-f]+ <[^>]+> 0010 0006 break 0x6 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 0010 0008 break 0x8 +[0-9a-f]+ <[^>]+> 0010 0009 break 0x9 +[0-9a-f]+ <[^>]+> 0010 000a break 0xa +[0-9a-f]+ <[^>]+> 0010 000b break 0xb +[0-9a-f]+ <[^>]+> 0010 000c break 0xc +[0-9a-f]+ <[^>]+> 0010 000d break 0xd +[0-9a-f]+ <[^>]+> 0010 000e break 0xe +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0000 break +[0-9a-f]+ <[^>]+> 0010 0001 break 0x1 +[0-9a-f]+ <[^>]+> 0010 0002 break 0x2 +[0-9a-f]+ <[^>]+> 0010 000f break 0xf +[0-9a-f]+ <[^>]+> 0010 003f break 0x3f +[0-9a-f]+ <[^>]+> 0010 0040 break 0x40 +[0-9a-f]+ <[^>]+> 0010 03ff break 0x3ff +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a402 3900 cache 0x0,0\(t4\) +[0-9a-f]+ <[^>]+> 8022 8800 addiu at,t4,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 07ff addiu at,t4,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8022 8801 addiu at,t4,-2049 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 0022 0800 addiu at,t4,2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a400 3900 cache 0x0,0\(zero\) +[0-9a-f]+ <[^>]+> a420 3900 cache 0x1,0\(zero\) +[0-9a-f]+ <[^>]+> a440 3900 cache 0x2,0\(zero\) +[0-9a-f]+ <[^>]+> a460 3900 cache 0x3,0\(zero\) +[0-9a-f]+ <[^>]+> a480 3900 cache 0x4,0\(zero\) +[0-9a-f]+ <[^>]+> a4a0 3900 cache 0x5,0\(zero\) +[0-9a-f]+ <[^>]+> a4c0 3900 cache 0x6,0\(zero\) +[0-9a-f]+ <[^>]+> a7e0 3900 cache 0x1f,0\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a401 3900 cache 0x0,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0023 0800 addiu at,t5,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8023 8801 addiu at,t5,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e3 b9ff cache 0x1f,-1\(t5\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2061 0950 addu at,at,t5 +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0023 ffff addiu at,t5,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 0020 0800 li at,2048 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8801 li at,-2049 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> a7e0 b9ff cache 0x1f,-1\(zero\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a7e1 3901 cache 0x1f,1\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a7e1 3900 cache 0x1f,0\(at\) +[0-9a-f]+ <[^>]+> 2043 4b3f clo t4,t5 +[0-9a-f]+ <[^>]+> 2062 4b3f clo t5,t4 +[0-9a-f]+ <[^>]+> 2043 5b3f clz t4,t5 +[0-9a-f]+ <[^>]+> 2062 5b3f clz t5,t4 +[0-9a-f]+ <[^>]+> 2000 e37f deret +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2000 477f di +[0-9a-f]+ <[^>]+> 2040 477f di t4 +[0-9a-f]+ <[^>]+> 2060 477f di t5 +[0-9a-f]+ <[^>]+> 23c0 477f di fp +[0-9a-f]+ <[^>]+> 23e0 477f di ra +[0-9a-f]+ <[^>]+> 2062 0118 div zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0118 div zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0118 div zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0118 div zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1118 div t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1118 div t4,t5,a0 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 2004 1a90 move t5,a0 +[0-9a-f]+ <[^>]+> 2080 1990 neg t5,a0 +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1918 div t5,a0,at +[0-9a-f]+ <[^>]+> 2062 0198 divu zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0198 divu zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0198 divu zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0198 divu zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1198 divu t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1198 divu t4,t5,a0 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 2004 1a90 move t5,a0 +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1998 divu t5,a0,at +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2000 577f ei +[0-9a-f]+ <[^>]+> 2040 577f ei t4 +[0-9a-f]+ <[^>]+> 2060 577f ei t5 +[0-9a-f]+ <[^>]+> 23c0 577f ei fp +[0-9a-f]+ <[^>]+> 23e0 577f ei ra +[0-9a-f]+ <[^>]+> 2000 f37f eret +[0-9a-f]+ <[^>]+> 8043 f385 ext t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 f7c0 ext t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 f01f ext t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe f01f ext ra,fp,31,1 +[0-9a-f]+ <[^>]+> 8043 e4c5 ins t4,t5,5,15 +[0-9a-f]+ <[^>]+> 8043 e7c0 ins t4,t5,0,32 +[0-9a-f]+ <[^>]+> 8043 e7df ins t4,t5,31,1 +[0-9a-f]+ <[^>]+> 83fe e7df ins ra,fp,31,1 +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4800 1000 jrc.hb zero +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 4803 1000 jrc.hb t5 +[0-9a-f]+ <[^>]+> 4804 1000 jrc.hb a0 +[0-9a-f]+ <[^>]+> 4805 1000 jrc.hb a1 +[0-9a-f]+ <[^>]+> 4806 1000 jrc.hb a2 +[0-9a-f]+ <[^>]+> 4807 1000 jrc.hb a3 +[0-9a-f]+ <[^>]+> 4808 1000 jrc.hb a4 +[0-9a-f]+ <[^>]+> 481e 1000 jrc.hb fp +[0-9a-f]+ <[^>]+> 481f 1000 jrc.hb ra +[0-9a-f]+ <[^>]+> 4800 0000 jrc zero +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4803 0000 jrc t5 +[0-9a-f]+ <[^>]+> 4804 0000 jrc a0 +[0-9a-f]+ <[^>]+> 4805 0000 jrc a1 +[0-9a-f]+ <[^>]+> 4806 0000 jrc a2 +[0-9a-f]+ <[^>]+> 4807 0000 jrc a3 +[0-9a-f]+ <[^>]+> 4808 0000 jrc a4 +[0-9a-f]+ <[^>]+> 481e 0000 jrc fp +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> 4be0 0000 jalrc zero +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4be4 0000 jalrc a0 +[0-9a-f]+ <[^>]+> 4be5 0000 jalrc a1 +[0-9a-f]+ <[^>]+> 4be6 0000 jalrc a2 +[0-9a-f]+ <[^>]+> 4be7 0000 jalrc a3 +[0-9a-f]+ <[^>]+> 4be8 0000 jalrc a4 +[0-9a-f]+ <[^>]+> 4bfe 0000 jalrc fp +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> 4840 0000 jalrc t4,zero +[0-9a-f]+ <[^>]+> 4862 0000 jalrc t5,t4 +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4844 0000 jalrc t4,a0 +[0-9a-f]+ <[^>]+> 4845 0000 jalrc t4,a1 +[0-9a-f]+ <[^>]+> 4846 0000 jalrc t4,a2 +[0-9a-f]+ <[^>]+> 4847 0000 jalrc t4,a3 +[0-9a-f]+ <[^>]+> 4848 0000 jalrc t4,a4 +[0-9a-f]+ <[^>]+> 485e 0000 jalrc t4,fp +[0-9a-f]+ <[^>]+> 485f 0000 jalrc t4,ra +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4be0 1000 jalrc.hb zero +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4be3 1000 jalrc.hb t5 +[0-9a-f]+ <[^>]+> 4be4 1000 jalrc.hb a0 +[0-9a-f]+ <[^>]+> 4be5 1000 jalrc.hb a1 +[0-9a-f]+ <[^>]+> 4be6 1000 jalrc.hb a2 +[0-9a-f]+ <[^>]+> 4be7 1000 jalrc.hb a3 +[0-9a-f]+ <[^>]+> 4be8 1000 jalrc.hb a4 +[0-9a-f]+ <[^>]+> 4bfe 1000 jalrc.hb fp +[0-9a-f]+ <[^>]+> 4bdf 1000 jalrc.hb fp,ra +[0-9a-f]+ <[^>]+> 4840 1000 jalrc.hb t4,zero +[0-9a-f]+ <[^>]+> 4862 1000 jalrc.hb t5,t4 +[0-9a-f]+ <[^>]+> 4843 1000 jalrc.hb t4,t5 +[0-9a-f]+ <[^>]+> 4844 1000 jalrc.hb t4,a0 +[0-9a-f]+ <[^>]+> 4845 1000 jalrc.hb t4,a1 +[0-9a-f]+ <[^>]+> 4846 1000 jalrc.hb t4,a2 +[0-9a-f]+ <[^>]+> 4847 1000 jalrc.hb t4,a3 +[0-9a-f]+ <[^>]+> 4848 1000 jalrc.hb t4,a4 +[0-9a-f]+ <[^>]+> 485e 1000 jalrc.hb t4,fp +[0-9a-f]+ <[^>]+> 485f 1000 jalrc.hb t4,ra +[0-9a-f]+ <[^>]+> 4843 0000 jalrc t4,t5 +[0-9a-f]+ <[^>]+> 4bdf 0000 jalrc fp,ra +[0-9a-f]+ <[^>]+> 4be3 0000 jalrc t5 +[0-9a-f]+ <[^>]+> 4bff 0000 jalrc ra +[0-9a-f]+ <[^>]+> 2a00 0000 balc 00000000 + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 test2 +[0-9a-f]+ <[^>]+> e040 0000 lui t4,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 test +[0-9a-f]+ <[^>]+> 8042 0000 ori t4,t4,0x0 + [0-9a-f]+: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 0000 lb t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 0004 lb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 80ff lb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 0000 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 0000 lb s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 0004 lb t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0001 lb t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0000 lb t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 80ff lb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 0678 lb t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a443 90ff lbu t4,-1\(t5\) +[0-9a-f]+ <[^>]+> 8653 2000 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 2000 lbu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 2001 lbu s2,1\(s3\) +[0-9a-f]+ <[^>]+> 8653 2002 lbu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 8653 2003 lbu s2,3\(s3\) +[0-9a-f]+ <[^>]+> 8443 2004 lbu t4,4\(t5\) +[0-9a-f]+ <[^>]+> 8443 2005 lbu t4,5\(t5\) +[0-9a-f]+ <[^>]+> 8443 2006 lbu t4,6\(t5\) +[0-9a-f]+ <[^>]+> 8443 2007 lbu t4,7\(t5\) +[0-9a-f]+ <[^>]+> 8443 2008 lbu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 2009 lbu t4,9\(t5\) +[0-9a-f]+ <[^>]+> 8443 200a lbu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 200b lbu t4,11\(t5\) +[0-9a-f]+ <[^>]+> 8443 200c lbu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 200d lbu t4,13\(t5\) +[0-9a-f]+ <[^>]+> 8443 200e lbu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8442 200e lbu t4,14\(t4\) +[0-9a-f]+ <[^>]+> 8444 200e lbu t4,14\(a0\) +[0-9a-f]+ <[^>]+> 8445 200e lbu t4,14\(a1\) +[0-9a-f]+ <[^>]+> 8446 200e lbu t4,14\(a2\) +[0-9a-f]+ <[^>]+> 8447 200e lbu t4,14\(a3\) +[0-9a-f]+ <[^>]+> 8450 200e lbu t4,14\(s0\) +[0-9a-f]+ <[^>]+> 8451 200e lbu t4,14\(s1\) +[0-9a-f]+ <[^>]+> 8471 200e lbu t5,14\(s1\) +[0-9a-f]+ <[^>]+> 8491 200e lbu a0,14\(s1\) +[0-9a-f]+ <[^>]+> 84b1 200e lbu a1,14\(s1\) +[0-9a-f]+ <[^>]+> 84d1 200e lbu a2,14\(s1\) +[0-9a-f]+ <[^>]+> 84f1 200e lbu a3,14\(s1\) +[0-9a-f]+ <[^>]+> 8611 200e lbu s0,14\(s1\) +[0-9a-f]+ <[^>]+> 8631 200e lbu s1,14\(s1\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 2000 lbu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 2004 lbu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 90ff lbu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 2000 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 2000 lbu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 2004 lbu t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2001 lbu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2000 lbu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 90ff lbu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 2678 lbu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 4000 lh t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 4004 lh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 a0ff lh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 4000 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 4000 lh s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 4004 lh s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4001 lh t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4000 lh t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 a0ff lh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 4678 lh t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8653 6000 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 6000 lhu s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 6002 lhu s2,2\(s3\) +[0-9a-f]+ <[^>]+> 8653 6004 lhu s2,4\(s3\) +[0-9a-f]+ <[^>]+> 8653 6006 lhu s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 6008 lhu t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 600a lhu t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 600c lhu t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 600e lhu t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 6010 lhu t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 6012 lhu t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 6014 lhu t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 6016 lhu t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 6018 lhu t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 601a lhu t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 601c lhu t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 601e lhu t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 601e lhu t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 601e lhu t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 601e lhu t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 601e lhu t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 601e lhu t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 601e lhu t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 601e lhu t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 601e lhu t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 601e lhu a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 601e lhu a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 601e lhu a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 601e lhu a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8611 601e lhu s0,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 601e lhu s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 6000 lhu t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 6004 lhu t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 b0ff lhu t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 6000 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 6000 lhu s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 6004 lhu s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6001 lhu t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6000 lhu t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 b0ff lhu t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 6678 lhu t5,1656\(t5\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5100 ll t5,0\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5104 ll t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8060 8001 li t5,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8063 0678 ori t5,t5,0x678 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5100 ll t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5104 ll t5,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5104 ll t5,4\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> 8064 8001 addiu t5,a0,-1 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8063 0678 ori t5,t5,0x678 +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> a463 5100 ll t5,0\(t5\) +[0-9a-f]+ <[^>]+> e060 0000 lui t5,0x0 +[0-9a-f]+ <[^>]+> e07f 0ffc lui t5,%hi\(0x7fff0000\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8644 8000 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 8000 lw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 8004 lw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 8644 8008 lw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 8644 800c lw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 8644 8010 lw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 8644 8014 lw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 8644 8018 lw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 8644 801c lw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 8644 8020 lw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 8644 8024 lw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 8644 8028 lw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 8644 802c lw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 8644 8030 lw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 8644 8034 lw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 8644 8038 lw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 8644 803c lw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 8645 803c lw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 8646 803c lw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 8647 803c lw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 8652 803c lw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 8653 803c lw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 8650 803c lw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 8651 803c lw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 8671 803c lw s3,60\(s1\) +[0-9a-f]+ <[^>]+> 8491 803c lw a0,60\(s1\) +[0-9a-f]+ <[^>]+> 84b1 803c lw a1,60\(s1\) +[0-9a-f]+ <[^>]+> 84d1 803c lw a2,60\(s1\) +[0-9a-f]+ <[^>]+> 84f1 803c lw a3,60\(s1\) +[0-9a-f]+ <[^>]+> 8611 803c lw s0,60\(s1\) +[0-9a-f]+ <[^>]+> 8631 803c lw s1,60\(s1\) +[0-9a-f]+ <[^>]+> 849d 8000 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 849d 8000 lw a0,0\(sp\) +[0-9a-f]+ <[^>]+> 849d 8004 lw a0,4\(sp\) +[0-9a-f]+ <[^>]+> 849d 8008 lw a0,8\(sp\) +[0-9a-f]+ <[^>]+> 849d 800c lw a0,12\(sp\) +[0-9a-f]+ <[^>]+> 849d 8010 lw a0,16\(sp\) +[0-9a-f]+ <[^>]+> 849d 8014 lw a0,20\(sp\) +[0-9a-f]+ <[^>]+> 849d 807c lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 845d 807c lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 845d 807c lw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 847d 807c lw t5,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 807c lw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 84bd 807c lw a1,124\(sp\) +[0-9a-f]+ <[^>]+> 84dd 807c lw a2,124\(sp\) +[0-9a-f]+ <[^>]+> 84fd 807c lw a3,124\(sp\) +[0-9a-f]+ <[^>]+> 851d 807c lw a4,124\(sp\) +[0-9a-f]+ <[^>]+> 853d 807c lw a5,124\(sp\) +[0-9a-f]+ <[^>]+> 855d 807c lw a6,124\(sp\) +[0-9a-f]+ <[^>]+> 87dd 807c lw fp,124\(sp\) +[0-9a-f]+ <[^>]+> 87fd 807c lw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 81f8 lw a0,504\(sp\) +[0-9a-f]+ <[^>]+> 849d 81fc lw a0,508\(sp\) +[0-9a-f]+ <[^>]+> 861d 81fc lw s0,508\(sp\) +[0-9a-f]+ <[^>]+> 863d 81fc lw s1,508\(sp\) +[0-9a-f]+ <[^>]+> 865d 81fc lw s2,508\(sp\) +[0-9a-f]+ <[^>]+> 867d 81fc lw s3,508\(sp\) +[0-9a-f]+ <[^>]+> 869d 81fc lw s4,508\(sp\) +[0-9a-f]+ <[^>]+> 86bd 81fc lw s5,508\(sp\) +[0-9a-f]+ <[^>]+> 87fd 81fc lw ra,508\(sp\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8000 lw t5,0\(zero\) +[0-9a-f]+ <[^>]+> 8460 8004 lw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0060 7fff li t5,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0060 ffff li t5,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a460 c0ff lw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 8664 8000 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 8000 lw s3,0\(a0\) +[0-9a-f]+ <[^>]+> 8664 8004 lw s3,4\(a0\) +[0-9a-f]+ <[^>]+> 0064 7fff addiu t5,a0,32767 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> 0064 ffff addiu t5,a0,65535 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> e07f 0ffd lui t5,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e07f 8ffd lui t5,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8001 lw t5,1\(t5\) +[0-9a-f]+ <[^>]+> e060 0e01 lui t5,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8000 lw t5,0\(t5\) +[0-9a-f]+ <[^>]+> a464 c0ff lw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e074 5244 lui t5,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2083 1950 addu t5,t5,a0 +[0-9a-f]+ <[^>]+> 8463 8678 lw t5,1656\(t5\) +[0-9a-f]+ <[^>]+> 20a4 9c47 lwxs s3,a0\(a1\) +[0-9a-f]+ <[^>]+> 2040 0030 mfc0 t4,index +[0-9a-f]+ <[^>]+> 2041 0030 mfc0 t4,random +[0-9a-f]+ <[^>]+> 2042 0830 mfc0 t4,tcstatus +[0-9a-f]+ <[^>]+> 2042 1030 mfc0 t4,tcbind +[0-9a-f]+ <[^>]+> 2043 0070 mtc0 t4,entrylo1 +[0-9a-f]+ <[^>]+> 2044 0070 mtc0 t4,context +[0-9a-f]+ <[^>]+> 2045 3070 mtc0 t4,pwfield +[0-9a-f]+ <[^>]+> 2045 3870 mtc0 t4,pwsize +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1610 movn t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1610 movn t4,t5,a0 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2062 1210 movz t4,t4,t5 +[0-9a-f]+ <[^>]+> 2083 1210 movz t4,t5,a0 +[0-9a-f]+ <[^>]+> 2083 1018 mul t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e818 mul sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1018 mul t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1018 mul t4,t4,at +[0-9a-f]+ <[^>]+> 2060 1190 neg t4,t5 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2040 1190 neg t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2012 92d0 not s2,s2 +[0-9a-f]+ <[^>]+> 2012 92d0 not s2,s2 +[0-9a-f]+ <[^>]+> 2013 92d0 not s2,s3 +[0-9a-f]+ <[^>]+> 2004 92d0 not s2,a0 +[0-9a-f]+ <[^>]+> 2005 92d0 not s2,a1 +[0-9a-f]+ <[^>]+> 2006 92d0 not s2,a2 +[0-9a-f]+ <[^>]+> 2007 92d0 not s2,a3 +[0-9a-f]+ <[^>]+> 2010 92d0 not s2,s0 +[0-9a-f]+ <[^>]+> 2011 92d0 not s2,s1 +[0-9a-f]+ <[^>]+> 2011 9ad0 not s3,s1 +[0-9a-f]+ <[^>]+> 2011 22d0 not a0,s1 +[0-9a-f]+ <[^>]+> 2011 2ad0 not a1,s1 +[0-9a-f]+ <[^>]+> 2011 32d0 not a2,s1 +[0-9a-f]+ <[^>]+> 2011 3ad0 not a3,s1 +[0-9a-f]+ <[^>]+> 2011 82d0 not s0,s1 +[0-9a-f]+ <[^>]+> 2011 8ad0 not s1,s1 +[0-9a-f]+ <[^>]+> 2007 12d0 not t4,a3 +[0-9a-f]+ <[^>]+> 20e0 12d0 nor t4,zero,a3 +[0-9a-f]+ <[^>]+> 2083 12d0 nor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ead0 nor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 12d0 nor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 12d0 nor t4,t5,at +[0-9a-f]+ <[^>]+> 2016 1290 move t4,s6 +[0-9a-f]+ <[^>]+> 2002 b290 move s6,t4 +[0-9a-f]+ <[^>]+> 22c0 1290 or t4,zero,s6 +[0-9a-f]+ <[^>]+> 2040 b290 or s6,zero,t4 +[0-9a-f]+ <[^>]+> 2252 9290 or s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9290 or s2,s2,s3 +[0-9a-f]+ <[^>]+> 2092 9290 or s2,s2,a0 +[0-9a-f]+ <[^>]+> 20b2 9290 or s2,s2,a1 +[0-9a-f]+ <[^>]+> 20d2 9290 or s2,s2,a2 +[0-9a-f]+ <[^>]+> 20f2 9290 or s2,s2,a3 +[0-9a-f]+ <[^>]+> 2212 9290 or s2,s2,s0 +[0-9a-f]+ <[^>]+> 2232 9290 or s2,s2,s1 +[0-9a-f]+ <[^>]+> 2253 9a90 or s3,s3,s2 +[0-9a-f]+ <[^>]+> 2244 2290 or a0,a0,s2 +[0-9a-f]+ <[^>]+> 2245 2a90 or a1,a1,s2 +[0-9a-f]+ <[^>]+> 2246 3290 or a2,a2,s2 +[0-9a-f]+ <[^>]+> 2247 3a90 or a3,a3,s2 +[0-9a-f]+ <[^>]+> 2250 8290 or s0,s0,s2 +[0-9a-f]+ <[^>]+> 2251 8a90 or s1,s1,s2 +[0-9a-f]+ <[^>]+> 2252 9290 or s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9290 or s2,s2,s3 +[0-9a-f]+ <[^>]+> 2253 9290 or s2,s3,s2 +[0-9a-f]+ <[^>]+> 2083 1290 or t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe ea90 or sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1290 or t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8043 0fff ori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1290 or t4,t5,at +[0-9a-f]+ <[^>]+> 8064 0000 ori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8064 0fff ori t5,a0,0xfff +[0-9a-f]+ <[^>]+> 2040 01c0 rdhwr t4,hwr_cpunum +[0-9a-f]+ <[^>]+> 2041 01c0 rdhwr t4,hwr_synci_step +[0-9a-f]+ <[^>]+> 2042 01c0 rdhwr t4,hwr_cc +[0-9a-f]+ <[^>]+> 2043 01c0 rdhwr t4,hwr_ccres +[0-9a-f]+ <[^>]+> 2044 01c0 rdhwr t4,hwr_perfcnt +[0-9a-f]+ <[^>]+> 2045 01c0 rdhwr t4,hwr_xnp +[0-9a-f]+ <[^>]+> 2046 01c0 rdhwr t4,\$6 +[0-9a-f]+ <[^>]+> 2047 01c0 rdhwr t4,\$7 +[0-9a-f]+ <[^>]+> 2048 01c0 rdhwr t4,\$8 +[0-9a-f]+ <[^>]+> 2049 01c0 rdhwr t4,\$9 +[0-9a-f]+ <[^>]+> 204a 01c0 rdhwr t4,\$10 +[0-9a-f]+ <[^>]+> 2043 e17f rdpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2042 e17f rdpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2062 0158 mod zero,t4,t5 +[0-9a-f]+ <[^>]+> 23fe 0158 mod zero,fp,ra +[0-9a-f]+ <[^>]+> 2060 0158 mod zero,zero,t5 +[0-9a-f]+ <[^>]+> 23e0 0158 mod zero,zero,ra +[0-9a-f]+ <[^>]+> 2003 1158 mod t4,t5,zero +[0-9a-f]+ <[^>]+> 2083 1158 mod t4,t5,a0 +[0-9a-f]+ <[^>]+> 0010 0007 break 0x7 +[0-9a-f]+ <[^>]+> 2000 1a90 move t5,zero +[0-9a-f]+ <[^>]+> 2000 1a90 move t5,zero +[0-9a-f]+ <[^>]+> 0020 0002 li at,2 +[0-9a-f]+ <[^>]+> 2024 1958 mod t5,a0,at +[0-9a-f]+ <[^>]+> 2080 11d0 negu t4,a0 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2080 09d0 negu at,a0 +[0-9a-f]+ <[^>]+> 2022 10d0 rotrv t4,t4,at +[0-9a-f]+ <[^>]+> 2060 11d0 negu t4,t5 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 2040 11d0 negu t4,t4 +[0-9a-f]+ <[^>]+> 2043 10d0 rotrv t4,t5,t4 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8042 c0c1 rotr t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 c0c0 rotr t4,t5,0 +[0-9a-f]+ <[^>]+> 8043 c0c1 rotr t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 c0df rotr t4,t5,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c0df rotr t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2083 10d0 rotrv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 10d0 rotrv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8413 1000 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 8413 1000 sb zero,0\(s3\) +[0-9a-f]+ <[^>]+> 8413 1001 sb zero,1\(s3\) +[0-9a-f]+ <[^>]+> 8413 1002 sb zero,2\(s3\) +[0-9a-f]+ <[^>]+> 8413 1003 sb zero,3\(s3\) +[0-9a-f]+ <[^>]+> 8403 1004 sb zero,4\(t5\) +[0-9a-f]+ <[^>]+> 8403 1005 sb zero,5\(t5\) +[0-9a-f]+ <[^>]+> 8403 1006 sb zero,6\(t5\) +[0-9a-f]+ <[^>]+> 8403 1007 sb zero,7\(t5\) +[0-9a-f]+ <[^>]+> 8403 1008 sb zero,8\(t5\) +[0-9a-f]+ <[^>]+> 8403 1009 sb zero,9\(t5\) +[0-9a-f]+ <[^>]+> 8403 100a sb zero,10\(t5\) +[0-9a-f]+ <[^>]+> 8403 100b sb zero,11\(t5\) +[0-9a-f]+ <[^>]+> 8403 100c sb zero,12\(t5\) +[0-9a-f]+ <[^>]+> 8403 100d sb zero,13\(t5\) +[0-9a-f]+ <[^>]+> 8403 100e sb zero,14\(t5\) +[0-9a-f]+ <[^>]+> 8403 100f sb zero,15\(t5\) +[0-9a-f]+ <[^>]+> 8443 100f sb t4,15\(t5\) +[0-9a-f]+ <[^>]+> 8463 100f sb t5,15\(t5\) +[0-9a-f]+ <[^>]+> 8483 100f sb a0,15\(t5\) +[0-9a-f]+ <[^>]+> 84a3 100f sb a1,15\(t5\) +[0-9a-f]+ <[^>]+> 84c3 100f sb a2,15\(t5\) +[0-9a-f]+ <[^>]+> 84e3 100f sb a3,15\(t5\) +[0-9a-f]+ <[^>]+> 8623 100f sb s1,15\(t5\) +[0-9a-f]+ <[^>]+> 8624 100f sb s1,15\(a0\) +[0-9a-f]+ <[^>]+> 8625 100f sb s1,15\(a1\) +[0-9a-f]+ <[^>]+> 8626 100f sb s1,15\(a2\) +[0-9a-f]+ <[^>]+> 8627 100f sb s1,15\(a3\) +[0-9a-f]+ <[^>]+> 8622 100f sb s1,15\(t4\) +[0-9a-f]+ <[^>]+> 8630 100f sb s1,15\(s0\) +[0-9a-f]+ <[^>]+> 8631 100f sb s1,15\(s1\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1004 sb t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 1fff sb t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 88ff sb t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1000 sb t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 1fff sb t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1001 sb t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1000 sb t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 88ff sb t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 1678 sb t5,1656\(at\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> a460 5904 sc t5,4\(zero\) +[0-9a-f]+ <[^>]+> 0020 07ff li at,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8800 li at,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8020 8001 li at,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8021 0678 ori at,at,0x678 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> a464 5900 sc t5,0\(a0\) +[0-9a-f]+ <[^>]+> 0024 07ff addiu at,a0,2047 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8800 addiu at,a0,-2048 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 7fff addiu at,a0,32767 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5904 sc t5,4\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 8024 8001 addiu at,a0,-1 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8021 0678 ori at,at,0x678 +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> a461 5900 sc t5,0\(at\) +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0001 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 0018 0002 sdbbp 0x2 +[0-9a-f]+ <[^>]+> 0018 0003 sdbbp 0x3 +[0-9a-f]+ <[^>]+> 0018 0004 sdbbp 0x4 +[0-9a-f]+ <[^>]+> 0018 0005 sdbbp 0x5 +[0-9a-f]+ <[^>]+> 0018 0006 sdbbp 0x6 +[0-9a-f]+ <[^>]+> 0018 0007 sdbbp 0x7 +[0-9a-f]+ <[^>]+> 0018 0008 sdbbp 0x8 +[0-9a-f]+ <[^>]+> 0018 0009 sdbbp 0x9 +[0-9a-f]+ <[^>]+> 0018 000a sdbbp 0xa +[0-9a-f]+ <[^>]+> 0018 000b sdbbp 0xb +[0-9a-f]+ <[^>]+> 0018 000c sdbbp 0xc +[0-9a-f]+ <[^>]+> 0018 000d sdbbp 0xd +[0-9a-f]+ <[^>]+> 0018 000e sdbbp 0xe +[0-9a-f]+ <[^>]+> 0018 000f sdbbp 0xf +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0000 sdbbp +[0-9a-f]+ <[^>]+> 0018 0001 sdbbp 0x1 +[0-9a-f]+ <[^>]+> 0018 0002 sdbbp 0x2 +[0-9a-f]+ <[^>]+> 0018 00ff sdbbp 0xff +[0-9a-f]+ <[^>]+> 2043 0008 seb t4,t5 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2042 0008 seb t4,t4 +[0-9a-f]+ <[^>]+> 2043 0048 seh t4,t5 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2042 0048 seh t4,t4 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8044 5001 sltiu t4,a0,1 +[0-9a-f]+ <[^>]+> 8043 5001 sltiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8043 6001 seqi t4,t5,1 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 8042 5001 sltiu t4,t4,1 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8653 5000 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 5000 sh s2,0\(s3\) +[0-9a-f]+ <[^>]+> 8653 5002 sh s2,2\(s3\) +[0-9a-f]+ <[^>]+> 8653 5004 sh s2,4\(s3\) +[0-9a-f]+ <[^>]+> 8653 5006 sh s2,6\(s3\) +[0-9a-f]+ <[^>]+> 8443 5008 sh t4,8\(t5\) +[0-9a-f]+ <[^>]+> 8443 500a sh t4,10\(t5\) +[0-9a-f]+ <[^>]+> 8443 500c sh t4,12\(t5\) +[0-9a-f]+ <[^>]+> 8443 500e sh t4,14\(t5\) +[0-9a-f]+ <[^>]+> 8443 5010 sh t4,16\(t5\) +[0-9a-f]+ <[^>]+> 8443 5012 sh t4,18\(t5\) +[0-9a-f]+ <[^>]+> 8443 5014 sh t4,20\(t5\) +[0-9a-f]+ <[^>]+> 8443 5016 sh t4,22\(t5\) +[0-9a-f]+ <[^>]+> 8443 5018 sh t4,24\(t5\) +[0-9a-f]+ <[^>]+> 8443 501a sh t4,26\(t5\) +[0-9a-f]+ <[^>]+> 8443 501c sh t4,28\(t5\) +[0-9a-f]+ <[^>]+> 8443 501e sh t4,30\(t5\) +[0-9a-f]+ <[^>]+> 8444 501e sh t4,30\(a0\) +[0-9a-f]+ <[^>]+> 8445 501e sh t4,30\(a1\) +[0-9a-f]+ <[^>]+> 8446 501e sh t4,30\(a2\) +[0-9a-f]+ <[^>]+> 8447 501e sh t4,30\(a3\) +[0-9a-f]+ <[^>]+> 8442 501e sh t4,30\(t4\) +[0-9a-f]+ <[^>]+> 8450 501e sh t4,30\(s0\) +[0-9a-f]+ <[^>]+> 8451 501e sh t4,30\(s1\) +[0-9a-f]+ <[^>]+> 8471 501e sh t5,30\(s1\) +[0-9a-f]+ <[^>]+> 8491 501e sh a0,30\(s1\) +[0-9a-f]+ <[^>]+> 84b1 501e sh a1,30\(s1\) +[0-9a-f]+ <[^>]+> 84d1 501e sh a2,30\(s1\) +[0-9a-f]+ <[^>]+> 84f1 501e sh a3,30\(s1\) +[0-9a-f]+ <[^>]+> 8631 501e sh s1,30\(s1\) +[0-9a-f]+ <[^>]+> 8411 501e sh zero,30\(s1\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5004 sh t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 5fff sh t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 a8ff sh t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5000 sh t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 5fff sh t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5001 sh t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5000 sh t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 a8ff sh t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 5678 sh t5,1656\(at\) +[0-9a-f]+ <[^>]+> 2064 1350 slt t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1350 slt t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1350 slt t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2064 1390 sltu t4,a0,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 2044 1390 sltu t4,a0,t4 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2061 1390 sltu t4,at,t5 +[0-9a-f]+ <[^>]+> 8042 1001 xori t4,t4,0x1 +[0-9a-f]+ <[^>]+> 8252 c001 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 8252 c002 sll s2,s2,2 +[0-9a-f]+ <[^>]+> 8252 c003 sll s2,s2,3 +[0-9a-f]+ <[^>]+> 8252 c004 sll s2,s2,4 +[0-9a-f]+ <[^>]+> 8252 c005 sll s2,s2,5 +[0-9a-f]+ <[^>]+> 8252 c006 sll s2,s2,6 +[0-9a-f]+ <[^>]+> 8252 c007 sll s2,s2,7 +[0-9a-f]+ <[^>]+> 8252 c008 sll s2,s2,8 +[0-9a-f]+ <[^>]+> 8253 c008 sll s2,s3,8 +[0-9a-f]+ <[^>]+> 8244 c008 sll s2,a0,8 +[0-9a-f]+ <[^>]+> 8245 c008 sll s2,a1,8 +[0-9a-f]+ <[^>]+> 8246 c008 sll s2,a2,8 +[0-9a-f]+ <[^>]+> 8247 c008 sll s2,a3,8 +[0-9a-f]+ <[^>]+> 8250 c008 sll s2,s0,8 +[0-9a-f]+ <[^>]+> 8251 c008 sll s2,s1,8 +[0-9a-f]+ <[^>]+> 8272 c008 sll s3,s2,8 +[0-9a-f]+ <[^>]+> 8092 c008 sll a0,s2,8 +[0-9a-f]+ <[^>]+> 80b2 c008 sll a1,s2,8 +[0-9a-f]+ <[^>]+> 80d2 c008 sll a2,s2,8 +[0-9a-f]+ <[^>]+> 80f2 c008 sll a3,s2,8 +[0-9a-f]+ <[^>]+> 8212 c008 sll s0,s2,8 +[0-9a-f]+ <[^>]+> 8232 c008 sll s1,s2,8 +[0-9a-f]+ <[^>]+> 8252 c001 sll s2,s2,1 +[0-9a-f]+ <[^>]+> 8273 c001 sll s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1010 sllv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1010 sllv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c000 sll t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c001 sll t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c01f sll t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c01f sll t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1350 slt t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1350 slt t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8043 4000 slti t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1350 slt t4,t5,at +[0-9a-f]+ <[^>]+> 8064 4000 slti t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 4fff slti t5,a0,4095 +[0-9a-f]+ <[^>]+> 8064 5000 sltiu t5,a0,0 +[0-9a-f]+ <[^>]+> 8064 5fff sltiu t5,a0,4095 +[0-9a-f]+ <[^>]+> 2083 1390 sltu t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1390 sltu t4,t4,a0 +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 8043 5000 sltiu t4,t5,0 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> e021 0000 lui at,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1390 sltu t4,t5,at +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2080 1390 sltu t4,zero,a0 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 2060 1390 sltu t4,zero,t5 +[0-9a-f]+ <[^>]+> 8043 1001 xori t4,t5,0x1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 0001 addiu t4,t5,1 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 0043 8001 addiu t4,t5,32769 +[0-9a-f]+ <[^>]+> 2040 1390 sltu t4,zero,t4 +[0-9a-f]+ <[^>]+> 2083 1090 srav t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1090 srav t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c080 sra t4,a0,0 +[0-9a-f]+ <[^>]+> 8044 c081 sra t4,a0,1 +[0-9a-f]+ <[^>]+> 8044 c09f sra t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c09f sra t4,t4,31 +[0-9a-f]+ <[^>]+> 2083 1050 srlv t4,t5,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1050 srlv t4,t4,a0 +[0-9a-f]+ <[^>]+> 8044 c040 srl t4,a0,0 +[0-9a-f]+ <[^>]+> 8244 c041 srl s2,a0,1 +[0-9a-f]+ <[^>]+> 8044 c05f srl t4,a0,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 8042 c05f srl t4,t4,31 +[0-9a-f]+ <[^>]+> 8252 c041 srl s2,s2,1 +[0-9a-f]+ <[^>]+> 8252 c042 srl s2,s2,2 +[0-9a-f]+ <[^>]+> 8252 c043 srl s2,s2,3 +[0-9a-f]+ <[^>]+> 8252 c044 srl s2,s2,4 +[0-9a-f]+ <[^>]+> 8252 c045 srl s2,s2,5 +[0-9a-f]+ <[^>]+> 8252 c046 srl s2,s2,6 +[0-9a-f]+ <[^>]+> 8252 c047 srl s2,s2,7 +[0-9a-f]+ <[^>]+> 8252 c048 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 8253 c048 srl s2,s3,8 +[0-9a-f]+ <[^>]+> 8244 c048 srl s2,a0,8 +[0-9a-f]+ <[^>]+> 8245 c048 srl s2,a1,8 +[0-9a-f]+ <[^>]+> 8246 c048 srl s2,a2,8 +[0-9a-f]+ <[^>]+> 8247 c048 srl s2,a3,8 +[0-9a-f]+ <[^>]+> 8250 c048 srl s2,s0,8 +[0-9a-f]+ <[^>]+> 8251 c048 srl s2,s1,8 +[0-9a-f]+ <[^>]+> 8252 c048 srl s2,s2,8 +[0-9a-f]+ <[^>]+> 8272 c048 srl s3,s2,8 +[0-9a-f]+ <[^>]+> 8092 c048 srl a0,s2,8 +[0-9a-f]+ <[^>]+> 80b2 c048 srl a1,s2,8 +[0-9a-f]+ <[^>]+> 80d2 c048 srl a2,s2,8 +[0-9a-f]+ <[^>]+> 80f2 c048 srl a3,s2,8 +[0-9a-f]+ <[^>]+> 8212 c048 srl s0,s2,8 +[0-9a-f]+ <[^>]+> 8232 c048 srl s1,s2,8 +[0-9a-f]+ <[^>]+> 8273 c041 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 8273 c041 srl s3,s3,1 +[0-9a-f]+ <[^>]+> 2083 1190 sub t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e990 sub sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1190 sub t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 0000 li at,0 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 0001 li at,1 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 1190 sub t4,t4,at +[0-9a-f]+ <[^>]+> 2253 91d0 subu s2,s3,s2 +[0-9a-f]+ <[^>]+> 2273 91d0 subu s2,s3,s3 +[0-9a-f]+ <[^>]+> 2093 91d0 subu s2,s3,a0 +[0-9a-f]+ <[^>]+> 20b3 91d0 subu s2,s3,a1 +[0-9a-f]+ <[^>]+> 20d3 91d0 subu s2,s3,a2 +[0-9a-f]+ <[^>]+> 20f3 91d0 subu s2,s3,a3 +[0-9a-f]+ <[^>]+> 2213 91d0 subu s2,s3,s0 +[0-9a-f]+ <[^>]+> 2233 91d0 subu s2,s3,s1 +[0-9a-f]+ <[^>]+> 2232 91d0 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2224 91d0 subu s2,a0,s1 +[0-9a-f]+ <[^>]+> 2225 91d0 subu s2,a1,s1 +[0-9a-f]+ <[^>]+> 2226 91d0 subu s2,a2,s1 +[0-9a-f]+ <[^>]+> 2227 91d0 subu s2,a3,s1 +[0-9a-f]+ <[^>]+> 2230 91d0 subu s2,s0,s1 +[0-9a-f]+ <[^>]+> 2231 91d0 subu s2,s1,s1 +[0-9a-f]+ <[^>]+> 2232 91d0 subu s2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 99d0 subu s3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 21d0 subu a0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 29d0 subu a1,s2,s1 +[0-9a-f]+ <[^>]+> 2232 31d0 subu a2,s2,s1 +[0-9a-f]+ <[^>]+> 2232 39d0 subu a3,s2,s1 +[0-9a-f]+ <[^>]+> 2232 81d0 subu s0,s2,s1 +[0-9a-f]+ <[^>]+> 2232 89d0 subu s1,s2,s1 +[0-9a-f]+ <[^>]+> 2247 39d0 subu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2247 39d0 subu a3,a3,s2 +[0-9a-f]+ <[^>]+> 2083 11d0 subu t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe e9d0 subu sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 11d0 subu t4,t4,a0 +[0-9a-f]+ <[^>]+> 0042 0000 addiu t4,t4,0 +[0-9a-f]+ <[^>]+> 8042 8001 addiu t4,t4,-1 +[0-9a-f]+ <[^>]+> 0020 7fff li at,32767 +[0-9a-f]+ <[^>]+> 2022 11d0 subu t4,t4,at +[0-9a-f]+ <[^>]+> 0042 8000 addiu t4,t4,32768 +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 2022 11d0 subu t4,t4,at +[0-9a-f]+ <[^>]+> 8644 9000 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 9000 sw s2,0\(a0\) +[0-9a-f]+ <[^>]+> 8644 9004 sw s2,4\(a0\) +[0-9a-f]+ <[^>]+> 8644 9008 sw s2,8\(a0\) +[0-9a-f]+ <[^>]+> 8644 900c sw s2,12\(a0\) +[0-9a-f]+ <[^>]+> 8644 9010 sw s2,16\(a0\) +[0-9a-f]+ <[^>]+> 8644 9014 sw s2,20\(a0\) +[0-9a-f]+ <[^>]+> 8644 9018 sw s2,24\(a0\) +[0-9a-f]+ <[^>]+> 8644 901c sw s2,28\(a0\) +[0-9a-f]+ <[^>]+> 8644 9020 sw s2,32\(a0\) +[0-9a-f]+ <[^>]+> 8644 9024 sw s2,36\(a0\) +[0-9a-f]+ <[^>]+> 8644 9028 sw s2,40\(a0\) +[0-9a-f]+ <[^>]+> 8644 902c sw s2,44\(a0\) +[0-9a-f]+ <[^>]+> 8644 9030 sw s2,48\(a0\) +[0-9a-f]+ <[^>]+> 8644 9034 sw s2,52\(a0\) +[0-9a-f]+ <[^>]+> 8644 9038 sw s2,56\(a0\) +[0-9a-f]+ <[^>]+> 8644 903c sw s2,60\(a0\) +[0-9a-f]+ <[^>]+> 8645 903c sw s2,60\(a1\) +[0-9a-f]+ <[^>]+> 8646 903c sw s2,60\(a2\) +[0-9a-f]+ <[^>]+> 8647 903c sw s2,60\(a3\) +[0-9a-f]+ <[^>]+> 8650 903c sw s2,60\(s0\) +[0-9a-f]+ <[^>]+> 8651 903c sw s2,60\(s1\) +[0-9a-f]+ <[^>]+> 8652 903c sw s2,60\(s2\) +[0-9a-f]+ <[^>]+> 8653 903c sw s2,60\(s3\) +[0-9a-f]+ <[^>]+> 8673 903c sw s3,60\(s3\) +[0-9a-f]+ <[^>]+> 8493 903c sw a0,60\(s3\) +[0-9a-f]+ <[^>]+> 84b3 903c sw a1,60\(s3\) +[0-9a-f]+ <[^>]+> 84d3 903c sw a2,60\(s3\) +[0-9a-f]+ <[^>]+> 84f3 903c sw a3,60\(s3\) +[0-9a-f]+ <[^>]+> 8633 903c sw s1,60\(s3\) +[0-9a-f]+ <[^>]+> 8413 903c sw zero,60\(s3\) +[0-9a-f]+ <[^>]+> 841d 9000 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> 841d 9000 sw zero,0\(sp\) +[0-9a-f]+ <[^>]+> 841d 9004 sw zero,4\(sp\) +[0-9a-f]+ <[^>]+> 841d 9008 sw zero,8\(sp\) +[0-9a-f]+ <[^>]+> 841d 900c sw zero,12\(sp\) +[0-9a-f]+ <[^>]+> 841d 9010 sw zero,16\(sp\) +[0-9a-f]+ <[^>]+> 841d 9014 sw zero,20\(sp\) +[0-9a-f]+ <[^>]+> 841d 9078 sw zero,120\(sp\) +[0-9a-f]+ <[^>]+> 841d 907c sw zero,124\(sp\) +[0-9a-f]+ <[^>]+> 845d 907c sw t4,124\(sp\) +[0-9a-f]+ <[^>]+> 863d 907c sw s1,124\(sp\) +[0-9a-f]+ <[^>]+> 847d 907c sw t5,124\(sp\) +[0-9a-f]+ <[^>]+> 849d 907c sw a0,124\(sp\) +[0-9a-f]+ <[^>]+> 84bd 907c sw a1,124\(sp\) +[0-9a-f]+ <[^>]+> 84dd 907c sw a2,124\(sp\) +[0-9a-f]+ <[^>]+> 84fd 907c sw a3,124\(sp\) +[0-9a-f]+ <[^>]+> 87fd 907c sw ra,124\(sp\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9004 sw t5,4\(zero\) +[0-9a-f]+ <[^>]+> 8460 9fff sw t5,4095\(zero\) +[0-9a-f]+ <[^>]+> 0020 ffff li at,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a460 c8ff sw t5,-1\(zero\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9000 sw t5,0\(a0\) +[0-9a-f]+ <[^>]+> 8464 9fff sw t5,4095\(a0\) +[0-9a-f]+ <[^>]+> 0024 ffff addiu at,a0,65535 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> e03f 0ffd lui at,%hi\(0xffff0000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9001 sw t5,1\(at\) +[0-9a-f]+ <[^>]+> e020 0e01 lui at,%hi\(0xf0000000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9000 sw t5,0\(at\) +[0-9a-f]+ <[^>]+> a464 c8ff sw t5,-1\(a0\) +[0-9a-f]+ <[^>]+> e034 5244 lui at,%hi\(0x12345000\) +[0-9a-f]+ <[^>]+> 2081 0950 addu at,at,a0 +[0-9a-f]+ <[^>]+> 8461 9678 sw t5,1656\(at\) +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8000 c006 sync +[0-9a-f]+ <[^>]+> 8001 c006 sync 0x1 +[0-9a-f]+ <[^>]+> 8002 c006 sync 0x2 +[0-9a-f]+ <[^>]+> 8003 c006 sync 0x3 +[0-9a-f]+ <[^>]+> 8005 c006 sync 0x5 +[0-9a-f]+ <[^>]+> 801e c006 sync 0x1e +[0-9a-f]+ <[^>]+> 801f c006 sync 0x1f +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3000 synci 0\(zero\) +[0-9a-f]+ <[^>]+> 87e0 37ff synci 2047\(zero\) +[0-9a-f]+ <[^>]+> 87e0 3800 synci 2048\(zero\) +[0-9a-f]+ <[^>]+> 87e2 3000 synci 0\(t4\) +[0-9a-f]+ <[^>]+> 87e3 3000 synci 0\(t5\) +[0-9a-f]+ <[^>]+> 87e3 30ff synci 255\(t5\) +[0-9a-f]+ <[^>]+> a7e3 9800 synci -256\(t5\) +[0-9a-f]+ <[^>]+> 87e3 3800 synci 2048\(t5\) +[0-9a-f]+ <[^>]+> 0008 0000 syscall +[0-9a-f]+ <[^>]+> 0008 0000 syscall +[0-9a-f]+ <[^>]+> 0008 0001 syscall 0x1 +[0-9a-f]+ <[^>]+> 0008 0002 syscall 0x2 +[0-9a-f]+ <[^>]+> 0008 00ff syscall 0xff +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2000 c37f wait +[0-9a-f]+ <[^>]+> 2001 c37f wait 0x1 +[0-9a-f]+ <[^>]+> 20ff c37f wait 0xff +[0-9a-f]+ <[^>]+> 2043 f17f wrpgpr t4,t5 +[0-9a-f]+ <[^>]+> 2044 f17f wrpgpr t4,a0 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 2042 f17f wrpgpr t4,t4 +[0-9a-f]+ <[^>]+> 8043 d608 byterevh t4,t5 +[0-9a-f]+ <[^>]+> 8044 d608 byterevh t4,a0 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 8042 d608 byterevh t4,t4 +[0-9a-f]+ <[^>]+> 2252 9310 xor s2,s2,s2 +[0-9a-f]+ <[^>]+> 2272 9310 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2092 9310 xor s2,s2,a0 +[0-9a-f]+ <[^>]+> 20b2 9310 xor s2,s2,a1 +[0-9a-f]+ <[^>]+> 20d2 9310 xor s2,s2,a2 +[0-9a-f]+ <[^>]+> 20f2 9310 xor s2,s2,a3 +[0-9a-f]+ <[^>]+> 2212 9310 xor s2,s2,s0 +[0-9a-f]+ <[^>]+> 2232 9310 xor s2,s2,s1 +[0-9a-f]+ <[^>]+> 2233 9b10 xor s3,s3,s1 +[0-9a-f]+ <[^>]+> 2224 2310 xor a0,a0,s1 +[0-9a-f]+ <[^>]+> 2225 2b10 xor a1,a1,s1 +[0-9a-f]+ <[^>]+> 2226 3310 xor a2,a2,s1 +[0-9a-f]+ <[^>]+> 2227 3b10 xor a3,a3,s1 +[0-9a-f]+ <[^>]+> 2230 8310 xor s0,s0,s1 +[0-9a-f]+ <[^>]+> 2231 8b10 xor s1,s1,s1 +[0-9a-f]+ <[^>]+> 2272 9310 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2272 9310 xor s2,s2,s3 +[0-9a-f]+ <[^>]+> 2253 9310 xor s2,s3,s2 +[0-9a-f]+ <[^>]+> 2083 1310 xor t4,t5,a0 +[0-9a-f]+ <[^>]+> 23fe eb10 xor sp,fp,ra +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 2082 1310 xor t4,t4,a0 +[0-9a-f]+ <[^>]+> 0020 8000 li at,32768 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8043 1fff xori t4,t5,0xfff +[0-9a-f]+ <[^>]+> 0020 1000 li at,4096 +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 8ffd lui at,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> e03f 7ffd lui at,%hi\(0xffff7000\) +[0-9a-f]+ <[^>]+> 8021 0fff ori at,at,0xfff +[0-9a-f]+ <[^>]+> 2023 1310 xor t4,t5,at +[0-9a-f]+ <[^>]+> 8064 1000 xori t5,a0,0x0 +[0-9a-f]+ <[^>]+> 8063 1fff xori t5,t5,0xfff +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8949 0000 beqc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c920 0800 beqic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8940 8000 blezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 896a 8000 bgec a6,a7,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c948 1000 bgeic a6,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 c000 bgeuc t4,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8840 c000 bgeuc zero,t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8862 c000 bgeuc t4,t5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 0000 bnezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c84c 1000 bgeiuc t4,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8802 8000 bgezc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a840 8000 bgtzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a802 8000 bltzc t4,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8809 8000 bgezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c928 1000 bgeic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> e020 0001 lui at,%hi\(0x80000000\) +[0-9a-f]+ <[^>]+> 8021 0001 ori at,at,0x1 +[0-9a-f]+ <[^>]+> 2029 0b50 slt at,a5,at +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> a820 0000 bnezc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c92c 1000 bgeiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 8000 bgtzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 880a 8000 bgezc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b50 slt at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 212a 0b90 sltu at,a6,a5 +[0-9a-f]+ <[^>]+> 8820 0000 beqzc at,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 2800 0000 bc 00000000 <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC25_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 8000 bgtzc a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 8000 bltc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 8000 blezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c938 1000 bltic a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 c000 bltuc a5,zero,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a940 c000 bltuc zero,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 c000 bltuc a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 c000 nop +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8920 0000 beqzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c93c 1000 bltiuc a5,2,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a809 8000 bltzc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a949 0000 bnec a5,a6,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> a920 0000 bnezc a5,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC14_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> c930 0800 bneic a5,1,[0-9a-f]+ <[^>]+> + [0-9a-f]+: R_NANOMIPS_PC11_S1 test +[0-9a-f]+ <[^>]+> 20a4 9950 addu s3,a0,a1 +[0-9a-f]+ <[^>]+> 8000 3003 restore.jrc 0 +[0-9a-f]+ <[^>]+> 8000 300b restore.jrc 8 +[0-9a-f]+ <[^>]+> 8000 3013 restore.jrc 16 +[0-9a-f]+ <[^>]+> 8000 301b restore.jrc 24 +[0-9a-f]+ <[^>]+> 8000 3023 restore.jrc 32 +[0-9a-f]+ <[^>]+> 8000 302b restore.jrc 40 +[0-9a-f]+ <[^>]+> 03bd 0004 addiu sp,sp,4 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 000c addiu sp,sp,12 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0014 addiu sp,sp,20 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 001c addiu sp,sp,28 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 03bd 0024 addiu sp,sp,36 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 8000 307b restore.jrc 120 +[0-9a-f]+ <[^>]+> 03bd 007c addiu sp,sp,124 +[0-9a-f]+ <[^>]+> 481f 0000 jrc ra +[0-9a-f]+ <[^>]+> 0018 03ff sdbbp 0x3ff +[0-9a-f]+ <[^>]+> 23ff c37f wait 0x3ff +[0-9a-f]+ <[^>]+> 0008 03ff syscall 0x3ff +[0-9a-f]+ <[^>]+> 2a00 0000 balc [0-9a-f]+ + [0-9a-f]+: R_NANOMIPS_PC25_S1 test_delay_slot +[0-9a-f]+ <[^>]+> 4be2 0000 jalrc t4 +[0-9a-f]+ <[^>]+> 4802 0000 jrc t4 +[0-9a-f]+ <[^>]+> 4be2 1000 jalrc.hb t4 +[0-9a-f]+ <[^>]+> 4802 1000 jrc.hb t4 +[0-9a-f]+ <[^>]+> 4240 01fe lw s2,508\(gp\) +[0-9a-f]+ <[^>]+> 4260 01fe lw s3,508\(gp\) +[0-9a-f]+ <[^>]+> 4080 01fe lw a0,508\(gp\) +[0-9a-f]+ <[^>]+> 40a0 01fe lw a1,508\(gp\) +[0-9a-f]+ <[^>]+> 40c0 01fe lw a2,508\(gp\) +[0-9a-f]+ <[^>]+> 40e0 01fe lw a3,508\(gp\) +[0-9a-f]+ <[^>]+> 4200 01fe lw s0,508\(gp\) +[0-9a-f]+ <[^>]+> 4220 01fe lw s1,508\(gp\) +[0-9a-f]+ <[^>]+> 4220 01fa lw s1,504\(gp\) +[0-9a-f]+ <[^>]+> 4220 01f6 lw s1,500\(gp\) +[0-9a-f]+ <[^>]+> 4220 0002 lw s1,0\(gp\) +[0-9a-f]+ <[^>]+> 4220 0006 lw s1,4\(gp\) +[0-9a-f]+ <[^>]+> 4220 00fa lw s1,248\(gp\) +[0-9a-f]+ <[^>]+> 4220 00fe lw s1,252\(gp\) +[0-9a-f]+ <[^>]+> 4220 0102 lw s1,256\(gp\) +[0-9a-f]+ <[^>]+> 823c 8104 addiu s1,gp,-260 +[0-9a-f]+ <[^>]+> 8631 8000 lw s1,0\(s1\) +[0-9a-f]+ <[^>]+> 863c 8001 lw s1,1\(gp\) +[0-9a-f]+ <[^>]+> 863c 8002 lw s1,2\(gp\) +[0-9a-f]+ <[^>]+> 863c 8003 lw s1,3\(gp\) +[0-9a-f]+ <[^>]+> a63c c0ff lw s1,-1\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fe lw s1,-2\(gp\) +[0-9a-f]+ <[^>]+> a63c c0fd lw s1,-3\(gp\) +[0-9a-f]+ <[^>]+> 863b 8000 lw s1,0\(k1\) +[0-9a-f]+ <[^>]+> 8042 2fff andi t4,t4,0xfff +[0-9a-f]+ <[^>]+> 8043 f300 ext t4,t5,0,13 +[0-9a-f]+ <[^>]+> 8044 f340 ext t4,a0,0,14 +[0-9a-f]+ <[^>]+> 8045 f380 ext t4,a1,0,15 +[0-9a-f]+ <[^>]+> 8046 f3c0 ext t4,a2,0,16 +[0-9a-f]+ <[^>]+> 8047 f500 ext t4,a3,0,21 +[0-9a-f]+ <[^>]+> 8048 f540 ext t4,a4,0,22 +[0-9a-f]+ <[^>]+> 8049 f580 ext t4,a5,0,23 +[0-9a-f]+ <[^>]+> 8050 f5c0 ext t4,s0,0,24 +[0-9a-f]+ <[^>]+> e040 0000 lui t4,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 test +[0-9a-f]+ <[^>]+> 8042 0000 ori t4,t4,0x0 + [0-9a-f]+: R_NANOMIPS_LO12 test +[0-9a-f]+ <[^>]+> 2000 0390 dvp +[0-9a-f]+ <[^>]+> 20a0 0390 dvp a1 +[0-9a-f]+ <[^>]+> 2000 0790 evp +[0-9a-f]+ <[^>]+> 20c0 0790 evp a2 +#pass diff --git a/gas/testsuite/gas/nanomips/nms@la-lpic-mclarge.d b/gas/testsuite/gas/nanomips/nms@la-lpic-mclarge.d new file mode 100644 index 00000000000..16aefdc55f9 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@la-lpic-mclarge.d @@ -0,0 +1,206 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS subset la PIC large memory model +#as: -mPIC -mcmodel=large -G0 +#source: la.s + +# Test the la macro with mPIC on nanoMIPS subset and large memory model + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x3e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x3e9 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x83e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x7c18 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x103e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a98d +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/nms@la-lpic-mcmedium.d b/gas/testsuite/gas/nanomips/nms@la-lpic-mcmedium.d new file mode 100644 index 00000000000..faf13e3bafd --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@la-lpic-mcmedium.d @@ -0,0 +1,206 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS subset la PIC medium memory model +#as: -mPIC -mcmodel=medium -G0 +#source: la.s + +# Test the la macro with mPIC on nanoMIPS subset and medium memory model + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x3e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x3e9 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x83e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x7c18 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x103e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a98d +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_GOTPC_HI20 big_external_data_label +[0-9a-f]+ <[^>]+> 8484 8000 lw a0,0\(a0\) + [0-9a-f]+: R_NANOMIPS_GOT_LO12 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/nms@la-mclarge-pcrel.d b/gas/testsuite/gas/nanomips/nms@la-mclarge-pcrel.d new file mode 100644 index 00000000000..bfd896008ab --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@la-mclarge-pcrel.d @@ -0,0 +1,206 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS PC-relative la without li[48] for large memory model +#as: -mlegacyregs -mpcrel +#source: la.s + +# Test the la macro PC-relative expansion for mcmodel=large + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 44: R_NANOMIPS_PCHI20 data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 48: R_NANOMIPS_LO12 .data +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 4c: R_NANOMIPS_PCHI20 big_external_data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 50: R_NANOMIPS_LO12 big_external_data_label +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 54: R_NANOMIPS_PCHI20 small_external_data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 58: R_NANOMIPS_LO12 small_external_data_label +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 5c: R_NANOMIPS_PCHI20 big_external_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 60: R_NANOMIPS_LO12 big_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 64: R_NANOMIPS_PCHI20 small_external_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 68: R_NANOMIPS_LO12 small_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 6c: R_NANOMIPS_PCHI20 big_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 70: R_NANOMIPS_LO12 .bss +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 74: R_NANOMIPS_PCHI20 small_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 78: R_NANOMIPS_LO12 .sbss +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 7c: R_NANOMIPS_PCHI20 data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 80: R_NANOMIPS_LO12 .data\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 84: R_NANOMIPS_PCHI20 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 88: R_NANOMIPS_LO12 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 8c: R_NANOMIPS_PCHI20 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 90: R_NANOMIPS_LO12 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 94: R_NANOMIPS_PCHI20 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 98: R_NANOMIPS_LO12 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 9c: R_NANOMIPS_PCHI20 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + a0: R_NANOMIPS_LO12 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + a4: R_NANOMIPS_PCHI20 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + a8: R_NANOMIPS_LO12 .bss\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + ac: R_NANOMIPS_PCHI20 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + b0: R_NANOMIPS_LO12 .sbss\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + b4: R_NANOMIPS_PCHI20 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + b8: R_NANOMIPS_LO12 .data\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + bc: R_NANOMIPS_PCHI20 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + c0: R_NANOMIPS_LO12 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + c4: R_NANOMIPS_PCHI20 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + c8: R_NANOMIPS_LO12 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + cc: R_NANOMIPS_PCHI20 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + d0: R_NANOMIPS_LO12 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + d4: R_NANOMIPS_PCHI20 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + d8: R_NANOMIPS_LO12 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + dc: R_NANOMIPS_PCHI20 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + e0: R_NANOMIPS_LO12 .bss\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + e4: R_NANOMIPS_PCHI20 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + e8: R_NANOMIPS_LO12 .sbss\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + ec: R_NANOMIPS_PCHI20 data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + f0: R_NANOMIPS_LO12 .data-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + f4: R_NANOMIPS_PCHI20 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + f8: R_NANOMIPS_LO12 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + fc: R_NANOMIPS_PCHI20 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 100: R_NANOMIPS_LO12 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 104: R_NANOMIPS_PCHI20 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 108: R_NANOMIPS_LO12 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 10c: R_NANOMIPS_PCHI20 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 110: R_NANOMIPS_LO12 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 114: R_NANOMIPS_PCHI20 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 118: R_NANOMIPS_LO12 .bss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 11c: R_NANOMIPS_PCHI20 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 120: R_NANOMIPS_LO12 .sbss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 124: R_NANOMIPS_PCHI20 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 128: R_NANOMIPS_LO12 .data\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 12c: R_NANOMIPS_PCHI20 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 130: R_NANOMIPS_LO12 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 134: R_NANOMIPS_PCHI20 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 138: R_NANOMIPS_LO12 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 13c: R_NANOMIPS_PCHI20 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 140: R_NANOMIPS_LO12 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 144: R_NANOMIPS_PCHI20 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 148: R_NANOMIPS_LO12 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 14c: R_NANOMIPS_PCHI20 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 150: R_NANOMIPS_LO12 .bss\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 154: R_NANOMIPS_PCHI20 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 158: R_NANOMIPS_LO12 .sbss\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 15c: R_NANOMIPS_PCHI20 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 160: R_NANOMIPS_LO12 .data\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 164: R_NANOMIPS_PCHI20 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 168: R_NANOMIPS_LO12 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 16c: R_NANOMIPS_PCHI20 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 170: R_NANOMIPS_LO12 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 174: R_NANOMIPS_PCHI20 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 178: R_NANOMIPS_LO12 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 17c: R_NANOMIPS_PCHI20 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 180: R_NANOMIPS_LO12 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 184: R_NANOMIPS_PCHI20 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 188: R_NANOMIPS_LO12 .bss\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 18c: R_NANOMIPS_PCHI20 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 190: R_NANOMIPS_LO12 .sbss\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 1ac: R_NANOMIPS_PCHI20 big_external_data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 1b0: R_NANOMIPS_LO12 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/nms@la-mclarge.d b/gas/testsuite/gas/nanomips/nms@la-mclarge.d new file mode 100644 index 00000000000..91d13cdd7ed --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@la-mclarge.d @@ -0,0 +1,206 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS la without li[48] for large memory model +#as: +#source: la.s + +# Test the la macro for mcmodel=large + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> li a0,0 +[0-9a-f]+ <[^>]*> li a0,1 +[0-9a-f]+ <[^>]*> li a0,32768 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]*> addiu a0,a1,0 +[0-9a-f]+ <[^>]*> addiu a0,a1,1 +[0-9a-f]+ <[^>]*> addiu a0,a1,32768 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_common +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_common +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.sbss +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.sbss +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_common\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_common\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.sbss\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.sbss\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_common\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_common\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.sbss\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.sbss\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_common-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_common-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.sbss-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.sbss-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_common\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_common\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.sbss\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.sbss\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.sbss\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.sbss\+0x1a5a5 +[0-9a-f]+ <[^>]*> addiu a0,a1,0 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x456 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x456 +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/nms@la-pcrel.d b/gas/testsuite/gas/nanomips/nms@la-pcrel.d new file mode 100644 index 00000000000..8b135b38cc1 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@la-pcrel.d @@ -0,0 +1,176 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS PC-relative la without li[48] +#as: -mlegacyregs -mpcrel +#source: la.s + +# Test the la macro PC-relative expansion for NMS. + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 44: R_NANOMIPS_PCHI20 data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 48: R_NANOMIPS_LO12 .data +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 4c: R_NANOMIPS_PCHI20 big_external_data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 50: R_NANOMIPS_LO12 big_external_data_label +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 54: R_NANOMIPS_GPREL19_S2 small_external_data_label +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 58: R_NANOMIPS_PCHI20 big_external_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 5c: R_NANOMIPS_LO12 big_external_common +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 60: R_NANOMIPS_GPREL19_S2 small_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 64: R_NANOMIPS_PCHI20 big_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 68: R_NANOMIPS_LO12 .bss +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 6c: R_NANOMIPS_GPREL19_S2 .sbss +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 70: R_NANOMIPS_PCHI20 data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 74: R_NANOMIPS_LO12 .data\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 78: R_NANOMIPS_PCHI20 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 7c: R_NANOMIPS_LO12 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 80: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 84: R_NANOMIPS_PCHI20 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 88: R_NANOMIPS_LO12 big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 8c: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 90: R_NANOMIPS_PCHI20 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 94: R_NANOMIPS_LO12 .bss\+0x1 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 98: R_NANOMIPS_GPREL19_S2 .sbss\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 9c: R_NANOMIPS_PCHI20 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + a0: R_NANOMIPS_LO12 .data\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + a4: R_NANOMIPS_PCHI20 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + a8: R_NANOMIPS_LO12 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + ac: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + b0: R_NANOMIPS_PCHI20 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + b4: R_NANOMIPS_LO12 big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + b8: R_NANOMIPS_GPREL19_S2 small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + bc: R_NANOMIPS_PCHI20 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + c0: R_NANOMIPS_LO12 .bss\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + c4: R_NANOMIPS_GPREL19_S2 .sbss\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + c8: R_NANOMIPS_PCHI20 data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + cc: R_NANOMIPS_LO12 .data-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + d0: R_NANOMIPS_PCHI20 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + d4: R_NANOMIPS_LO12 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + d8: R_NANOMIPS_PCHI20 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + dc: R_NANOMIPS_LO12 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + e0: R_NANOMIPS_PCHI20 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + e4: R_NANOMIPS_LO12 big_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + e8: R_NANOMIPS_PCHI20 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + ec: R_NANOMIPS_LO12 small_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + f0: R_NANOMIPS_PCHI20 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + f4: R_NANOMIPS_LO12 .bss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + f8: R_NANOMIPS_PCHI20 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + fc: R_NANOMIPS_LO12 .sbss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 100: R_NANOMIPS_PCHI20 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 104: R_NANOMIPS_LO12 .data\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 108: R_NANOMIPS_PCHI20 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 10c: R_NANOMIPS_LO12 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 110: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 114: R_NANOMIPS_PCHI20 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 118: R_NANOMIPS_LO12 big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 11c: R_NANOMIPS_GPREL19_S2 small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 120: R_NANOMIPS_PCHI20 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 124: R_NANOMIPS_LO12 .bss\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 128: R_NANOMIPS_GPREL19_S2 .sbss\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 12c: R_NANOMIPS_PCHI20 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 130: R_NANOMIPS_LO12 .data\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 134: R_NANOMIPS_PCHI20 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 138: R_NANOMIPS_LO12 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 13c: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 140: R_NANOMIPS_PCHI20 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 144: R_NANOMIPS_LO12 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 148: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 14c: R_NANOMIPS_PCHI20 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 150: R_NANOMIPS_LO12 .bss\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0000 addiu a0,gp,0 + 154: R_NANOMIPS_GPREL19_S2 .sbss\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + 170: R_NANOMIPS_PCHI20 big_external_data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + 174: R_NANOMIPS_LO12 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/nms@la-pic-mclarge.d b/gas/testsuite/gas/nanomips/nms@la-pic-mclarge.d new file mode 100644 index 00000000000..afc50521687 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@la-pic-mclarge.d @@ -0,0 +1,156 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: nanoMIPS subset la pic large memory model +#as: -mpic -mcmodel=large -G0 +#source: la.s + +# Test the la macro with mpic on nanoMIPS subset and large memory model + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]+> 0080 0000 li a0,0 +[0-9a-f]+ <[^>]+> 0080 0001 li a0,1 +[0-9a-f]+ <[^>]+> 0080 8000 li a0,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> 0085 0001 addiu a0,a1,1 +[0-9a-f]+ <[^>]+> 0085 8000 addiu a0,a1,32768 +[0-9a-f]+ <[^>]+> e09f 8ffd lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 0000 lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e081 a000 lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]+> 8084 05a5 ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x3e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x1 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x3e9 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x83e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common-0x8000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x8000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common-0x8000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x7c18 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x10000 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x10000 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x10000 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x103e8 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 big_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]+> e080 0002 aluipc a0,%pcrel_hi\([0-9a-f]+ <[^>]+>\) + [0-9a-f]+: R_NANOMIPS_PCHI20 small_local_common\+0x1a5a5 +[0-9a-f]+ <[^>]+> 0084 0000 addiu a0,a0,0 + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a98d +[0-9a-f]+ <[^>]+> 0085 0000 addiu a0,a1,0 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> e092 3000 lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]+> 8084 0456 ori a0,a0,0x456 +[0-9a-f]+ <[^>]+> 20a4 2150 addu a0,a0,a1 +[0-9a-f]+ <[^>]+> 4080 0002 lw a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_DISP big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/nms@la.d b/gas/testsuite/gas/nanomips/nms@la.d new file mode 100644 index 00000000000..e7d64b78ad8 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@la.d @@ -0,0 +1,175 @@ +#objdump: -dr --prefix-addresses +#name: nanoMIPS la without li[48] +#as: +#source: la.s + +# Test the la macro. +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> li a0,0 +[0-9a-f]+ <[^>]*> li a0,1 +[0-9a-f]+ <[^>]*> li a0,32768 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]*> addiu a0,a1,0 +[0-9a-f]+ <[^>]*> addiu a0,a1,1 +[0-9a-f]+ <[^>]*> addiu a0,a1,32768 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0xffff8000\) +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x10000\) +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x1a000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x5a5 +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x1 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x8000 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x8000 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 small_external_common-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 small_external_common-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.sbss-0x8000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.sbss-0x8000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x10000 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x10000 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x10000 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x10000 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_data_label\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 small_external_common\+0x1a5a5 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a5a5 +[0-9a-f]+ <[^>]*> addiu a0,gp,0 +[ ]*[0-9a-f]+: R_NANOMIPS_GPREL19_S2 \.sbss\+0x1a5a5 +[0-9a-f]+ <[^>]*> addiu a0,a1,0 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x456 +[0-9a-f]+ <[^>]*> lui a0,%hi\(0x123000\) +[0-9a-f]+ <[^>]*> ori a0,a0,0x456 +[0-9a-f]+ <[^>]*> addu a0,a0,a1 +[0-9a-f]+ <[^>]*> lui a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label +[0-9a-f]+ <[^>]*> ori a0,a0,0x0 +[ ]*[0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label +#pass diff --git a/gas/testsuite/gas/nanomips/nms@lif-pic-mem.d b/gas/testsuite/gas/nanomips/nms@lif-pic-mem.d new file mode 100644 index 00000000000..872f126fa78 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@lif-pic-mem.d @@ -0,0 +1,23 @@ +#objdump: -dr --no-show-raw-insn +#name: LI float nanoMIPS subset sysVr4 PIC mode w/o float construction +#as: -mpic --no-construct-floats +#source: lifloat.s + +# Test loading immediate floating point values from memory in PIC (nanoMIPS subset) + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +00000000 : + 0: lw at,0\(gp\) + 0: R_NANOMIPS_GOT_PAGE .rodata + 4: lw a0,0\(at\) + 4: R_NANOMIPS_GOT_OFST .rodata + 8: lw a1,0\(at\) + 8: R_NANOMIPS_GOT_OFST .rodata\+0x4 + c: aluipc a0,%pcrel_hi\(8 \) + c: R_NANOMIPS_PCHI20 L0\^A + 10: lw a0,0\(a0\) + 10: R_NANOMIPS_LO12 .rodata\+0x8 +#pass diff --git a/gas/testsuite/gas/nanomips/nms@lif-pic.d b/gas/testsuite/gas/nanomips/nms@lif-pic.d new file mode 100644 index 00000000000..6d84a7b0cd6 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@lif-pic.d @@ -0,0 +1,21 @@ +#objdump: -dr --no-show-raw-insn +#name: LI float nanoMIPS subset sysVr4 PIC mode +#as: -mpic +#source: lifloat.s + +# Test loading immediate floating point values in PIC (nanoMIPS subset) + +.*: +file format .*nanomips.* + +Disassembly of section \.text: + +[0-9a-f]+ : + 0: lw at,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GOT_PAGE \.rodata + 4: lw a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST \.rodata + 8: lw a1,0\(at\) + [0-9a-f]+: R_NANOMIPS_GOT_OFST \.rodata\+0x4 + c: lui a0,%hi\(0x3f8fc000\) + 10: ori a0,a0,0xd36 +#pass diff --git a/gas/testsuite/gas/nanomips/nms@save-error.l b/gas/testsuite/gas/nanomips/nms@save-error.l new file mode 100644 index 00000000000..ce26dac107c --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@save-error.l @@ -0,0 +1,10 @@ +.*\.s: Assembler messages: +.*\.s:10: Warning: frame too small for save/restore register list +.*\.s:14: Error: non-contiguous save of \$gp is not available for nanoMIPS subset `save 64,\$s0-\$s3,\$gp' +.*\.s:15: Error: non-contiguous save of \$gp is not available for nanoMIPS subset `save 64,\$a0-\$s0,\$gp' +.*\.s:16: Error: non-contiguous save of \$gp is not available for nanoMIPS subset `save 128,\$t3,\$s0,\$s1,\$gp' +.*\.s:19: Error: non-contiguous restore of \$gp is not available for nanoMIPS subset `restore 64,\$s0,\$s1,\$s2,\$s3,\$gp' +.*\.s:20: Error: non-contiguous restore of \$gp is not available for nanoMIPS subset `restore 64,\$t4,\$t5,\$gp' +.*\.s:22: Error: non-contiguous restore.jrc of \$gp is not available for nanoMIPS subset `restore.jrc 64,\$s0,\$s1,\$s2,\$s3,\$gp' +.*\.s:23: Error: non-contiguous restore.jrc of \$gp is not available for nanoMIPS subset `restore.jrc 64,\$t4,\$t5,\$gp' +.*\.s:24: Error: non-contiguous restore.jrc of \$gp is not available for nanoMIPS subset `restore.jrc 128,\$fp,\$ra,\$s0,\$s1,\$gp' diff --git a/gas/testsuite/gas/nanomips/nms@save-error.s b/gas/testsuite/gas/nanomips/nms@save-error.s new file mode 100644 index 00000000000..fd2d5f89af2 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nms@save-error.s @@ -0,0 +1,26 @@ + .text + .ent test + .globl test +test: + /* save[16] */ + save 16 + save 128 + save 240 + + save 32,$ra,$s0-$s7 + save 48,$fp,$ra,$s0-$t8 + + /* save[32] */ + save 64,$s0-$s3,$gp + save 64,$a0-$s0,$gp + save 128,$t3,$s0,$s1,$gp + + /* restore[32] */ + restore 64,$s0,$s1,$s2,$s3,$gp + restore 64,$t4,$t5,$gp + + restore.jrc 64,$s0,$s1,$s2,$s3,$gp + restore.jrc 64,$t4,$t5,$gp + restore.jrc 128,$fp,$ra,$s0,$s1,$gp + + .end test diff --git a/gas/testsuite/gas/nanomips/nolinkrelax-relocs.d b/gas/testsuite/gas/nanomips/nolinkrelax-relocs.d new file mode 100644 index 00000000000..33a9c1485f3 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nolinkrelax-relocs.d @@ -0,0 +1,14 @@ +#name: No-relax relocations +#DUMPPROG: readelf +#readelf: -Wr -A +#source: linkrelax.s + +#... +Relocation section '.rela?.text' at offset 0x[0-9a-f]+ contains 4 entries: + Offset Info Type Sym. Value Symbol's Name( \+ Addend|) +00000008 [0-9a-f]+ R_NANOMIPS_PC25_S1 00000030 test2 \+ 0 +00000010 [0-9a-f]+ R_NANOMIPS_PC10_S1 00000030 test2 \+ 0 +00000018 [0-9a-f]+ R_NANOMIPS_PC25_S1 00000030 test2 \+ 0 +00000020 [0-9a-f]+ R_NANOMIPS_PC10_S1 00000030 test2 \+ 0 + +#... diff --git a/gas/testsuite/gas/nanomips/nolinkrelax.d b/gas/testsuite/gas/nanomips/nolinkrelax.d new file mode 100644 index 00000000000..247668eff73 --- /dev/null +++ b/gas/testsuite/gas/nanomips/nolinkrelax.d @@ -0,0 +1,17 @@ +#name: No relaxation code dump for nanoMIPS little endian +#objdump: -sj.text +#source: linkrelax.s +#as: -EL + +#... +Contents of section .text: + 0000 48000400 008000c0 00280000 008000c0 .* + 0010 00180890 43000400 00280000 008000c0 .* + 0020 00180890 008000c0 08900890 008000c0 .* + 0030 4c900a0a 0a0a0a0a 08900080 00c00080 .* + 0040 00c0cdcd cdcdcdcd 008000c0 cdabcdab .* + 0050 008000c0 3412cdab 43000400 0b0b0b0b .* + 0060 08900890 babababa babababa babababa .* + 0070 008000c0 badcbadc badcbadc badcbadc .* + 0080 008000c0 badc2143 badc2143 badc2143 .* + 0090 08900890 00c00080 00c00080 00c00080 .* diff --git a/gas/testsuite/gas/nanomips/rol.d b/gas/testsuite/gas/nanomips/rol.d new file mode 100644 index 00000000000..06df4a3f012 --- /dev/null +++ b/gas/testsuite/gas/nanomips/rol.d @@ -0,0 +1,28 @@ +#objdump: -dr --prefix-addresses --show-raw-insn +#name: hardware rol/ror on nanoMIPS +#source: rol.s + +# Test the rol and ror macros (nanoMIPS). + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +0+0000 20a0 09d0 negu at,a1 +0+0004 2024 20d0 rotrv a0,a0,at +0+0008 20c0 21d0 negu a0,a2 +0+000c 2085 20d0 rotrv a0,a1,a0 +0+0010 8084 c0df rotr a0,a0,31 +0+0014 8085 c0df rotr a0,a1,31 +0+0018 8085 c0c0 rotr a0,a1,0 +0+001c 20a4 20d0 rotrv a0,a0,a1 +0+0020 20c5 20d0 rotrv a0,a1,a2 +0+0024 8084 c0c1 rotr a0,a0,1 +0+0028 8085 c0c1 rotr a0,a1,1 +0+002c 8085 c0c0 rotr a0,a1,0 +0+0030 8085 c0c0 rotr a0,a1,0 +0+0034 8085 c0df rotr a0,a1,31 +0+0038 8085 c0c1 rotr a0,a1,1 +0+003c 8085 c0c0 rotr a0,a1,0 +0+0040 8085 c0c1 rotr a0,a1,1 +0+0044 8085 c0df rotr a0,a1,31 +#pass diff --git a/gas/testsuite/gas/nanomips/rol.s b/gas/testsuite/gas/nanomips/rol.s new file mode 100644 index 00000000000..6e0ab9e4605 --- /dev/null +++ b/gas/testsuite/gas/nanomips/rol.s @@ -0,0 +1,22 @@ +# Source file used to test the rol and ror macros. + +foo: + rol $4,$5 + rol $4,$5,$6 + rol $4,1 + rol $4,$5,1 + rol $4,$5,0 + + ror $4,$5 + ror $4,$5,$6 + ror $4,1 + ror $4,$5,1 + ror $4,$5,0 + + rol $4,$5,32 + rol $4,$5,33 + rol $4,$5,63 + + ror $4,$5,32 + ror $4,$5,33 + ror $4,$5,63 diff --git a/gas/testsuite/gas/nanomips/save-error.l b/gas/testsuite/gas/nanomips/save-error.l new file mode 100644 index 00000000000..ec4edf352aa --- /dev/null +++ b/gas/testsuite/gas/nanomips/save-error.l @@ -0,0 +1,16 @@ +.*\.s: Assembler messages: +.*\.s:10: Warning: frame too small for save/restore register list +.*\.s:14: Error: non-contiguous save of \$gp is not available for 16-bit instructions `save16 64,\$s0-\$s3,\$gp' +.*\.s:26: Error: register list not contiguous between \$fp and \$s0 `save 48,\$fp,\$s0-\$s7' +.*\.s:27: Error: register list not contiguous between \$s7 and \$t9 `restore.jrc 48,\$fp,\$ra,\$s0-\$s7,\$t9' +.*\.s:28: Error: register list not contiguous between \$t3 and \$t4 `restore 48,\$t0,\$t1,\$t2,\$t3,\$t4,\$t5' +.*\.s:29: Error: register range \(\$t0-\$t5\) is not in increasing order `restore 48,\$t0-\$t5' +.*\.s:31: Error: \$fp must be the first register in the list `save 48,\$ra,\$fp,\$s0-\$s7' +.*\.s:32: Error: restore\.jrc can handle a maximum of 16 register, 27 requested `restore.jrc 256,\$t4-\$gp' +.*\.s:33: Error: first register for 16-bit restore.jrc must be \$fp or \$ra `restore16 48,\$s0' +.*\.s:35: Error: save register list should not contain \$sp `save 128,\$k0-\$sp' +.*\.s:36: Error: \$fp must be the first register in the list `restore 128,\$s0-\$s7,\$fp,\$ra' +.*\.s:37: Error: \$ra must be the first register in the list `save 128,\$s0-\$s7,\$ra' +.*\.s:38: Error: \$ra must be the first register in the list `restore 128,\$s0-\$s7,\$ra,\$fp' +.*\.s:39: Error: \$fp must be the first register in the list `save 128,\$ra,\$s0-\$s7,\$fp' +.*\.s:40: Error: \$ra must be followed by \$s0 `restore 128,\$fp,\$ra,\$s1' diff --git a/gas/testsuite/gas/nanomips/save-error.s b/gas/testsuite/gas/nanomips/save-error.s new file mode 100644 index 00000000000..556df3fe887 --- /dev/null +++ b/gas/testsuite/gas/nanomips/save-error.s @@ -0,0 +1,42 @@ + .text + .ent test + .globl test +test: + /* save[16] */ + save 16 + save 128 + save 240 + + save 32,$ra,$s0-$s7 + save 48,$fp,$ra,$s0-$t8 + + /* save[32] */ + save16 64,$s0-$s3,$gp + save 64,$a0-$s0,$gp + save 128,$t3,$s0,$s1,$gp + + /* restore[32] */ + restore 64,$s0,$s1,$s2,$s3,$gp + restore 64,$t4,$t5,$gp + + restore.jrc 64,$s0,$s1,$s2,$s3,$gp + restore.jrc 64,$t4,$t5,$gp + restore.jrc 128,$fp,$ra,$s0,$s1,$gp + + save 48,$fp,$s0-$s7 + restore.jrc 48,$fp,$ra,$s0-$s7,$t9 + restore 48,$t0,$t1,$t2,$t3,$t4,$t5 + restore 48,$t0-$t5 + + save 48,$ra,$fp,$s0-$s7 + restore.jrc 256,$t4-$gp + restore16 48,$s0 + + save 128,$k0-$sp + restore 128,$s0-$s7,$fp,$ra + save 128,$s0-$s7,$ra + restore 128,$s0-$s7,$ra,$fp + save 128,$ra,$s0-$s7,$fp + restore 128,$fp,$ra,$s1 + + .end test diff --git a/gas/testsuite/gas/nanomips/save-relocs.d b/gas/testsuite/gas/nanomips/save-relocs.d new file mode 100644 index 00000000000..8dbce9e77f8 --- /dev/null +++ b/gas/testsuite/gas/nanomips/save-relocs.d @@ -0,0 +1,22 @@ +#name: SAVE/RESTORE relocations on nanoMIPS +#DUMPPROG: readelf +#readelf: -Wr +#as: --linkrelax -mpic +#source: save.s + +#... +Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 12 entries: + Offset Info Type Sym. Value Symbol's Name \+ Addend +00000034 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000038 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +0000003c [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000040 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000054 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000058 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +0000005c [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000060 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000078 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +0000007c [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000080 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +00000084 [0-9a-f]+47 R_NANOMIPS_SAVERESTORE 00000000 test \+ 0 +#pass diff --git a/gas/testsuite/gas/nanomips/save.d b/gas/testsuite/gas/nanomips/save.d new file mode 100644 index 00000000000..c65f0e33272 --- /dev/null +++ b/gas/testsuite/gas/nanomips/save.d @@ -0,0 +1,64 @@ +#objdump: -d --prefix-addresses --show-raw-insn +#name: nanoMIPS save/restore instructions + +# Check nanoMIPS save/restore instructions + +.*: +file format .*nanomips.* + +Disassembly of section \.text: +[0-9a-f]+ 1c10 save 16 +[0-9a-f]+ 1c80 save 128 +[0-9a-f]+ 1cf0 save 240 +[0-9a-f]+ 1e21 save 32,ra +[0-9a-f]+ 1c22 save 32,fp,ra +[0-9a-f]+ 1e22 save 32,ra,s0 +[0-9a-f]+ 1e25 save 32,ra,s0-s3 +[0-9a-f]+ 1ece save 192,ra,s0-k1,gp +[0-9a-f]+ 1ccf save 192,fp,ra,s0-k1,gp +[0-9a-f]+ 1c8f save 128,fp,ra,s0-k1,gp +[0-9a-f]+ 1d10 restore.jrc 16 +[0-9a-f]+ 1d80 restore.jrc 128 +[0-9a-f]+ 1df0 restore.jrc 240 +[0-9a-f]+ 1f21 restore.jrc 32,ra +[0-9a-f]+ 1d22 restore.jrc 32,fp,ra +[0-9a-f]+ 1f22 restore.jrc 32,ra,s0 +[0-9a-f]+ 1f25 restore.jrc 32,ra,s0-s3 +[0-9a-f]+ 1fce restore.jrc 192,ra,s0-k1,gp +[0-9a-f]+ 1dcf restore.jrc 192,fp,ra,s0-k1,gp +[0-9a-f]+ 1d8f restore.jrc 128,fp,ra,s0-k1,gp +[0-9a-f]+ 83e1 3028 save 40,ra +[0-9a-f]+ 83c2 3100 save 256,fp,ra +[0-9a-f]+ 83e2 3400 save 1024,ra,s0 +[0-9a-f]+ 8002 30a4 save 160,zero,gp +[0-9a-f]+ 8205 3044 save 64,s0-s3,gp +[0-9a-f]+ 808e 3044 save 64,a0-s0,gp +[0-9a-f]+ 81e4 3084 save 128,t3-s1,gp +[0-9a-f]+ 810c 3080 save 128,a4-s3 +[0-9a-f]+ 83e1 3032 restore 48,ra +[0-9a-f]+ 83c2 3102 restore 256,fp,ra +[0-9a-f]+ 83e2 3402 restore 1024,ra,s0 +[0-9a-f]+ 8002 30a6 restore 160,zero,gp +[0-9a-f]+ 8205 3046 restore 64,s0-s3,gp +[0-9a-f]+ 8043 3046 restore 64,t4-t5,gp +[0-9a-f]+ 83c5 3086 restore 128,fp,ra,s0-s1,gp +[0-9a-f]+ 83cf 307a restore 120,fp,ra,s0-k1,gp +[0-9a-f]+ 83e1 303b restore.jrc 56,ra +[0-9a-f]+ 83c2 3103 restore.jrc 256,fp,ra +[0-9a-f]+ 83e2 3403 restore.jrc 1024,ra,s0 +[0-9a-f]+ 00a0 00c8 li a1,200 +[0-9a-f]+ 8002 30a7 restore.jrc 160,zero,gp +[0-9a-f]+ 8205 3047 restore.jrc 64,s0-s3,gp +[0-9a-f]+ 8043 3047 restore.jrc 64,t4-t5,gp +[0-9a-f]+ 83c5 3087 restore.jrc 128,fp,ra,s0-s1,gp +[0-9a-f]+ 83cf 307b restore.jrc 120,fp,ra,s0-k1,gp +[0-9a-f]+ 1d4a restore.jrc 64,fp,ra,s0-s7 +[0-9a-f]+ 1d60 restore.jrc 96 +[0-9a-f]+ 8000 3ff3 restore.jrc 4080 +[0-9a-f]+ 03bd fff0 addiu sp,sp,65520 +[0-9a-f]+ dbe0 jrc ra +[0-9a-f]+ 03bd 0800 addiu sp,sp,2048 +[0-9a-f]+ dbe0 jrc ra +[0-9a-f]+ 6020 fff0 000f li at,0xffff0 +[0-9a-f]+ 203d e950 addu sp,sp,at +[0-9a-f]+ dbe0 jrc ra +#pass diff --git a/gas/testsuite/gas/nanomips/save.s b/gas/testsuite/gas/nanomips/save.s new file mode 100644 index 00000000000..3b41efc68bb --- /dev/null +++ b/gas/testsuite/gas/nanomips/save.s @@ -0,0 +1,94 @@ + .text + .ent test + .globl test +test: + /* save[16] */ + save 16 + save 128 + save 240 + + save 32,$ra + save 32,$fp,$ra + save 32,$ra,$s0 + save 32,$ra,$s0-$s3 + save 192,$ra,$s0-$gp + save 192,$fp,$ra,$s0-$gp + save 128,$fp,$ra,$s0-$k1,$gp + + /* restore16.jrc */ + restore.jrc 16 + restore.jrc 128 + restore.jrc 240 + + restore.jrc 32,$ra + restore.jrc 32,$fp,$ra + restore.jrc 32,$ra,$s0 + restore.jrc 32,$ra,$s0-$s3 + restore.jrc 192,$ra,$s0-$gp + restore.jrc 192,$fp,$ra,$s0-$gp + restore.jrc 128,$fp,$ra,$s0-$k1,$gp + + + /* save[32] */ + save 40,$ra + save 256,$fp,$ra + save 1024,$ra,$s0 + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + save 160,$zero,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + save 64,$s0-$s3,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + save 64,$a0-$s0,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + save 128,$t3,$s0,$s1,$gp + save 128,$a4-$t3,$s0-$s3 + + /* restore[32] */ + restore 48,$ra + restore 256,$fp,$ra + restore 1024,$ra,$s0 + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore 160,$zero,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore 64,$s0,$s1,$s2,$s3,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore 64,$t4,$t5,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore 128,$fp,$ra,$s0,$s1,$gp + restore 120,$fp,$ra,$s0-$k1,$gp + + restore.jrc 56,$ra + restore.jrc 256,$fp,$ra + restore.jrc 1024,$ra,$s0 + + li $a1,200 + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore.jrc 160,$zero,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore.jrc 64,$s0,$s1,$s2,$s3,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore.jrc 64,$t4,$t5,$gp + .reloc 1f,R_NANOMIPS_SAVERESTORE,test +1: + restore.jrc 128,$fp,$ra,$s0,$s1,$gp + restore.jrc 120,$fp,$ra,$s0-$k1,$gp + restore.jrc 64,$fp,$ra,$s0-$s7 + jraddiusp 96 # restore.jrc[16] + jraddiusp 4080 # restore.jrc[32] + + jraddiusp 65520 + jraddiusp -2048 + jraddiusp 1048560 + + .end test diff --git a/gas/testsuite/gas/nanomips/sb.d b/gas/testsuite/gas/nanomips/sb.d new file mode 100644 index 00000000000..16abad89641 --- /dev/null +++ b/gas/testsuite/gas/nanomips/sb.d @@ -0,0 +1,175 @@ +#objdump: -dr --no-show-raw-insn +#name: nanoMIPS sb + +# Test the sb macro. + +.*: +file format .*nanomips.* + +Disassembly of section .text: + +0+0000 <.text>: + [0-9a-f]+: sb a0,0\(zero\) + [0-9a-f]+: sb a0,1\(zero\) + [0-9a-f]+: li at,32768 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: lui at,%hi\(0xffff8000\) + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: lui at,%hi\(0x10000\) + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: lui at,%hi\(0x1a000\) + [0-9a-f]+: sb a0,1445\(at\) + [0-9a-f]+: sb a0,0\(a1\) + [0-9a-f]+: sb a0,1\(a1\) + [0-9a-f]+: addiu at,a1,32768 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: lui at,%hi\(0xffff8000\) + [0-9a-f]+: addu at,at,a1 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: lui at,%hi\(0x10000\) + [0-9a-f]+: addu at,at,a1 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: lui at,%hi\(0x1a000\) + [0-9a-f]+: addu at,at,a1 + [0-9a-f]+: sb a0,1445\(at\) + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.bss + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.bss + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 \.sbss + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x1 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x1 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x1 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x1 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 \.sbss\+0x1 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x8000 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x8000 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x8000 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 \.sbss\+0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data-0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data-0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label-0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label-0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 small_external_data_label-0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 small_external_data_label-0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common-0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common-0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 small_external_common-0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 small_external_common-0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.bss-0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.bss-0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.sbss-0x8000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.sbss-0x8000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x10000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x10000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x10000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x10000 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x10000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x10000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x10000 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x10000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x10000 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x10000 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 \.sbss\+0x10000 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.data\+0x1a5a5 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.data\+0x1a5a5 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_data_label\+0x1a5a5 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_data_label\+0x1a5a5 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_data_label\+0x1a5a5 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 big_external_common\+0x1a5a5 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 big_external_common\+0x1a5a5 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 small_external_common\+0x1a5a5 + [0-9a-f]+: lui at,0x0 + [0-9a-f]+: R_NANOMIPS_HI20 \.bss\+0x1a5a5 + [0-9a-f]+: sb a0,0\(at\) + [0-9a-f]+: R_NANOMIPS_LO12 \.bss\+0x1a5a5 + [0-9a-f]+: sb a0,0\(gp\) + [0-9a-f]+: R_NANOMIPS_GPREL18 \.sbss\+0x1a5a5 + [0-9a-f]+: swm a0,0\(zero\),2 + [0-9a-f]+: sh a0,0\(zero\) + [0-9a-f]+: sw a0,0\(zero\) +#pass diff --git a/gas/testsuite/gas/nanomips/sb.s b/gas/testsuite/gas/nanomips/sb.s new file mode 100644 index 00000000000..8c7e8498b45 --- /dev/null +++ b/gas/testsuite/gas/nanomips/sb.s @@ -0,0 +1,71 @@ +# Source file used to test the sb macro. + + .data +data_label: + .extern big_external_data_label,1000 + .extern small_external_data_label,1 + .comm big_external_common,1000 + .comm small_external_common,1 + .lcomm big_local_common,1000 + .lcomm small_local_common,1 + + .text + sb $4,0 + sb $4,1 + sb $4,0x8000 + sb $4,-0x8000 + sb $4,0x10000 + sb $4,0x1a5a5 + sb $4,0($5) + sb $4,1($5) + sb $4,0x8000($5) + sb $4,-0x8000($5) + sb $4,0x10000($5) + sb $4,0x1a5a5($5) + sb $4,data_label + sb $4,big_external_data_label + sb $4,small_external_data_label + sb $4,big_external_common + sb $4,small_external_common + sb $4,big_local_common + sb $4,small_local_common + sb $4,data_label+1 + sb $4,big_external_data_label+1 + sb $4,small_external_data_label+1 + sb $4,big_external_common+1 + sb $4,small_external_common+1 + sb $4,big_local_common+1 + sb $4,small_local_common+1 + sb $4,data_label+0x8000 + sb $4,big_external_data_label+0x8000 + sb $4,small_external_data_label+0x8000 + sb $4,big_external_common+0x8000 + sb $4,small_external_common+0x8000 + sb $4,big_local_common+0x8000 + sb $4,small_local_common+0x8000 + sb $4,data_label-0x8000 + sb $4,big_external_data_label-0x8000 + sb $4,small_external_data_label-0x8000 + sb $4,big_external_common-0x8000 + sb $4,small_external_common-0x8000 + sb $4,big_local_common-0x8000 + sb $4,small_local_common-0x8000 + sb $4,data_label+0x10000 + sb $4,big_external_data_label+0x10000 + sb $4,small_external_data_label+0x10000 + sb $4,big_external_common+0x10000 + sb $4,small_external_common+0x10000 + sb $4,big_local_common+0x10000 + sb $4,small_local_common+0x10000 + sb $4,data_label+0x1a5a5 + sb $4,big_external_data_label+0x1a5a5 + sb $4,small_external_data_label+0x1a5a5 + sb $4,big_external_common+0x1a5a5 + sb $4,small_external_common+0x1a5a5 + sb $4,big_local_common+0x1a5a5 + sb $4,small_local_common+0x1a5a5 + +# Several macros are handled like sb. Sanity check them. + sd $4,0 + sh $4,0 + sw $4,0