From patchwork Wed Jul 8 14:20:26 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 138739 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BD79D4BA2E30 for ; Wed, 8 Jul 2026 14:25:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BD79D4BA2E30 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=W/2gCiFs X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by sourceware.org (Postfix) with ESMTPS id 21D124BA2E05 for ; Wed, 8 Jul 2026 14:24:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 21D124BA2E05 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 21D124BA2E05 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1783520642; cv=none; b=oY8S8V1pSZW8aioRttXtXIXj++g4s+4xkChcrTdRyUtOgZj6pHX/rDXwR5ixFtAnROz4oWwr/K2ssFKCZ8L0pLLgbKfpxFWy43GNvhd34YNp5NwZgMQREv+dPH3v8dYpw5WDM8eX2ErjyZPlOhjfCcwmLte1tjEEcrIZWJ6Y3+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1783520642; c=relaxed/simple; bh=+uQkAyQWfToVp8fI9VVs5TeYgPGALq6JVQ48LOKrHaM=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=EZpQ04jJRcXT15xTfez2BhrTpOg12U5fRB14sWEunE2h+091r4YrO5einVTesazSIva8hvsTbhgZA0oS19mG1hBUG9f7de53gfA3PWNUhu8MVWc8sGGEEbrFodEnHTrAi58iXf/v8/iS0oNLnArsCGjx15mhX6w+cYjQR59ZqYU= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=W/2gCiFs DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 21D124BA2E05 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783520642; x=1815056642; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+uQkAyQWfToVp8fI9VVs5TeYgPGALq6JVQ48LOKrHaM=; b=W/2gCiFs28XVkWYLnmON1VO6JtNt5dCU+f3zIchiXARQ7ptbJKzEHi2U /JhXLS1KtWc8+8+HZkzCdM7bp9bzKKbQ/OcHOVdT4tgHs+6+GQrCMvgQi EH09SKqE3wA44O9RBkL98xB0L3EZa/dOkrX8dTFhz9haEJMPRK44XVQJU oa/b+4VfgegMiX8KShX/G09lrTwcx0rPpPbe+pYFOxtr4EEEcQltEWuuR IxUOe7wxV9cqpyjN/bvZcvcHNpUk3f4h+xhIFPIe/WwR+78W4xy1X6QzA Y9H+QmpUqqTioxFtU+b4PVCC0mIMMUTWsyCbsABZWpXNxTmA9I2kOjsrQ A==; X-CSE-ConnectionGUID: +Fb7vtPVTWi0oDgUceSQQQ== X-CSE-MsgGUID: 7zOKqamMTCGgd4K72mc1Jg== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="86729828" X-IronPort-AV: E=Sophos;i="6.25,153,1779174000"; d="scan'208";a="86729828" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2026 07:23:59 -0700 X-CSE-ConnectionGUID: qhY5Q3DxRvCYPbQLPVJRnQ== X-CSE-MsgGUID: hmx6sjj+RpuSknCJU/gltw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,153,1779174000"; d="scan'208";a="256214068" Received: from panli.sh.intel.com ([10.239.159.61]) by fmviesa004.fm.intel.com with ESMTP; 08 Jul 2026 07:23:56 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 1/5] RISC-V: Allow RVV register overlap for v[sz]ext.vf4 Date: Wed, 8 Jul 2026 22:20:26 +0800 Message-ID: <20260708142206.215039-2-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708142206.215039-1-pan2.li@intel.com> References: <20260708142206.215039-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Like v[sz]ext.vf2, allow the rvv register overlap for v[sz]ext.vf4. gcc/ChangeLog: * config/riscv/riscv-protos.h (is_frac_vlmul_p): Add new func decl to predicate frac vlmul for a mode. * config/riscv/riscv-v.cc (is_frac_vlmul_p): Add new func impl for above. (riscv_v_widen_constraint_ok): Add Source and Dest lmul less and equal 1 handling. * config/riscv/vector.md: Leverage widen constraint Wvr. Signed-off-by: Pan Li --- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 26 +++++++++++++++++++++++++- gcc/config/riscv/vector.md | 16 ++++++++-------- 3 files changed, 34 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index e7bce0db7a3..b72d660f37e 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -642,6 +642,7 @@ void emit_nonvlmax_insn (unsigned, unsigned, rtx *, rtx); void emit_avltype_insn (unsigned, unsigned, rtx *, avl_type, rtx = nullptr); void emit_vlmax_insn_lra (unsigned, unsigned, rtx *, rtx); enum vlmul_type get_vlmul (machine_mode); +bool is_frac_vlmul_p (machine_mode); rtx get_vlmax_rtx (machine_mode); unsigned int get_ratio (machine_mode); unsigned int get_nf (machine_mode); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 48cc56ea3d9..c4e62cfc372 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2054,6 +2054,27 @@ get_vlmul (machine_mode mode) return mode_vtype_infos.vlmul[mode]; } +bool +is_frac_vlmul_p (machine_mode mode) +{ + switch (get_vlmul (mode)) + { + case LMUL_1: + case LMUL_2: + case LMUL_4: + case LMUL_8: + return false; + case LMUL_F8: + case LMUL_F4: + case LMUL_F2: + return true; + default: + break; + } + + gcc_unreachable (); +} + /* Return the VLMAX rtx of vector mode MODE. */ rtx get_vlmax_rtx (machine_mode mode) @@ -6505,7 +6526,7 @@ riscv_v_widen_constraint_ok (unsigned int regno, machine_mode mode, unsigned int wide_nregs = riscv_hard_regno_nregs (wide_regno, wide_mode); unsigned int nregs = riscv_hard_regno_nregs (regno, mode); - if (wide_nregs == nregs) /* Source LMUL < 1. */ + if (wide_nregs == nregs) /* Dest LMUL <= 1. */ { gcc_checking_assert (nregs == 1); @@ -6519,6 +6540,9 @@ riscv_v_widen_constraint_ok (unsigned int regno, machine_mode mode, if (regno + nregs <= wide_regno || wide_regno + wide_nregs <= regno) return true; + if (is_frac_vlmul_p (mode)) /* Source LMUL < 1. */ + return false; + unsigned int highest_num = wide_nregs - nregs; return (regno % wide_nregs) == highest_num; diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 5d22edb0f3f..a5ebc85b764 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4110,19 +4110,19 @@ (define_insn "@pred__vf2" ;; Vector Quad-Widening Sign-extend and Zero-extend. (define_insn "@pred__vf4" - [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr") + [(set (match_operand:VQEXTI 0 "register_operand" "=vr, vr, vd, vd") (if_then_else:VQEXTI (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 4 "vector_length_operand" " rvl, rvl") - (match_operand 5 "const_int_operand" " i, i") - (match_operand 6 "const_int_operand" " i, i") - (match_operand 7 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "Wc1, Wc1, vm, vm") + (match_operand 4 "vector_length_operand" "rvl, rvl, rvl, rvl") + (match_operand 5 "const_int_operand" " i, i, i, i") + (match_operand 6 "const_int_operand" " i, i, i, i") + (match_operand 7 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_extend:VQEXTI - (match_operand: 3 "register_operand" " vr, vr")) - (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))] + (match_operand: 3 "register_operand" "Wvr, Wvr, Wvr, Wvr")) + (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR && !TARGET_XTHEADVECTOR" "vext.vf4\t%0,%3%p1" [(set_attr "type" "vext") From patchwork Wed Jul 8 14:20:27 2026 Content-Type: text/plain; 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d="scan'208";a="256214077" Received: from panli.sh.intel.com ([10.239.159.61]) by fmviesa004.fm.intel.com with ESMTP; 08 Jul 2026 07:23:59 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 2/5] RISC-V: Add test cases for vsext.vf4 reg overlap Date: Wed, 8 Jul 2026 22:20:27 +0800 Message-ID: <20260708142206.215039-3-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708142206.215039-1-pan2.li@intel.com> References: <20260708142206.215039-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add test cases for vsext.vf4 register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf8.c: New test. Signed-off-by: Pan Li --- .../autovec/group_overlap/vsext_vf4-i16-m1.c | 17 ++++++++++++++ .../autovec/group_overlap/vsext_vf4-i16-m2.c | 17 ++++++++++++++ .../autovec/group_overlap/vsext_vf4-i16-mf2.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vsext_vf4-i16-mf4.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vsext_vf4-i8-m1.c | 17 ++++++++++++++ .../autovec/group_overlap/vsext_vf4-i8-m2.c | 17 ++++++++++++++ .../autovec/group_overlap/vsext_vf4-i8-mf2.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vsext_vf4-i8-mf4.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vsext_vf4-i8-mf8.c | 23 +++++++++++++++++++ 9 files changed, 183 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m1.c new file mode 100644 index 00000000000..e28ff65154f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vint16m1_t, + vint64m4_t, + __riscv_vle16_v_i16m1, + __riscv_vsext_vf4_i64m4, + __riscv_vse64_v_i64m4, + vsext_vf, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v4,v7} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m2.c new file mode 100644 index 00000000000..4a9b6520ef7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m2, + vint16m2_t, + vint64m8_t, + __riscv_vle16_v_i16m2, + __riscv_vsext_vf4_i64m8, + __riscv_vse64_v_i64m8, + vsext_vf, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v0,v6} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v8,v14} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf2.c new file mode 100644 index 00000000000..0264d7a0853 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vint16mf2_t, + vint64m2_t, + __riscv_vle16_v_i16mf2, + __riscv_vsext_vf4_i64m2, + __riscv_vse64_v_i64m2, + vsext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf4.c new file mode 100644 index 00000000000..6c7b46d0c33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i16-mf4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vint16mf4_t, + vint64m1_t, + __riscv_vle16_v_i16mf4, + __riscv_vsext_vf4_i64m1, + __riscv_vse64_v_i64m1, + vsext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m1.c new file mode 100644 index 00000000000..b7aac36cde1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vint8m1_t, + vint32m4_t, + __riscv_vle8_v_i8m1, + __riscv_vsext_vf4_i32m4, + __riscv_vse32_v_i32m4, + vsext_vf, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v4,v7} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m2.c new file mode 100644 index 00000000000..c90130d274c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m2, + vint8m2_t, + vint32m8_t, + __riscv_vle8_v_i8m2, + __riscv_vsext_vf4_i32m8, + __riscv_vse32_v_i32m8, + vsext_vf, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v0,v6} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf4\s+v8,v14} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf2.c new file mode 100644 index 00000000000..e8268f5f02a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vint8mf2_t, + vint32m2_t, + __riscv_vle8_v_i8mf2, + __riscv_vsext_vf4_i32m2, + __riscv_vse32_v_i32m2, + vsext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf4.c new file mode 100644 index 00000000000..60f16139b0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vint8mf4_t, + vint32m1_t, + __riscv_vle8_v_i8mf4, + __riscv_vsext_vf4_i32m1, + __riscv_vse32_v_i32m1, + vsext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf8.c new file mode 100644 index 00000000000..0f758f8deed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf4-i8-mf8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vint8mf8_t, + vint32mf2_t, + __riscv_vle8_v_i8mf8, + __riscv_vsext_vf4_i32mf2, + __riscv_vse32_v_i32mf2, + vsext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf4\s+v28,v31} } } */ From patchwork Wed Jul 8 14:20:28 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 138737 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 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d="scan'208";a="256214085" Received: from panli.sh.intel.com ([10.239.159.61]) by fmviesa004.fm.intel.com with ESMTP; 08 Jul 2026 07:24:01 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 3/5] RISC-V: Add test cases for vzext.vf4 reg overlap Date: Wed, 8 Jul 2026 22:20:28 +0800 Message-ID: <20260708142206.215039-4-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708142206.215039-1-pan2.li@intel.com> References: <20260708142206.215039-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Add test cases for vzext.vf4 register group overlap, please note it is not overlap as much as possible. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c: New test. * gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c: New test. Signed-off-by: Pan Li --- .../autovec/group_overlap/vzext_vf4-u16-m1.c | 17 ++++++++++++++ .../autovec/group_overlap/vzext_vf4-u16-m2.c | 17 ++++++++++++++ .../autovec/group_overlap/vzext_vf4-u16-mf2.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vzext_vf4-u16-mf4.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vzext_vf4-u8-m1.c | 17 ++++++++++++++ .../autovec/group_overlap/vzext_vf4-u8-m2.c | 17 ++++++++++++++ .../autovec/group_overlap/vzext_vf4-u8-mf2.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vzext_vf4-u8-mf4.c | 23 +++++++++++++++++++ .../autovec/group_overlap/vzext_vf4-u8-mf8.c | 23 +++++++++++++++++++ 9 files changed, 183 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c new file mode 100644 index 00000000000..cce2d1a9426 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16m1_t, + vuint64m4_t, + __riscv_vle16_v_u16m1, + __riscv_vzext_vf4_u64m4, + __riscv_vse64_v_u64m4, + vzext_vf, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v4,v7} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c new file mode 100644 index 00000000000..845917e4eea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m2, + vuint16m2_t, + vuint64m8_t, + __riscv_vle16_v_u16m2, + __riscv_vzext_vf4_u64m8, + __riscv_vse64_v_u64m8, + vzext_vf, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v6} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v8,v14} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c new file mode 100644 index 00000000000..c56b984c5c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf2_t, + vuint64m2_t, + __riscv_vle16_v_u16mf2, + __riscv_vzext_vf4_u64m2, + __riscv_vse64_v_u64m2, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c new file mode 100644 index 00000000000..055839b8e94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u16-mf4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e16m1, + vuint16mf4_t, + vuint64m1_t, + __riscv_vle16_v_u16mf4, + __riscv_vzext_vf4_u64m1, + __riscv_vse64_v_u64m1, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c new file mode 100644 index 00000000000..525be7621a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8m1_t, + vuint32m4_t, + __riscv_vle8_v_u8m1, + __riscv_vzext_vf4_u32m4, + __riscv_vse32_v_u32m4, + vzext_vf, + LOOP_UNARY_BODY_X8) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v3([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v4,v7} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c new file mode 100644 index 00000000000..159808de53a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-m2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m2, + vuint8m2_t, + vuint32m8_t, + __riscv_vle8_v_u8m2, + __riscv_vzext_vf4_u32m8, + __riscv_vse32_v_u32m8, + vzext_vf, + LOOP_UNARY_BODY_X4) + +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v0,v6} 1 } } */ +/* { dg-final { scan-assembler-times {vzext\.vf4\s+v8,v14} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c new file mode 100644 index 00000000000..9188968bb95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf2.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf2_t, + vuint32m2_t, + __riscv_vle8_v_u8mf2, + __riscv_vzext_vf4_u32m2, + __riscv_vse32_v_u32m2, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c new file mode 100644 index 00000000000..b5d233b5d6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf4.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf4_t, + vuint32m1_t, + __riscv_vle8_v_u8mf4, + __riscv_vzext_vf4_u32m1, + __riscv_vse32_v_u32m1, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c new file mode 100644 index 00000000000..a8aab4cfc0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vzext_vf4-u8-mf8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "group_overlap.h" + +DEF_GROUP_OVERLAP_UNARY_0( + __riscv_vsetvlmax_e8m1, + vuint8mf8_t, + vuint32mf2_t, + __riscv_vle8_v_u8mf8, + __riscv_vzext_vf4_u32mf2, + __riscv_vse32_v_u32mf2, + vzext_vf, + LOOP_UNARY_BODY_X16) + +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v0,v3([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v4,v7} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v8,v11} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v12,v15} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v16,v19} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v20,v23} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v24,v27} } } */ +/* { dg-final { scan-assembler-not {vzext\.vf4\s+v28,v31} } } */ From patchwork Wed Jul 8 14:20:29 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" X-Patchwork-Id: 138741 X-Patchwork-Delegate: rdapp.gcc@gmail.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 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d="scan'208";a="256214097" Received: from panli.sh.intel.com ([10.239.159.61]) by fmviesa004.fm.intel.com with ESMTP; 08 Jul 2026 07:24:04 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 4/5] RISC-V: Adjust the scan asm for v[sz]ext.vf2 for v1 and v12 Date: Wed, 8 Jul 2026 22:20:29 +0800 Message-ID: <20260708142206.215039-5-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708142206.215039-1-pan2.li@intel.com> References: <20260708142206.215039-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li The previous match v1 may match the v12 as well, therefore add the non-num boundary. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m1.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m2.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m4.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf2.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf4.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m1.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m2.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-mf2.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m1.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m2.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf2.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf4.c: * gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf8.c: Signed-off-by: Pan Li --- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m1.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m2.c | 2 +- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m4.c | 2 +- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf2.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf4.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m1.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m2.c | 2 +- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i32-mf2.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m1.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m2.c | 2 +- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf2.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf4.c | 4 ++-- .../riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf8.c | 4 ++-- 13 files changed, 22 insertions(+), 22 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m1.c index 6b59a0da8ee..6508a99b960 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m1.c @@ -13,5 +13,5 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v1} 1 } } */ -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v2,v3} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m2.c index 0396046a7b1..6b8c9935d2f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m2.c @@ -13,5 +13,5 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X8) -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v2([^0-9]|$)} 1 } } */ /* { dg-final { scan-assembler-times {vsext\.vf2\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m4.c index 1670668d04b..7aded370306 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-m4.c @@ -13,5 +13,5 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X4) -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v4} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v4([^0-9]|$)} 1 } } */ /* { dg-final { scan-assembler-times {vsext\.vf2\s+v8,v12} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf2.c index e700eb532a9..c9c6cb83565 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf2.c @@ -13,8 +13,8 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1} } } */ -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3([^0-9]|$)} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v4,v5} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v6,v7} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v8,v9} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf4.c index ca48d17e13d..4f22473dcd0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i16-mf4.c @@ -13,8 +13,8 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1} } } */ -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3([^0-9]|$)} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v4,v5} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v6,v7} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v8,v9} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m1.c index 461f4ef6b1a..c2d2e38cd28 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m1.c @@ -13,5 +13,5 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v1} 1 } } */ -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v2,v3} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m2.c index 6c7d8a5193b..e8d61fa50c3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-m2.c @@ -13,5 +13,5 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X8) -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v2([^0-9]|$)} 1 } } */ /* { dg-final { scan-assembler-times {vsext\.vf2\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-mf2.c index 4144306df4e..4faf542eff2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-mf2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i32-mf2.c @@ -13,8 +13,8 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1} } } */ -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3([^0-9]|$)} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v4,v5} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v6,v7} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v8,v9} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m1.c index 7a4ecd72d18..381cf6934fb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m1.c @@ -13,5 +13,5 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v1} 1 } } */ -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v2,v3} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v1([^0-9]|$)} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v2,v3([^0-9]|$)} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m2.c index 318360f9374..a292cfb8370 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-m2.c @@ -13,5 +13,5 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X8) -/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v2} 1 } } */ +/* { dg-final { scan-assembler-times {vsext\.vf2\s+v0,v2([^0-9]|$)} 1 } } */ /* { dg-final { scan-assembler-times {vsext\.vf2\s+v4,v6} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf2.c index fde319ec37a..ab9b0307058 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf2.c @@ -13,8 +13,8 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1} } } */ -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3([^0-9]|$)} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v4,v5} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v6,v7} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v8,v9} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf4.c index 1a1922abef4..023304b6f8a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf4.c @@ -13,8 +13,8 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1} } } */ -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3([^0-9]|$)} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v4,v5} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v6,v7} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v8,v9} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf8.c index 49b56468cc9..4db324051ab 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vsext_vf2-i8-mf8.c @@ -13,8 +13,8 @@ DEF_GROUP_OVERLAP_UNARY_0( vsext_vf, LOOP_UNARY_BODY_X16) -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1} } } */ -/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v0,v1([^0-9]|$)} } } */ +/* { dg-final { scan-assembler-not {vsext\.vf2\s+v2,v3([^0-9]|$)} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v4,v5} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v6,v7} } } */ /* { dg-final { scan-assembler-not {vsext\.vf2\s+v8,v9} } } */ From patchwork Wed Jul 8 14:20:30 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2" 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ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2026 07:24:08 -0700 X-CSE-ConnectionGUID: fpONRP3nRfSuV0R8CWQpjA== X-CSE-MsgGUID: oWHnT7tqTGKZ10AhDyCCXQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,153,1779174000"; d="scan'208";a="256214121" Received: from panli.sh.intel.com ([10.239.159.61]) by fmviesa004.fm.intel.com with ESMTP; 08 Jul 2026 07:24:06 -0700 From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com, Pan Li Subject: [PATCH v1 5/5] RISC-V: Adjust test case due to vf[sz]ext.vf4 overlap Date: Wed, 8 Jul 2026 22:20:30 +0800 Message-ID: <20260708142206.215039-6-pan2.li@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708142206.215039-1-pan2.li@intel.com> References: <20260708142206.215039-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, TXREP, T_SPF_TEMPERROR shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Pan Li Remove the xfail due to vf4 changes. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112431-16.c: Remove xfail. * gcc.target/riscv/rvv/base/pr112431-17.c: Ditto. Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c index 42d11611d98..98f42458883 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c @@ -65,4 +65,4 @@ foo (char const *buf, size_t len) /* { dg-final { scan-assembler-not {vmv2r} } } */ /* { dg-final { scan-assembler-not {vmv4r} } } */ /* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c index 9ecc62e234b..9b60005344d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c @@ -48,4 +48,4 @@ foo (char const *buf, size_t len) /* { dg-final { scan-assembler-not {vmv2r} } } */ /* { dg-final { scan-assembler-not {vmv4r} } } */ /* { dg-final { scan-assembler-not {vmv8r} } } */ -/* { dg-final { scan-assembler-not {csrr} { xfail riscv*-*-* } } } */ +/* { dg-final { scan-assembler-not {csrr} } } */