From patchwork Wed Jul 8 02:46:35 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Lin X-Patchwork-Id: 138705 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D59D34BA2E0B for ; Wed, 8 Jul 2026 02:47:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D59D34BA2E0B X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from Atcsqr.andestech.com (atcsqr.andestech.com [220.128.198.184]) by sourceware.org (Postfix) with ESMTPS id F2F2E4BA2E08 for ; Wed, 8 Jul 2026 02:46:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F2F2E4BA2E08 Authentication-Results: sourceware.org; dmarc=pass (p=reject dis=none) header.from=andestech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=andestech.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F2F2E4BA2E08 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=220.128.198.184 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1783478808; cv=none; b=LZ61w7ky2bdaf4kawqrEGTSlu54itKRWCTkBqQkqRnTM5S/KvynS7XIZvmPw8F0m/Kx1ishsMXHd63KF6U+Iik5h03g0QKYXl5ANdRqJ9o0u7qZy8mmzNjIimLj7a9rm1LSWSGCsRaSdlWx/yB6GUXPFKiRqCCjSH6JTRNQCwUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1783478808; c=relaxed/simple; bh=EVqaa79ZwWNIg+U5RkgzN6P28GF8TvQTuRuknwxQmig=; h=From:To:Subject:Date:Message-ID:MIME-Version; b=Gr4SfJm70VwMheZ0Zr13jzA0PRNCP7fPPBXN160QzaX6F8HVDLGv49bU6ObQtuDPvj4WOb3MOnFcU2RqRjKCEh3slfysc6kFKAzxMgYNYI54TrNTLdyU2NoBE8mLdA1mkFeX0tyi1q7YOMF67+cNIoByegdV7dLDU3MAyfGhYIw= ARC-Authentication-Results: i=1; sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F2F2E4BA2E08 Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTPS id 6682kdcx047974 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=OK) for ; Wed, 8 Jul 2026 10:46:39 +0800 (+08) (envelope-from jim@andestech.com) Received: from atccpl01.andestech.com (10.0.15.149) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 8 Jul 2026 10:46:39 +0800 From: Jim Lin To: CC: Jim Lin Subject: [PATCH] RISC-V: Enable TARGET_SFB_ALU for andes-45-series Date: Wed, 8 Jul 2026 10:46:35 +0800 Message-ID: <20260708024635.139877-1-jim@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.149] X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 6682kdcx047974 X-Spam-Status: No, score=-13.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org Enable short forward branch (SFB) ALU support for the andes-45-series tune, matching the existing sfb_alu scheduling reservation already present in andes-45-series.md. gcc/ChangeLog: * config/riscv/riscv.h (TARGET_SFB_ALU): Add andes_45_series. --- gcc/config/riscv/riscv.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index d72c06ec37f..7eb85d654a7 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -974,7 +974,8 @@ extern enum riscv_cc get_riscv_cc (const rtx use); #define TARGET_SFB_ALU \ ((riscv_microarchitecture == sifive_7) \ || (riscv_microarchitecture == sifive_p400) \ - || (riscv_microarchitecture == sifive_p600)) + || (riscv_microarchitecture == sifive_p600) \ + || (riscv_microarchitecture == andes_45_series)) /* True if the target supports misaligned vector loads and stores. */ #define TARGET_VECTOR_MISALIGN_SUPPORTED \