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(unknown [10.2.6.7]) by front1 (Coremail) with SMTP id qMiowJAxHsfgrU1qAwMFAA--.29781S2; Wed, 08 Jul 2026 09:54:40 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, zhaozhou@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, luweining@loongson.cn, mengqinggang@loongson.cn Subject: [PATCH v0 1/4] LoongArch: Fix the size of tls desc relocations Date: Wed, 8 Jul 2026 01:47:16 +0800 Message-Id: <20260707174719.1883721-2-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260707174719.1883721-1-mengqinggang@loongson.cn> References: <20260707174719.1883721-1-mengqinggang@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowJAxHsfgrU1qAwMFAA--.29781S2 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Change the size of R_LARCH_TLS_DESC64_* from 8 to 4. --- bfd/elfxx-loongarch.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bfd/elfxx-loongarch.c b/bfd/elfxx-loongarch.c index 11754d62737..b39a5c50b8d 100644 --- a/bfd/elfxx-loongarch.c +++ b/bfd/elfxx-loongarch.c @@ -1642,7 +1642,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = /* TLS_DESC64 LARGE PCREL. */ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_PC_LO20, /* type (113). */ 32, /* rightshift. */ - 8, /* size. */ + 4, /* size. */ 20, /* bitsize. */ true, /* pc_relative. */ 5, /* bitpos. */ @@ -1659,7 +1659,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_PC_HI12, /* type (114). */ 52, /* rightshift. */ - 8, /* size. */ + 4, /* size. */ 12, /* bitsize. */ true, /* pc_relative. */ 10, /* bitpos. */ @@ -1712,7 +1712,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = /* TLS_DESC64 LARGE ABS. */ LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_LO20, /* type (117). */ 32, /* rightshift. */ - 8, /* size. */ + 4, /* size. */ 20, /* bitsize. */ false, /* pc_relative. */ 5, /* bitpos. */ @@ -1729,7 +1729,7 @@ static loongarch_reloc_howto_type loongarch_howto_table[] = LOONGARCH_HOWTO (R_LARCH_TLS_DESC64_HI12, /* type (118). */ 52, /* rightshift. */ - 8, /* size. */ + 4, /* size. */ 12, /* bitsize. */ false, /* pc_relative. */ 10, /* bitpos. */ From patchwork Tue Jul 7 17:47:17 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mengqinggang X-Patchwork-Id: 138700 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6912E4BA2E36 for ; Wed, 8 Jul 2026 01:55:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6912E4BA2E36 X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id D6DE54BA2E0E for ; Wed, 8 Jul 2026 01:54:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D6DE54BA2E0E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D6DE54BA2E0E Authentication-Results: sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1783475690; cv=none; b=GdGTJD7Io5yWNnmOzK/VtHUrhrkrIJw7x46gGyK7rgn4WM15GZPJ0RspdeD2rO5ySwa++cw3k5wz5TMzC7aZJvY8G1HRNRhd8A/a3245u01VQx5iIIeDPAQpZGwQxQpmCVYzMuwnfCA5+jZdKusY1907D9czndlJDg16dlkEwYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1783475690; c=relaxed/simple; bh=AyKeXE4xDo8umdjQ9xEBXkpbFk/bquEWkZqEgwmt2n8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=fLs+o2MLuCfiDvEhL6sdmHzAmXItSLxdlbcKrHQGtqxWVArRqIi67/hS2T5du4udVw54sxmd6kTdx+oxR1gx2z1bb5DFmsEQ3ytnHSUtsFql2tChP9EFOFVaSgyLHnY3m3CAPFrB23MA3CRapOvGw59wQM8OeZ/PjMsWa8NCO4c= ARC-Authentication-Results: i=1; sourceware.org DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D6DE54BA2E0E Received: from loongson.cn (unknown [10.2.6.7]) by gateway (Coremail) with SMTP id _____8DxeevnrU1q0DsBAA--.5324S3; Wed, 08 Jul 2026 09:54:47 +0800 (CST) Received: from amd9754.. (unknown [10.2.6.7]) by front1 (Coremail) with SMTP id qMiowJAx3cbhrU1qBgMFAA--.29210S2; Wed, 08 Jul 2026 09:54:41 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, zhaozhou@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, luweining@loongson.cn, mengqinggang@loongson.cn Subject: [PATCH v0 2/4] LoongArch: Do not emit relocation if addsy and subsy are in the same frag Date: Wed, 8 Jul 2026 01:47:17 +0800 Message-Id: <20260707174719.1883721-3-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260707174719.1883721-1-mengqinggang@loongson.cn> References: <20260707174719.1883721-1-mengqinggang@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowJAx3cbhrU1qBgMFAA--.29210S2 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Let relaxed instructions and alignment nops in a single frag. Do not emit relocation if addsy and subsy are in the same frag. --- gas/config/tc-loongarch.c | 127 ++++---- gas/testsuite/gas/elf/ehopt0.d | 3 - gas/testsuite/gas/loongarch/no_thin_add_sub.d | 30 +- gas/testsuite/gas/loongarch/no_thin_add_sub.s | 1 + .../gas/loongarch/relax_debug_line.d | 9 +- gas/testsuite/gas/loongarch/relocs_32.d | 175 +++++------ gas/testsuite/gas/loongarch/relocs_32.s | 11 +- gas/testsuite/gas/loongarch/relocs_64.d | 291 +++++++++--------- gas/testsuite/gas/loongarch/relocs_64.s | 3 + .../gas/loongarch/thin_add_sub_relax.d | 20 +- .../gas/loongarch/thin_add_sub_relax.s | 2 + ld/testsuite/ld-elf/compressed1d.d | 3 - 12 files changed, 344 insertions(+), 331 deletions(-) diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index d067318ce24..de862f07a6c 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -82,6 +82,9 @@ struct loongarch_cl_insn The macros or instructions expanded from macros do not output register deprecated warning. */ unsigned int expand_from_macro; + + /* Whether the instruction is linker-relaxable. */ + bool linker_relax; }; #ifndef DEFAULT_ARCH @@ -816,6 +819,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; ip->reloc_info[ip->reloc_num].value = const_0; ip->reloc_num++; + ip->linker_relax = true; } else ip->match_now = 0; @@ -889,6 +893,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; ip->reloc_info[ip->reloc_num].value = const_0; ip->reloc_num++; + ip->linker_relax = true; } /* Only one register macros (used in normal code model) @@ -896,8 +901,7 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used to generate the code model of absolute addresses, and we do not relax this code model. */ - if (LARCH_opts.relax && (ip->expand_from_macro & 1) - && !(LARCH_opts.ase_labs | LARCH_opts.ase_gabs) + if (LARCH_opts.relax && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type @@ -917,9 +921,19 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, || BFD_RELOC_LARCH_TLS_IE_PCADD_HI20 == reloc_type || BFD_RELOC_LARCH_TLS_IE_PCADD_LO12 == reloc_type)) { - ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; - ip->reloc_info[ip->reloc_num].value = const_0; - ip->reloc_num++; + /* R_LARCH_RELAX can be emitted by .reloc, so always set + link_relax for instructions. + For example: + .reloc .,R_LARCH_RELAX + pcalau12i $r12,%ie_pc_hi20(.LANCHOR0) */ + ip->linker_relax = true; + if ((ip->expand_from_macro & 1) + && !(LARCH_opts.ase_labs | LARCH_opts.ase_gabs)) + { + ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; + ip->reloc_info[ip->reloc_num].value = const_0; + ip->reloc_num++; + } } break; } @@ -1179,7 +1193,14 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where) static void append_fixed_insn (struct loongarch_cl_insn *insn) { - /* Ensure the jirl is emitted to the same frag as the pcaddu18i. */ + /* Start a new frag only used for relaxable instrucntions. */ + if (LARCH_opts.relax && insn->linker_relax) + { + frag_wane (frag_now); + frag_new (0); + } + + /* Ensure pcaddu18i/pcaddu12i + jirl in the same frag. */ if (insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL36 || insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL30) frag_grow (8); @@ -1187,19 +1208,45 @@ append_fixed_insn (struct loongarch_cl_insn *insn) char *f = frag_more (insn->insn_length); move_insn (insn, frag_now, f - frag_now->fr_literal); - if (call_reloc) + /* We need to start a new frag after any instruction that can be + optimized away or compressed by the linker during relaxation, to prevent + the assembler from computing static offsets across such an instruction. + + This is necessary to get correct .eh_frame FDE DW_CFA_advance_loc info. + If one cfi_insn_data's two symbols are not in the same frag, it will + generate ADD and SUB relocations pairs to calculate DW_CFA_advance_loc. + (gas/dw2gencfi.c: output_cfi_insn: + if (symbol_get_frag (to) == symbol_get_frag (from))) + + Since the relocations of the normal code model and the extreme code model + of the old LE instruction sequence are the same, it is impossible to + distinguish which code model it is based on relocation alone, so the + extreme code model has to be relaxed. */ + + /* End the frag to ensure it only used for relaxable instructions. */ + if (LARCH_opts.relax && insn->linker_relax + && insn->reloc_info[0].type != BFD_RELOC_LARCH_CALL36 + && insn->reloc_info[0].type != BFD_RELOC_LARCH_CALL30) + { + frag_wane (frag_now); + frag_new (0); + } + + /* To ensure pcaddu18i/pcaddu12i + jirl in the same frag. + End the frag after the jirl instruction. */ + if (LARCH_opts.relax && call_reloc) { if (strcmp (insn->name, "jirl") == 0) { - /* See comment at end of append_fixp_and_insn. */ frag_wane (frag_now); frag_new (0); } call_reloc = 0; } - if (insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL36 - || insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL30) + if (LARCH_opts.relax + && (insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL36 + || insn->reloc_info[0].type == BFD_RELOC_LARCH_CALL30)) call_reloc = 1; } @@ -1269,43 +1316,6 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) as_fatal (_("Internal error: not support relax now")); else append_fixed_insn (ip); - - /* We need to start a new frag after any instruction that can be - optimized away or compressed by the linker during relaxation, to prevent - the assembler from computing static offsets across such an instruction. - - This is necessary to get correct .eh_frame FDE DW_CFA_advance_loc info. - If one cfi_insn_data's two symbols are not in the same frag, it will - generate ADD and SUB relocations pairs to calculate DW_CFA_advance_loc. - (gas/dw2gencfi.c: output_cfi_insn: - if (symbol_get_frag (to) == symbol_get_frag (from))) - - For macro instructions, only the first instruction expanded from macro - need to start a new frag. - Since the relocations of the normal code model and the extreme code model - of the old LE instruction sequence are the same, it is impossible to - distinguish which code model it is based on relocation alone, so the - extreme code model has to be relaxed. */ - if (LARCH_opts.relax - && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LE_HI20_R == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LE_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LE_LO12 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LE64_LO20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_LE64_HI12 == reloc_info[0].type - || BFD_RELOC_LARCH_GOT_PCADD_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_IE_PCADD_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_DESC_PCADD_HI20 == reloc_info[0].type)) - { - frag_wane (frag_now); - frag_new (0); - } } /* Ask helper for returning a malloced c_str or NULL. */ @@ -1588,11 +1598,18 @@ loongarch_force_relocation_sub_local (fixS *fixp, segT sec ATTRIBUTE_UNUSED) || (S_GET_SEGMENT (fixp->fx_subsy)->flags & SEC_CODE) == 0)); } -/* Postpone text-section label subtraction calculation until linking, since - linker relaxations might change the deltas. */ +/* Postpone text-section label subtraction calculation until linking, + since linker relaxations might change the deltas. */ bool loongarch_force_relocation_sub_same(fixS *fixp ATTRIBUTE_UNUSED, segT sec) { + fragS *add_frag = symbol_get_frag (fixp->fx_addsy); + fragS *sub_frag = symbol_get_frag (fixp->fx_subsy); + + /* Not emit relocation if addsy and subsy are in the same frag. */ + if (add_frag == sub_frag) + return false; + return LARCH_opts.relax && (sec->flags & SEC_CODE) != 0; } @@ -2117,6 +2134,10 @@ loongarch_frag_align_code (int n, int max) if (align_bytes <= 4) return true; + /* Start a new frag only used for alignment. */ + frag_wane (frag_now); + frag_new (0); + /* If max <= 0, ignore max. If max >= worst_case_bytes, max has no effect. Similar to gas/write.c relax_segment function rs_align_code case: @@ -2160,9 +2181,11 @@ loongarch_frag_align_code (int n, int max) /* Default write NOP for aligned bytes. */ loongarch_make_nops (nops, worst_case_bytes); - /* We need to start a new frag after the alignment which may be removed by - the linker, to prevent the assembler from computing static offsets. - This is necessary to get correct EH info. */ + /* We need to start a new frag after the alignment which may be + removed by the linker, to prevent the assembler from computing + static offsets. This is necessary to get correct EH info. + + End the frag to ensure it is only used for alignment. */ frag_wane (frag_now); frag_new (0); diff --git a/gas/testsuite/gas/elf/ehopt0.d b/gas/testsuite/gas/elf/ehopt0.d index 64c5fb5ddc4..a13c4f26e33 100644 --- a/gas/testsuite/gas/elf/ehopt0.d +++ b/gas/testsuite/gas/elf/ehopt0.d @@ -1,8 +1,5 @@ #objdump: -s -j .eh_frame #name: elf ehopt0 -# The loongarch target do not evaluate .eh_frame fde cfa advance loc at assembly time. -# Because loongarch use add/sub reloc evaluate cfa advance loc, so gas should write 0 to cfa advance loc address. -#xfail: loongarch*-* .*: +file format .* diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.d b/gas/testsuite/gas/loongarch/no_thin_add_sub.d index 614aca71d66..625b8ac97c7 100644 --- a/gas/testsuite/gas/loongarch/no_thin_add_sub.d +++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.d @@ -1,24 +1,20 @@ -#as: +#as: -mrelax #objdump: -Dr -.*:[ ]+file format .* +#... +.*<.L1>: +#... +.*R_LARCH_ADD32[ ]+.L3 +.*R_LARCH_SUB32[ ]+.L1 +.*R_LARCH_ADD32[ ]+.L3 +.*R_LARCH_SUB32[ ]+.L1 - -Disassembly of section .text: - -00000000.* <.L1>: -[ ]+... -[ ]+0:[ ]+R_LARCH_ADD32[ ]+.L3 -[ ]+0:[ ]+R_LARCH_SUB32[ ]+.L1 -[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 -[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 - -0*00000008[ ]+<.L2>: +.*<.L2>: [ ]+... -[ ]+8:[ ]+R_LARCH_ADD64[ ]+.L3 -[ ]+8:[ ]+R_LARCH_SUB64[ ]+.L2 -[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 -[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2 +.*:[ ]+R_LARCH_ADD64[ ]+.L3 +.*:[ ]+R_LARCH_SUB64[ ]+.L2 +.*:[ ]+R_LARCH_ADD64[ ]+.L3 +.*:[ ]+R_LARCH_SUB64[ ]+.L2 Disassembly[ ]+of[ ]+section[ ]+sx: diff --git a/gas/testsuite/gas/loongarch/no_thin_add_sub.s b/gas/testsuite/gas/loongarch/no_thin_add_sub.s index c680168956f..e84da86ea0a 100644 --- a/gas/testsuite/gas/loongarch/no_thin_add_sub.s +++ b/gas/testsuite/gas/loongarch/no_thin_add_sub.s @@ -1,5 +1,6 @@ .section .text .L1: + call .text # add32+sub32 .4byte .L3-.L1 .4byte .L3-.L1 diff --git a/gas/testsuite/gas/loongarch/relax_debug_line.d b/gas/testsuite/gas/loongarch/relax_debug_line.d index c17813c20ed..7ff44789a99 100644 --- a/gas/testsuite/gas/loongarch/relax_debug_line.d +++ b/gas/testsuite/gas/loongarch/relax_debug_line.d @@ -1,12 +1,9 @@ -#as: --gdwarf-5 +#as: --gdwarf-5 -mrelax #readelf: -r --wide -#skip: loongarch32-*-* -Relocation section '\.rela\.debug_line' at offset .* contains 5 entries: +Relocation section '\.rela\.debug_line' at offset .* contains 3 entries: #... 0+22.*R_LARCH_32[ \t]+[0-9]+.* 0+2c.*R_LARCH_32[ \t]+[0-9]+.* -0+36.*R_LARCH_64[ \t]+[0-9]+.* -0+42.*R_LARCH_ADD16[ \t]+[0-9]+.* -0+42.*R_LARCH_SUB16[ \t]+[0-9]+.* +0+36.*R_LARCH_(32|64)[ \t]+[0-9]+.* #pass diff --git a/gas/testsuite/gas/loongarch/relocs_32.d b/gas/testsuite/gas/loongarch/relocs_32.d index c88aef5c4d8..58059513877 100644 --- a/gas/testsuite/gas/loongarch/relocs_32.d +++ b/gas/testsuite/gas/loongarch/relocs_32.d @@ -2,124 +2,117 @@ #objdump: -dr #skip: loongarch64-*-* -.*:[ ]+file format .* - - -Disassembly of section .text: - -0+ <.*>: - 0: 4c0050a4 jirl \$a0, \$a1, 80 - 0: R_LARCH_B16 .L1 - 4: 50004c00 b 76 # 50 <.L1> - 4: R_LARCH_B26 .L1 - 8: 14000004 lu12i.w \$a0, 0 - 8: R_LARCH_ABS_HI20 .L1 - c: 038000a4 ori \$a0, \$a1, 0x0 - c: R_LARCH_ABS_LO12 .L1 - 10: 1a000004 pcalau12i \$a0, 0 - 10: R_LARCH_PCALA_HI20 .L1 - 14: 02800085 addi.w \$a1, \$a0, 0 - 14: R_LARCH_PCALA_LO12 .L1 - 18: 1a000004 pcalau12i \$a0, 0 - 18: R_LARCH_GOT_PC_HI20 .L1 - 1c: 28800085 ld.w \$a1, \$a0, 0 - 1c: R_LARCH_GOT_PC_LO12 .L1 - 20: 14000004 lu12i.w \$a0, 0 - 20: R_LARCH_GOT_HI20 .L1 - 24: 03800084 ori \$a0, \$a0, 0x0 - 24: R_LARCH_GOT_LO12 .L1 - 28: 14000004 lu12i.w \$a0, 0 - 28: R_LARCH_TLS_LE_HI20 TLSL1 - 28: R_LARCH_RELAX \*ABS\* - 2c: 03800085 ori \$a1, \$a0, 0x0 - 2c: R_LARCH_TLS_LE_LO12 TLSL1 - 2c: R_LARCH_RELAX \*ABS\* - 30: 1a000004 pcalau12i \$a0, 0 - 30: R_LARCH_TLS_IE_PC_HI20 TLSL1 - 34: 02c00005 li.d \$a1, 0 - 34: R_LARCH_TLS_IE_PC_LO12 TLSL1 +#... + 0: 1c000001 pcaddu12i \$ra, 0 + 0: R_LARCH_CALL30 .L1 + 0: R_LARCH_RELAX \*ABS\* + 4: 4c000021 jirl \$ra, \$ra, 0 + 8: 1c000001 pcaddu12i \$ra, 0 + 8: R_LARCH_CALL30 .L1 + 8: R_LARCH_RELAX \*ABS\* + c: 4c000020 ret + 10: 4ffff0a4 jirl \$a0, \$a1, -16 + 10: R_LARCH_B16 .L1 + 14: 53ffefff b -20 # 0 <.L1> + 14: R_LARCH_B26 .L1 + 18: 14000004 lu12i.w \$a0, 0 + 18: R_LARCH_ABS_HI20 .L1 + 1c: 038000a4 ori \$a0, \$a1, 0x0 + 1c: R_LARCH_ABS_LO12 .L1 + 20: 1a000004 pcalau12i \$a0, 0 + 20: R_LARCH_PCALA_HI20 .L1 + 24: 02800085 addi.w \$a1, \$a0, 0 + 24: R_LARCH_PCALA_LO12 .L1 + 28: 1a000004 pcalau12i \$a0, 0 + 28: R_LARCH_GOT_PC_HI20 .L1 + 2c: 28800085 ld.w \$a1, \$a0, 0 + 2c: R_LARCH_GOT_PC_LO12 .L1 + 30: 14000004 lu12i.w \$a0, 0 + 30: R_LARCH_GOT_HI20 .L1 + 34: 03800084 ori \$a0, \$a0, 0x0 + 34: R_LARCH_GOT_LO12 .L1 38: 14000004 lu12i.w \$a0, 0 - 38: R_LARCH_TLS_IE_HI20 TLSL1 - 3c: 03800084 ori \$a0, \$a0, 0x0 - 3c: R_LARCH_TLS_IE_LO12 TLSL1 + 38: R_LARCH_TLS_LE_HI20 TLSL1 + 38: R_LARCH_RELAX \*ABS\* + 3c: 03800085 ori \$a1, \$a0, 0x0 + 3c: R_LARCH_TLS_LE_LO12 TLSL1 + 3c: R_LARCH_RELAX \*ABS\* 40: 1a000004 pcalau12i \$a0, 0 - 40: R_LARCH_TLS_LD_PC_HI20 TLSL1 - 44: 14000004 lu12i.w \$a0, 0 - 44: R_LARCH_TLS_LD_HI20 TLSL1 - 48: 1a000004 pcalau12i \$a0, 0 - 48: R_LARCH_TLS_GD_PC_HI20 TLSL1 - 4c: 14000004 lu12i.w \$a0, 0 - 4c: R_LARCH_TLS_GD_HI20 TLSL1 - -0+50 <.L1>: - 50: 00000000 .word 0x00000000 - 50: R_LARCH_32_PCREL .L2 + 40: R_LARCH_TLS_IE_PC_HI20 TLSL1 + 44: 02c00005 li.d \$a1, 0 + 44: R_LARCH_TLS_IE_PC_LO12 TLSL1 + 48: 14000004 lu12i.w \$a0, 0 + 48: R_LARCH_TLS_IE_HI20 TLSL1 + 4c: 03800084 ori \$a0, \$a0, 0x0 + 4c: R_LARCH_TLS_IE_LO12 TLSL1 + 50: 1a000004 pcalau12i \$a0, 0 + 50: R_LARCH_TLS_LD_PC_HI20 TLSL1 + 54: 14000004 lu12i.w \$a0, 0 + 54: R_LARCH_TLS_LD_HI20 TLSL1 + 58: 1a000004 pcalau12i \$a0, 0 + 58: R_LARCH_TLS_GD_PC_HI20 TLSL1 + 5c: 14000004 lu12i.w \$a0, 0 + 5c: R_LARCH_TLS_GD_HI20 TLSL1 + 60: 00000000 .word 0x00000000 + 60: R_LARCH_ADD32 .L2 + 60: R_LARCH_SUB32 .L1 -0+54 <.L2>: - 54: 03400000 nop - 58: 03400000 nop - 58: R_LARCH_ALIGN .* - 5c: 03400000 nop - 60: 03400000 nop - 64: 1800000c pcaddi \$t0, 0 - 64: R_LARCH_PCREL20_S2 .L1 - 68: 1a000004 pcalau12i \$a0, 0 - 68: R_LARCH_TLS_DESC_PC_HI20 TLSL1 - 6c: 028000a5 addi.w \$a1, \$a1, 0 - 6c: R_LARCH_TLS_DESC_PC_LO12 TLSL1 - 70: 14000004 lu12i.w \$a0, 0 - 70: R_LARCH_TLS_DESC_HI20 TLSL1 - 74: 03800084 ori \$a0, \$a0, 0x0 - 74: R_LARCH_TLS_DESC_LO12 TLSL1 - 78: 28800081 ld.w \$ra, \$a0, 0 - 78: R_LARCH_TLS_DESC_LD TLSL1 - 7c: 4c000021 jirl \$ra, \$ra, 0 - 7c: R_LARCH_TLS_DESC_CALL TLSL1 -0+80 : - 80: 1c000001 pcaddu12i \$ra, 0 - 80: R_LARCH_CALL30 \.L1 - 80: R_LARCH_RELAX \*ABS\* - 84: 4c000021 jirl \$ra, \$ra, 0 - 88: 1c000001 pcaddu12i \$ra, 0 - 88: R_LARCH_CALL30 \.L1 - 88: R_LARCH_RELAX \*ABS\* - 8c: 4c000020 ret +00000064 <.L2>: + 64: 03400000 nop + 68: 03400000 nop + 68: R_LARCH_ALIGN \*ABS\*\+0xc + 6c: 03400000 nop + 70: 03400000 nop + 74: 1800000c pcaddi \$t0, 0 + 74: R_LARCH_PCREL20_S2 .L1 + 78: 1a000004 pcalau12i \$a0, 0 + 78: R_LARCH_TLS_DESC_PC_HI20 TLSL1 + 7c: 028000a5 addi.w \$a1, \$a1, 0 + 7c: R_LARCH_TLS_DESC_PC_LO12 TLSL1 + 80: 14000004 lu12i.w \$a0, 0 + 80: R_LARCH_TLS_DESC_HI20 TLSL1 + 84: 03800084 ori \$a0, \$a0, 0x0 + 84: R_LARCH_TLS_DESC_LO12 TLSL1 + 88: 28800081 ld.w \$ra, \$a0, 0 + 88: R_LARCH_TLS_DESC_LD TLSL1 + 8c: 4c000021 jirl \$ra, \$ra, 0 + 8c: R_LARCH_TLS_DESC_CALL TLSL1 -0+90 <\.Lpcadd_hi0>: +00000090 <.Lpcadd_hi0>: 90: 1c000004 pcaddu12i \$a0, 0 90: R_LARCH_PCADD_HI20 s 94: 02800084 addi.w \$a0, \$a0, 0 - 94: R_LARCH_PCADD_LO12 \.Lpcadd_hi0 + 94: R_LARCH_PCADD_LO12 .Lpcadd_hi0 -0+98 <\.Lpcadd_hi1>: +00000098 <.Lpcadd_hi1>: 98: 1c000004 pcaddu12i \$a0, 0 98: R_LARCH_GOT_PCADD_HI20 s 9c: 28800084 ld.w \$a0, \$a0, 0 - 9c: R_LARCH_GOT_PCADD_LO12 \.Lpcadd_hi1 + 9c: R_LARCH_GOT_PCADD_LO12 .Lpcadd_hi1 -0+a0 <\.Lpcadd_hi2>: +000000a0 <.Lpcadd_hi2>: a0: 1c000004 pcaddu12i \$a0, 0 a0: R_LARCH_TLS_IE_PCADD_HI20 TLSL1 a4: 28800084 ld.w \$a0, \$a0, 0 - a4: R_LARCH_TLS_IE_PCADD_LO12 \.Lpcadd_hi2 + a4: R_LARCH_TLS_IE_PCADD_LO12 .Lpcadd_hi2 -0+a8 <\.Lpcadd_hi3>: +000000a8 <.Lpcadd_hi3>: a8: 1c000004 pcaddu12i \$a0, 0 a8: R_LARCH_TLS_LD_PCADD_HI20 TLSL1 ac: 02800084 addi.w \$a0, \$a0, 0 - ac: R_LARCH_TLS_LD_PCADD_LO12 \.Lpcadd_hi3 + ac: R_LARCH_TLS_LD_PCADD_LO12 .Lpcadd_hi3 -0+b0 <\.Lpcadd_hi4>: +000000b0 <.Lpcadd_hi4>: b0: 1c000004 pcaddu12i \$a0, 0 b0: R_LARCH_TLS_GD_PCADD_HI20 TLSL1 b4: 02800084 addi.w \$a0, \$a0, 0 - b4: R_LARCH_TLS_GD_PCADD_LO12 \.Lpcadd_hi4 + b4: R_LARCH_TLS_GD_PCADD_LO12 .Lpcadd_hi4 -0+b8 <\.Lpcadd_hi5>: +000000b8 <.Lpcadd_hi5>: b8: 1c000004 pcaddu12i \$a0, 0 b8: R_LARCH_TLS_DESC_PCADD_HI20 TLS1 bc: 02800084 addi.w \$a0, \$a0, 0 - bc: R_LARCH_TLS_DESC_PCADD_LO12 \.Lpcadd_hi5 + bc: R_LARCH_TLS_DESC_PCADD_LO12 .Lpcadd_hi5 c0: 28800081 ld.w \$ra, \$a0, 0 c0: R_LARCH_TLS_DESC_LD TLS1 c4: 4c000021 jirl \$ra, \$ra, 0 diff --git a/gas/testsuite/gas/loongarch/relocs_32.s b/gas/testsuite/gas/loongarch/relocs_32.s index 8a6074d018a..65675a16e5a 100644 --- a/gas/testsuite/gas/loongarch/relocs_32.s +++ b/gas/testsuite/gas/loongarch/relocs_32.s @@ -1,3 +1,8 @@ +.L1: +/* LA32S/R medium call. */ +call30 .L1 +tail30 $r1, .L1 + /* b16. */ jirl $r4,$r5,%b16(.L1) @@ -39,7 +44,6 @@ pcalau12i $r4,%gd_pc_hi20(TLSL1) lu12i.w $r4,%gd_hi20(TLSL1) /* Test insn relocs. */ -.L1: /* 32-bit PC relative. */ .4byte .L2-.L1 .L2: @@ -60,11 +64,6 @@ ori $r4,$r4,%desc_lo12(TLSL1) ld.w $r1,$r4,%desc_ld(TLSL1) jirl $r1,$r1,%desc_call(TLSL1) -NEW: -/* LA32S/R medium call. */ -call30 .L1 -tail30 $r1, .L1 - /* LA32R PCREL. */ .Lpcadd_hi0: pcaddu12i $r4, %pcadd_hi20(s) diff --git a/gas/testsuite/gas/loongarch/relocs_64.d b/gas/testsuite/gas/loongarch/relocs_64.d index ce5216a2b73..a12849126e2 100644 --- a/gas/testsuite/gas/loongarch/relocs_64.d +++ b/gas/testsuite/gas/loongarch/relocs_64.d @@ -1,148 +1,153 @@ -#as: +#as: -mrelax #objdump: -dr -#skip: loongarch32-*-* -.*:[ ]+file format .* +#... +[ ]+0:[ ]+4c008ca4[ ]+jirl[ ]+\$a0,[ ]+\$a1,[ ]+140 +[ ]+0:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+4:[ ]+40008880[ ]+beqz[ ]+\$a0,[ ]+136[ ]+#[ ]+8c[ ]+<.L1> +[ ]+4:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+8:[ ]+50008400[ ]+b[ ]+132[ ]+#[ ]+8c[ ]+<.L1> +[ ]+8:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+c:[ ]+R_LARCH_ABS_HI20[ ]+.L1 +[ ]+10:[ ]+038000a4[ ]+ori[ ]+\$a0,[ ]+\$a1,[ ]+0x0 +[ ]+10:[ ]+R_LARCH_ABS_LO12[ ]+.L1 +[ ]+14:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+14:[ ]+R_LARCH_ABS64_LO20[ ]+.L1 +[ ]+18:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+18:[ ]+R_LARCH_ABS64_HI12[ ]+.L1 +[ ]+1c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+1c:[ ]+R_LARCH_PCALA_HI20[ ]+.L1 +[ ]+20:[ ]+02c00085[ ]+addi.d[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+20:[ ]+R_LARCH_PCALA_LO12[ ]+.L1 +[ ]+24:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+24:[ ]+R_LARCH_PCALA64_LO20[ ]+.L1 +[ ]+28:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+28:[ ]+R_LARCH_PCALA64_HI12[ ]+.L1 +[ ]+2c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+2c:[ ]+R_LARCH_GOT_PC_HI20[ ]+.L1 +[ ]+30:[ ]+28c00085[ ]+ld.d[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+30:[ ]+R_LARCH_GOT_PC_LO12[ ]+.L1 +[ ]+34:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+34:[ ]+R_LARCH_GOT64_PC_LO20[ ]+.L1 +[ ]+38:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+38:[ ]+R_LARCH_GOT64_PC_HI12[ ]+.L1 +[ ]+3c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+3c:[ ]+R_LARCH_GOT_HI20[ ]+.L1 +[ ]+40:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 +[ ]+40:[ ]+R_LARCH_GOT_LO12[ ]+.L1 +[ ]+44:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+44:[ ]+R_LARCH_GOT64_LO20[ ]+.L1 +[ ]+48:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+48:[ ]+R_LARCH_GOT64_HI12[ ]+.L1 +[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+4c:[ ]+R_LARCH_TLS_LE_HI20[ ]+TLSL1 +[ ]+4c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+50:[ ]+03800085[ ]+ori[ ]+\$a1,[ ]+\$a0,[ ]+0x0 +[ ]+50:[ ]+R_LARCH_TLS_LE_LO12[ ]+TLSL1 +[ ]+50:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+54:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+54:[ ]+R_LARCH_TLS_LE64_LO20[ ]+TLSL1 +[ ]+54:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+58:[ ]+03000085[ ]+lu52i.d[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+58:[ ]+R_LARCH_TLS_LE64_HI12[ ]+TLSL1 +[ ]+58:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+5c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+5c:[ ]+R_LARCH_TLS_IE_PC_HI20[ ]+TLSL1 +[ ]+60:[ ]+02c00005[ ]+li.d[ ]+\$a1,[ ]+0 +[ ]+60:[ ]+R_LARCH_TLS_IE_PC_LO12[ ]+TLSL1 +[ ]+64:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+64:[ ]+R_LARCH_TLS_IE64_PC_LO20[ ]+TLSL1 +[ ]+68:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+68:[ ]+R_LARCH_TLS_IE64_PC_HI12[ ]+TLSL1 +[ ]+6c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+6c:[ ]+R_LARCH_TLS_IE_HI20[ ]+TLSL1 +[ ]+70:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 +[ ]+70:[ ]+R_LARCH_TLS_IE_LO12[ ]+TLSL1 +[ ]+74:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+74:[ ]+R_LARCH_TLS_IE64_LO20[ ]+TLSL1 +[ ]+78:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+78:[ ]+R_LARCH_TLS_IE64_HI12[ ]+TLSL1 +[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+7c:[ ]+R_LARCH_TLS_LD_PC_HI20[ ]+TLSL1 +[ ]+80:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+80:[ ]+R_LARCH_TLS_LD_HI20[ ]+TLSL1 +[ ]+84:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+84:[ ]+R_LARCH_TLS_GD_PC_HI20[ ]+TLSL1 +[ ]+88:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+88:[ ]+R_LARCH_TLS_GD_HI20[ ]+TLSL1 +.*<.L1>: +[ ]+8c:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra,[ ]+0 +[ ]+8c:[ ]+R_LARCH_CALL36[ ]+.L1 +[ ]+8c:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+90:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0 +[ ]+94:[ ]+00000000[ ]+.word[ ]+0x00000000 +[ ]+94:[ ]+R_LARCH_ADD32[ ]+.L2 +[ ]+94:[ ]+R_LARCH_SUB32[ ]+.L1 -Disassembly of section .text: - -[ ]*0000000000000000 <.L1-0x8c>: -[ ]+0:[ ]+4c008ca4[ ]+jirl[ ]+\$a0, \$a1, 140 -[ ]+0: R_LARCH_B16[ ]+.L1 -[ ]+4:[ ]+40008880[ ]+beqz[ ]+\$a0, 136[ ]+# 8c <.L1> -[ ]+4: R_LARCH_B21[ ]+.L1 -[ ]+8:[ ]+50008400[ ]+b[ ]+132[ ]+# 8c <.L1> -[ ]+8: R_LARCH_B26[ ]+.L1 -[ ]+c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+c: R_LARCH_ABS_HI20[ ]+.L1 -[ ]+10:[ ]+038000a4[ ]+ori[ ]+\$a0, \$a1, 0x0 -[ ]+10: R_LARCH_ABS_LO12[ ]+.L1 -[ ]+14:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -[ ]+14: R_LARCH_ABS64_LO20[ ]+.L1 -[ ]+18:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -[ ]+18: R_LARCH_ABS64_HI12[ ]+.L1 -[ ]+1c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -[ ]+1c: R_LARCH_PCALA_HI20[ ]+.L1 -[ ]+20:[ ]+02c00085[ ]+addi.d[ ]+\$a1, \$a0, 0 -[ ]+20: R_LARCH_PCALA_LO12[ ]+.L1 -[ ]+24:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -[ ]+24: R_LARCH_PCALA64_LO20[ ]+.L1 -[ ]+28:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -[ ]+28: R_LARCH_PCALA64_HI12[ ]+.L1 -[ ]+2c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -[ ]+2c: R_LARCH_GOT_PC_HI20[ ]+.L1 -[ ]+30:[ ]+28c00085[ ]+ld.d[ ]+\$a1, \$a0, 0 -[ ]+30: R_LARCH_GOT_PC_LO12[ ]+.L1 -[ ]+34:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -[ ]+34: R_LARCH_GOT64_PC_LO20[ ]+.L1 -[ ]+38:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -[ ]+38: R_LARCH_GOT64_PC_HI12[ ]+.L1 -[ ]+3c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+3c: R_LARCH_GOT_HI20[ ]+.L1 -[ ]+40:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -[ ]+40: R_LARCH_GOT_LO12[ ]+.L1 -[ ]+44:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -[ ]+44: R_LARCH_GOT64_LO20[ ]+.L1 -[ ]+48:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -[ ]+48: R_LARCH_GOT64_HI12[ ]+.L1 -[ ]+4c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+4c: R_LARCH_TLS_LE_HI20[ ]+TLSL1 -[ ]+4c: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+50:[ ]+03800085[ ]+ori[ ]+\$a1, \$a0, 0x0 -[ ]+50: R_LARCH_TLS_LE_LO12[ ]+TLSL1 -[ ]+50: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+54:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -[ ]+54: R_LARCH_TLS_LE64_LO20[ ]+TLSL1 -[ ]+54: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+58:[ ]+03000085[ ]+lu52i.d[ ]+\$a1, \$a0, 0 -[ ]+58: R_LARCH_TLS_LE64_HI12[ ]+TLSL1 -[ ]+58: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+5c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -[ ]+5c: R_LARCH_TLS_IE_PC_HI20[ ]+TLSL1 -[ ]+60:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 -[ ]+60: R_LARCH_TLS_IE_PC_LO12[ ]+TLSL1 -[ ]+64:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -[ ]+64: R_LARCH_TLS_IE64_PC_LO20[ ]+TLSL1 -[ ]+68:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -[ ]+68: R_LARCH_TLS_IE64_PC_HI12[ ]+TLSL1 -[ ]+6c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+6c: R_LARCH_TLS_IE_HI20[ ]+TLSL1 -[ ]+70:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -[ ]+70: R_LARCH_TLS_IE_LO12[ ]+TLSL1 -[ ]+74:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -[ ]+74: R_LARCH_TLS_IE64_LO20[ ]+TLSL1 -[ ]+78:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0 -[ ]+78: R_LARCH_TLS_IE64_HI12[ ]+TLSL1 -[ ]+7c:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -[ ]+7c: R_LARCH_TLS_LD_PC_HI20[ ]+TLSL1 -[ ]+80:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+80: R_LARCH_TLS_LD_HI20[ ]+TLSL1 -[ ]+84:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -[ ]+84: R_LARCH_TLS_GD_PC_HI20[ ]+TLSL1 -[ ]+88:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+88: R_LARCH_TLS_GD_HI20[ ]+TLSL1 -000000000000008c <.L1>: -[ ]+8c:[ ]+00000000[ ]+.word[ ]+[ ]+0x00000000 -[ ]+8c: R_LARCH_ADD32[ ]+.L2 -[ ]+8c: R_LARCH_SUB32[ ]+.L1 -0000000000000090 <.L2>: +.*<.L2>: +[ ]+98:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra,[ ]+0 +[ ]+98:[ ]+R_LARCH_CALL36[ ]+.L1 +[ ]+98:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+9c:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0 [ ]+... -[ ]+90: R_LARCH_ADD64[ ]+.L3 -[ ]+90: R_LARCH_SUB64[ ]+.L2 -0000000000000098 <.L3>: -[ ]+98:[ ]+03400000[ ]+nop -[ ]+9c:[ ]+03400000[ ]+nop -[ ]+9c: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -[ ]+a0:[ ]+03400000[ ]+nop -[ ]+a4:[ ]+03400000[ ]+nop -[ ]+a8:[ ]+1800000c[ ]+pcaddi[ ]+\$t0, 0 -[ ]+a8: R_LARCH_PCREL20_S2[ ]+.L1 -[ ]+ac:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra, 0 -[ ]+ac: R_LARCH_CALL36[ ]+a -[ ]+ac: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+b0:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -[ ]+b4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 -[ ]+b4: R_LARCH_TLS_DESC_PC_HI20[ ]+TLSL1 -[ ]+b8:[ ]+02c000a5[ ]+addi.d[ ]+\$a1, \$a1, 0 -[ ]+b8: R_LARCH_TLS_DESC_PC_LO12[ ]+TLSL1 -[ ]+bc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1, 0 -[ ]+bc: R_LARCH_TLS_DESC64_PC_LO20[ ]+TLSL1 -[ ]+c0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1, \$a1, 0 -[ ]+c0: R_LARCH_TLS_DESC64_PC_HI12[ ]+TLSL1 -[ ]+c4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+c4: R_LARCH_TLS_DESC_HI20[ ]+TLSL1 -[ ]+c8:[ ]+03800084[ ]+ori[ ]+\$a0, \$a0, 0x0 -[ ]+c8: R_LARCH_TLS_DESC_LO12[ ]+TLSL1 -[ ]+cc:[ ]+16000004[ ]+lu32i.d[ ]+\$a0, 0 -[ ]+cc: R_LARCH_TLS_DESC64_LO20[ ]+TLSL1 -[ ]+d0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0, \$a0, 0 -[ ]+d0: R_LARCH_TLS_DESC64_HI12[ ]+TLSL1 -[ ]+d4:[ ]+28c00081[ ]+ld.d[ ]+\$ra, \$a0, 0 -[ ]+d4: R_LARCH_TLS_DESC_LD[ ]+TLSL1 -[ ]+d8:[ ]+4c000021[ ]+jirl[ ]+\$ra, \$ra, 0 -[ ]+d8: R_LARCH_TLS_DESC_CALL[ ]+TLSL1 -[ ]+dc:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+dc: R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 -[ ]+dc: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+e0:[ ]+001090a5[ ]+add.d[ ]+\$a1, \$a1, \$a0 -[ ]+e0: R_LARCH_TLS_LE_ADD_R[ ]+TLSL1 -[ ]+e0: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+e4:[ ]+29800085[ ]+st.w[ ]+\$a1, \$a0, 0 -[ ]+e4: R_LARCH_TLS_LE_LO12_R[ ]+TLSL1 -[ ]+e4: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+e8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0, 0 -[ ]+e8: R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 -[ ]+e8: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+ec:[ ]+001090a5[ ]+add.d[ ]+\$a1, \$a1, \$a0 -[ ]+ec: R_LARCH_TLS_LE_ADD_R[ ]+TLSL1 -[ ]+ec: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+f0:[ ]+29800085[ ]+st.w[ ]+\$a1, \$a0, 0 -[ ]+f0: R_LARCH_TLS_LE_LO12_R[ ]+TLSL1 -[ ]+f0: R_LARCH_RELAX[ ]+\*ABS\* -[ ]+f4:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0 -[ ]+f4: R_LARCH_TLS_LD_PCREL20_S2[ ]+TLSL1 -[ ]+f8:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0 -[ ]+f8: R_LARCH_TLS_GD_PCREL20_S2[ ]+TLSL1 -[ ]+fc:[ ]+18000004[ ]+pcaddi[ ]+\$a0, 0 -[ ]+fc: R_LARCH_TLS_DESC_PCREL20_S2[ ]+TLSL1 +[ ]+a0:[ ]+R_LARCH_ADD64[ ]+.L3 +[ ]+a0:[ ]+R_LARCH_SUB64[ ]+.L2 + +.*<.L3>: +[ ]+a8:[ ]+03400000[ ]+nop +[ ]+ac:[ ]+03400000[ ]+nop +[ ]+ac:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+b0:[ ]+03400000[ ]+nop +[ ]+b4:[ ]+03400000[ ]+nop +[ ]+b8:[ ]+1800000c[ ]+pcaddi[ ]+\$t0,[ ]+0 +[ ]+b8:[ ]+R_LARCH_PCREL20_S2[ ]+.L1 +[ ]+bc:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra,[ ]+0 +[ ]+bc:[ ]+R_LARCH_CALL36[ ]+a +[ ]+bc:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+c0:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0 +[ ]+c4:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0,[ ]+0 +[ ]+c4:[ ]+R_LARCH_TLS_DESC_PC_HI20[ ]+TLSL1 +[ ]+c8:[ ]+02c000a5[ ]+addi.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+c8:[ ]+R_LARCH_TLS_DESC_PC_LO12[ ]+TLSL1 +[ ]+cc:[ ]+16000005[ ]+lu32i.d[ ]+\$a1,[ ]+0 +[ ]+cc:[ ]+R_LARCH_TLS_DESC64_PC_LO20[ ]+TLSL1 +[ ]+d0:[ ]+030000a5[ ]+lu52i.d[ ]+\$a1,[ ]+\$a1,[ ]+0 +[ ]+d0:[ ]+R_LARCH_TLS_DESC64_PC_HI12[ ]+TLSL1 +[ ]+d4:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+d4:[ ]+R_LARCH_TLS_DESC_HI20[ ]+TLSL1 +[ ]+d8:[ ]+03800084[ ]+ori[ ]+\$a0,[ ]+\$a0,[ ]+0x0 +[ ]+d8:[ ]+R_LARCH_TLS_DESC_LO12[ ]+TLSL1 +[ ]+dc:[ ]+16000004[ ]+lu32i.d[ ]+\$a0,[ ]+0 +[ ]+dc:[ ]+R_LARCH_TLS_DESC64_LO20[ ]+TLSL1 +[ ]+e0:[ ]+03000084[ ]+lu52i.d[ ]+\$a0,[ ]+\$a0,[ ]+0 +[ ]+e0:[ ]+R_LARCH_TLS_DESC64_HI12[ ]+TLSL1 +[ ]+e4:[ ]+28c00081[ ]+ld.d[ ]+\$ra,[ ]+\$a0,[ ]+0 +[ ]+e4:[ ]+R_LARCH_TLS_DESC_LD[ ]+TLSL1 +[ ]+e8:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0 +[ ]+e8:[ ]+R_LARCH_TLS_DESC_CALL[ ]+TLSL1 +[ ]+ec:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+ec:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 +[ ]+ec:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+f0:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0 +[ ]+f0:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1 +[ ]+f0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+f4:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+f4:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1 +[ ]+f4:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+f8:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+f8:[ ]+R_LARCH_TLS_LE_HI20_R[ ]+TLSL1 +[ ]+f8:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+fc:[ ]+001090a5[ ]+add.d[ ]+\$a1,[ ]+\$a1,[ ]+\$a0 +[ ]+fc:[ ]+R_LARCH_TLS_LE_ADD_R[ ]+TLSL1 +[ ]+fc:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+100:[ ]+29800085[ ]+st.w[ ]+\$a1,[ ]+\$a0,[ ]+0 +[ ]+100:[ ]+R_LARCH_TLS_LE_LO12_R[ ]+TLSL1 +[ ]+100:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+104:[ ]+18000004[ ]+pcaddi[ ]+\$a0,[ ]+0 +[ ]+104:[ ]+R_LARCH_TLS_LD_PCREL20_S2[ ]+TLSL1 +[ ]+108:[ ]+18000004[ ]+pcaddi[ ]+\$a0,[ ]+0 +[ ]+108:[ ]+R_LARCH_TLS_GD_PCREL20_S2[ ]+TLSL1 +[ ]+10c:[ ]+18000004[ ]+pcaddi[ ]+\$a0,[ ]+0 +[ ]+10c:[ ]+R_LARCH_TLS_DESC_PCREL20_S2[ ]+TLSL1 diff --git a/gas/testsuite/gas/loongarch/relocs_64.s b/gas/testsuite/gas/loongarch/relocs_64.s index 1d1548f5b68..d22c03ec4f9 100644 --- a/gas/testsuite/gas/loongarch/relocs_64.s +++ b/gas/testsuite/gas/loongarch/relocs_64.s @@ -1,3 +1,4 @@ +.text /* b16. */ jirl $r4,$r5,%b16(.L1) @@ -61,9 +62,11 @@ lu12i.w $r4,%gd_hi20(TLSL1) /* Test insn relocs. */ .L1: +call36 .L1 /* 32-bit PC relative. */ .4byte .L2-.L1 .L2: +call36 .L1 /* 64-bit PC relative. */ .8byte .L3-.L2 diff --git a/gas/testsuite/gas/loongarch/thin_add_sub_relax.d b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d index 9455c3e66bf..92d9157b0d7 100644 --- a/gas/testsuite/gas/loongarch/thin_add_sub_relax.d +++ b/gas/testsuite/gas/loongarch/thin_add_sub_relax.d @@ -1,4 +1,4 @@ -#as: -mthin-add-sub +#as: -mthin-add-sub -mrelax #objdump: -Dr .*:[ ]+file format .* @@ -8,16 +8,16 @@ Disassembly of section .text: 00000000.* <.L1>: [ ]+... -[ ]+0:[ ]+R_LARCH_32_PCREL[ ]+.L3 -[ ]+4:[ ]+R_LARCH_ADD32[ ]+.L3 -[ ]+4:[ ]+R_LARCH_SUB32[ ]+.L1 - -0*00000008[ ]+<.L2>: +.*R_LARCH_32_PCREL[ ]+.L3 +.*R_LARCH_ADD32[ ]+.L3 +.*R_LARCH_SUB32[ ]+.L1 +#... +.*<.L2>: [ ]+... -[ ]+8:[ ]+R_LARCH_64_PCREL[ ]+.L3 -[ ]+10:[ ]+R_LARCH_ADD64[ ]+.L3 -[ ]+10:[ ]+R_LARCH_SUB64[ ]+.L2 - +.*R_LARCH_64_PCREL[ ]+.L3 +.*R_LARCH_ADD64[ ]+.L3 +.*R_LARCH_SUB64[ ]+.L2 +#... Disassembly[ ]+of[ ]+section[ ]+sx: 0*00000000[ ]+<.L3>: diff --git a/gas/testsuite/gas/loongarch/thin_add_sub_relax.s b/gas/testsuite/gas/loongarch/thin_add_sub_relax.s index ded275fa72c..2cfd739ff62 100644 --- a/gas/testsuite/gas/loongarch/thin_add_sub_relax.s +++ b/gas/testsuite/gas/loongarch/thin_add_sub_relax.s @@ -4,11 +4,13 @@ .4byte .L3-.L1 # add32+sub32 .4byte .L3-.L1 + call36 .L1 .L2: # 64_pcrel .8byte .L3-.L2 # add64+sub64 .8byte .L3-.L2 + call36 .L1 .section sx .L3: diff --git a/ld/testsuite/ld-elf/compressed1d.d b/ld/testsuite/ld-elf/compressed1d.d index b178695e23f..9d891c1933f 100644 --- a/ld/testsuite/ld-elf/compressed1d.d +++ b/ld/testsuite/ld-elf/compressed1d.d @@ -4,13 +4,10 @@ #readelf: -SW #xfail: [uses_genelf] #xfail: [riscv_little_endian] -#xfail: loongarch*-*-* # Not all ELF targets use the elf.em emulation... # RISC-V has linker relaxations that delete code, so text label subtractions # do not get resolved at assembly time, which results in a compressed section # for little endian targets; but it is uncompressed for big endian targets. -# LoongArch has linker relaxations that delete code, so text label subtractions -# do not get resolved at assembly time, which results in a compressed section. #failif #... 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(unknown [10.2.6.7]) by front1 (Coremail) with SMTP id qMiowJDxfsXorU1qCgMFAA--.28001S2; Wed, 08 Jul 2026 09:54:48 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, zhaozhou@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, luweining@loongson.cn, mengqinggang@loongson.cn Subject: [PATCH v0 3/4] LoongArch: Emit fewer relocations for label subtraction Date: Wed, 8 Jul 2026 01:47:18 +0800 Message-Id: <20260707174719.1883721-4-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260707174719.1883721-1-mengqinggang@loongson.cn> References: <20260707174719.1883721-1-mengqinggang@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowJDxfsXorU1qCgMFAA--.28001S2 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, GIT_PATCH_0, KAM_DMARC_STATUS, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Mark the frag and section to indicate if they have a relaxed instruction. For label subtraction, if there are no relaxed instructions between addsy and subsy, do not emit relocations. --- gas/config/tc-loongarch.c | 111 ++++++- gas/config/tc-loongarch.h | 11 + gas/testsuite/gas/all/gas.exp | 2 +- gas/testsuite/gas/all/relax.d | 4 - gas/testsuite/gas/loongarch/insn_int32.d | 279 +++++++++--------- gas/testsuite/gas/loongarch/insn_int64.d | 29 +- gas/testsuite/gas/loongarch/jmp_op.d | 94 +++--- gas/testsuite/gas/loongarch/jmp_op.s | 2 +- .../gas/loongarch/la_branch_relax_1.d | 118 ++++---- .../gas/loongarch/la_branch_relax_1.s | 2 + .../gas/loongarch/la_branch_relax_2.d | 64 ++-- .../gas/loongarch/la_branch_relax_2.s | 23 +- gas/testsuite/gas/loongarch/relax-uleb128.d | 9 + gas/testsuite/gas/loongarch/relax-uleb128.s | 18 ++ gas/testsuite/gas/loongarch/uleb128.d | 36 --- gas/testsuite/gas/loongarch/uleb128.s | 20 -- ld/testsuite/ld-loongarch-elf/jmp_op.d | 50 ---- ld/testsuite/ld-loongarch-elf/jmp_op.s | 23 -- .../ld-loongarch-elf/ld-loongarch-elf.exp | 2 - 19 files changed, 429 insertions(+), 468 deletions(-) create mode 100644 gas/testsuite/gas/loongarch/relax-uleb128.d create mode 100644 gas/testsuite/gas/loongarch/relax-uleb128.s delete mode 100644 gas/testsuite/gas/loongarch/uleb128.d delete mode 100644 gas/testsuite/gas/loongarch/uleb128.s delete mode 100644 ld/testsuite/ld-loongarch-elf/jmp_op.d delete mode 100644 ld/testsuite/ld-loongarch-elf/jmp_op.s diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index de862f07a6c..ed5d47a0360 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -1187,6 +1187,13 @@ move_insn (struct loongarch_cl_insn *insn, fragS *frag, long where) } } install_insn (insn); + + /* Mark the current section and frag as linker relaxable. */ + if (insn->linker_relax) + { + now_seg->sec_flg1 = true; + insn->frag->tc_frag_data.linker_relax = true; + } } /* Add INSN to the end of the output. */ @@ -1598,21 +1605,57 @@ loongarch_force_relocation_sub_local (fixS *fixp, segT sec ATTRIBUTE_UNUSED) || (S_GET_SEGMENT (fixp->fx_subsy)->flags & SEC_CODE) == 0)); } -/* Postpone text-section label subtraction calculation until linking, - since linker relaxations might change the deltas. */ -bool -loongarch_force_relocation_sub_same(fixS *fixp ATTRIBUTE_UNUSED, segT sec) + +/* Whether emit relocations for label subtraction in same section. */ +static bool +_loongarch_force_relocation_sub_same (segT sec, + fragS *addfrag, + fragS *subfrag) { - fragS *add_frag = symbol_get_frag (fixp->fx_addsy); - fragS *sub_frag = symbol_get_frag (fixp->fx_subsy); + if (!LARCH_opts.relax) + return false; + + /* Not emit relocation if section has no relaxable frag. */ + if (!sec->sec_flg1) + return false; /* Not emit relocation if addsy and subsy are in the same frag. */ - if (add_frag == sub_frag) + if (addfrag == subfrag) return false; - return LARCH_opts.relax && (sec->flags & SEC_CODE) != 0; + /* Emit relocation if find a frag is relaxable from addsy to subsy. */ + fragS *s; + for (s = subfrag; s != NULL && s != addfrag; s = s->fr_next) + { + if (s->tc_frag_data.linker_relax) + return true; + } + if (s == addfrag) + return false; + + for (s = addfrag; s != NULL && s != subfrag; s = s->fr_next) + { + if (s->tc_frag_data.linker_relax) + return true; + } + if (s == subfrag) + return false; + + return true; } + +/* Postpone text-section label subtraction calculation until linking, + since linker relaxations might change the deltas. */ +bool +loongarch_force_relocation_sub_same (fixS *fixp ATTRIBUTE_UNUSED, segT sec) +{ + fragS *addfrag = symbol_get_frag (fixp->fx_addsy); + fragS *subfrag = symbol_get_frag (fixp->fx_subsy); + return _loongarch_force_relocation_sub_same (sec, addfrag, subfrag); +} + + static void fix_reloc_insn (fixS *fixP, bfd_vma reloc_val, char *buf) { reloc_howto_type *howto; @@ -1840,6 +1883,16 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; case BFD_RELOC_LARCH_CFA: + unsigned int subtype; + fragS *opfrag = (fragS *) fixP->fx_frag->fr_opcode; + subtype = bfd_get_8 (NULL, opfrag->fr_literal + fixP->fx_where); + + /* Update to the real size after relax_segment. */ + if (subtype == DW_CFA_advance_loc2) + fixP->fx_size = 2; + if (subtype == DW_CFA_advance_loc4) + fixP->fx_size = 4; + if (fixP->fx_addsy && fixP->fx_subsy) { fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); @@ -1848,10 +1901,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) fixP->fx_next->fx_offset = 0; fixP->fx_subsy = NULL; - unsigned int subtype; offsetT loc; - fragS *opfrag = (fragS *) fixP->fx_frag->fr_opcode; - subtype = bfd_get_8 (NULL, opfrag->fr_literal + fixP->fx_where); loc = fixP->fx_frag->fr_fix - (subtype & 7); switch (subtype) { @@ -1864,8 +1914,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; case DW_CFA_advance_loc2: - fixP->fx_size = 2; - fixP->fx_next->fx_size = 2; fixP->fx_where = loc + 1; fixP->fx_next->fx_where = loc + 1; fixP->fx_r_type = BFD_RELOC_LARCH_ADD16; @@ -1874,8 +1922,6 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; case DW_CFA_advance_loc4: - fixP->fx_size = 4; - fixP->fx_next->fx_size = 4; fixP->fx_where = loc; fixP->fx_next->fx_where = loc; fixP->fx_r_type = BFD_RELOC_LARCH_ADD32; @@ -1898,6 +1944,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; } } + + if (fixP->fx_addsy == NULL) + fixP->fx_done = 1; break; case BFD_RELOC_LARCH_B16: @@ -1917,7 +1966,10 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) /* If relax, symbol value may change at link time, so reloc need to be saved. */ - if (!LARCH_opts.relax) + fragS *addfrag = symbol_get_frag (fixP->fx_addsy); + if (! _loongarch_force_relocation_sub_same (seg, + addfrag, + fixP->fx_frag)) fixP->fx_done = 1; } break; @@ -2074,6 +2126,8 @@ loongarch_pre_output_hook (void) frag chains have been chained together. */ subseg_set (s, frch->frch_subseg); + /* Set the size to 1 temporary. The size may change in + relax_segment. Update to the real size in md_apply_fix. */ fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, BFD_RELOC_LARCH_CFA); } @@ -2138,6 +2192,10 @@ loongarch_frag_align_code (int n, int max) frag_wane (frag_now); frag_new (0); + /* Mark the current section and frag as linker relaxable. */ + now_seg->sec_flg1 = true; + frag_now->tc_frag_data.linker_relax = true; + /* If max <= 0, ignore max. If max >= worst_case_bytes, max has no effect. Similar to gas/write.c relax_segment function rs_align_code case: @@ -2227,6 +2285,24 @@ loongarch_handle_align (fragS *fragp) fragp->fr_var = size; } + +/* Whether force relocation for label subtraction calculation, + sincc linker relaxation might change the deltas. */ + +static bool +loongarch_force_reloc_sub (symbolS *addsy, symbolS *subsy) +{ + segT addsec = S_GET_SEGMENT (addsy); + segT subsec = S_GET_SEGMENT (subsy); + if (addsec != subsec) + return true; + + fragS *addfrag = symbol_get_frag (addsy); + fragS *subfrag = symbol_get_frag (subsy); + return _loongarch_force_relocation_sub_same (addsec, addfrag, subfrag); +} + + /* Scan uleb128 subtraction expressions and insert fixups for them. e.g., .uleb128 .L1 - .L0 Because relaxation may change the value of the subtraction, we @@ -2258,6 +2334,9 @@ loongarch_insert_uleb128_fixes (bfd *abfd ATTRIBUTE_UNUSED, if (fragP->fr_subtype != 0) continue; + if (! loongarch_force_reloc_sub (exp->X_add_symbol, exp->X_op_symbol)) + continue; + exp_dup = xmemdup (exp, sizeof (*exp), sizeof (*exp)); exp_dup->X_op = O_symbol; exp_dup->X_op_symbol = NULL; diff --git a/gas/config/tc-loongarch.h b/gas/config/tc-loongarch.h index 5587ac1bb86..146844e772e 100644 --- a/gas/config/tc-loongarch.h +++ b/gas/config/tc-loongarch.h @@ -148,4 +148,15 @@ extern void loongarch_md_finish (void); /* The target supports Object Attributes v1. */ #define TC_OBJ_ATTR_v1 1 + +/* Define target fragment type. */ +#define TC_FRAG_TYPE struct loongarch_frag_type +struct loongarch_frag_type +{ + bool linker_relax; +}; + +#define TC_FRAG_INIT(FRAGP, MAX_BYTES) \ + do { (FRAGP)->tc_frag_data.linker_relax = false; } while (0) + #endif diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp index 940df901167..46451fb5a90 100644 --- a/gas/testsuite/gas/all/gas.exp +++ b/gas/testsuite/gas/all/gas.exp @@ -293,7 +293,7 @@ if { ![istarget *c30*-*-*] && ![istarget h8300*-*-*] && ![istarget hppa*-*-*] } then { # msp430, mn10[23]00 and riscv emit two relocs to handle the difference of two symbols. - setup_xfail "am3*-*-*" "loongarch*-*-*" "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "riscv*-*-*" + setup_xfail "am3*-*-*" "mn10200-*-*" "mn10300*-*-*" "msp430*-*-*" "riscv*-*-*" do_930509a } diff --git a/gas/testsuite/gas/all/relax.d b/gas/testsuite/gas/all/relax.d index 00fba6d62cd..f394043b017 100644 --- a/gas/testsuite/gas/all/relax.d +++ b/gas/testsuite/gas/all/relax.d @@ -4,10 +4,6 @@ # because symbol values are not known until after linker relaxation has been # performed. #notarget : riscv*-*-* -# LoongArch doesn't resolve .uleb operands that are the difference of two -# symbols because gas write zero to object file and generate add_uleb128 and -# sub_uleb128 reloc pair. -#xfail: loongarch*-*-* .*: .* diff --git a/gas/testsuite/gas/loongarch/insn_int32.d b/gas/testsuite/gas/loongarch/insn_int32.d index d90dbe402c4..43a7f05be6c 100644 --- a/gas/testsuite/gas/loongarch/insn_int32.d +++ b/gas/testsuite/gas/loongarch/insn_int32.d @@ -2,146 +2,139 @@ #objdump: -d -M no-aliases #skip: loongarch64-*-* -.*: file format .* - - -Disassembly of section .text: - -0+ <.*>: - 0: 020000a4 slti \$a0, \$a1, 0 - 4: 021ffca4 slti \$a0, \$a1, 2047 - 8: 022004a4 slti \$a0, \$a1, -2047 - c: 024000a4 sltui \$a0, \$a1, 0 - 10: 025ffca4 sltui \$a0, \$a1, 2047 - 14: 026004a4 sltui \$a0, \$a1, -2047 - 18: 028000a4 addi.w \$a0, \$a1, 0 - 1c: 029ffca4 addi.w \$a0, \$a1, 2047 - 20: 02a004a4 addi.w \$a0, \$a1, -2047 - 24: 034000a4 andi \$a0, \$a1, 0x0 - 28: 035ffca4 andi \$a0, \$a1, 0x7ff - 2c: 038000a4 ori \$a0, \$a1, 0x0 - 30: 039ffca4 ori \$a0, \$a1, 0x7ff - 34: 03c000a4 xori \$a0, \$a1, 0x0 - 38: 03dffca4 xori \$a0, \$a1, 0x7ff - 3c: 14000004 lu12i.w \$a0, 0 - 40: 14ffffe4 lu12i.w \$a0, 524287 - 44: 1c000004 pcaddu12i \$a0, 0 - 48: 1cffffe4 pcaddu12i \$a0, 524287 - 4c: 1d000024 pcaddu12i \$a0, -524287 - 50: 0004b58b alsl.w \$a7, \$t0, \$t1, 0x2 - 54: 0006b58b alsl.wu \$a7, \$t0, \$t1, 0x2 - 58: 002a0002 break 0x2 - 5c: 002a8002 dbcl 0x2 - 60: 002b0002 syscall 0x2 - 64: 0040898b slli.w \$a7, \$t0, 0x2 - 68: 0044898b srli.w \$a7, \$t0, 0x2 - 6c: 004889ac srai.w \$t0, \$t1, 0x2 - 70: 02048dac slti \$t0, \$t1, 291 - 74: 02448dac sltui \$t0, \$t1, 291 - 78: 02848dac addi.w \$t0, \$t1, 291 - 7c: 034009ac andi \$t0, \$t1, 0x2 - 80: 038009ac ori \$t0, \$t1, 0x2 - 84: 03c009ac xori \$t0, \$t1, 0x2 - 88: 1400246c lu12i.w \$t0, 291 - 8c: 1c00246c pcaddu12i \$t0, 291 - 90: 04048c0c csrrd \$t0, 0x123 - 94: 04048c2c csrwr \$t0, 0x123 - 98: 040009ac csrxchg \$t0, \$t1, 0x2 - 9c: 060009a2 cacop 0x2, \$t1, 2 - a0: 064009ac lddir \$t0, \$t1, 0x2 - a4: 06440980 ldpte \$t0, 0x2 - a8: 0649b9a2 invtlb 0x2, \$t1, \$t2 - ac: 000060a4 rdtimel.w \$a0, \$a1 - b0: 000064a4 rdtimeh.w \$a0, \$a1 - b4: 000418a4 alsl.w \$a0, \$a1, \$a2, 0x1 - b8: 000598a4 alsl.w \$a0, \$a1, \$a2, 0x4 - bc: 000618a4 alsl.wu \$a0, \$a1, \$a2, 0x1 - c0: 000798a4 alsl.wu \$a0, \$a1, \$a2, 0x4 - c4: 001018a4 add.w \$a0, \$a1, \$a2 - c8: 001118a4 sub.w \$a0, \$a1, \$a2 - cc: 001218a4 slt \$a0, \$a1, \$a2 - d0: 001298a4 sltu \$a0, \$a1, \$a2 - d4: 001418a4 nor \$a0, \$a1, \$a2 - d8: 001498a4 and \$a0, \$a1, \$a2 - dc: 001518a4 or \$a0, \$a1, \$a2 - e0: 001598a4 xor \$a0, \$a1, \$a2 - e4: 001718a4 sll.w \$a0, \$a1, \$a2 - e8: 001798a4 srl.w \$a0, \$a1, \$a2 - ec: 001818a4 sra.w \$a0, \$a1, \$a2 - f0: 001c18a4 mul.w \$a0, \$a1, \$a2 - f4: 001c98a4 mulh.w \$a0, \$a1, \$a2 - f8: 001d18a4 mulh.wu \$a0, \$a1, \$a2 - fc: 002018a4 div.w \$a0, \$a1, \$a2 - 100: 002098a4 mod.w \$a0, \$a1, \$a2 - 104: 002118a4 div.wu \$a0, \$a1, \$a2 - 108: 002198a4 mod.wu \$a0, \$a1, \$a2 - 10c: 002a0000 break 0x0 - 110: 002a7fff break 0x7fff - 114: 002a8000 dbcl 0x0 - 118: 002affff dbcl 0x7fff - 11c: 004080a4 slli.w \$a0, \$a1, 0x0 - 120: 004084a4 slli.w \$a0, \$a1, 0x1 - 124: 0040fca4 slli.w \$a0, \$a1, 0x1f - 128: 004480a4 srli.w \$a0, \$a1, 0x0 - 12c: 004484a4 srli.w \$a0, \$a1, 0x1 - 130: 0044fca4 srli.w \$a0, \$a1, 0x1f - 134: 004880a4 srai.w \$a0, \$a1, 0x0 - 138: 004884a4 srai.w \$a0, \$a1, 0x1 - 13c: 0048fca4 srai.w \$a0, \$a1, 0x1f - 140: 200000a4 ll.w \$a0, \$a1, 0 - 144: 203ffca4 ll.w \$a0, \$a1, 16380 - 148: 210000a4 sc.w \$a0, \$a1, 0 - 14c: 213ffca4 sc.w \$a0, \$a1, 16380 - 150: 280000a4 ld.b \$a0, \$a1, 0 - 154: 281ffca4 ld.b \$a0, \$a1, 2047 - 158: 282004a4 ld.b \$a0, \$a1, -2047 - 15c: 284000a4 ld.h \$a0, \$a1, 0 - 160: 285ffca4 ld.h \$a0, \$a1, 2047 - 164: 286004a4 ld.h \$a0, \$a1, -2047 - 168: 288000a4 ld.w \$a0, \$a1, 0 - 16c: 289ffca4 ld.w \$a0, \$a1, 2047 - 170: 28a004a4 ld.w \$a0, \$a1, -2047 - 174: 290000a4 st.b \$a0, \$a1, 0 - 178: 291ffca4 st.b \$a0, \$a1, 2047 - 17c: 292004a4 st.b \$a0, \$a1, -2047 - 180: 294000a4 st.h \$a0, \$a1, 0 - 184: 295ffca4 st.h \$a0, \$a1, 2047 - 188: 296004a4 st.h \$a0, \$a1, -2047 - 18c: 298000a4 st.w \$a0, \$a1, 0 - 190: 299ffca4 st.w \$a0, \$a1, 2047 - 194: 29a004a4 st.w \$a0, \$a1, -2047 - 198: 2a0000a4 ld.bu \$a0, \$a1, 0 - 19c: 2a1ffca4 ld.bu \$a0, \$a1, 2047 - 1a0: 2a2004a4 ld.bu \$a0, \$a1, -2047 - 1a4: 2a4000a4 ld.hu \$a0, \$a1, 0 - 1a8: 2a5ffca4 ld.hu \$a0, \$a1, 2047 - 1ac: 2a6004a4 ld.hu \$a0, \$a1, -2047 - 1b0: 2ac000a0 preld 0x0, \$a1, 0 - 1b4: 2adffcbf preld 0x1f, \$a1, 2047 - 1b8: 2ae004bf preld 0x1f, \$a1, -2047 - 1bc: 385714c4 sc.q \$a0, \$a1, \$a2 - 1c0: 385714c4 sc.q \$a0, \$a1, \$a2 - 1c4: 385780a4 llacq.w \$a0, \$a1 - 1c8: 385780a4 llacq.w \$a0, \$a1 - 1cc: 385784a4 screl.w \$a0, \$a1 - 1d0: 385784a4 screl.w \$a0, \$a1 - 1d4: 38720000 dbar 0x0 - 1d8: 38727fff dbar 0x7fff - 1dc: 38728000 ibar 0x0 - 1e0: 3872ffff ibar 0x7fff - -0+1e4 <.L1>: - 1e4: 03400000 andi \$zero, \$zero, 0x0 - 1e8: 53ffffff b -4 # 1e4 <.L1> - 1ec: 57fffbff bl -8 # 1e4 <.L1> - 1f0: 5bfff485 beq \$a0, \$a1, -12 # 1e4 <.L1> - 1f4: 5ffff085 bne \$a0, \$a1, -16 # 1e4 <.L1> - 1f8: 63ffec85 blt \$a0, \$a1, -20 # 1e4 <.L1> - 1fc: 63ffe8a4 blt \$a1, \$a0, -24 # 1e4 <.L1> - 200: 67ffe485 bge \$a0, \$a1, -28 # 1e4 <.L1> - 204: 67ffe0a4 bge \$a1, \$a0, -32 # 1e4 <.L1> - 208: 6bffdc85 bltu \$a0, \$a1, -36 # 1e4 <.L1> - 20c: 6bffd8a4 bltu \$a1, \$a0, -40 # 1e4 <.L1> - 210: 6fffd485 bgeu \$a0, \$a1, -44 # 1e4 <.L1> - 214: 6fffd0a4 bgeu \$a1, \$a0, -48 # 1e4 <.L1> - 218: 4c000080 jirl \$zero, \$a0, 0 +#... +[ ]+0:[ ]+020000a4[ ]+slti[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+4:[ ]+021ffca4[ ]+slti[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+8:[ ]+022004a4[ ]+slti[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+c:[ ]+024000a4[ ]+sltui[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+10:[ ]+025ffca4[ ]+sltui[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+14:[ ]+026004a4[ ]+sltui[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+18:[ ]+028000a4[ ]+addi.w[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+1c:[ ]+029ffca4[ ]+addi.w[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+20:[ ]+02a004a4[ ]+addi.w[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+24:[ ]+034000a4[ ]+andi[ ]+\$a0,[ ]+\$a1,[ ]+0x0 +[ ]+28:[ ]+035ffca4[ ]+andi[ ]+\$a0,[ ]+\$a1,[ ]+0x7ff +[ ]+2c:[ ]+038000a4[ ]+ori[ ]+\$a0,[ ]+\$a1,[ ]+0x0 +[ ]+30:[ ]+039ffca4[ ]+ori[ ]+\$a0,[ ]+\$a1,[ ]+0x7ff +[ ]+34:[ ]+03c000a4[ ]+xori[ ]+\$a0,[ ]+\$a1,[ ]+0x0 +[ ]+38:[ ]+03dffca4[ ]+xori[ ]+\$a0,[ ]+\$a1,[ ]+0x7ff +[ ]+3c:[ ]+14000004[ ]+lu12i.w[ ]+\$a0,[ ]+0 +[ ]+40:[ ]+14ffffe4[ ]+lu12i.w[ ]+\$a0,[ ]+524287 +[ ]+44:[ ]+1c000004[ ]+pcaddu12i[ ]+\$a0,[ ]+0 +[ ]+48:[ ]+1cffffe4[ ]+pcaddu12i[ ]+\$a0,[ ]+524287 +[ ]+4c:[ ]+1d000024[ ]+pcaddu12i[ ]+\$a0,[ ]+-524287 +[ ]+50:[ ]+0004b58b[ ]+alsl.w[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+54:[ ]+0006b58b[ ]+alsl.wu[ ]+\$a7,[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+58:[ ]+002a0002[ ]+break[ ]+0x2 +[ ]+5c:[ ]+002a8002[ ]+dbcl[ ]+0x2 +[ ]+60:[ ]+002b0002[ ]+syscall[ ]+0x2 +[ ]+64:[ ]+0040898b[ ]+slli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 +[ ]+68:[ ]+0044898b[ ]+srli.w[ ]+\$a7,[ ]+\$t0,[ ]+0x2 +[ ]+6c:[ ]+004889ac[ ]+srai.w[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+70:[ ]+02048dac[ ]+slti[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+74:[ ]+02448dac[ ]+sltui[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+78:[ ]+02848dac[ ]+addi.w[ ]+\$t0,[ ]+\$t1,[ ]+291 +[ ]+7c:[ ]+034009ac[ ]+andi[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+80:[ ]+038009ac[ ]+ori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+84:[ ]+03c009ac[ ]+xori[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+88:[ ]+1400246c[ ]+lu12i.w[ ]+\$t0,[ ]+291 +[ ]+8c:[ ]+1c00246c[ ]+pcaddu12i[ ]+\$t0,[ ]+291 +[ ]+90:[ ]+04048c0c[ ]+csrrd[ ]+\$t0,[ ]+0x123 +[ ]+94:[ ]+04048c2c[ ]+csrwr[ ]+\$t0,[ ]+0x123 +[ ]+98:[ ]+040009ac[ ]+csrxchg[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+9c:[ ]+060009a2[ ]+cacop[ ]+0x2,[ ]+\$t1,[ ]+2 +[ ]+a0:[ ]+064009ac[ ]+lddir[ ]+\$t0,[ ]+\$t1,[ ]+0x2 +[ ]+a4:[ ]+06440980[ ]+ldpte[ ]+\$t0,[ ]+0x2 +[ ]+a8:[ ]+0649b9a2[ ]+invtlb[ ]+0x2,[ ]+\$t1,[ ]+\$t2 +[ ]+ac:[ ]+000060a4[ ]+rdtimel.w[ ]+\$a0,[ ]+\$a1 +[ ]+b0:[ ]+000064a4[ ]+rdtimeh.w[ ]+\$a0,[ ]+\$a1 +[ ]+b4:[ ]+000418a4[ ]+alsl.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2,[ ]+0x1 +[ ]+b8:[ ]+000598a4[ ]+alsl.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2,[ ]+0x4 +[ ]+bc:[ ]+000618a4[ ]+alsl.wu[ ]+\$a0,[ ]+\$a1,[ ]+\$a2,[ ]+0x1 +[ ]+c0:[ ]+000798a4[ ]+alsl.wu[ ]+\$a0,[ ]+\$a1,[ ]+\$a2,[ ]+0x4 +[ ]+c4:[ ]+001018a4[ ]+add.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+c8:[ ]+001118a4[ ]+sub.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+cc:[ ]+001218a4[ ]+slt[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+d0:[ ]+001298a4[ ]+sltu[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+d4:[ ]+001418a4[ ]+nor[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+d8:[ ]+001498a4[ ]+and[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+dc:[ ]+001518a4[ ]+or[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+e0:[ ]+001598a4[ ]+xor[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+e4:[ ]+001718a4[ ]+sll.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+e8:[ ]+001798a4[ ]+srl.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+ec:[ ]+001818a4[ ]+sra.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+f0:[ ]+001c18a4[ ]+mul.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+f4:[ ]+001c98a4[ ]+mulh.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+f8:[ ]+001d18a4[ ]+mulh.wu[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+fc:[ ]+002018a4[ ]+div.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+100:[ ]+002098a4[ ]+mod.w[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+104:[ ]+002118a4[ ]+div.wu[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+108:[ ]+002198a4[ ]+mod.wu[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+10c:[ ]+002a0000[ ]+break[ ]+0x0 +[ ]+110:[ ]+002a7fff[ ]+break[ ]+0x7fff +[ ]+114:[ ]+002a8000[ ]+dbcl[ ]+0x0 +[ ]+118:[ ]+002affff[ ]+dbcl[ ]+0x7fff +[ ]+11c:[ ]+004080a4[ ]+slli.w[ ]+\$a0,[ ]+\$a1,[ ]+0x0 +[ ]+120:[ ]+004084a4[ ]+slli.w[ ]+\$a0,[ ]+\$a1,[ ]+0x1 +[ ]+124:[ ]+0040fca4[ ]+slli.w[ ]+\$a0,[ ]+\$a1,[ ]+0x1f +[ ]+128:[ ]+004480a4[ ]+srli.w[ ]+\$a0,[ ]+\$a1,[ ]+0x0 +[ ]+12c:[ ]+004484a4[ ]+srli.w[ ]+\$a0,[ ]+\$a1,[ ]+0x1 +[ ]+130:[ ]+0044fca4[ ]+srli.w[ ]+\$a0,[ ]+\$a1,[ ]+0x1f +[ ]+134:[ ]+004880a4[ ]+srai.w[ ]+\$a0,[ ]+\$a1,[ ]+0x0 +[ ]+138:[ ]+004884a4[ ]+srai.w[ ]+\$a0,[ ]+\$a1,[ ]+0x1 +[ ]+13c:[ ]+0048fca4[ ]+srai.w[ ]+\$a0,[ ]+\$a1,[ ]+0x1f +[ ]+140:[ ]+200000a4[ ]+ll.w[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+144:[ ]+203ffca4[ ]+ll.w[ ]+\$a0,[ ]+\$a1,[ ]+16380 +[ ]+148:[ ]+210000a4[ ]+sc.w[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+14c:[ ]+213ffca4[ ]+sc.w[ ]+\$a0,[ ]+\$a1,[ ]+16380 +[ ]+150:[ ]+280000a4[ ]+ld.b[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+154:[ ]+281ffca4[ ]+ld.b[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+158:[ ]+282004a4[ ]+ld.b[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+15c:[ ]+284000a4[ ]+ld.h[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+160:[ ]+285ffca4[ ]+ld.h[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+164:[ ]+286004a4[ ]+ld.h[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+168:[ ]+288000a4[ ]+ld.w[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+16c:[ ]+289ffca4[ ]+ld.w[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+170:[ ]+28a004a4[ ]+ld.w[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+174:[ ]+290000a4[ ]+st.b[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+178:[ ]+291ffca4[ ]+st.b[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+17c:[ ]+292004a4[ ]+st.b[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+180:[ ]+294000a4[ ]+st.h[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+184:[ ]+295ffca4[ ]+st.h[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+188:[ ]+296004a4[ ]+st.h[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+18c:[ ]+298000a4[ ]+st.w[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+190:[ ]+299ffca4[ ]+st.w[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+194:[ ]+29a004a4[ ]+st.w[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+198:[ ]+2a0000a4[ ]+ld.bu[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+19c:[ ]+2a1ffca4[ ]+ld.bu[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+1a0:[ ]+2a2004a4[ ]+ld.bu[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+1a4:[ ]+2a4000a4[ ]+ld.hu[ ]+\$a0,[ ]+\$a1,[ ]+0 +[ ]+1a8:[ ]+2a5ffca4[ ]+ld.hu[ ]+\$a0,[ ]+\$a1,[ ]+2047 +[ ]+1ac:[ ]+2a6004a4[ ]+ld.hu[ ]+\$a0,[ ]+\$a1,[ ]+-2047 +[ ]+1b0:[ ]+2ac000a0[ ]+preld[ ]+0x0,[ ]+\$a1,[ ]+0 +[ ]+1b4:[ ]+2adffcbf[ ]+preld[ ]+0x1f,[ ]+\$a1,[ ]+2047 +[ ]+1b8:[ ]+2ae004bf[ ]+preld[ ]+0x1f,[ ]+\$a1,[ ]+-2047 +[ ]+1bc:[ ]+385714c4[ ]+sc.q[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+1c0:[ ]+385714c4[ ]+sc.q[ ]+\$a0,[ ]+\$a1,[ ]+\$a2 +[ ]+1c4:[ ]+385780a4[ ]+llacq.w[ ]+\$a0,[ ]+\$a1 +[ ]+1c8:[ ]+385780a4[ ]+llacq.w[ ]+\$a0,[ ]+\$a1 +[ ]+1cc:[ ]+385784a4[ ]+screl.w[ ]+\$a0,[ ]+\$a1 +[ ]+1d0:[ ]+385784a4[ ]+screl.w[ ]+\$a0,[ ]+\$a1 +[ ]+1d4:[ ]+38720000[ ]+dbar[ ]+0x0 +[ ]+1d8:[ ]+38727fff[ ]+dbar[ ]+0x7fff +[ ]+1dc:[ ]+38728000[ ]+ibar[ ]+0x0 +[ ]+1e0:[ ]+3872ffff[ ]+ibar[ ]+0x7fff +[ ]+1e4:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0 +[ ]+1e8:[ ]+53ffffff[ ]+b[ ]+-4[ ]+#[ ]+1e4[ ]+ +[ ]+1ec:[ ]+57fffbff[ ]+bl[ ]+-8[ ]+#[ ]+1e4[ ]+ +[ ]+1f0:[ ]+5bfff485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-12[ ]+#[ ]+1e4[ ]+ +[ ]+1f4:[ ]+5ffff085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-16[ ]+#[ ]+1e4[ ]+ +[ ]+1f8:[ ]+63ffec85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-20[ ]+#[ ]+1e4[ ]+ +[ ]+1fc:[ ]+63ffe8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-24[ ]+#[ ]+1e4[ ]+ +[ ]+200:[ ]+67ffe485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-28[ ]+#[ ]+1e4[ ]+ +[ ]+204:[ ]+67ffe0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-32[ ]+#[ ]+1e4[ ]+ +[ ]+208:[ ]+6bffdc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-36[ ]+#[ ]+1e4[ ]+ +[ ]+20c:[ ]+6bffd8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-40[ ]+#[ ]+1e4[ ]+ +[ ]+210:[ ]+6fffd485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-44[ ]+#[ ]+1e4[ ]+ +[ ]+214:[ ]+6fffd0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-48[ ]+#[ ]+1e4[ ]+ +[ ]+218:[ ]+4c000080[ ]+jirl[ ]+\$zero,[ ]+\$a0,[ ]+0 diff --git a/gas/testsuite/gas/loongarch/insn_int64.d b/gas/testsuite/gas/loongarch/insn_int64.d index 360b840d415..dcfeaac8e52 100644 --- a/gas/testsuite/gas/loongarch/insn_int64.d +++ b/gas/testsuite/gas/loongarch/insn_int64.d @@ -411,20 +411,19 @@ Disassembly of section .text: 640: 385f94c4 amadd_db.h \$a0, \$a1, \$a2 644: 385f98a4 amadd_db.h \$a0, \$a2, \$a1 -0+648 <.L1>: 648: 03400000 andi \$zero, \$zero, 0x0 - 64c: 43fffc9f beqz \$a0, -4 # 648 <.L1> - 650: 47fff89f bnez \$a0, -8 # 648 <.L1> - 654: 53fff7ff b -12 # 648 <.L1> - 658: 57fff3ff bl -16 # 648 <.L1> - 65c: 5bffec85 beq \$a0, \$a1, -20 # 648 <.L1> - 660: 5fffe885 bne \$a0, \$a1, -24 # 648 <.L1> - 664: 63ffe485 blt \$a0, \$a1, -28 # 648 <.L1> - 668: 63ffe0a4 blt \$a1, \$a0, -32 # 648 <.L1> - 66c: 67ffdc85 bge \$a0, \$a1, -36 # 648 <.L1> - 670: 67ffd8a4 bge \$a1, \$a0, -40 # 648 <.L1> - 674: 6bffd485 bltu \$a0, \$a1, -44 # 648 <.L1> - 678: 6bffd0a4 bltu \$a1, \$a0, -48 # 648 <.L1> - 67c: 6fffcc85 bgeu \$a0, \$a1, -52 # 648 <.L1> - 680: 6fffc8a4 bgeu \$a1, \$a0, -56 # 648 <.L1> + 64c: 43fffc9f beqz \$a0, -4.* + 650: 47fff89f bnez \$a0, -8.* + 654: 53fff7ff b -12.* + 658: 57fff3ff bl -16.* + 65c: 5bffec85 beq \$a0, \$a1, -20.* + 660: 5fffe885 bne \$a0, \$a1, -24.* + 664: 63ffe485 blt \$a0, \$a1, -28.* + 668: 63ffe0a4 blt \$a1, \$a0, -32.* + 66c: 67ffdc85 bge \$a0, \$a1, -36.* + 670: 67ffd8a4 bge \$a1, \$a0, -40.* + 674: 6bffd485 bltu \$a0, \$a1, -44.* + 678: 6bffd0a4 bltu \$a1, \$a0, -48.* + 67c: 6fffcc85 bgeu \$a0, \$a1, -52.* + 680: 6fffc8a4 bgeu \$a1, \$a0, -56.* 684: 4c000080 jirl \$zero, \$a0, 0 diff --git a/gas/testsuite/gas/loongarch/jmp_op.d b/gas/testsuite/gas/loongarch/jmp_op.d index 21576072aab..1a552b2c7b5 100644 --- a/gas/testsuite/gas/loongarch/jmp_op.d +++ b/gas/testsuite/gas/loongarch/jmp_op.d @@ -1,50 +1,48 @@ -#as: +#as: -mrelax #objdump: -dr -.*:[ ]+file format .* - - -Disassembly of section .text: - -00000000.* <.L1>: -[ ]+0:[ ]+03400000[ ]+nop -[ ]+4:[ ]+63fffc04[ ]+bgtz[ ]+\$a0,[ ]+-4[ ]+#[ ]+0[ ]+<\.L1> -[ ]+4:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+8:[ ]+67fff880[ ]+bgez[ ]+\$a0,[ ]+-8[ ]+#[ ]+0[ ]+<\.L1> -[ ]+8:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+c:[ ]+67fff404[ ]+blez[ ]+\$a0,[ ]+-12[ ]+#[ ]+0[ ]+<\.L1> -[ ]+c:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16[ ]+#[ ]+0[ ]+<\.L1> -[ ]+10:[ ]+R_LARCH_B21[ ]+\.L1 -[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20[ ]+#[ ]+0[ ]+<\.L1> -[ ]+14:[ ]+R_LARCH_B21[ ]+\.L1 -[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24[ ]+#[ ]+0[ ]+<\.L1> -[ ]+18:[ ]+R_LARCH_B21[ ]+\.L1 -[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28[ ]+#[ ]+0[ ]+<\.L1> -[ ]+1c:[ ]+R_LARCH_B21[ ]+\.L1 -[ ]+20:[ ]+4c000080[ ]+jr[ ]+\$a0 -[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36[ ]+#[ ]+0[ ]+<\.L1> -[ ]+24:[ ]+R_LARCH_B26[ ]+\.L1 -[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40[ ]+#[ ]+0[ ]+<\.L1> -[ ]+28:[ ]+R_LARCH_B26[ ]+\.L1 -[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44[ ]+#[ ]+0[ ]+<\.L1> -[ ]+2c:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48[ ]+#[ ]+0[ ]+<\.L1> -[ ]+30:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52[ ]+#[ ]+0[ ]+<\.L1> -[ ]+34:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56[ ]+#[ ]+0[ ]+<\.L1> -[ ]+38:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60[ ]+#[ ]+0[ ]+<\.L1> -[ ]+3c:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64[ ]+#[ ]+0[ ]+<\.L1> -[ ]+40:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68[ ]+#[ ]+0[ ]+<\.L1> -[ ]+44:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72[ ]+#[ ]+0[ ]+<\.L1> -[ ]+48:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76[ ]+#[ ]+0[ ]+<\.L1> -[ ]+4c:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80[ ]+#[ ]+0[ ]+<\.L1> -[ ]+50:[ ]+R_LARCH_B16[ ]+\.L1 -[ ]+54:[ ]+4c000020[ ]+ret +#... +[ ]+0:[ ]+1e000001[ ]+pcaddu18i[ ]+\$ra,[ ]+0 +[ ]+0:[ ]+R_LARCH_CALL36[ ]+.L1 +[ ]+0:[ ]+R_LARCH_RELAX[ ]+\*ABS\* +[ ]+4:[ ]+4c000021[ ]+jirl[ ]+\$ra,[ ]+\$ra,[ ]+0 +[ ]+8:[ ]+63fff804[ ]+bgtz[ ]+\$a0,[ ]+-8[ ]+#[ ]+0[ ]+<.L1> +[ ]+8:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+c:[ ]+67fff480[ ]+bgez[ ]+\$a0,[ ]+-12[ ]+#[ ]+0[ ]+<.L1> +[ ]+c:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+10:[ ]+67fff004[ ]+blez[ ]+\$a0,[ ]+-16[ ]+#[ ]+0[ ]+<.L1> +[ ]+10:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+14:[ ]+43ffec9f[ ]+beqz[ ]+\$a0,[ ]+-20[ ]+#[ ]+0[ ]+<.L1> +[ ]+14:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+18:[ ]+47ffe89f[ ]+bnez[ ]+\$a0,[ ]+-24[ ]+#[ ]+0[ ]+<.L1> +[ ]+18:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+1c:[ ]+4bffe41f[ ]+bceqz[ ]+\$fcc0,[ ]+-28[ ]+#[ ]+0[ ]+<.L1> +[ ]+1c:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+20:[ ]+4bffe11f[ ]+bcnez[ ]+\$fcc0,[ ]+-32[ ]+#[ ]+0[ ]+<.L1> +[ ]+20:[ ]+R_LARCH_B21[ ]+.L1 +[ ]+24:[ ]+4c000080[ ]+jr[ ]+\$a0 +[ ]+28:[ ]+53ffdbff[ ]+b[ ]+-40[ ]+#[ ]+0[ ]+<.L1> +[ ]+28:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+2c:[ ]+57ffd7ff[ ]+bl[ ]+-44[ ]+#[ ]+0[ ]+<.L1> +[ ]+2c:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+30:[ ]+5bffd085[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-48[ ]+#[ ]+0[ ]+<.L1> +[ ]+30:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+34:[ ]+5fffcc85[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-52[ ]+#[ ]+0[ ]+<.L1> +[ ]+34:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+38:[ ]+63ffc885[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-56[ ]+#[ ]+0[ ]+<.L1> +[ ]+38:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+3c:[ ]+63ffc4a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-60[ ]+#[ ]+0[ ]+<.L1> +[ ]+3c:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+40:[ ]+67ffc085[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-64[ ]+#[ ]+0[ ]+<.L1> +[ ]+40:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+44:[ ]+67ffbca4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-68[ ]+#[ ]+0[ ]+<.L1> +[ ]+44:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+48:[ ]+6bffb885[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-72[ ]+#[ ]+0[ ]+<.L1> +[ ]+48:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+4c:[ ]+6bffb4a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-76[ ]+#[ ]+0[ ]+<.L1> +[ ]+4c:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+50:[ ]+6fffb085[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-80[ ]+#[ ]+0[ ]+<.L1> +[ ]+50:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+54:[ ]+6fffaca4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-84[ ]+#[ ]+0[ ]+<.L1> +[ ]+54:[ ]+R_LARCH_B16[ ]+.L1 +[ ]+58:[ ]+4c000020[ ]+ret diff --git a/gas/testsuite/gas/loongarch/jmp_op.s b/gas/testsuite/gas/loongarch/jmp_op.s index 56f986784e2..9630ca82a6f 100644 --- a/gas/testsuite/gas/loongarch/jmp_op.s +++ b/gas/testsuite/gas/loongarch/jmp_op.s @@ -1,5 +1,5 @@ .L1: -nop +call36 .L1 bgtz $r4,.L1 bgez $r4,.L1 blez $r4,.L1 diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_1.d b/gas/testsuite/gas/loongarch/la_branch_relax_1.d index 7984b6dfca5..b2c90641267 100644 --- a/gas/testsuite/gas/loongarch/la_branch_relax_1.d +++ b/gas/testsuite/gas/loongarch/la_branch_relax_1.d @@ -1,64 +1,58 @@ -#as: +#as: -mrelax #objdump: -dr -.*:[ ]+file format .* - - -Disassembly of section .text: - -0* <.L1>: -[ ]+... -[ ]+48d158:[ ]+5c00098d[ ]+bne[ ]+\$t0, \$t1, 8[ ]+# 48d160 <.L1\+0x48d160> -[ ]+48d15c:[ ]+532ea7ed[ ]+b[ ]+-4772188[ ]+# 0 <.L1> -[ ]+48d15c: R_LARCH_B26[ ]+.L1 -[ ]+48d160:[ ]+5800098d[ ]+beq[ ]+\$t0, \$t1, 8[ ]+# 48d168 <.L1\+0x48d168> -[ ]+48d164:[ ]+532e9fed[ ]+b[ ]+-4772196[ ]+# 0 <.L1> -[ ]+48d164: R_LARCH_B26[ ]+.L1 -[ ]+48d168:[ ]+6400098d[ ]+bge[ ]+\$t0, \$t1, 8[ ]+# 48d170 <.L1\+0x48d170> -[ ]+48d16c:[ ]+532e97ed[ ]+b[ ]+-4772204[ ]+# 0 <.L1> -[ ]+48d16c: R_LARCH_B26[ ]+.L1 -[ ]+48d170:[ ]+640009ac[ ]+bge[ ]+\$t1, \$t0, 8[ ]+# 48d178 <.L1\+0x48d178> -[ ]+48d174:[ ]+532e8fed[ ]+b[ ]+-4772212[ ]+# 0 <.L1> -[ ]+48d174: R_LARCH_B26[ ]+.L1 -[ ]+48d178:[ ]+64000980[ ]+bgez[ ]+\$t0, 8[ ]+# 48d180 <.L1\+0x48d180> -[ ]+48d17c:[ ]+532e87ed[ ]+b[ ]+-4772220[ ]+# 0 <.L1> -[ ]+48d17c: R_LARCH_B26[ ]+.L1 -[ ]+48d180:[ ]+6400080c[ ]+blez[ ]+\$t0, 8[ ]+# 48d188 <.L1\+0x48d188> -[ ]+48d184:[ ]+532e7fed[ ]+b[ ]+-4772228[ ]+# 0 <.L1> -[ ]+48d184: R_LARCH_B26[ ]+.L1 -[ ]+48d188:[ ]+600009ac[ ]+blt[ ]+\$t1, \$t0, 8[ ]+# 48d190 <.L1\+0x48d190> -[ ]+48d18c:[ ]+532e77ed[ ]+b[ ]+-4772236[ ]+# 0 <.L1> -[ ]+48d18c: R_LARCH_B26[ ]+.L1 -[ ]+48d190:[ ]+6000098d[ ]+blt[ ]+\$t0, \$t1, 8[ ]+# 48d198 <.L1\+0x48d198> -[ ]+48d194:[ ]+532e6fed[ ]+b[ ]+-4772244[ ]+# 0 <.L1> -[ ]+48d194: R_LARCH_B26[ ]+.L1 -[ ]+48d198:[ ]+6000080c[ ]+bgtz[ ]+\$t0, 8[ ]+# 48d1a0 <.L1\+0x48d1a0> -[ ]+48d19c:[ ]+532e67ed[ ]+b[ ]+-4772252[ ]+# 0 <.L1> -[ ]+48d19c: R_LARCH_B26[ ]+.L1 -[ ]+48d1a0:[ ]+60000980[ ]+bltz[ ]+\$t0, 8[ ]+# 48d1a8 <.L1\+0x48d1a8> -[ ]+48d1a4:[ ]+532e5fed[ ]+b[ ]+-4772260[ ]+# 0 <.L1> -[ ]+48d1a4: R_LARCH_B26[ ]+.L1 -[ ]+48d1a8:[ ]+6c00098d[ ]+bgeu[ ]+\$t0, \$t1, 8[ ]+# 48d1b0 <.L1\+0x48d1b0> -[ ]+48d1ac:[ ]+532e57ed[ ]+b[ ]+-4772268[ ]+# 0 <.L1> -[ ]+48d1ac: R_LARCH_B26[ ]+.L1 -[ ]+48d1b0:[ ]+6c0009ac[ ]+bgeu[ ]+\$t1, \$t0, 8[ ]+# 48d1b8 <.L1\+0x48d1b8> -[ ]+48d1b4:[ ]+532e4fed[ ]+b[ ]+-4772276[ ]+# 0 <.L1> -[ ]+48d1b4: R_LARCH_B26[ ]+.L1 -[ ]+48d1b8:[ ]+680009ac[ ]+bltu[ ]+\$t1, \$t0, 8[ ]+# 48d1c0 <.L1\+0x48d1c0> -[ ]+48d1bc:[ ]+532e47ed[ ]+b[ ]+-4772284[ ]+# 0 <.L1> -[ ]+48d1bc: R_LARCH_B26[ ]+.L1 -[ ]+48d1c0:[ ]+6800098d[ ]+bltu[ ]+\$t0, \$t1, 8[ ]+# 48d1c8 <.L1\+0x48d1c8> -[ ]+48d1c4:[ ]+532e3fed[ ]+b[ ]+-4772292[ ]+# 0 <.L1> -[ ]+48d1c4: R_LARCH_B26[ ]+.L1 -[ ]+48d1c8:[ ]+44000980[ ]+bnez[ ]+\$t0, 8[ ]+# 48d1d0 <.L1\+0x48d1d0> -[ ]+48d1cc:[ ]+532e37ed[ ]+b[ ]+-4772300[ ]+# 0 <.L1> -[ ]+48d1cc: R_LARCH_B26[ ]+.L1 -[ ]+48d1d0:[ ]+40000980[ ]+beqz[ ]+\$t0, 8[ ]+# 48d1d8 <.L1\+0x48d1d8> -[ ]+48d1d4:[ ]+532e2fed[ ]+b[ ]+-4772308[ ]+# 0 <.L1> -[ ]+48d1d4: R_LARCH_B26[ ]+.L1 -[ ]+48d1d8:[ ]+48000900[ ]+bcnez[ ]+\$fcc0, 8[ ]+# 48d1e0 <.L1\+0x48d1e0> -[ ]+48d1dc:[ ]+532e27ed[ ]+b[ ]+-4772316[ ]+# 0 <.L1> -[ ]+48d1dc: R_LARCH_B26[ ]+.L1 -[ ]+48d1e0:[ ]+48000800[ ]+bceqz[ ]+\$fcc0, 8[ ]+# 48d1e8 <.L1\+0x48d1e8> -[ ]+48d1e4:[ ]+532e1fed[ ]+b[ ]+-4772324[ ]+# 0 <.L1> -[ ]+48d1e4: R_LARCH_B26[ ]+.L1 +#... +[ ]+48d160:[ ]+5c00098d[ ]+bne[ ]+\$t0,[ ]+\$t1,[ ]+8[ ]+#[ ]+48d168[ ]+<.L1\+0x48d168> +[ ]+48d164:[ ]+532e9fed[ ]+b[ ]+-4772196[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d164:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d168:[ ]+5800098d[ ]+beq[ ]+\$t0,[ ]+\$t1,[ ]+8[ ]+#[ ]+48d170[ ]+<.L1\+0x48d170> +[ ]+48d16c:[ ]+532e97ed[ ]+b[ ]+-4772204[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d16c:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d170:[ ]+6400098d[ ]+bge[ ]+\$t0,[ ]+\$t1,[ ]+8[ ]+#[ ]+48d178[ ]+<.L1\+0x48d178> +[ ]+48d174:[ ]+532e8fed[ ]+b[ ]+-4772212[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d174:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d178:[ ]+640009ac[ ]+bge[ ]+\$t1,[ ]+\$t0,[ ]+8[ ]+#[ ]+48d180[ ]+<.L1\+0x48d180> +[ ]+48d17c:[ ]+532e87ed[ ]+b[ ]+-4772220[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d17c:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d180:[ ]+64000980[ ]+bgez[ ]+\$t0,[ ]+8[ ]+#[ ]+48d188[ ]+<.L1\+0x48d188> +[ ]+48d184:[ ]+532e7fed[ ]+b[ ]+-4772228[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d184:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d188:[ ]+6400080c[ ]+blez[ ]+\$t0,[ ]+8[ ]+#[ ]+48d190[ ]+<.L1\+0x48d190> +[ ]+48d18c:[ ]+532e77ed[ ]+b[ ]+-4772236[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d18c:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d190:[ ]+600009ac[ ]+blt[ ]+\$t1,[ ]+\$t0,[ ]+8[ ]+#[ ]+48d198[ ]+<.L1\+0x48d198> +[ ]+48d194:[ ]+532e6fed[ ]+b[ ]+-4772244[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d194:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d198:[ ]+6000098d[ ]+blt[ ]+\$t0,[ ]+\$t1,[ ]+8[ ]+#[ ]+48d1a0[ ]+<.L1\+0x48d1a0> +[ ]+48d19c:[ ]+532e67ed[ ]+b[ ]+-4772252[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d19c:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1a0:[ ]+6000080c[ ]+bgtz[ ]+\$t0,[ ]+8[ ]+#[ ]+48d1a8[ ]+<.L1\+0x48d1a8> +[ ]+48d1a4:[ ]+532e5fed[ ]+b[ ]+-4772260[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1a4:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1a8:[ ]+60000980[ ]+bltz[ ]+\$t0,[ ]+8[ ]+#[ ]+48d1b0[ ]+<.L1\+0x48d1b0> +[ ]+48d1ac:[ ]+532e57ed[ ]+b[ ]+-4772268[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1ac:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1b0:[ ]+6c00098d[ ]+bgeu[ ]+\$t0,[ ]+\$t1,[ ]+8[ ]+#[ ]+48d1b8[ ]+<.L1\+0x48d1b8> +[ ]+48d1b4:[ ]+532e4fed[ ]+b[ ]+-4772276[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1b4:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1b8:[ ]+6c0009ac[ ]+bgeu[ ]+\$t1,[ ]+\$t0,[ ]+8[ ]+#[ ]+48d1c0[ ]+<.L1\+0x48d1c0> +[ ]+48d1bc:[ ]+532e47ed[ ]+b[ ]+-4772284[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1bc:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1c0:[ ]+680009ac[ ]+bltu[ ]+\$t1,[ ]+\$t0,[ ]+8[ ]+#[ ]+48d1c8[ ]+<.L1\+0x48d1c8> +[ ]+48d1c4:[ ]+532e3fed[ ]+b[ ]+-4772292[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1c4:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1c8:[ ]+6800098d[ ]+bltu[ ]+\$t0,[ ]+\$t1,[ ]+8[ ]+#[ ]+48d1d0[ ]+<.L1\+0x48d1d0> +[ ]+48d1cc:[ ]+532e37ed[ ]+b[ ]+-4772300[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1cc:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1d0:[ ]+44000980[ ]+bnez[ ]+\$t0,[ ]+8[ ]+#[ ]+48d1d8[ ]+<.L1\+0x48d1d8> +[ ]+48d1d4:[ ]+532e2fed[ ]+b[ ]+-4772308[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1d4:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1d8:[ ]+40000980[ ]+beqz[ ]+\$t0,[ ]+8[ ]+#[ ]+48d1e0[ ]+<.L1\+0x48d1e0> +[ ]+48d1dc:[ ]+532e27ed[ ]+b[ ]+-4772316[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1dc:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1e0:[ ]+48000900[ ]+bcnez[ ]+\$fcc0,[ ]+8[ ]+#[ ]+48d1e8[ ]+<.L1\+0x48d1e8> +[ ]+48d1e4:[ ]+532e1fed[ ]+b[ ]+-4772324[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1e4:[ ]+R_LARCH_B26[ ]+.L1 +[ ]+48d1e8:[ ]+48000800[ ]+bceqz[ ]+\$fcc0,[ ]+8[ ]+#[ ]+48d1f0[ ]+<.L1\+0x48d1f0> +[ ]+48d1ec:[ ]+532e17ed[ ]+b[ ]+-4772332[ ]+#[ ]+0[ ]+<.L1> +[ ]+48d1ec:[ ]+R_LARCH_B26[ ]+.L1 diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_1.s b/gas/testsuite/gas/loongarch/la_branch_relax_1.s index 53288f25013..233a1774c41 100644 --- a/gas/testsuite/gas/loongarch/la_branch_relax_1.s +++ b/gas/testsuite/gas/loongarch/la_branch_relax_1.s @@ -1,8 +1,10 @@ # Instruction and Relocation generating tests +.text .L1: .fill 0x123456, 4, 0x0 + call .L1 # R_LARCH_B16 beq $r12, $r13, .L1 bne $r12, $r13, .L1 diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_2.d b/gas/testsuite/gas/loongarch/la_branch_relax_2.d index 4a3c6384d9c..00357d10cb3 100644 --- a/gas/testsuite/gas/loongarch/la_branch_relax_2.d +++ b/gas/testsuite/gas/loongarch/la_branch_relax_2.d @@ -1,40 +1,28 @@ -#as: +#as: -mrelax #objdump: -dr -.*:[ ]+file format .* - - -Disassembly of section .text: - -0* <.L1>: -[ ]+... -[ ]+20000:[ ]+5a00018d[ ]+beq[ ]+\$t0, \$t1, -131072[ ]+# 0 <.L1> -[ ]+20000: R_LARCH_B16[ ]+.L1 -[ ]+20004:[ ]+5c00098d[ ]+bne[ ]+\$t0, \$t1, 8[ ]+# 2000c <.L1\+0x2000c> -[ ]+20008:[ ]+51fffbff[ ]+b[ ]+-131080[ ]+# 0 <.L1> -[ ]+20008: R_LARCH_B26[ ]+.L1 -[ ]+2000c:[ ]+5c00098d[ ]+bne[ ]+\$t0, \$t1, 8[ ]+# 20014 <.L1\+0x20014> -[ ]+20010:[ ]+52000000[ ]+b[ ]+131072[ ]+# 40010 <.L2> -[ ]+20010: R_LARCH_B26[ ]+.L2 -[ ]+20014:[ ]+59fffd8d[ ]+beq[ ]+\$t0, \$t1, 131068[ ]+# 40010 <.L2> -[ ]+20014: R_LARCH_B16[ ]+.L2 -[ ]+... -0*40010 <.L2>: -[ ]+... -[ ]+440010:[ ]+40000190[ ]+beqz[ ]+\$t0, -4194304[ ]+# 40010 <.L2> -[ ]+440010: R_LARCH_B21[ ]+.L2 -[ ]+440014:[ ]+44000980[ ]+bnez[ ]+\$t0, 8[ ]+# 44001c <.L2\+0x40000c> -[ ]+440018:[ ]+53fffbef[ ]+b[ ]+-4194312[ ]+# 40010 <.L2> -[ ]+440018: R_LARCH_B26[ ]+.L2 -[ ]+44001c:[ ]+44000980[ ]+bnez[ ]+\$t0, 8[ ]+# 440024 <.L2\+0x400014> -[ ]+440020:[ ]+50000010[ ]+b[ ]+4194304[ ]+# 840020 <.L3> -[ ]+440020: R_LARCH_B26[ ]+.L3 -[ ]+440024:[ ]+43fffd8f[ ]+beqz[ ]+\$t0, 4194300[ ]+# 840020 <.L3> -[ ]+440024: R_LARCH_B21[ ]+.L3 -[ ]+... -0*840020 <.L3>: -[ ]+840020:[ ]+5800018d[ ]+beq[ ]+\$t0, \$t1, 0[ ]+# 840020 <.L3> -[ ]+840020: R_LARCH_B16[ ]+.L4 -0*840024 <.L5>: -[ ]+840024:[ ]+40000180[ ]+beqz[ ]+\$t0, 0[ ]+# 840024 <.L5> -[ ]+840024: R_LARCH_B21[ ]+.L5 +#... +.*beq.* +.*R_LARCH_B16.* +.*bne.* +.*b .* +.*R_LARCH_B26.* +.*bne.* +.*b .* +.*R_LARCH_B26.* +.*beq.* +.*R_LARCH_B16.* +#... +.*beqz.* +.*R_LARCH_B21.* +.*bnez.* +.*b .* +.*R_LARCH_B26.* +.*bnez.* +.*b .* +.*R_LARCH_B26.* +.*beqz.* +.*R_LARCH_B21.* +#... +.*beq.*t0.*t1, 0.* +.*beqz.*t0, 0.* diff --git a/gas/testsuite/gas/loongarch/la_branch_relax_2.s b/gas/testsuite/gas/loongarch/la_branch_relax_2.s index 3e6c5534315..76ccc043a41 100644 --- a/gas/testsuite/gas/loongarch/la_branch_relax_2.s +++ b/gas/testsuite/gas/loongarch/la_branch_relax_2.s @@ -1,22 +1,27 @@ # Immediate boundary value tests +.text .L1: - .fill 0x8000, 4, 0 + .fill 0x7ffe, 4, 0 + call .L1 beq $r12, $r13, .L1 # min imm -0x20000 - beq $r12, $r13, .L1 # out of range - beq $r12, $r13, .L2 # out of range + beq $r12, $r13, .L1 # out of range, chang to bne+b + beq $r12, $r13, .L2 # out of range, change to bne+b beq $r12, $r13, .L2 # max imm 0x1fffc - .fill 0x7ffe, 4, 0 + call .L1 + .fill 0x7ffc, 4, 0 .L2: - .fill 0x100000, 4, 0 + .fill 0xffffe, 4, 0 + call .L1 beqz $r12, .L2 # min imm -0x400000 - beqz $r12, .L2 # out of range - beqz $r12, .L3 # out of range + beqz $r12, .L2 # out of range, change to bnez+b + beqz $r12, .L3 # out of range, change to bnez+b beqz $r12, .L3 # max imm 0x3ffffc - .fill 0xffffe, 4, 0 + call .L1 + .fill 0xffffc, 4, 0 .L3: -# 0 imm +# 0 imm: branch target is current pc .L4: beq $r12, $r13, .L4 .L5: diff --git a/gas/testsuite/gas/loongarch/relax-uleb128.d b/gas/testsuite/gas/loongarch/relax-uleb128.d new file mode 100644 index 00000000000..720caf22e00 --- /dev/null +++ b/gas/testsuite/gas/loongarch/relax-uleb128.d @@ -0,0 +1,9 @@ +#source: relax-uleb128.s +#as: -mrelax +#readelf: -rW + +#... +.*R_LARCH_ADD_ULEB128.*10.*L2.* +.*R_LARCH_SUB_ULEB128.*00.*L1.* +.*R_LARCH_ADD_ULEB128.*1c.*L3.* +.*R_LARCH_SUB_ULEB128.*10.*L2.* diff --git a/gas/testsuite/gas/loongarch/relax-uleb128.s b/gas/testsuite/gas/loongarch/relax-uleb128.s new file mode 100644 index 00000000000..cc5ffe48520 --- /dev/null +++ b/gas/testsuite/gas/loongarch/relax-uleb128.s @@ -0,0 +1,18 @@ +.text +.L1: + nop + call .L1 + nop +.L2: + nop + .p2align 3 + nop +.L3: + nop +.L4: + nop + +.data + .uleb128 .L2-.L1 # Emit add/sub uleb128 relocs. + .uleb128 .L3-.L2 # Emit add/sub uleb128 relocs. + .uleb128 .L4-.L3 # Not emit add/sub uleb128 relocs. diff --git a/gas/testsuite/gas/loongarch/uleb128.d b/gas/testsuite/gas/loongarch/uleb128.d deleted file mode 100644 index 1a6730f3aab..00000000000 --- a/gas/testsuite/gas/loongarch/uleb128.d +++ /dev/null @@ -1,36 +0,0 @@ -#as: -#objdump: -Dr -#skip: loongarch32-*-* - -.*:[ ]+file format .* - - -Disassembly of section .data: - -00000000.* : -[ ]*0:[ ]*80030201[ ]*\.word[ ]*0x80030201 -[ ]*3:[ ]*R_LARCH_ADD_ULEB128[ ]*L2 -[ ]*3:[ ]*R_LARCH_SUB_ULEB128[ ]*L1 -[ ]*\.\.\. - -[ ]*0000000000000005[ ]*: -[ ]*\.\.\. -[ ]*81:[ ]*ff040000[ ]*\.word[ ]*0xff040000 -[ ]*85:[ ]*cacop[ ]*0x1f,[ ]*\$t3,[ ]*1 - -[ ]*0000000000000086[ ]*: -[ ]*86:[ ]*07060005[ ]*\.word[ ]*0x07060005 -[ ]*8a:[ ]*x86inc\.b[ ]*\$a0 -[ ]*8a:[ ]*R_LARCH_ADD_ULEB128[ ]*L4 -[ ]*8a:[ ]*R_LARCH_SUB_ULEB128[ ]*L3 - -[ ]*000000000000008d[ ]*: -[ ]*\.\.\. -[ ]*4089:[ ]*ff080000[ ]*\.word[ ]*0xff080000 -[ ]*408d:[ ]*\.word[ ]*0x09ffffff - -[ ]*0000000000004090[ ]*: -[ ]*4090:[ ]*09090909[ ]*\.word[ ]*0x09090909 -[ ]*4094:[ ]*09090909[ ]*\.word[ ]*0x09090909 -[ ]*4098:[ ]*09090909[ ]*\.word[ ]*0x09090909 -[ ]*409c:[ ]*09090909[ ]*\.word[ ]*0x09090909 diff --git a/gas/testsuite/gas/loongarch/uleb128.s b/gas/testsuite/gas/loongarch/uleb128.s deleted file mode 100644 index 104a8956bd6..00000000000 --- a/gas/testsuite/gas/loongarch/uleb128.s +++ /dev/null @@ -1,20 +0,0 @@ - .data - .byte 1, 2, 3 - .uleb128 L2 - L1 -L1: - .space 128 - 2 - .byte 4 - .p2align 1, 0xff -L2: - .byte 5 - - .p2align 2 - .byte 6, 7 - .uleb128 L4 - L3 -L3: - .space 128*128 - 2 - .byte 8 - .p2align 2, 0xff -L4: - .byte 9 - .p2align 4, 9 diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.d b/ld/testsuite/ld-loongarch-elf/jmp_op.d deleted file mode 100644 index 231d780923e..00000000000 --- a/ld/testsuite/ld-loongarch-elf/jmp_op.d +++ /dev/null @@ -1,50 +0,0 @@ -#as: -#objdump: -dr -M no-aliases - -.*:[ ]+file format .* - - -Disassembly of section .text: - -00000000.* <.L1>: -[ ]+0:[ ]+03400000[ ]+andi[ ]+\$zero,[ ]+\$zero,[ ]+0x0 -[ ]+4:[ ]+63fffc04[ ]+blt[ ]+\$zero,[ ]+\$a0,[ ]+-4[ ]+#[ ]+0[ ]+<.L1> -[ ]+4:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+8:[ ]+67fff880[ ]+bge[ ]+\$a0,[ ]+\$zero,[ ]+-8[ ]+#[ ]+0[ ]+<.L1> -[ ]+8:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+c:[ ]+67fff404[ ]+bge[ ]+\$zero,[ ]+\$a0,[ ]+-12[ ]+#[ ]+0[ ]+<.L1> -[ ]+c:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+10:[ ]+43fff09f[ ]+beqz[ ]+\$a0,[ ]+-16[ ]+#[ ]+0[ ]+<.L1> -[ ]+10:[ ]+R_LARCH_B21[ ]+.L1 -[ ]+14:[ ]+47ffec9f[ ]+bnez[ ]+\$a0,[ ]+-20[ ]+#[ ]+0[ ]+<.L1> -[ ]+14:[ ]+R_LARCH_B21[ ]+.L1 -[ ]+18:[ ]+4bffe81f[ ]+bceqz[ ]+\$fcc0,[ ]+-24[ ]+#[ ]+0[ ]+<.L1> -[ ]+18:[ ]+R_LARCH_B21[ ]+.L1 -[ ]+1c:[ ]+4bffe51f[ ]+bcnez[ ]+\$fcc0,[ ]+-28[ ]+#[ ]+0[ ]+<.L1> -[ ]+1c:[ ]+R_LARCH_B21[ ]+.L1 -[ ]+20:[ ]+4c000080[ ]+jirl[ ]+\$zero,[ ]+\$a0,[ ]+0 -[ ]+24:[ ]+53ffdfff[ ]+b[ ]+-36[ ]+#[ ]+0[ ]+<.L1> -[ ]+24:[ ]+R_LARCH_B26[ ]+.L1 -[ ]+28:[ ]+57ffdbff[ ]+bl[ ]+-40[ ]+#[ ]+0[ ]+<.L1> -[ ]+28:[ ]+R_LARCH_B26[ ]+.L1 -[ ]+2c:[ ]+5bffd485[ ]+beq[ ]+\$a0,[ ]+\$a1,[ ]+-44[ ]+#[ ]+0[ ]+<.L1> -[ ]+2c:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+30:[ ]+5fffd085[ ]+bne[ ]+\$a0,[ ]+\$a1,[ ]+-48[ ]+#[ ]+0[ ]+<.L1> -[ ]+30:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+34:[ ]+63ffcc85[ ]+blt[ ]+\$a0,[ ]+\$a1,[ ]+-52[ ]+#[ ]+0[ ]+<.L1> -[ ]+34:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+38:[ ]+63ffc8a4[ ]+blt[ ]+\$a1,[ ]+\$a0,[ ]+-56[ ]+#[ ]+0[ ]+<.L1> -[ ]+38:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+3c:[ ]+67ffc485[ ]+bge[ ]+\$a0,[ ]+\$a1,[ ]+-60[ ]+#[ ]+0[ ]+<.L1> -[ ]+3c:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+40:[ ]+67ffc0a4[ ]+bge[ ]+\$a1,[ ]+\$a0,[ ]+-64[ ]+#[ ]+0[ ]+<.L1> -[ ]+40:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+44:[ ]+6bffbc85[ ]+bltu[ ]+\$a0,[ ]+\$a1,[ ]+-68[ ]+#[ ]+0[ ]+<.L1> -[ ]+44:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+48:[ ]+6bffb8a4[ ]+bltu[ ]+\$a1,[ ]+\$a0,[ ]+-72[ ]+#[ ]+0[ ]+<.L1> -[ ]+48:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+4c:[ ]+6fffb485[ ]+bgeu[ ]+\$a0,[ ]+\$a1,[ ]+-76[ ]+#[ ]+0[ ]+<.L1> -[ ]+4c:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+50:[ ]+6fffb0a4[ ]+bgeu[ ]+\$a1,[ ]+\$a0,[ ]+-80[ ]+#[ ]+0[ ]+<.L1> -[ ]+50:[ ]+R_LARCH_B16[ ]+.L1 -[ ]+54:[ ]+4c000020[ ]+jirl[ ]+\$zero,[ ]+\$ra,[ ]+0 diff --git a/ld/testsuite/ld-loongarch-elf/jmp_op.s b/ld/testsuite/ld-loongarch-elf/jmp_op.s deleted file mode 100644 index 56f986784e2..00000000000 --- a/ld/testsuite/ld-loongarch-elf/jmp_op.s +++ /dev/null @@ -1,23 +0,0 @@ -.L1: -nop -bgtz $r4,.L1 -bgez $r4,.L1 -blez $r4,.L1 -beqz $r4,.L1 -bnez $r4,.L1 -bceqz $fcc0,.L1 -bcnez $fcc0,.L1 -jr $r4 -b .L1 -bl .L1 -beq $r4,$r5,.L1 -bne $r4,$r5,.L1 -blt $r4,$r5,.L1 -bgt $r4,$r5,.L1 -bge $r4,$r5,.L1 -ble $r4,$r5,.L1 -bltu $r4,$r5,.L1 -bgtu $r4,$r5,.L1 -bgeu $r4,$r5,.L1 -bleu $r4,$r5,.L1 -ret diff --git a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp index d702e5138c6..ce1bf651b5a 100644 --- a/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp +++ b/ld/testsuite/ld-loongarch-elf/ld-loongarch-elf.exp @@ -20,7 +20,6 @@ # if [istarget "loongarch64-*-*"] { - run_dump_test "jmp_op" run_dump_test "macro_op" run_dump_test "syscall" run_dump_test "disas-jirl" @@ -58,7 +57,6 @@ if [istarget "loongarch64-*-*"] { } if [istarget "loongarch32-*-*"] { - run_dump_test "jmp_op" run_dump_test "macro_op_32" run_dump_test "syscall" run_dump_test "disas-jirl-32" From patchwork Tue Jul 7 17:47:19 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: mengqinggang X-Patchwork-Id: 138699 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 91C884BA23C5 for ; Wed, 8 Jul 2026 01:55:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 91C884BA23C5 X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 0FE054BA2E22 for ; Wed, 8 Jul 2026 01:54:53 +0000 (GMT) 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(unknown [10.2.6.7]) by front1 (Coremail) with SMTP id qMiowJCxLcXprU1qDAMFAA--.17715S2; Wed, 08 Jul 2026 09:54:49 +0800 (CST) From: mengqinggang To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, zhaozhou@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, luweining@loongson.cn, mengqinggang@loongson.cn Subject: [PATCH v0 4/4] LoongArch: Emit alignment relocations after relaxed instructions Date: Wed, 8 Jul 2026 01:47:19 +0800 Message-Id: <20260707174719.1883721-5-mengqinggang@loongson.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260707174719.1883721-1-mengqinggang@loongson.cn> References: <20260707174719.1883721-1-mengqinggang@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: qMiowJCxLcXprU1qDAMFAA--.17715S2 X-CM-SenderInfo: 5phqw15lqjwttqj6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DATE_IN_PAST_06_12, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Alignment cannot change before relaxed instructions. Emit alignment relocations only after them. Similar with https://github.com/llvm/llvm-project/pull/150816. --- gas/config/tc-loongarch.c | 8 ++- .../gas/loongarch/negative_right_shift.d | 67 +++++++++---------- .../gas/loongarch/negative_right_shift.s | 9 ++- gas/testsuite/gas/loongarch/relax-align.d | 46 +++++++++++++ .../{relax_align.l => relax-align.l} | 0 .../{relax_align.s => relax-align.s} | 6 +- gas/testsuite/gas/loongarch/relax-align1.d | 8 +++ gas/testsuite/gas/loongarch/relax-align1.s | 16 +++++ gas/testsuite/gas/loongarch/relax-align2.d | 27 +++----- gas/testsuite/gas/loongarch/relax-align2.s | 4 ++ gas/testsuite/gas/loongarch/relax_align.d | 52 -------------- ld/testsuite/ld-undefined/undefined.exp | 2 - 12 files changed, 130 insertions(+), 115 deletions(-) create mode 100644 gas/testsuite/gas/loongarch/relax-align.d rename gas/testsuite/gas/loongarch/{relax_align.l => relax-align.l} (100%) rename gas/testsuite/gas/loongarch/{relax_align.s => relax-align.s} (79%) create mode 100644 gas/testsuite/gas/loongarch/relax-align1.d create mode 100644 gas/testsuite/gas/loongarch/relax-align1.s delete mode 100644 gas/testsuite/gas/loongarch/relax_align.d diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index ed5d47a0360..e67394c460c 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -2178,6 +2178,11 @@ loongarch_frag_align_code (int n, int max) if (!LARCH_opts.relax) return false; + /* Only create an alignment frag if the current section already + has relaxed instructions. */ + if (!now_seg->sec_flg1) + return false; + bfd_vma align_bytes = (bfd_vma) 1 << n; bfd_vma worst_case_bytes = align_bytes - 4; bfd_vma addend = worst_case_bytes; @@ -2192,8 +2197,7 @@ loongarch_frag_align_code (int n, int max) frag_wane (frag_now); frag_new (0); - /* Mark the current section and frag as linker relaxable. */ - now_seg->sec_flg1 = true; + /* Mark the current frag as linker relaxable. */ frag_now->tc_frag_data.linker_relax = true; /* If max <= 0, ignore max. diff --git a/gas/testsuite/gas/loongarch/negative_right_shift.d b/gas/testsuite/gas/loongarch/negative_right_shift.d index 4237710c2b3..9221e61f3ab 100644 --- a/gas/testsuite/gas/loongarch/negative_right_shift.d +++ b/gas/testsuite/gas/loongarch/negative_right_shift.d @@ -1,40 +1,33 @@ -#as: +#as: -mrelax #objdump: -d -#skip: loongarch32-*-* #warning_output: negative_right_shift.l -.*: file format .* - - -Disassembly of section \.text: - -0+ : - 0: 03400000 nop - 4: 00000001 \.word 0x00000001 - 8: 00000001 \.word 0x00000001 - -0+c : - c: 02bff9ac addi.w \$t0, \$t1, -2 - 10: 02fff9ac addi.d \$t0, \$t1, -2 - 14: 13fff9ac addu16i.d \$t0, \$t1, -2 - 18: 15ffffcc lu12i.w \$t0, -2 - 1c: 17ffffcc lu32i.d \$t0, -2 - 20: 033ff9ac lu52i.d \$t0, \$t1, -2 - 24: 023ff9ac slti \$t0, \$t1, -2 - 28: 027ff9ac sltui \$t0, \$t1, -2 - 2c: 19ffffcc pcaddi \$t0, -2 - 30: 1dffffcc pcaddu12i \$t0, -2 - 34: 1fffffcc pcaddu18i \$t0, -2 - 38: 1bffffcc pcalau12i \$t0, -2 - 3c: 02bffdac addi.w \$t0, \$t1, -1 - 40: 02fffdac addi.d \$t0, \$t1, -1 - 44: 13fffdac addu16i.d \$t0, \$t1, -1 - 48: 15ffffec lu12i.w \$t0, -1 - 4c: 17ffffec lu32i.d \$t0, -1 - 50: 033ffdac lu52i.d \$t0, \$t1, -1 - 54: 023ffdac slti \$t0, \$t1, -1 - 58: 027ffdac sltui \$t0, \$t1, -1 - 5c: 19ffffec pcaddi \$t0, -1 - 60: 1dffffec pcaddu12i \$t0, -1 - 64: 1fffffec pcaddu18i \$t0, -1 - 68: 1bffffec pcalau12i \$t0, -1 +#... +.*03400000 nop +.*00000001 \.word 0x00000001 +.*00000001 \.word 0x00000001 +#... +.*02bff9ac addi.w \$t0, \$t1, -2 +.*02fff9ac addi.d \$t0, \$t1, -2 +.*13fff9ac addu16i.d \$t0, \$t1, -2 +.*15ffffcc lu12i.w \$t0, -2 +.*17ffffcc lu32i.d \$t0, -2 +.*033ff9ac lu52i.d \$t0, \$t1, -2 +.*023ff9ac slti \$t0, \$t1, -2 +.*027ff9ac sltui \$t0, \$t1, -2 +.*19ffffcc pcaddi \$t0, -2 +.*1dffffcc pcaddu12i \$t0, -2 +.*1fffffcc pcaddu18i \$t0, -2 +.*1bffffcc pcalau12i \$t0, -2 +.*02bffdac addi.w \$t0, \$t1, -1 +.*02fffdac addi.d \$t0, \$t1, -1 +.*13fffdac addu16i.d \$t0, \$t1, -1 +.*15ffffec lu12i.w \$t0, -1 +.*17ffffec lu32i.d \$t0, -1 +.*033ffdac lu52i.d \$t0, \$t1, -1 +.*023ffdac slti \$t0, \$t1, -1 +.*027ffdac sltui \$t0, \$t1, -1 +.*19ffffec pcaddi \$t0, -1 +.*1dffffec pcaddu12i \$t0, -1 +.*1fffffec pcaddu18i \$t0, -1 +.*1bffffec pcalau12i \$t0, -1 diff --git a/gas/testsuite/gas/loongarch/negative_right_shift.s b/gas/testsuite/gas/loongarch/negative_right_shift.s index c6a8a1e7c6e..302dba1fb8f 100644 --- a/gas/testsuite/gas/loongarch/negative_right_shift.s +++ b/gas/testsuite/gas/loongarch/negative_right_shift.s @@ -1,9 +1,12 @@ -directives: +.text +call .text + +directives: # unsigned shift .align -1>>62 .word -1>>63 .4byte -1>>63 -insns: +insns: #signed left shift addi.w $t0, $t1, -1<<1 addi.d $t0, $t1, -1<<1 addu16i.d $t0, $t1, -1<<1 @@ -17,7 +20,7 @@ pcaddu12i $t0, -1<<1 pcaddu18i $t0, -1<<1 pcalau12i $t0, -1<<1 -# warn +# warn signed right shift addi.w $t0, $t1, -1>>63 addi.d $t0, $t1, -1>>63 addu16i.d $t0, $t1, -1>>63 diff --git a/gas/testsuite/gas/loongarch/relax-align.d b/gas/testsuite/gas/loongarch/relax-align.d new file mode 100644 index 00000000000..8e61da5c217 --- /dev/null +++ b/gas/testsuite/gas/loongarch/relax-align.d @@ -0,0 +1,46 @@ +#as: -mrelax +#objdump: -dr +#warning_output: relax-align.l + +#... +[ ]+8:[ ]+4c000020[ ]+ret +[ ]+c:[ ]+03400000[ ]+nop +[ ]+c:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+10:[ ]+03400000[ ]+nop +[ ]+14:[ ]+03400000[ ]+nop +[ ]+18:[ ]+4c000020[ ]+ret +[ ]+1c:[ ]+03400000[ ]+nop +[ ]+1c:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+20:[ ]+03400000[ ]+nop +[ ]+24:[ ]+03400000[ ]+nop +[ ]+28:[ ]+4c000020[ ]+ret +[ ]+2c:[ ]+03400000[ ]+nop +[ ]+2c:[ ]+R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x104 +[ ]+30:[ ]+03400000[ ]+nop +[ ]+34:[ ]+03400000[ ]+nop +[ ]+38:[ ]+4c000020[ ]+ret +[ ]+3c:[ ]+03400000[ ]+nop +[ ]+3c:[ ]+R_LARCH_ALIGN[ ]+.Lla-relax-align\+0xb04 +[ ]+40:[ ]+03400000[ ]+nop +[ ]+44:[ ]+03400000[ ]+nop +[ ]+48:[ ]+4c000020[ ]+ret +[ ]+4c:[ ]+03400000[ ]+nop +[ ]+4c:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+50:[ ]+03400000[ ]+nop +[ ]+54:[ ]+03400000[ ]+nop +[ ]+58:[ ]+4c000020[ ]+ret +[ ]+5c:[ ]+03400000[ ]+nop +[ ]+5c:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+60:[ ]+03400000[ ]+nop +[ ]+64:[ ]+03400000[ ]+nop +[ ]+68:[ ]+4c000020[ ]+ret +[ ]+6c:[ ]+03400000[ ]+nop +[ ]+6c:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+70:[ ]+03400000[ ]+nop +[ ]+74:[ ]+03400000[ ]+nop +[ ]+78:[ ]+4c000020[ ]+ret +[ ]+7c:[ ]+03400000[ ]+nop +[ ]+7c:[ ]+R_LARCH_ALIGN[ ]+\*ABS\*\+0xc +[ ]+80:[ ]+03400000[ ]+nop +[ ]+84:[ ]+03400000[ ]+nop +[ ]+88:[ ]+4c000020[ ]+ret diff --git a/gas/testsuite/gas/loongarch/relax_align.l b/gas/testsuite/gas/loongarch/relax-align.l similarity index 100% rename from gas/testsuite/gas/loongarch/relax_align.l rename to gas/testsuite/gas/loongarch/relax-align.l diff --git a/gas/testsuite/gas/loongarch/relax_align.s b/gas/testsuite/gas/loongarch/relax-align.s similarity index 79% rename from gas/testsuite/gas/loongarch/relax_align.s rename to gas/testsuite/gas/loongarch/relax-align.s index 079f549895c..be78f4c3687 100644 --- a/gas/testsuite/gas/loongarch/relax_align.s +++ b/gas/testsuite/gas/loongarch/relax-align.s @@ -1,6 +1,6 @@ # Range of max: 0<= max <= 0xffffffff - .text -.L1: +.text + call .text ret .align 4 ret @@ -14,7 +14,7 @@ ret .align 4, , 0xffffffff ret -# ignore out of range alignment maxumum + # ignore out of range alignment maxumum .align 4, , -1 ret .align 4, , -0x80000000 diff --git a/gas/testsuite/gas/loongarch/relax-align1.d b/gas/testsuite/gas/loongarch/relax-align1.d new file mode 100644 index 00000000000..13576df9dca --- /dev/null +++ b/gas/testsuite/gas/loongarch/relax-align1.d @@ -0,0 +1,8 @@ +#as: -mrelax +#objdump: -dr + +#... +.*10: R_LARCH_ALIGN.*0x4 +#... +.*10: R_LARCH_ALIGN.*0x4 +#... diff --git a/gas/testsuite/gas/loongarch/relax-align1.s b/gas/testsuite/gas/loongarch/relax-align1.s new file mode 100644 index 00000000000..dfb9342d507 --- /dev/null +++ b/gas/testsuite/gas/loongarch/relax-align1.s @@ -0,0 +1,16 @@ +# Emit align relocation only if the current section +# already has relaxed instrctions. +.text + addi.d $t0, $t0, 1 + .align 3 # Do not emit an align relocation + call .text + .align 3 # Emit an align relocation + addi.d $t0, $t0, 1 + +.section ".text.a", "ax" + addi.d $t0, $t0, 1 + .align 3 # Do not emit an align relocation + call .text + .align 3 # Emit an align relocation + addi.d $t0, $t0, 1 + diff --git a/gas/testsuite/gas/loongarch/relax-align2.d b/gas/testsuite/gas/loongarch/relax-align2.d index cbef84f8777..516091a5735 100644 --- a/gas/testsuite/gas/loongarch/relax-align2.d +++ b/gas/testsuite/gas/loongarch/relax-align2.d @@ -1,24 +1,19 @@ #as: --no-warn #readelf: -rsW -#skip: loongarch32-*-* -Relocation section '\.rela\.text' at offset .* contains 2 entries: -.* -0+04[ ]+0000000000000066[ ]+R_LARCH_ALIGN[ ]+c -0+14[ ]+0000000500000066[ ]+R_LARCH_ALIGN[ ]+0+[ ]+\.Lla-relax-align \+ 404 - -Relocation section '\.rela\.text2' at offset .* contains 2 entries: -.* -0+04[ ]+0000000000000066[ ]+R_LARCH_ALIGN[ ]+c -0+14[ ]+0000000600000066[ ]+R_LARCH_ALIGN[ ]+0+[ ]+\.Lla-relax-align \+ 404 - -Symbol table '\.symtab' contains .* entries: #... -[ ]+.*:[ ]+0+[ ]+0[ ]+SECTION[ ]+LOCAL[ ]+DEFAULT[ ]+1[ ]+\.text +Relocation section '\.rela\.text'.* #... -[ ]+.*:[ ]+0+[ ]+0[ ]+SECTION[ ]+LOCAL[ ]+DEFAULT[ ]+5[ ]+\.text2 +.*R_LARCH_ALIGN.*c +.*R_LARCH_ALIGN.*\.Lla-relax-align.*404 #... -[ ]+.*:[ ]+0+[ ]+0[ ]+NOTYPE[ ]+LOCAL[ ]+DEFAULT[ ]+1[ ]+\.Lla-relax-align +Relocation section '\.rela\.text2'.* +#... +.*R_LARCH_ALIGN.*c +.*R_LARCH_ALIGN.*\.Lla-relax-align.*404 +#... +Symbol table '\.symtab' contains .* entries: #... -[ ]+.*:[ ]+0+[ ]+0[ ]+NOTYPE[ ]+LOCAL[ ]+DEFAULT[ ]+5[ ]+\.Lla-relax-align +.*1.*\.Lla-relax-align +.*5.*\.Lla-relax-align #pass diff --git a/gas/testsuite/gas/loongarch/relax-align2.s b/gas/testsuite/gas/loongarch/relax-align2.s index 6cd6bd8731b..4e73d47bf7a 100644 --- a/gas/testsuite/gas/loongarch/relax-align2.s +++ b/gas/testsuite/gas/loongarch/relax-align2.s @@ -1,10 +1,14 @@ +# Make align symbol .Lla-relax-align in same section with .align + .section ".text", "ax" +call .text nop .align 4 nop .align 4, , 4 .section ".text2", "ax" +call .text nop .align 4 nop diff --git a/gas/testsuite/gas/loongarch/relax_align.d b/gas/testsuite/gas/loongarch/relax_align.d deleted file mode 100644 index a92df37c636..00000000000 --- a/gas/testsuite/gas/loongarch/relax_align.d +++ /dev/null @@ -1,52 +0,0 @@ -#as: -#objdump: -dr -#skip: loongarch32-*-* -#warning_output: relax_align.l - -.*:[ ]+file format .* - - -Disassembly of section .text: - -[ ]*0000000000000000 <.Lla-relax-align>: -[ ]+0:[ ]+4c000020[ ]+ret -[ ]+4:[ ]+03400000[ ]+nop -[ ]+4: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -[ ]+8:[ ]+03400000[ ]+nop -[ ]+c:[ ]+03400000[ ]+nop -[ ]+10:[ ]+4c000020[ ]+ret -[ ]+14:[ ]+03400000[ ]+nop -[ ]+14: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -[ ]+18:[ ]+03400000[ ]+nop -[ ]+1c:[ ]+03400000[ ]+nop -[ ]+20:[ ]+4c000020[ ]+ret -[ ]+24:[ ]+03400000[ ]+nop -[ ]+24: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0x104 -[ ]+28:[ ]+03400000[ ]+nop -[ ]+2c:[ ]+03400000[ ]+nop -[ ]+30:[ ]+4c000020[ ]+ret -[ ]+34:[ ]+03400000[ ]+nop -[ ]+34: R_LARCH_ALIGN[ ]+.Lla-relax-align\+0xb04 -[ ]+38:[ ]+03400000[ ]+nop -[ ]+3c:[ ]+03400000[ ]+nop -[ ]+40:[ ]+4c000020[ ]+ret -[ ]+44:[ ]+03400000[ ]+nop -[ ]+44: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -[ ]+48:[ ]+03400000[ ]+nop -[ ]+4c:[ ]+03400000[ ]+nop -[ ]+50:[ ]+4c000020[ ]+ret -[ ]+54:[ ]+03400000[ ]+nop -[ ]+54: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -[ ]+58:[ ]+03400000[ ]+nop -[ ]+5c:[ ]+03400000[ ]+nop -[ ]+60:[ ]+4c000020[ ]+ret -[ ]+64:[ ]+03400000[ ]+nop -[ ]+64: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -[ ]+68:[ ]+03400000[ ]+nop -[ ]+6c:[ ]+03400000[ ]+nop -[ ]+70:[ ]+4c000020[ ]+ret -[ ]+74:[ ]+03400000[ ]+nop -[ ]+74: R_LARCH_ALIGN[ ]+\*ABS\*\+0xc -[ ]+78:[ ]+03400000[ ]+nop -[ ]+7c:[ ]+03400000[ ]+nop -[ ]+80:[ ]+4c000020[ ]+ret diff --git a/ld/testsuite/ld-undefined/undefined.exp b/ld/testsuite/ld-undefined/undefined.exp index 45c70b4732b..d4ea14e105c 100644 --- a/ld/testsuite/ld-undefined/undefined.exp +++ b/ld/testsuite/ld-undefined/undefined.exp @@ -74,7 +74,6 @@ if { ![check_compiler_available] } { # in a literal pool outside the function, so that both the # "undefined function" and "undefined line" tests fail. setup_xfail xtensa*-*-linux* - setup_xfail loongarch*-*-* set mf "tmpdir/undefined.o* in function `function':" checkund $mf $testfn @@ -155,7 +154,6 @@ if { ![check_compiler_available] } { # eBPF doesn't support dwarf yet. setup_xfail bpf-*-* - setup_xfail loongarch*-*-* checkund $ml $testline }