From patchwork Mon Jun 22 10:52:00 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 137543 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3A55A4B9DB6E for ; Mon, 22 Jun 2026 10:52:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3A55A4B9DB6E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1782125571; bh=1ZXJurpCDO3DiIZcd52/q+RMGkjHUVW+9qHIRZjnT2E=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=jMDbHPUZiIpLfAfvzg0RwAse/CHSzeGuqrdYmJr7cTYdQaHpe/ULZSsg3fluWj3Jo QtVrxczw5kY6dAEYLeg36QptlSXrX1n8UA/7ZBaulob6Yn5NPUDVP5XdYU82B0gNCK I5kzMOytDtisUeTxGgxetQUGF4xGzgw77o47ZFmM= X-Original-To: newlib@sourceware.org Delivered-To: newlib@sourceware.org Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id DF6224BA540B for ; Mon, 22 Jun 2026 10:52:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DF6224BA540B ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DF6224BA540B ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782125534; cv=none; b=gVmANetgmFmDixnCLU4xU62ZLOi9GquxxJa5xmThLeflO1+9jz8JWpeU870Q2+eSSoGxrrPQc5Ax7UQCGLCML8eDjpqtWzS3lE2DvvuevChmRVZtLMWad20DMktCZ3dcukRFWhN+xQvTsAbWOnS5wOtFFhUJq9mGWsEle5aKTb0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782125534; c=relaxed/simple; bh=5ik+XBU2aRpY/7Gt7fNY6V4BgbhZN20z2JGlZ/Ba/tA=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=OOlIFyIgOtP/uJC+p4tHhcfb+/5U2tAqgEwgjyNzQCedX01XJVMcTuWsBGK2ujcWzmvr2zshHA7o8Tp+ns1mQSdmls9GC5AalIkkt7FAagmYl8xZjXNAJwJEUXJxzbUBJikv6TLiG2py/bdfOuUvLw1sFlg7DE7MBhry+gUXCis= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=IrwmWDcu DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DF6224BA540B Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-c8ec0e0e77aso417412a12.3 for ; Mon, 22 Jun 2026 03:52:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782125532; x=1782730332; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=1ZXJurpCDO3DiIZcd52/q+RMGkjHUVW+9qHIRZjnT2E=; b=MzNmM4KfTBpQkY1sDYcRpkv73q/cu/husQLkJN+945lxtKTv9rm9EyO6h/AAGKqqmR VudLB6Wq9/kbnEmgvBlbakn8r8LFNgIPN4bJmxuJbP+HFRnn0yqF71Tmz1ZR75irrQmU J/pr4zaEBclLLh6ZZY427PSPViXtoqHtifQKDq7t9fIvfMSFMQXf03w3f2dKyPnSsdXj sadnwYP4mrgvQ+7t/2kQ7H5cM9JNdhFFCoTnlQvF2ZRId3shaIYn1JFX6+zlKQKWmE+A DYrcsopwxv6Ww41CkUGJcQxqhYDaPxLhVwCYxt5SPHCSsyZZjcMRa4Jzopar9xXa6WBD e0Pg== X-Gm-Message-State: AOJu0YyXd1LU9g1POWuyU94xF2lhL4US1OOkLzguNqBtysD4fsjo81t6 lfz9J6T6XO4VEUonHh1sQvazOqd8NnEMxpIdA0QI4BK5mKajam5rMcyckQAL7p+kOAbQrbGwax5 fG0cBp+BsbIqAwl/nkIfbPkDsmTinN62/eRrjt+ohdxqcIObQKaOXn7d3lGbuzyDmIITVcypZvd TjmYxyWALfxGOT2Z0KR6ExYA2vwkjHyRW1Ww0rUqLPF4FI X-Gm-Gg: AfdE7clMdNUAjVhjvM+qX9fDqrofKG6Sbru9iTRu9+wpfMaEBLNkwzlIPmxLri5ImaP nue4GKcDhX4uOns8UqJ7uJTJjyNcOQ1uE7K+5v5TzxqBw9uVUAZJJR6NPOlsC6WF2J0IdZ0lf/m d912f4Nl1ZiXixNLVurkTWxiEScdGpBDeG1qxkn2wz+Fq7ABZq70mCBDwnFAiMuRi+4lMZ/WQ2k tI4fJxJ6t1JWwhzGvoVHNILUBZWttrVfWfhVBWGCr/5JnVkLE+x/BdnpXQRTzWrbgY/vQGMo4+g QyfmI/qUeVTrknfmuVFEMsvGLfjQHwxY/FiMQmjtQvD5r8Qvq9H3YhP8XjSWHAsIT9rRe2YCYoI SNeKtYhfXaBJXtJY4uQKEj17Vf4fqp+7yjp+5iwBnvymsdHDIXUVV9pCacX3He3vA2YMh3nuhyN kGV8IvQbgkmDkbNNiydkcboAnXnjONWEhRTBZXEg== X-Received: by 2002:a05:6a21:9e0f:b0:3b4:888f:b3f7 with SMTP id adf61e73a8af0-3bb34e697f6mr18052492637.42.1782125532055; Mon, 22 Jun 2026 03:52:12 -0700 (PDT) Received: from hsinchu18.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c8bc5a1dc13sm6847599a12.26.2026.06.22.03.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 03:52:11 -0700 (PDT) To: newlib@sourceware.org, kito.cheng@gmail.com Cc: Kito Cheng Subject: [committed 1/3] RISC-V: introduce ENTRY/END assembler macros for function boilerplate Date: Mon, 22 Jun 2026 18:52:00 +0800 Message-ID: <20260622105202.664207-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.54.0 MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Newlib mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kito Cheng via Newlib From: Kito Cheng Reply-To: Kito Cheng Errors-To: newlib-bounces~patchwork=sourceware.org@sourceware.org Factor out the repeated .text, .globl, .type, landing-pad (lpad) and .size boilerplate at the start and end of each assembly function into ENTRY/END style macros, and convert the RISC-V assembly routines to use them. --- libgloss/riscv/asm.h | 84 +++++++++++++++++++++++ libgloss/riscv/crt0.S | 8 +-- newlib/libc/machine/riscv/memccpy-asm.S | 12 ++-- newlib/libc/machine/riscv/memchr-asm.S | 12 ++-- newlib/libc/machine/riscv/memcmp-asm.S | 12 ++-- newlib/libc/machine/riscv/memcpy-asm.S | 27 ++------ newlib/libc/machine/riscv/memmove-asm.S | 25 ++----- newlib/libc/machine/riscv/mempcpy-asm.S | 13 ++-- newlib/libc/machine/riscv/memrchr-asm.S | 12 ++-- newlib/libc/machine/riscv/memset.S | 13 +--- newlib/libc/machine/riscv/rawmemchr-asm.S | 12 ++-- newlib/libc/machine/riscv/setjmp.S | 18 ++--- newlib/libc/machine/riscv/strcmp.S | 10 +-- newlib/libc/machine/riscv/sys/asm.h | 34 +++++++++ 14 files changed, 165 insertions(+), 127 deletions(-) create mode 100644 libgloss/riscv/asm.h diff --git a/libgloss/riscv/asm.h b/libgloss/riscv/asm.h new file mode 100644 index 000000000..a9190b1f4 --- /dev/null +++ b/libgloss/riscv/asm.h @@ -0,0 +1,84 @@ +/* Copyright (c) 2026 SiFive Inc. All rights reserved. + + This copyrighted material is made available to anyone wishing to use, + modify, copy, or redistribute it subject to the terms and conditions + of the FreeBSD License. This program is distributed in the hope that + it will be useful, but WITHOUT ANY WARRANTY expressed or implied, + including the implied warranties of MERCHANTABILITY or FITNESS FOR + A PARTICULAR PURPOSE. A copy of this license is available at + http://www.opensource.org/licenses. +*/ + +#ifndef _ASM_H +#define _ASM_H + +/* + * Macros to handle different pointer/register sizes for 32/64-bit code + */ +#if __riscv_xlen == 64 +# define PTRLOG 3 +# define SZREG 8 +# define REG_S sd +# define REG_L ld +#elif __riscv_xlen == 32 +# define PTRLOG 2 +# define SZREG 4 +# define REG_S sw +# define REG_L lw +#else +# error __riscv_xlen must equal 32 or 64 +#endif + +#ifndef __riscv_float_abi_soft +/* For ABI uniformity, reserve 8 bytes for floats, even if double-precision + floating-point is not supported in hardware. */ +# define SZFREG 8 +# ifdef __riscv_float_abi_single +# define FREG_L flw +# define FREG_S fsw +# elif defined(__riscv_float_abi_double) +# define FREG_L fld +# define FREG_S fsd +# elif defined(__riscv_float_abi_quad) +# define FREG_L flq +# define FREG_S fsq +# else +# error unsupported FLEN +# endif +#endif + +/* Use 2-byte alignment when compressed instructions are available, since + they keep functions naturally aligned at 2 bytes; otherwise fall back to + 4-byte alignment to match the 32-bit instruction width. When landing + pads are enabled, force 4-byte alignment so every lpad target is aligned + to the 32-bit instruction width. */ +#if (defined(__riscv_c) || defined(__riscv_zca) || defined(__riscv_compressed)) && !defined(__riscv_landing_pad) +#define _ENTRY(name) \ + .text; \ + .balign 2; \ + .globl name; \ +name: +#else +#define _ENTRY(name) \ + .text; \ + .balign 4; \ + .globl name; \ +name: +#endif + +#define FUNC(name) .type name,@function +#define END(name) \ + .size name,.-name + +#if __riscv_landing_pad +#define LPAD lpad 0 +#else +#define LPAD +#endif + +#define ENTRY(name) \ + _ENTRY (name) \ + .type name,@function; \ + LPAD + +#endif /* _ASM_H */ diff --git a/libgloss/riscv/crt0.S b/libgloss/riscv/crt0.S index aa5ac3684..dc1964a9c 100644 --- a/libgloss/riscv/crt0.S +++ b/libgloss/riscv/crt0.S @@ -10,15 +10,13 @@ */ #include "newlib.h" +#include "asm.h" #========================================================================= # crt0.S : Entry point for RISC-V user programs #========================================================================= - .text - .global _start - .type _start, @function -_start: +ENTRY(_start) # Initialize global pointer .option push .option norelax @@ -105,4 +103,4 @@ _start: .weak __libc_fini_array .dword __libc_fini_array #endif - .size _start, .-_start +END(_start) diff --git a/newlib/libc/machine/riscv/memccpy-asm.S b/newlib/libc/machine/riscv/memccpy-asm.S index 5e3591eb6..dceb41359 100644 --- a/newlib/libc/machine/riscv/memccpy-asm.S +++ b/newlib/libc/machine/riscv/memccpy-asm.S @@ -1,11 +1,7 @@ +#include + #if defined(__riscv_vector) && !defined(__OPTIMIZE_SIZE__) && !defined(PREFER_SIZE_OVER_SPEED) -.text -.global memccpy -.type memccpy, @function -memccpy: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memccpy) beqz a3, .Lnot_found andi a2, a2, 0xff mv a5, a0 @@ -32,5 +28,5 @@ memccpy: vse8.v v0, (a5) add a0, a5, a6 ret -.size memccpy, .-memccpy +END(memccpy) #endif diff --git a/newlib/libc/machine/riscv/memchr-asm.S b/newlib/libc/machine/riscv/memchr-asm.S index 437505bd4..f46465edd 100644 --- a/newlib/libc/machine/riscv/memchr-asm.S +++ b/newlib/libc/machine/riscv/memchr-asm.S @@ -1,11 +1,7 @@ +#include + #if defined(__riscv_vector) && !defined(__OPTIMIZE_SIZE__) && !defined(PREFER_SIZE_OVER_SPEED) -.text -.global memchr -.type memchr, @function -memchr: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memchr) beqz a2, .Lnot_found andi a1, a1, 0xff .Lloop: @@ -30,5 +26,5 @@ memchr: .Lfound: add a0, a0, a4 ret -.size memchr, .-memchr +END(memchr) #endif diff --git a/newlib/libc/machine/riscv/memcmp-asm.S b/newlib/libc/machine/riscv/memcmp-asm.S index 1cf1680e2..462d65f01 100644 --- a/newlib/libc/machine/riscv/memcmp-asm.S +++ b/newlib/libc/machine/riscv/memcmp-asm.S @@ -1,11 +1,7 @@ +#include + #if defined(__riscv_vector) && !defined(__OPTIMIZE_SIZE__) && !defined(PREFER_SIZE_OVER_SPEED) -.text -.global memcmp -.type memcmp, @function -memcmp: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memcmp) beqz a2, .Lequal .Lloop: vsetvli a3, a2, e8, m8, ta, ma @@ -34,5 +30,5 @@ memcmp: lbu a4, 0(a1) sub a0, a0, a4 ret -.size memcmp, .-memcmp +END(memcmp) #endif diff --git a/newlib/libc/machine/riscv/memcpy-asm.S b/newlib/libc/machine/riscv/memcpy-asm.S index abc8481a6..14ac9498e 100644 --- a/newlib/libc/machine/riscv/memcpy-asm.S +++ b/newlib/libc/machine/riscv/memcpy-asm.S @@ -9,14 +9,10 @@ http://www.opensource.org/licenses. */ +#include + #if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__) -.text -.global memcpy -.type memcpy, @function -memcpy: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memcpy) mv a3, a0 beqz a2, 2f @@ -31,18 +27,9 @@ memcpy: 2: ret - - .size memcpy, .-memcpy +END(memcpy) #elif defined(__riscv_vector) -.text -.option push -.option arch, +zve32x -.global memcpy -.type memcpy, @function -memcpy: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memcpy) mv t0, a0 /* t0 = running dst */ mv t1, a1 /* t1 = running src */ beqz a2, .Ldone /* if n == 0, return */ @@ -85,7 +72,5 @@ memcpy: .Ldone: ret - - .size memcpy, .-memcpy - .option pop +END(memcpy) #endif diff --git a/newlib/libc/machine/riscv/memmove-asm.S b/newlib/libc/machine/riscv/memmove-asm.S index 92e52fcbc..1594ea339 100644 --- a/newlib/libc/machine/riscv/memmove-asm.S +++ b/newlib/libc/machine/riscv/memmove-asm.S @@ -9,14 +9,10 @@ http://www.opensource.org/licenses. */ +#include + #if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__) -.text -.global memmove -.type memmove, @function -memmove: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memmove) beqz a2, .Ldone /* in case there are 0 bytes to be copied, return immediately */ @@ -40,17 +36,9 @@ memmove: .Ldone: ret - .size memmove, .-memmove +END(memmove) #elif defined(__riscv_vector) -.text -.global memmove -.type memmove, @function -.option push -.option arch, +zve32x -memmove: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memmove) beqz a2, .Ldone_move /* n == 0 */ beq a0, a1, .Ldone_move /* dst == src */ @@ -135,6 +123,5 @@ memmove: .Ldone_move: ret - .size memmove, .-memmove - .option pop +END(memmove) #endif diff --git a/newlib/libc/machine/riscv/mempcpy-asm.S b/newlib/libc/machine/riscv/mempcpy-asm.S index 9acf65d0a..7b674459d 100644 --- a/newlib/libc/machine/riscv/mempcpy-asm.S +++ b/newlib/libc/machine/riscv/mempcpy-asm.S @@ -1,11 +1,7 @@ +#include + #if defined(__riscv_vector) && !defined(__OPTIMIZE_SIZE__) && !defined(PREFER_SIZE_OVER_SPEED) -.text -.global mempcpy -.type mempcpy, @function -mempcpy: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(mempcpy) mv t0, a0 /* t0 = running dst */ mv t1, a1 /* t1 = running src */ beqz a2, .Ldone /* if n == 0, return */ @@ -49,6 +45,5 @@ mempcpy: .Ldone: mv a0, t0 /* return dst + n */ ret - - .size mempcpy, .-mempcpy +END(mempcpy) #endif diff --git a/newlib/libc/machine/riscv/memrchr-asm.S b/newlib/libc/machine/riscv/memrchr-asm.S index e400611f5..60a82dfc3 100644 --- a/newlib/libc/machine/riscv/memrchr-asm.S +++ b/newlib/libc/machine/riscv/memrchr-asm.S @@ -1,11 +1,7 @@ +#include + #if defined(__riscv_vector) && !defined(__OPTIMIZE_SIZE__) && !defined(PREFER_SIZE_OVER_SPEED) -.text -.global memrchr -.type memrchr, @function -memrchr: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(memrchr) andi a1, a1, 0xff add a0, a0, a2 .Lloop: @@ -33,5 +29,5 @@ memrchr: .Lnohit: li a0, 0 ret -.size memrchr, .-memrchr +END(memrchr) #endif diff --git a/newlib/libc/machine/riscv/memset.S b/newlib/libc/machine/riscv/memset.S index b64ae768b..7c92bdced 100644 --- a/newlib/libc/machine/riscv/memset.S +++ b/newlib/libc/machine/riscv/memset.S @@ -42,18 +42,9 @@ #endif -.text -.global memset -.type memset, @function - /* void *memset(void *s, int c, size_t n); */ - -memset: -#if __riscv_landing_pad - lpad 0 -#endif - +ENTRY(memset) #if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__) mv a3, a0 beqz a2, .Ldone @@ -323,4 +314,4 @@ memset: .Lexit: ret #endif -.size memset, .-memset +END(memset) diff --git a/newlib/libc/machine/riscv/rawmemchr-asm.S b/newlib/libc/machine/riscv/rawmemchr-asm.S index 058448716..8f3d40592 100644 --- a/newlib/libc/machine/riscv/rawmemchr-asm.S +++ b/newlib/libc/machine/riscv/rawmemchr-asm.S @@ -1,11 +1,7 @@ +#include + #if defined(__riscv_vector) && !defined(__OPTIMIZE_SIZE__) && !defined(PREFER_SIZE_OVER_SPEED) -.text -.global rawmemchr -.type rawmemchr, @function -rawmemchr: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(rawmemchr) andi a1, a1, 0xff .Lloop: vsetvli t0, zero, e8, m1, ta, ma @@ -23,5 +19,5 @@ rawmemchr: .Lfound: add a0, a0, a2 ret -.size rawmemchr, .-rawmemchr +END(rawmemchr) #endif diff --git a/newlib/libc/machine/riscv/setjmp.S b/newlib/libc/machine/riscv/setjmp.S index 9cc85e747..a29c15f29 100644 --- a/newlib/libc/machine/riscv/setjmp.S +++ b/newlib/libc/machine/riscv/setjmp.S @@ -12,12 +12,7 @@ #include /* int setjmp (jmp_buf); */ - .globl setjmp - .type setjmp, @function -setjmp: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(setjmp) REG_S ra, 0*SZREG(a0) #if __riscv_xlen == 32 && (__riscv_zilsd) && (__riscv_misaligned_fast) sd s0, 1*SZREG(a0) @@ -67,15 +62,10 @@ setjmp: li a0, 0 ret - .size setjmp, .-setjmp +END(setjmp) /* volatile void longjmp (jmp_buf, int); */ - .globl longjmp - .type longjmp, @function -longjmp: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(longjmp) REG_L ra, 0*SZREG(a0) #if __riscv_xlen == 32 && (__riscv_zilsd) && (__riscv_misaligned_fast) ld s0, 1*SZREG(a0) @@ -125,4 +115,4 @@ longjmp: seqz a0, a1 add a0, a0, a1 # a0 = (a1 == 0) ? 1 : a1 ret - .size longjmp, .-longjmp +END(longjmp) diff --git a/newlib/libc/machine/riscv/strcmp.S b/newlib/libc/machine/riscv/strcmp.S index 49b999c0f..1fd0f1440 100644 --- a/newlib/libc/machine/riscv/strcmp.S +++ b/newlib/libc/machine/riscv/strcmp.S @@ -12,13 +12,7 @@ #include #include "newlib.h" -.text -.globl strcmp -.type strcmp, @function -strcmp: -#if __riscv_landing_pad - lpad 0 -#endif +ENTRY(strcmp) #if defined(PREFER_SIZE_OVER_SPEED) || defined(__OPTIMIZE_SIZE__) .Lcompare: @@ -240,7 +234,7 @@ strcmp: mask: .dword 0x7f7f7f7f7f7f7f7f #endif -.size strcmp, .-strcmp +END(strcmp) #if SZREG == 8 && !defined(__riscv_cmodel_large) .section .srodata.cst8,"aM",@progbits,8 diff --git a/newlib/libc/machine/riscv/sys/asm.h b/newlib/libc/machine/riscv/sys/asm.h index 8c8aeb3ae..0985d05bf 100644 --- a/newlib/libc/machine/riscv/sys/asm.h +++ b/newlib/libc/machine/riscv/sys/asm.h @@ -47,4 +47,38 @@ # endif #endif +/* Use 2-byte alignment when compressed instructions are available, since + they keep functions naturally aligned at 2 bytes; otherwise fall back to + 4-byte alignment to match the 32-bit instruction width. When landing + pads are enabled, force 4-byte alignment so every lpad target is aligned + to the 32-bit instruction width. */ +#if (defined(__riscv_c) || defined(__riscv_zca) || defined(__riscv_compressed)) && !defined(__riscv_landing_pad) +#define _ENTRY(name) \ + .text; \ + .balign 2; \ + .globl name; \ +name: +#else +#define _ENTRY(name) \ + .text; \ + .balign 4; \ + .globl name; \ +name: +#endif + +#define FUNC(name) .type name,@function +#define END(name) \ + .size name,.-name + +#if __riscv_landing_pad +#define LPAD lpad 0 +#else +#define LPAD +#endif + +#define ENTRY(name) \ + _ENTRY (name) \ + .type name,@function; \ + LPAD + #endif /* sys/asm.h */ From patchwork Mon Jun 22 10:52:01 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 137542 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5F9084BA799B for ; Mon, 22 Jun 2026 10:52:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5F9084BA799B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1782125550; bh=ncidwnzaOE3uwa0WchvMamavgx323dyTQShXgdGss88=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=VaYnxJ9CtDiAFdie5uBs6h5mJELYgs8qXYFB9VMPhnBJOOhGawLJrwT9bInHA6x0+ SpHIYNBBQw3mJkzrP46QAlC1lonhs9h2K1c3Kno5K+jJrCUXz1QCB4jwMho/jdVvOr 09GMkV6MTO9Dw0UgYwsdZPFoGU5bEW5K7xaJAiPU= X-Original-To: newlib@sourceware.org Delivered-To: newlib@sourceware.org Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by sourceware.org (Postfix) with ESMTPS id D0B564BA2E0A for ; Mon, 22 Jun 2026 10:52:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D0B564BA2E0A ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D0B564BA2E0A ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782125535; cv=none; b=e6TceQ7abRC28yKR4qRoHpjqXFLbzWna791Gn90NlsxdDs3DYdN7eomdMGhINnZgpOyCrWJxqwBPhBSwPt5uI7DFV/5p+K4eEB/KHuDWrF6Xx0KGumcIm/nY9ss9voYWB4TTE7Z/HHR9/EiEcoMVqVERGkHqMa9PkmvE/MWQr/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782125535; c=relaxed/simple; bh=6R14wMCD6QVJk+Z65bRhPkvQcorEQ+DJxUF1Qjdw0MI=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=keDA9Q2EuBYDZ+BbTJoFCezY0xcF8G8F/4lo2HITmwFLRV/U/0IEEHlORmbGxsBrfdJBwLBO/Yu8JMkwtlvOR5R0lf3/QQj789TBmUvjXqnbDoBhdAz8aMKaATvFXvuM5GQAGKkOdQCwvAAzBQdUH/giAX94w6JO94RXpZZOypc= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=C3cI3+51 DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D0B564BA2E0A Received: by mail-pg1-x52e.google.com with SMTP id 41be03b00d2f7-c88b59bfba7so1786592a12.1 for ; Mon, 22 Jun 2026 03:52:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782125534; x=1782730334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ncidwnzaOE3uwa0WchvMamavgx323dyTQShXgdGss88=; b=WH5MjvB5PciQbbQK9/stKZmqc8fbEWYkFtMzInXuGKvhlxLHlH7QK6JTgQNT3QllMW hogb4GQgfNW3FHdfdpqkutppf2lJDuHh+pRKV0ahlmdvBX+LzOGb1xbBZZ4HskduBJ1n jhVkDBzHWXBuKx6KKYbA4HE2BYULmSs0muyzkxs8tYZpi6XXjD3KWV26CctMrcjoCcNI uxgnB9QWhU3aK7WHjb05TkeYpW0nrC7dWjkj443Wa7tZeYHbPyn+YJye1sWqCEKzSyY8 LwPOZKQfvSJDrCf7RUoR+g8SdGRxUICG9HX3ydi+DveT6IDQdRoYIi6Qx3EofsJ+azFU pqJQ== X-Gm-Message-State: AOJu0YwEe+w+xDo9r6ySe08iBEvBn3m0+40LQd3FpiilhRAvPCemwdYR 5rKOuetdN3F0rS83jJBVFF2mvKLkknbOZNr4eX/zfu9kBcckNF+8eWGJKFyuQiBDE02F6MMxe1N IGpvxxv9EmAydFnG/YyVyS0BmBly9A/0smm7fnnuZDzIOEOymYdyvK8hy2mP2f0lKSQJIR67C1/ ZG8zMf29gpzGphmulPI9qh+08rtMh7j11EtAlbVK9hHh8j X-Gm-Gg: AfdE7ck4E+Yn52kkPn2YnFJnHqYl/Hiio1KBc6rcs0qXVgY+oEHfuiIQPSceb22K/8s +wKSYWypkYYX5L2Yl40QErWIn4RGV4GWQ1+WfYnbL2qhgoUIomurv568BMWbRmdFPBAiXlB7B9t 8YaW3j4bK5bEXWcNaMCMZ7t/uV1Ir+HJVQJaNoNc4BpTTk+HmwZRrB/6QgnfEjymYqXmq1gQryV QqiDGgEGeGg0xtaSikUT/VmypMgSH28NqZ492fYALXjOpuXm/Q+Pj9mdCYVVmtNmi5HGMV9vcxW uFI4WxlES+5gHXxhuIrJFiPipCG4Z3A6Wty3hM9vHV15L/3Xsi7Zc98zICPyuuuadmsL4O7WRI7 MhXoaiFDxp5Xrm0MC446GmYG6Aks0F+So3sssdcgvCFy3Fgkcf14RlLg5wv++C206Wxauy50R/o pZwczOg3dOTjDOLy8+MfI5O9hR9ZY5qBex4rNltg== X-Received: by 2002:a05:6a20:9c8d:b0:3a3:2b7e:a49b with SMTP id adf61e73a8af0-3bb30453163mr13415461637.0.1782125533535; Mon, 22 Jun 2026 03:52:13 -0700 (PDT) Received: from hsinchu18.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c8bc5a1dc13sm6847599a12.26.2026.06.22.03.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 03:52:13 -0700 (PDT) To: newlib@sourceware.org, kito.cheng@gmail.com Cc: Jesse Huang Subject: [committed 2/3] RISC-V: add GNU property notes to assembly routines Date: Mon, 22 Jun 2026 18:52:01 +0800 Message-ID: <20260622105202.664207-2-kito.cheng@sifive.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260622105202.664207-1-kito.cheng@sifive.com> References: <20260622105202.664207-1-kito.cheng@sifive.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Newlib mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kito Cheng via Newlib From: Kito Cheng Reply-To: Kito Cheng Errors-To: newlib-bounces~patchwork=sourceware.org@sourceware.org From: Jesse Huang Emit a NT_GNU_PROPERTY_TYPE_0 note from sys/asm.h and libgloss/riscv/asm.h that advertises the control-flow integrity features (landing pad and shadow stack) supported by the assembly routines. Every object that includes these headers is then marked CFI-enabled when built with -fcf-protection=[full|branch|return], so the linker keeps the feature enabled for the whole image. --- libgloss/riscv/asm.h | 53 +++++++++++++++++++++++++++++ newlib/libc/machine/riscv/sys/asm.h | 53 +++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/libgloss/riscv/asm.h b/libgloss/riscv/asm.h index a9190b1f4..8fe3bbcfa 100644 --- a/libgloss/riscv/asm.h +++ b/libgloss/riscv/asm.h @@ -81,4 +81,57 @@ name: .type name,@function; \ LPAD +#define FEATURE_1_AND 0xc0000000 +/* Add a NT_GNU_PROPERTY_TYPE_0 note. */ +#if __riscv_xlen == 32 +# define GNU_PROPERTY(type, value) \ + .pushsection .note.gnu.property, "a"; \ + .p2align 2; \ + .word 4; \ + .word 12; \ + .word 5; \ + .asciz "GNU"; \ + .word type; \ + .word 4; \ + .word value; \ + .popsection; +#else +# define GNU_PROPERTY(type, value) \ + .pushsection .note.gnu.property, "a"; \ + .p2align 3; \ + .word 4; \ + .word 16; \ + .word 5; \ + .asciz "GNU"; \ + .word type; \ + .word 4; \ + .word value; \ + .word 0; \ + .popsection; +#endif + +/* Add GNU property note with the supported features to all asm code + where asm.h is included. */ +#undef __VALUE_FOR_FEATURE_1_AND +#if defined (__riscv_landing_pad) || defined (__riscv_shadow_stack) +# if defined (__riscv_landing_pad) +# if defined (__riscv_shadow_stack) +# define __VALUE_FOR_FEATURE_1_AND 0x3 +# else +# define __VALUE_FOR_FEATURE_1_AND 0x1 +# endif +# else +# if defined (__riscv_shadow_stack) +# define __VALUE_FOR_FEATURE_1_AND 0x2 +# else +# error "What?" +# endif +# endif +#endif + +#if defined (__VALUE_FOR_FEATURE_1_AND) && defined (__ASSEMBLER__) +GNU_PROPERTY (FEATURE_1_AND, __VALUE_FOR_FEATURE_1_AND) +#endif +#undef __VALUE_FOR_FEATURE_1_AND + #endif /* _ASM_H */ diff --git a/newlib/libc/machine/riscv/sys/asm.h b/newlib/libc/machine/riscv/sys/asm.h index 0985d05bf..0b1893bf9 100644 --- a/newlib/libc/machine/riscv/sys/asm.h +++ b/newlib/libc/machine/riscv/sys/asm.h @@ -81,4 +81,57 @@ name: .type name,@function; \ LPAD +#define FEATURE_1_AND 0xc0000000 +/* Add a NT_GNU_PROPERTY_TYPE_0 note. */ +#if __riscv_xlen == 32 +# define GNU_PROPERTY(type, value) \ + .pushsection .note.gnu.property, "a"; \ + .p2align 2; \ + .word 4; \ + .word 12; \ + .word 5; \ + .asciz "GNU"; \ + .word type; \ + .word 4; \ + .word value; \ + .popsection; +#else +# define GNU_PROPERTY(type, value) \ + .pushsection .note.gnu.property, "a"; \ + .p2align 3; \ + .word 4; \ + .word 16; \ + .word 5; \ + .asciz "GNU"; \ + .word type; \ + .word 4; \ + .word value; \ + .word 0; \ + .popsection; +#endif + +/* Add GNU property note with the supported features to all asm code + where asm.h is included. */ +#undef __VALUE_FOR_FEATURE_1_AND +#if defined (__riscv_landing_pad) || defined (__riscv_shadow_stack) +# if defined (__riscv_landing_pad) +# if defined (__riscv_shadow_stack) +# define __VALUE_FOR_FEATURE_1_AND 0x3 +# else +# define __VALUE_FOR_FEATURE_1_AND 0x1 +# endif +# else +# if defined (__riscv_shadow_stack) +# define __VALUE_FOR_FEATURE_1_AND 0x2 +# else +# error "What?" +# endif +# endif +#endif + +#if defined (__VALUE_FOR_FEATURE_1_AND) && defined (__ASSEMBLER__) +GNU_PROPERTY (FEATURE_1_AND, __VALUE_FOR_FEATURE_1_AND) +#endif +#undef __VALUE_FOR_FEATURE_1_AND + #endif /* sys/asm.h */ From patchwork Mon Jun 22 10:52:02 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 137544 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 300C34B9DB7B for ; Mon, 22 Jun 2026 10:52:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 300C34B9DB7B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1782125571; bh=okW+Y3OViOojtkT9kZRRVWnyY89WzJ1eebCDaiT8byE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=WqiSWiU4Tc7BTLoTKbq3OVOq0LvXs/iuDQO9c5tamYPprzHfSKoH1iHMwhSJ+V2MD 6Ifvnx1beaWmEXmNV4WPSVB5PDXRSv0mhMvhwUv9sDo4xknNzX4c0OKdckMVjHdCKS E53xk38OH1uxpjMFu+asTkwaivSUfukkdpMlGnA4= X-Original-To: newlib@sourceware.org Delivered-To: newlib@sourceware.org Received: from mail-pg1-x52f.google.com (mail-pg1-x52f.google.com [IPv6:2607:f8b0:4864:20::52f]) by sourceware.org (Postfix) with ESMTPS id 39BE14BA2E0C for ; Mon, 22 Jun 2026 10:52:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 39BE14BA2E0C ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 39BE14BA2E0C ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782125536; cv=none; b=Io8oqH1B8u9y+2il5VJFGYcw19sDsOK8ZPLbIjqaR1/IGWh4az8CSYXl9fk+NIYKkzO1qRxEpdNlVYArIHGd95VE0E/v3yYW8OPN6NIONer38q/1786WEJ+oYVECKMBpAMPnrA8SVIVF/t9E9T0F5pOpk7b1SrFc+GrFktGx7hY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1782125536; c=relaxed/simple; bh=0/YeiX5wmAulJpjesUuJbARJcZifkJ696WZRdvNaeLI=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=CJ5BpbuWiCPyn2gofPxBB68BvUxxXjFQW6xOuVYkdJfOs+lEaZkdDP80aOE+sltc92GsASqdNn8Tvk2NMfDAI4VRQqiA1ItYrcMCPlTR1+a21SC0FFPCkMne5QEhh5i6BuaaOBSSC4boniTYCSmdypS7NNhSQ0CLbbfwwj9MNZc= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=agCwtc60 DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 39BE14BA2E0C Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-c8b49639fbaso1608367a12.0 for ; Mon, 22 Jun 2026 03:52:16 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782125535; x=1782730335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=okW+Y3OViOojtkT9kZRRVWnyY89WzJ1eebCDaiT8byE=; b=a/dPDaEdS31Vpg9PS8S6dW2EYHd4X+7sbPNGuW82rhUVGy9vLGy8i0S8ytT56i6pAg fJU1HjeiWrDCSrdcSBBRvsG9ZWjEnhbF1hGeQ3VqqFnPpViqYDXk0dbaAOzqal2ibju8 4b8FrVDx5xYxGO1nWRq4f/A3luLYouxhb/5xy0ALvYXuwI5COR7gFBWLnIGvpR2+0exu FJ21Ym4t4x+/8VQxUvP02GH0P1xasPLm1NJJq8x/0Qeqhj4+FaZI/lEjdnurEwhEw0j7 23PuYxvRAvqZ2jNCLwf+nS8RjSup2mK76bh4j3WZKXfyr8b/Q7nvWb6nAD2yecGbz2bg RmlQ== X-Gm-Message-State: AOJu0YxI8z82XqAIGB7ScHZdQNUS18+brSHYkfv2F8bH0+m6LBR1VOcq ahYD1n43tb2iEQWRcMPwDtdiUsQHlJR7BL2KP8Y5am31sKr+alZtEEGRYyA7LEfrXb40Ld+5ec+ teTwVi2DslcBi+VGf/vdI0Bm0n4ZurAgY7i1gSIHfmpkmbk6qQz4R3ES8JGIFGLa/CvuN5SVWbY gj3qx0OdVEvMv2EcizGbxQXrKXUcCtuJ4IQ3h0LqGoWq+w X-Gm-Gg: AfdE7ck2E32I753l9v5vFOwkfC+qRPH28hMifakGMquhRbWoU6HZgW5ka7CiG1vNwWO D0GrVWvB/l4hlqyc6RJORLT0MPiet9eYlt+v7R+gx5MBxvpC0hppDtDSWnxR98xiKUPLq3+gt1O hnc8WrRXuMNjNxkmJgPn6IJJDKkL6ZiEv6WSCOC7YNvdavT4z4WA2KIu5AMenE95nV/h8QdQdnr Yu5PsaFV+uxFi+GMGfFlF1+j+jIs7bxywa5YpG0oybWjBtCYKKwRn6Xyx/C4FrJFaKLHezEUl81 Rv5gAD4+A0To9O+daFdfSEVQskc4d/ukzJTYABG89f+GDHb0qwZhV/BXaIjvz2bTzqaue/2SPi+ jbWKjVQl05vd6dFS8GoGqr6bt3rqyRkmVDrQNy2P12Esh7nkIDO7lVv7eEnBe9V1/sl1zFxpUbe XK2G1/8T+bm3ViC6oAZSvkpAg/XKEKozLN4hA1kw== X-Received: by 2002:a05:6a20:428b:b0:3b4:7cd8:5853 with SMTP id adf61e73a8af0-3bb69baf411mr14323093637.6.1782125534979; Mon, 22 Jun 2026 03:52:14 -0700 (PDT) Received: from hsinchu18.internal.sifive.com ([210.176.154.34]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c8bc5a1dc13sm6847599a12.26.2026.06.22.03.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 03:52:14 -0700 (PDT) To: newlib@sourceware.org, kito.cheng@gmail.com Cc: Jesse Huang Subject: [committed 3/3] RISC-V: save and restore ssp on setjmp/longjmp Date: Mon, 22 Jun 2026 18:52:02 +0800 Message-ID: <20260622105202.664207-3-kito.cheng@sifive.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260622105202.664207-1-kito.cheng@sifive.com> References: <20260622105202.664207-1-kito.cheng@sifive.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: newlib@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Newlib mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Kito Cheng via Newlib From: Kito Cheng Reply-To: Kito Cheng Errors-To: newlib-bounces~patchwork=sourceware.org@sourceware.org From: Jesse Huang --- newlib/libc/include/machine/setjmp.h | 11 +++++-- newlib/libc/machine/riscv/setjmp.S | 43 ++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 2 deletions(-) diff --git a/newlib/libc/include/machine/setjmp.h b/newlib/libc/include/machine/setjmp.h index ab820ed94..4e74bdb0f 100644 --- a/newlib/libc/include/machine/setjmp.h +++ b/newlib/libc/include/machine/setjmp.h @@ -431,10 +431,17 @@ _BEGIN_STD_C otherwise in rv32imafd, store/restore FPR may mis-align. */ #define _JBTYPE long long #ifdef __riscv_32e -#define _JBLEN ((4*sizeof(long))/sizeof(long)) +#define __JBLEN ((4*sizeof(long))/sizeof(long)) #else -#define _JBLEN ((14*sizeof(long) + 12*sizeof(double))/sizeof(long)) +#define __JBLEN ((14*sizeof(long) + 12*sizeof(double))/sizeof(long)) #endif + +#ifdef __riscv_shadow_stack +#define _JBLEN (__JBLEN + 1) +#else +#define _JBLEN (__JBLEN) +#endif + #endif #ifdef __CSKYABIV2__ diff --git a/newlib/libc/machine/riscv/setjmp.S b/newlib/libc/machine/riscv/setjmp.S index a29c15f29..336ac5b4e 100644 --- a/newlib/libc/machine/riscv/setjmp.S +++ b/newlib/libc/machine/riscv/setjmp.S @@ -60,6 +60,18 @@ ENTRY(setjmp) FREG_S fs11,14*SZREG+11*SZFREG(a0) #endif +#ifdef __riscv_shadow_stack + /* read ssp into t0 */ + ssrdp t0 +# ifndef __riscv_float_abi_soft + REG_S t0, 14*SZREG+12*SZFREG(a0) +# elif defined (__riscv_32e) + REG_S t0, 4*SZREG(a0) +# else + REG_S t0, 14*SZREG(a0) +# endif +#endif + li a0, 0 ret END(setjmp) @@ -110,6 +122,37 @@ ENTRY(longjmp) FREG_L fs9, 14*SZREG+ 9*SZFREG(a0) FREG_L fs10,14*SZREG+10*SZFREG(a0) FREG_L fs11,14*SZREG+11*SZFREG(a0) +#endif +#ifdef __riscv_shadow_stack + /* read ssp into t0 */ + ssrdp t0 + /* skip unwinding if ss is not enabled */ + beqz t0, .Lunwind_fin +# ifndef __riscv_float_abi_soft + REG_L t1, 14*SZREG+12*SZFREG(a0) +# elif defined (__riscv_32e) + REG_L t0, 4*SZREG(a0) +# else + REG_L t1, 14*SZREG(a0) +# endif +.Lunwind: + /* should not be taken in normal condition */ + bleu t1, t0, .Lunwind_fin + /* The unwinding algorithm came from the zicfiss spec, increase ssp + by at most a page size to ensure always run into a guard page + before accidentally point to another legal shadow stack page */ + /* t0 = (t1 - t0 >= 4096) ? t0 + 4096 : t1 */ + lui a0, 1 + add t0, t0, a0 + bleu t0, t1, 1f + mv t0, t1 +1: + csrw ssp, t0 + /* Test if the location pointed by ssp is legal */ + sspush x5 + sspopchk x5 + j .Lunwind +.Lunwind_fin: #endif seqz a0, a1