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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4650959ae47sm6985301f8f.16.2026.06.19.04.47.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:47:11 -0700 (PDT) Message-ID: <81e3d6d0-39d3-42e3-a8cd-d6b11b8449a4@suse.com> Date: Fri, 19 Jun 2026 13:47:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 01/13] RISC-V: add dedicated vector arithmetic .insn forms From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org As .insn documentation states, using the available .insn forms can be a little challenging. For OP_V and OP_VE, help the situation by providing a few more dedicated forms. Reviewed-by: Jiawei --- No form is provided for OPCFG: Such insns may better use "r" forms, or whatever is best suited there. For OPIVI permitting both signed (Vi) and unsigned (Vj) immediates might be nice, but won't work with the present parsing (needs delaying as_bad()). To help encoding V*UNARY* insns, forms with immediates in the respective positions may be helpful. Thoughts? (Some of the testcase additions are commented upon accordingly.) --- v3: Add O7 as first operand. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1631,6 +1631,7 @@ validate_riscv_insn (const struct riscv_ switch (*++oparg) { case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; + case '6': USE_BITS (OP_MASK_FUNCT6, OP_SH_FUNCT6); break; case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; default: @@ -3763,6 +3764,10 @@ riscv_ip (char *str, struct riscv_cl_ins INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); break; + case 6: + INSERT_OPERAND (FUNCT6, *ip, imm_expr->X_add_number); + break; + case 3: INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); break; --- a/gas/testsuite/gas/riscv/insn.d +++ b/gas/testsuite/gas/riscv/insn.d @@ -70,6 +70,20 @@ Disassembly of section .text: [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+022180d7[ ]+vadd\.vv[ ]+v1,v2,v3 +[^:]+:[ ]+2c2081d7[ ]+vxor\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+182091d7[ ]+vfmax\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+fc1111d7[ ]+vfwnmsac\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+422010d7[ ]+vfmv\.f\.s[ ]+ft1,v2 +[^:]+:[ ]+7a20a1d7[ ]+vmnor\.mm[ ]+v3,v2,v1 +[^:]+:[ ]+422020d7[ ]+vmv\.x\.s[ ]+ra,v2 +[^:]+:[ ]+8220a1f7[ ]+vsm3me\.vv[ ]+v3,v2,v1 +[^:]+:[ ]+2c20b1d7[ ]+vxor\.vi[ ]+v3,v2,1,v0\.t +[^:]+:[ ]+2c20c1d7[ ]+vxor\.vx[ ]+v3,v2,ra,v0\.t +[^:]+:[ ]+1820d1d7[ ]+vfmax\.vf[ ]+v3,v2,ft1,v0\.t +[^:]+:[ ]+fc1151d7[ ]+vfwnmsac\.vf[ ]+v3,ft2,v1,v0\.t +[^:]+:[ ]+420150d7[ ]+vfmv\.s\.f[ ]+v1,ft2 +[^:]+:[ ]+bc1161d7[ ]+vnmsac\.vx[ ]+v3,sp,v1,v0\.t +[^:]+:[ ]+420160d7[ ]+vmv\.s\.x[ ]+v1,sp [^:]+:[ ]+0001[ ]+nop [^:]+:[ ]+00000013[ ]+nop [^:]+:[ ]+001f 0000 0000[ ].* --- a/gas/testsuite/gas/riscv/insn.s +++ b/gas/testsuite/gas/riscv/insn.s @@ -56,6 +56,24 @@ target: .insn r OP_V, 0, 1, x1, x3, x2 + .option push + .option arch, +v,+zvksh # the latter only for disassembly + .insn ivv OP_V, 0x0b, v3, v2, v1, v0.t + .insn fvv OP_V, 0x06, v3, v2, v1, v0.t + .insn fvv OP_V, 0x3f, v3, v1, v2, v0.t + .insn fvv OP_V, 0x10, f1, v2, v0 # last operand is opcode + .insn mvv OP_V, 0x1e, v3, v2, v1 + .insn mvv OP_V, 0x10, x1, v2, v0 # last operand is opcode + .insn mvv OP_VE, 0x20, v3, v2, v1 + .insn ivi OP_V, 0x0b, v3, v2, 1, v0.t + .insn ivx OP_V, 0x0b, v3, v2, x1, v0.t + .insn fvf OP_V, 0x06, v3, v2, f1, v0.t + .insn fvf OP_V, 0x3f, v3, v1, f2, v0.t + .insn fvf OP_V, 0x10, v1, v0, f2 # middle operand is opcode + .insn mvx OP_V, 0x2f, v3, v1, x2, v0.t + .insn mvx OP_V, 0x10, v1, v0, x2 # middle operand is opcode + .option pop + .insn 0x0001 .insn 0x00000013 .insn 0x0000001f --- a/gas/testsuite/gas/riscv/insn-dwarf.d +++ b/gas/testsuite/gas/riscv/insn-dwarf.d @@ -60,28 +60,42 @@ insn.s +53 +0x9a.* insn.s +54 +0x9e.* insn.s +55 +0xa2.* insn.s +57 +0xa6.* -insn.s +59 +0xaa.* -insn.s +60 +0xac.* -insn.s +61 +0xb0.* -insn.s +62 +0xb6.* -insn.s +63 +0xbe.* -insn.s +64 +0xc8.* -insn.s +65 +0xd4.* -insn.s +66 +0xea.* -insn.s +67 +0xec.* -insn.s +68 +0xf0.* -insn.s +69 +0xf6.* -insn.s +70 +0xfe.* -insn.s +71 +0x108.* -insn.s +72 +0x114.* -insn.s +74 +0x12a.* -insn.s +75 +0x134.* -insn.s +76 +0x13e.* -insn.s +77 +0x154.* -insn.s +78 +0x16a.* -insn.s +79 +0x180.* -insn.s +80 +0x196.* -insn.s +81 +0x1ac.* -insn.s +83 +0x1c2.* -insn.s +- +0x1c6 +insn.s +61 +0xaa.* +insn.s +62 +0xae.* +insn.s +63 +0xb2.* +insn.s +64 +0xb6.* +insn.s +65 +0xba.* +insn.s +66 +0xbe.* +insn.s +67 +0xc2.* +insn.s +68 +0xc6.* +insn.s +69 +0xca.* +insn.s +70 +0xce.* +insn.s +71 +0xd2.* +insn.s +72 +0xd6.* +insn.s +73 +0xda.* +insn.s +74 +0xde.* +insn.s +77 +0xe2.* +insn.s +78 +0xe4.* +insn.s +79 +0xe8.* +insn.s +80 +0xee.* +insn.s +81 +0xf6.* +insn.s +82 +0x100.* +insn.s +83 +0x10c.* +insn.s +84 +0x122.* +insn.s +85 +0x124.* +insn.s +86 +0x128.* +insn.s +87 +0x12e.* +insn.s +88 +0x136.* +insn.s +89 +0x140.* +insn.s +90 +0x14c.* +insn.s +92 +0x162.* +insn.s +93 +0x16c.* +insn.s +94 +0x176.* +insn.s +95 +0x18c.* +insn.s +96 +0x1a2.* +insn.s +97 +0x1b8.* +insn.s +98 +0x1ce.* +insn.s +99 +0x1e4.* +insn.s +101 +0x1fa.* +insn.s +- +0x1fe #pass --- a/gas/testsuite/gas/riscv/insn-na.d +++ b/gas/testsuite/gas/riscv/insn-na.d @@ -59,6 +59,20 @@ Disassembly of section .text: [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+00c58533[ ]+add[ ]+a0,a1,a2 [^:]+:[ ]+022180d7[ ]+vadd\.vv[ ]+v1,v2,v3 +[^:]+:[ ]+2c2081d7[ ]+vxor\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+182091d7[ ]+vfmax\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+fc1111d7[ ]+vfwnmsac\.vv[ ]+v3,v2,v1,v0\.t +[^:]+:[ ]+422010d7[ ]+vfmv\.f\.s[ ]+ft1,v2 +[^:]+:[ ]+7a20a1d7[ ]+vmnor\.mm[ ]+v3,v2,v1 +[^:]+:[ ]+422020d7[ ]+vmv\.x\.s[ ]+ra,v2 +[^:]+:[ ]+8220a1f7[ ]+vsm3me\.vv[ ]+v3,v2,v1 +[^:]+:[ ]+2c20b1d7[ ]+vxor\.vi[ ]+v3,v2,1,v0\.t +[^:]+:[ ]+2c20c1d7[ ]+vxor\.vx[ ]+v3,v2,ra,v0\.t +[^:]+:[ ]+1820d1d7[ ]+vfmax\.vf[ ]+v3,v2,ft1,v0\.t +[^:]+:[ ]+fc1151d7[ ]+vfwnmsac\.vf[ ]+v3,ft2,v1,v0\.t +[^:]+:[ ]+420150d7[ ]+vfmv\.s\.f[ ]+v1,ft2 +[^:]+:[ ]+bc1161d7[ ]+vnmsac\.vx[ ]+v3,sp,v1,v0\.t +[^:]+:[ ]+420160d7[ ]+vmv\.s\.x[ ]+v1,sp [^:]+:[ ]+0001[ ]+c\.addi[ ]+zero,0 [^:]+:[ ]+00000013[ ]+addi[ ]+zero,zero,0 [^:]+:[ ]+001f 0000 0000[ ].* --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -351,6 +351,9 @@ static inline unsigned int riscv_insn_le /* RVV fields. */ +#define OP_MASK_FUNCT6 0x3fU +#define OP_SH_FUNCT6 26 + #define OP_MASK_VD 0x1f #define OP_SH_VD 7 #define OP_MASK_VS1 0x1f --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -3660,6 +3660,17 @@ const struct riscv_opcode riscv_insn_typ {"j", 0, INSN_CLASS_I, "O7,d,a", 0, 0, NULL, 0 }, {"j", 0, INSN_CLASS_F, "O7,D,a", 0, 0, NULL, 0 }, +{"ivv", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,VsVm", 0x0000, 0x7000, NULL, 0 }, +{"fvv", 0, INSN_CLASS_ZVEF, "O7,F6,Vd,Vt,VsVm", 0x1000, 0x7000, NULL, 0 }, +{"fvv", 0, INSN_CLASS_ZVEF, "O7,F6,D,Vt,VsVm", 0x1000, 0x7000, NULL, 0 }, +{"mvv", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,VsVm", 0x2000, 0x7000, NULL, 0 }, +{"mvv", 0, INSN_CLASS_V, "O7,F6,d,Vt,VsVm", 0x2000, 0x7000, NULL, 0 }, +{"ivi", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,ViVm", 0x3000, 0x7000, NULL, 0 }, +{"ivx", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,sVm", 0x4000, 0x7000, NULL, 0 }, +{"fvf", 0, INSN_CLASS_ZVEF, "O7,F6,Vd,Vt,SVm", 0x5000, 0x7000, NULL, 0 }, +{"mvx", 0, INSN_CLASS_V, "O7,F6,Vd,Vt,sVm", 0x6000, 0x7000, NULL, 0 }, +{"mvx", 0, INSN_CLASS_V, "O7,F6,d,Vt,sVm", 0x6000, 0x7000, NULL, 0 }, + {"cr", 0, INSN_CLASS_ZCA, "O2,CF4,d,CV", 0, 0, NULL, 0 }, {"cr", 0, INSN_CLASS_ZCF, "O2,CF4,D,CV", 0, 0, NULL, 0 }, {"cr", 0, INSN_CLASS_ZCF, "O2,CF4,d,CT", 0, 0, NULL, 0 }, From patchwork Fri Jun 19 11:47:41 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 137417 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CEAA24BAD17F for ; Fri, 19 Jun 2026 11:48:44 +0000 (GMT) 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49245711032sm17988995e9.0.2026.06.19.04.47.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:47:42 -0700 (PDT) Message-ID: <1a57710b-44d4-4852-91b1-01665b8f383c@suse.com> Date: Fri, 19 Jun 2026 13:47:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 02/13] RISC-V: EEW64 checking From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Like the assembler, the disassembler should also use the INSN_V_EEW64 flag. Respectively marked insns shouldn't be disassembled normally when Zve64x isn't enabled. While there also drop the redundant Zve32x check from gas: All affected insns are INSN_CLASS_V, which means Zve32x was already checked to be enabled (both V and Zve64x imply Zve32x). --- Question is why a flag was used in the first place: The property could be expressed by a new INSN_CLASS_ZVE64X, couldn't it? --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2964,10 +2964,9 @@ riscv_ip (char *str, struct riscv_cl_ins insn_with_csr = false; } - /* The (segmant) load and store with EEW 64 cannot be used + /* The (segment) load and store with EEW 64 cannot be used when zve32x is enabled. */ - if (ip->insn_mo->pinfo & INSN_V_EEW64 - && riscv_subset_supports (&riscv_rps_as, "zve32x") + if ((ip->insn_mo->pinfo & INSN_V_EEW64) && !riscv_subset_supports (&riscv_rps_as, "zve64x")) { error.msg = _("illegal opcode for zve32x"); --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -1018,10 +1018,16 @@ riscv_disassemble_insn (bfd_vma memaddr, && (op->xlen_requirement != pd->xlen)) continue; /* Is this instruction supported by the current architecture? */ - if (!pd->all_ext - && !riscv_multi_subset_supports (&pd->riscv_rps_dis, - op->insn_class)) - continue; + if (!pd->all_ext) + { + if (!riscv_multi_subset_supports (&pd->riscv_rps_dis, + op->insn_class)) + continue; + + if ((op->pinfo & INSN_V_EEW64) + && !riscv_subset_supports (&pd->riscv_rps_dis, "zve64x")) + continue; + } /* It's a match. */ (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic, --- /dev/null +++ b/gas/testsuite/gas/riscv/eew64.d @@ -0,0 +1,13 @@ +#as: -march=rv32i +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+0:[ ]+020ff007[ ]+\.insn[ ]+4, ?0x020ff007 + +0+004 : +[ ]+4:[ ]+020ff007[ ]+vle64\.v[ ]+v0,\(t6\) +#pass --- /dev/null +++ b/gas/testsuite/gas/riscv/eew64.s @@ -0,0 +1,12 @@ + .option arch, rv32i + .option arch, +zve32x + +eew32: + # vle64.v v0, (x31) + .insn 4, 0x020ff007 + + .option arch, rv32i + .option arch, +zve64x + +eew64: + vle64.v v0, (x31) From patchwork Fri Jun 19 11:48:10 2026 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-46508a04c15sm7617287f8f.3.2026.06.19.04.48.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:48:10 -0700 (PDT) Message-ID: <7be489de-fb0b-4062-9e40-1238e7a00fc1@suse.com> Date: Fri, 19 Jun 2026 13:48:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 03/13] bfd/RISC-V: Zvfbfwma implies Zvfbfmin From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This is pretty clear from the spec. --- While the spec is also explicit there: I would have expected Zvfbfmin (not Zvfbfwma) to be what implies Zfbfmin. Is there an explanation for this? --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1232,7 +1232,7 @@ static const struct riscv_implicit_subse {"v", "+zve64d,+zvl128b", check_implicit_always}, {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always}, {"zvfhmin", "+zve32f", check_implicit_always}, - {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always}, + {"zvfbfwma", "+zfbfmin,+zvfbfmin", check_implicit_always}, {"zvfbfmin", "+zve32f", check_implicit_always}, {"zve64d", "+d,+zve64f", check_implicit_always}, {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always}, --- a/gas/testsuite/gas/riscv/imply.d +++ b/gas/testsuite/gas/riscv/imply.d @@ -27,7 +27,7 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0 From patchwork Fri Jun 19 11:48:56 2026 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4650bc428d9sm7429738f8f.27.2026.06.19.04.48.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:48:56 -0700 (PDT) Message-ID: <0450f2b8-fa5b-4921-b330-d9fe2e2c54b2@suse.com> Date: Fri, 19 Jun 2026 13:48:56 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org The specification is quite explicit about this. --- Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it seems unlikely to be mere chance that Zve* come ahead of all other Zv* in riscv_supported_std_z_ext[]. --- v3: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1306,6 +1306,15 @@ static const struct riscv_implicit_subse {"zvksc", "+zvks,+zvbc", check_implicit_always}, {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always}, + {"zvbc", "+zve32x", check_implicit_always}, + {"zvkb", "+zve32x", check_implicit_always}, + {"zvkg", "+zve32x", check_implicit_always}, + {"zvkned", "+zve32x", check_implicit_always}, + {"zvknha", "+zve32x", check_implicit_always}, + {"zvknhb", "+zve32x", check_implicit_always}, + {"zvksed", "+zve32x", check_implicit_always}, + {"zvksh", "+zve32x", check_implicit_always}, + {"sdtrig", "+zicsr", check_implicit_always}, {"smaia", "+ssaia", check_implicit_always}, --- a/gas/testsuite/gas/riscv/imply.d +++ b/gas/testsuite/gas/riscv/imply.d @@ -87,13 +87,13 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0 -[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbb1p0_zve32x1p0_zvkb1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0 From patchwork Fri Jun 19 11:49:25 2026 Content-Type: text/plain; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4923fd1f886sm59693125e9.4.2026.06.19.04.49.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:49:26 -0700 (PDT) Message-ID: <50d06f39-9de9-476e-a0ed-e211ee777950@suse.com> Date: Fri, 19 Jun 2026 13:49:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 05/13] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Like FCVT.D.W{,U} and FCVT.Q.W{,U} these also are unaffected by rounding mode, and hence allowing for a respective operand is bogus. (Otherwise MASK_RM should also be used in the match field for the respectively other forms.) --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1165,9 +1165,7 @@ const struct riscv_opcode riscv_opcodes[ {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, {"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, {"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 }, {"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s,m", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_ZCA, "", 0, 0xffffU, match_opcode, 0 }, From patchwork Fri Jun 19 11:50:13 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 137421 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 00A4D4BAE7CD for ; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49246403653sm9374145e9.13.2026.06.19.04.50.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:50:13 -0700 (PDT) Message-ID: <4fe30051-625f-448d-82b3-a232e9b0308a@suse.com> Date: Fri, 19 Jun 2026 13:50:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 06/13] RISC-V: make FP rounding mode an optional operand From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, UPPERCASE_50_75 shortcircuit=no autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Model this after Vm (and somewhat after its VM counterpart): It's similarly always last, and we can hence similarly reduce the number of entries in the opcode table. The exception being FCVTMOD.W.D, where M needs using. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1612,6 +1612,7 @@ validate_riscv_insn (const struct riscv_ case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; case 'R': /* RS3, floating point. */ case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; + case 'M': case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; @@ -3505,7 +3506,17 @@ riscv_ip (char *str, struct riscv_cl_ins } continue; - case 'm': /* Rounding mode. */ + case 'm': /* Optional rounding mode. */ + if (*asarg == '\0') + { + INSERT_OPERAND (RM, *ip, OP_MASK_RM); + continue; + } + if (*asarg != ',') + break; + ++asarg; + /* Fall through. */ + case 'M': /* Rounding mode. */ if (arg_lookup (&asarg, riscv_rm, ARRAY_SIZE (riscv_rm), ®no)) { --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -536,6 +536,11 @@ print_insn_args (const char *oparg, insn break; case 'm': + if (EXTRACT_OPERAND (RM, l) == OP_MASK_RM) + break; + print (info->stream, dis_style_text, ","); + /* Fall through. */ + case 'M': arg_print (info, EXTRACT_OPERAND (RM, l), riscv_rm, ARRAY_SIZE (riscv_rm)); break; --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -915,61 +915,40 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 }, {"fsgnjn.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 }, {"fsgnjx.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 }, -{"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 }, -{"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 }, -{"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 }, -{"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 }, -{"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 }, -{"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 }, -{"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 }, -{"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,m", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 }, -{"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,S", MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 }, -{"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,S,m", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 }, +{"fadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 }, +{"fsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 }, +{"fmul.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 }, +{"fdiv.h", 0, INSN_CLASS_ZFH_INX, "D,S,Tm", MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 }, +{"fsqrt.h", 0, INSN_CLASS_ZFH_INX, "D,Sm", MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 }, {"fmin.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 }, {"fmax.h", 0, INSN_CLASS_ZFH_INX, "D,S,T", MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 }, -{"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 }, -{"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 }, -{"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 }, -{"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 }, -{"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 }, -{"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 }, -{"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R", MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 }, -{"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 }, -{"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 }, -{"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 }, -{"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 }, -{"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 }, -{"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, -{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, +{"fmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 }, +{"fnmadd.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 }, +{"fmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 }, +{"fnmsub.h", 0, INSN_CLASS_ZFH_INX, "D,S,T,Rm", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 }, +{"fcvt.w.h", 0, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 }, +{"fcvt.wu.h", 0, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 }, +{"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, +{"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, {"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, {"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, -{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 }, -{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,S,m", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S,m", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, -{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S,m", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, +{"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,Sm", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, +{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, +{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, {"fclass.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, {"flt.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, {"fle.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 }, {"fgt.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLT_H, MASK_FLT_H, match_opcode, INSN_ALIAS }, {"fge.h", 0, INSN_CLASS_ZFH_INX, "d,T,S", MATCH_FLE_H, MASK_FLE_H, match_opcode, INSN_ALIAS }, -{"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 }, -{"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, -{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,S,m", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 }, -{"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 }, -{"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 }, -{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s", MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,s,m", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, +{"fcvt.l.h", 64, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 }, +{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX, "d,Sm", MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 }, +{"fcvt.h.l", 64, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 }, +{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 }, /* Zfbfmin instructions. */ -{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 }, -{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, +{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,Sm", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 }, {"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S", MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 }, /* Single-precision floating-point instruction subset. */ @@ -1007,48 +986,31 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 }, {"fsgnjn.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 }, {"fsgnjx.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 }, -{"fadd.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 }, -{"fadd.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, -{"fsub.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 }, -{"fsub.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, -{"fmul.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 }, -{"fmul.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, -{"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 }, -{"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,T,m", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, -{"fsqrt.s", 0, INSN_CLASS_F_INX, "D,S", MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 }, -{"fsqrt.s", 0, INSN_CLASS_F_INX, "D,S,m", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, +{"fadd.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 }, +{"fsub.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 }, +{"fmul.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 }, +{"fdiv.s", 0, INSN_CLASS_F_INX, "D,S,Tm", MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 }, +{"fsqrt.s", 0, INSN_CLASS_F_INX, "D,Sm", MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 }, {"fmin.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 }, {"fmax.s", 0, INSN_CLASS_F_INX, "D,S,T", MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 }, -{"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 }, -{"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, -{"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 }, -{"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, -{"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 }, -{"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, -{"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R", MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 }, -{"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, -{"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 }, -{"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, -{"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, -{"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 }, -{"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, -{"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, +{"fmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 }, +{"fnmadd.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 }, +{"fmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 }, +{"fnmsub.s", 0, INSN_CLASS_F_INX, "D,S,T,Rm", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 }, +{"fcvt.w.s", 0, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 }, +{"fcvt.wu.s", 0, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 }, +{"fcvt.s.w", 0, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 }, +{"fcvt.s.wu", 0, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 }, {"fclass.s", 0, INSN_CLASS_F_INX, "d,S", MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 }, {"feq.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 }, {"flt.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 }, {"fle.s", 0, INSN_CLASS_F_INX, "d,S,T", MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 }, {"fgt.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLT_S, MASK_FLT_S, match_opcode, INSN_ALIAS }, {"fge.s", 0, INSN_CLASS_F_INX, "d,T,S", MATCH_FLE_S, MASK_FLE_S, match_opcode, INSN_ALIAS }, -{"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 }, -{"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, -{"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,S", MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,S,m", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, -{"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 }, -{"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, -{"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,s", MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,s,m", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, +{"fcvt.l.s", 64, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 }, +{"fcvt.lu.s", 64, INSN_CLASS_F_INX, "d,Sm", MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 }, +{"fcvt.s.l", 64, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 }, +{"fcvt.s.lu", 64, INSN_CLASS_F_INX, "D,sm", MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 }, /* Double-precision floating-point instruction subset. */ {"fld", 0, INSN_CLASS_ZCD, "D,Cn(Cc)", MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, @@ -1065,35 +1027,23 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, {"fsgnjn.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, {"fsgnjx.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,T,m", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, +{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, +{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, +{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, +{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, +{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, {"fmin.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, {"fmax.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R", MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, +{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, +{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, +{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, +{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, +{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, +{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, {"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, {"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, {"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,S,m", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, +{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, {"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, {"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, {"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, @@ -1102,14 +1052,10 @@ const struct riscv_opcode riscv_opcodes[ {"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 }, -{"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,S", MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,S,m", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 }, -{"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,s,m", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, +{"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, +{"fcvt.lu.d", 64, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 }, +{"fcvt.d.l", 64, INSN_CLASS_D_INX, "D,sm", MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 }, +{"fcvt.d.lu", 64, INSN_CLASS_D_INX, "D,sm", MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 }, /* Quad-precision floating-point instruction subset. */ {"flq", 0, INSN_CLASS_Q, "D,o(s)", MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE }, @@ -1122,48 +1068,33 @@ const struct riscv_opcode riscv_opcodes[ {"fsgnj.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, {"fsgnjn.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, {"fsgnjx.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,T,m", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, +{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, +{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, +{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, +{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, +{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, {"fmin.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, {"fmax.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R", MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, +{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, +{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, +{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, +{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, +{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, +{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, {"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, {"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, {"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, {"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,S,m", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, +{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, +{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, {"fclass.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, {"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, {"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, {"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, {"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS }, {"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS }, -{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S", MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,S,m", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, +{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, +{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, {"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, {"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, @@ -1306,23 +1237,15 @@ const struct riscv_opcode riscv_opcodes[ {"fmaxm.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,T", MATCH_FMAXM_Q, MASK_FMAXM_Q, match_opcode, 0 }, {"fminm.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMINM_H, MASK_FMINM_H, match_opcode, 0 }, {"fmaxm.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMAXM_H, MASK_FMAXM_H, match_opcode, 0 }, -{"fround.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUND_S|MASK_RM, MASK_FROUND_S|MASK_RM, match_opcode, 0 }, -{"fround.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUND_S, MASK_FROUND_S, match_opcode, 0 }, -{"froundnx.s", 0, INSN_CLASS_ZFA, "D,S", MATCH_FROUNDNX_S|MASK_RM, MASK_FROUNDNX_S|MASK_RM, match_opcode, 0 }, -{"froundnx.s", 0, INSN_CLASS_ZFA, "D,S,m", MATCH_FROUNDNX_S, MASK_FROUNDNX_S, match_opcode, 0 }, -{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUND_D|MASK_RM, MASK_FROUND_D|MASK_RM, match_opcode, 0 }, -{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUND_D, MASK_FROUND_D, match_opcode, 0 }, -{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S", MATCH_FROUNDNX_D|MASK_RM, MASK_FROUNDNX_D|MASK_RM, match_opcode, 0 }, -{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,S,m", MATCH_FROUNDNX_D, MASK_FROUNDNX_D, match_opcode, 0 }, -{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUND_Q|MASK_RM, MASK_FROUND_Q|MASK_RM, match_opcode, 0 }, -{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUND_Q, MASK_FROUND_Q, match_opcode, 0 }, -{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S", MATCH_FROUNDNX_Q|MASK_RM, MASK_FROUNDNX_Q|MASK_RM, match_opcode, 0 }, -{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,S,m", MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, match_opcode, 0 }, -{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUND_H|MASK_RM, MASK_FROUND_H|MASK_RM, match_opcode, 0 }, -{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUND_H, MASK_FROUND_H, match_opcode, 0 }, -{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S", MATCH_FROUNDNX_H|MASK_RM, MASK_FROUNDNX_H|MASK_RM, match_opcode, 0 }, -{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUNDNX_H, MASK_FROUNDNX_H, match_opcode, 0 }, -{"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,m", MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, match_opcode, 0 }, +{"fround.s", 0, INSN_CLASS_ZFA, "D,Sm", MATCH_FROUND_S, MASK_FROUND_S, match_opcode, 0 }, +{"froundnx.s", 0, INSN_CLASS_ZFA, "D,Sm", MATCH_FROUNDNX_S, MASK_FROUNDNX_S, match_opcode, 0 }, +{"fround.d", 0, INSN_CLASS_D_AND_ZFA, "D,Sm", MATCH_FROUND_D, MASK_FROUND_D, match_opcode, 0 }, +{"froundnx.d", 0, INSN_CLASS_D_AND_ZFA, "D,Sm", MATCH_FROUNDNX_D, MASK_FROUNDNX_D, match_opcode, 0 }, +{"fround.q", 0, INSN_CLASS_Q_AND_ZFA, "D,Sm", MATCH_FROUND_Q, MASK_FROUND_Q, match_opcode, 0 }, +{"froundnx.q", 0, INSN_CLASS_Q_AND_ZFA, "D,Sm", MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, match_opcode, 0 }, +{"fround.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,Sm", MATCH_FROUND_H, MASK_FROUND_H, match_opcode, 0 }, +{"froundnx.h", 0, INSN_CLASS_ZFH_AND_ZFA, "D,Sm", MATCH_FROUNDNX_H, MASK_FROUNDNX_H, match_opcode, 0 }, +{"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA, "d,S,M", MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, match_opcode, 0 }, {"fmvh.x.d", 32, INSN_CLASS_D_AND_ZFA, "d,S", MATCH_FMVH_X_D, MASK_FMVH_X_D, match_opcode, 0 }, {"fmvp.d.x", 32, INSN_CLASS_D_AND_ZFA, "D,s,t", MATCH_FMVP_D_X, MASK_FMVP_D_X, match_opcode, 0 }, {"fmvh.x.q", 64, INSN_CLASS_Q_AND_ZFA, "d,S", MATCH_FMVH_X_Q, MASK_FMVH_X_Q, match_opcode, 0 }, From patchwork Fri Jun 19 11:50:45 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 137423 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 540544BAD178 for ; Fri, 19 Jun 2026 11:55:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 540544BAD178 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4650bc429a1sm7224885f8f.30.2026.06.19.04.50.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:50:46 -0700 (PDT) Message-ID: Date: Fri, 19 Jun 2026 13:50:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 07/13] RISC-V: check operands for Zdinx in RV32 From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Like for Zilsd, register pair operands are required to be encoded with the low bit clear. Since match functions don't have XLEN available, introduce respective flags, to be used explicitly in assembler and disassembler. --- No similar checking is easily possible for scalar vector insns, as element width there isn't encoded in the insn. (Plus V and Zdinx can't be enabled together right now anyway.) We could further use RV32_EVEN_CHECK for Zilsd as well, then allowing to eliminate one or two match functions. (Hence RV32_EVEN_CHECK()'s scope is pretty wide.) --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2928,6 +2928,12 @@ riscv_ip (char *str, struct riscv_cl_ins *imm_reloc = BFD_RELOC_UNUSED; p = percent_op_null; +#define RV32_EVEN_CHECK(form, rclass, regno) \ + (!(ip->insn_mo->pinfo & INSN_RV32_EVEN_##form) \ + || xlen != 32 \ + || (rclass) != RCLASS_GPR \ + || !((regno) & 1)) + for (oparg = insn->args;; ++oparg) { opargStart = oparg; @@ -2935,6 +2941,8 @@ riscv_ip (char *str, struct riscv_cl_ins ++asarg; switch (*oparg) { + enum reg_class rclass; + case '\0': /* End of args. */ if (insn->match_func && !insn->match_func (insn, ip->insn_opcode)) break; @@ -3574,32 +3582,40 @@ riscv_ip (char *str, struct riscv_cl_ins case 'T': /* Floating point RS2. */ case 'U': /* Floating point RS1 and RS2. */ case 'R': /* Floating point RS3. */ - if (reg_lookup (&asarg, - (riscv_subset_supports (&riscv_rps_as, "zfinx") - ? RCLASS_GPR : RCLASS_FPR), ®no)) + rclass = riscv_subset_supports (&riscv_rps_as, "zfinx") + ? RCLASS_GPR : RCLASS_FPR; + if (reg_lookup (&asarg, rclass, ®no)) { char c = *oparg; if (is_whitespace (*asarg)) ++asarg; + switch (c) { case 'D': + if (!RV32_EVEN_CHECK (D, rclass, regno)) + break; INSERT_OPERAND (RD, *ip, regno); - break; + continue; case 'S': + if (!RV32_EVEN_CHECK (S, rclass, regno)) + break; INSERT_OPERAND (RS1, *ip, regno); - break; + continue; case 'U': INSERT_OPERAND (RS1, *ip, regno); /* Fall through. */ case 'T': + if (!RV32_EVEN_CHECK (T, rclass, regno)) + break; INSERT_OPERAND (RS2, *ip, regno); - break; + continue; case 'R': + if (!RV32_EVEN_CHECK (R, rclass, regno)) + break; INSERT_OPERAND (RS3, *ip, regno); - break; + continue; } - continue; } break; @@ -4295,6 +4311,8 @@ riscv_ip (char *str, struct riscv_cl_ins insn_with_csr = false; } +#undef RV32_EVEN_CHECK + out: /* Restore the character we might have clobbered above. */ if (save_c) --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32.d @@ -0,0 +1,52 @@ +#as: -march=rv32i_zdinx +#objdump: -dwr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+02e67553[ ]+fadd\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+02e60553[ ]+fadd\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+0ae67553[ ]+fsub\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+0ae60553[ ]+fsub\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+12e67553[ ]+fmul\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+12e60553[ ]+fmul\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+1ae67553[ ]+fdiv\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+1ae60553[ ]+fdiv\.d[ ]+a0,a2,a4,rne +[ ]+[0-9a-f]+:[ ]+5a067553[ ]+fsqrt\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+5a060553[ ]+fsqrt\.d[ ]+a0,a2,rne +[ ]+[0-9a-f]+:[ ]+2ae60553[ ]+fmin\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+2ae61553[ ]+fmax\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+82e67543[ ]+fmadd\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60543[ ]+fmadd\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754f[ ]+fnmadd\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054f[ ]+fnmadd\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e67547[ ]+fmsub\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e60547[ ]+fmsub\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+82e6754b[ ]+fnmsub\.d[ ]+a0,a2,a4,a6 +[ ]+[0-9a-f]+:[ ]+82e6054b[ ]+fnmsub\.d[ ]+a0,a2,a4,a6,rne +[ ]+[0-9a-f]+:[ ]+c20675d3[ ]+fcvt\.w\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c20605d3[ ]+fcvt\.w\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+c21675d3[ ]+fcvt\.wu\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+c21605d3[ ]+fcvt\.wu\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt\.d\.w[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt\.d\.wu[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt\.d\.s[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+401675d3[ ]+fcvt\.s\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+401605d3[ ]+fcvt\.s\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+42258553[ ]+fcvt\.d\.h[ ]+a0,a1 +[ ]+[0-9a-f]+:[ ]+441675d3[ ]+fcvt\.h\.d[ ]+a1,a2 +[ ]+[0-9a-f]+:[ ]+441605d3[ ]+fcvt\.h\.d[ ]+a1,a2,rne +[ ]+[0-9a-f]+:[ ]+22e60553[ ]+fsgnj\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e61553[ ]+fsgnjn\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+22e62553[ ]+fsgnjx\.d[ ]+a0,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e625d3[ ]+feq\.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e615d3[ ]+flt\.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2e605d3[ ]+fle\.d[ ]+a1,a2,a4 +[ ]+[0-9a-f]+:[ ]+a2c715d3[ ]+flt\.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+a2c705d3[ ]+fle\.d[ ]+a1,a4,a2 +[ ]+[0-9a-f]+:[ ]+22c60553[ ]+fmv\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c61553[ ]+fneg\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+22c62553[ ]+fabs\.d[ ]+a0,a2 +[ ]+[0-9a-f]+:[ ]+e20615d3[ ]+fclass\.d[ ]+a1,a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32.s @@ -0,0 +1,52 @@ +target: + fadd.d a0, a2, a4 + fadd.d a0, a2, a4, rne + fsub.d a0, a2, a4 + fsub.d a0, a2, a4, rne + fmul.d a0, a2, a4 + fmul.d a0, a2, a4, rne + fdiv.d a0, a2, a4 + fdiv.d a0, a2, a4, rne + fsqrt.d a0, a2 + fsqrt.d a0, a2, rne + fmin.d a0, a2, a4 + fmax.d a0, a2, a4 + fmadd.d a0, a2, a4, a6 + fmadd.d a0, a2, a4, a6, rne + fnmadd.d a0, a2, a4, a6 + fnmadd.d a0, a2, a4, a6, rne + fmsub.d a0, a2, a4, a6 + fmsub.d a0, a2, a4, a6, rne + fnmsub.d a0, a2, a4, a6 + fnmsub.d a0, a2, a4, a6, rne + + fcvt.w.d a1, a2 + fcvt.w.d a1, a2, rne + fcvt.wu.d a1, a2 + fcvt.wu.d a1, a2, rne + fcvt.d.w a0, a1 + fcvt.d.wu a0, a1 + + fcvt.d.s a0, a1 + fcvt.s.d a1, a2 + fcvt.s.d a1, a2, rne + + .option push + .option arch, +zhinxmin + fcvt.d.h a0, a1 + fcvt.h.d a1, a2 + fcvt.h.d a1, a2, rne + .option pop + + fsgnj.d a0, a2, a4 + fsgnjn.d a0, a2, a4 + fsgnjx.d a0, a2, a4 + feq.d a1, a2, a4 + flt.d a1, a2, a4 + fle.d a1, a2, a4 + fgt.d a1, a2, a4 + fge.d a1, a2, a4 + fmv.d a0, a2 + fneg.d a0, a2 + fabs.d a0, a2 + fclass.d a1, a2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zdinx +#source: zdinx.s +#error_output: zdinx-rv32-fail.l --- /dev/null +++ b/gas/testsuite/gas/riscv/zdinx-rv32-fail.l @@ -0,0 +1,47 @@ +.*: Assembler messages: +.*: Error: illegal operands `fadd\.d .*' +.*: Error: illegal operands `fadd\.d .*' +.*: Error: illegal operands `fsub\.d .*' +.*: Error: illegal operands `fsub\.d .*' +.*: Error: illegal operands `fmul\.d .*' +.*: Error: illegal operands `fmul\.d .*' +.*: Error: illegal operands `fdiv\.d .*' +.*: Error: illegal operands `fdiv\.d .*' +.*: Error: illegal operands `fsqrt\.d .*' +.*: Error: illegal operands `fsqrt\.d .*' +.*: Error: illegal operands `fmin\.d .*' +.*: Error: illegal operands `fmax\.d .*' +.*: Error: illegal operands `fmadd\.d .*' +.*: Error: illegal operands `fmadd\.d .*' +.*: Error: illegal operands `fnmadd\.d .*' +.*: Error: illegal operands `fnmadd\.d .*' +.*: Error: illegal operands `fmsub\.d .*' +.*: Error: illegal operands `fmsub\.d .*' +.*: Error: illegal operands `fnmsub\.d .*' +.*: Error: illegal operands `fnmsub\.d .*' +.*: Error: illegal operands `fcvt\.w\.d .*' +.*: Error: illegal operands `fcvt\.w\.d .*' +.*: Error: illegal operands `fcvt\.wu\.d .*' +.*: Error: illegal operands `fcvt\.wu\.d .*' +.*: Error: unrecognized opcode `fcvt\.l\.d .*' +.*: Error: unrecognized opcode `fcvt\.l\.d .*' +.*: Error: unrecognized opcode `fcvt\.lu\.d .*' +.*: Error: unrecognized opcode `fcvt\.lu\.d .*' +.*: Error: unrecognized opcode `fcvt\.d\.l .*' +.*: Error: unrecognized opcode `fcvt\.d\.l .*' +.*: Error: unrecognized opcode `fcvt\.d\.lu .*' +.*: Error: unrecognized opcode `fcvt\.d\.lu .*' +.*: Error: illegal operands `fcvt\.s\.d .*' +.*: Error: illegal operands `fcvt\.s\.d .*' +.*: Error: illegal operands `fsgnj\.d .*' +.*: Error: illegal operands `fsgnjn\.d .*' +.*: Error: illegal operands `fsgnjx\.d .*' +.*: Error: illegal operands `feq\.d .*' +.*: Error: illegal operands `flt\.d .*' +.*: Error: illegal operands `fle\.d .*' +.*: Error: illegal operands `fgt\.d .*' +.*: Error: illegal operands `fge\.d .*' +.*: Error: illegal operands `fmv\.d .*' +.*: Error: illegal operands `fneg\.d .*' +.*: Error: illegal operands `fabs\.d .*' +.*: Error: illegal operands `fclass\.d .*' --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -679,6 +679,18 @@ struct riscv_opcode #define INSN_8_BYTE 0x00000040 #define INSN_16_BYTE 0x00000050 +/* Operands required to be an even-numbered register (pair) in RV32. */ +#define INSN_RV32_EVEN_D 0x00000100 +#define INSN_RV32_EVEN_S 0x00000200 +#define INSN_RV32_EVEN_T 0x00000400 /* Also covering U. */ +#define INSN_RV32_EVEN_R 0x00000800 +/* Shorthands for combinations of the above. */ +#define INSN_RV32_EVEN_DS (INSN_RV32_EVEN_D | INSN_RV32_EVEN_S) +#define INSN_RV32_EVEN_DST (INSN_RV32_EVEN_DS | INSN_RV32_EVEN_T) +#define INSN_RV32_EVEN_DSTR (INSN_RV32_EVEN_DST | INSN_RV32_EVEN_R) +#define INSN_RV32_EVEN_DU (INSN_RV32_EVEN_D | INSN_RV32_EVEN_T) +#define INSN_RV32_EVEN_ST (INSN_RV32_EVEN_S | INSN_RV32_EVEN_T) + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -1032,6 +1032,23 @@ riscv_disassemble_insn (bfd_vma memaddr, if ((op->pinfo & INSN_V_EEW64) && !riscv_subset_supports (&pd->riscv_rps_dis, "zve64x")) continue; + + if (pd->xlen == 32 + && riscv_subset_supports (&pd->riscv_rps_dis, "zdinx")) + { + if ((op->pinfo & INSN_RV32_EVEN_D) + && (word & (1u << OP_SH_RD))) + continue; + if ((op->pinfo & INSN_RV32_EVEN_S) + && (word & (1u << OP_SH_RS1))) + continue; + if ((op->pinfo & INSN_RV32_EVEN_T) + && (word & (1u << OP_SH_RS2))) + continue; + if ((op->pinfo & INSN_RV32_EVEN_R) + && (word & (1u << OP_SH_RS3))) + continue; + } } /* It's a match. */ --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -931,10 +931,10 @@ const struct riscv_opcode riscv_opcodes[ {"fcvt.h.w", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 }, {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, -{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 }, -{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, +{"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,Sm", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, -{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 }, +{"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S }, {"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, {"fclass.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, @@ -1021,35 +1021,35 @@ const struct riscv_opcode riscv_opcodes[ {"fsd", 0, INSN_CLASS_ZCD, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,q(s)", MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE }, {"fsd", 0, INSN_CLASS_D, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, -{"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 }, -{"fsgnjn.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 }, -{"fsgnjx.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 }, -{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 }, -{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 }, -{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 }, -{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 }, -{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 }, -{"fmin.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 }, -{"fmax.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 }, -{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 }, -{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 }, -{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 }, -{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 }, -{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 }, -{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 }, -{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 }, -{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 }, -{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 }, -{"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 }, -{"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 }, -{"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 }, -{"fle.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 }, -{"fgt.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_ALIAS }, -{"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS }, +{"fmv.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU }, +{"fneg.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU }, +{"fabs.d", 0, INSN_CLASS_D_INX, "D,U", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU }, +{"fsgnj.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsgnjn.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsgnjx.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fadd.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsub.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fmul.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fdiv.d", 0, INSN_CLASS_D_INX, "D,S,Tm", MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fsqrt.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_RV32_EVEN_DS }, +{"fmin.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fmax.d", 0, INSN_CLASS_D_INX, "D,S,T", MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_RV32_EVEN_DST }, +{"fmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fnmadd.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fnmsub.d", 0, INSN_CLASS_D_INX, "D,S,T,Rm", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_RV32_EVEN_DSTR }, +{"fcvt.w.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_RV32_EVEN_S }, +{"fcvt.wu.d", 0, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_RV32_EVEN_S }, +{"fcvt.d.w", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.d.wu", 0, INSN_CLASS_D_INX, "D,s", MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.d.s", 0, INSN_CLASS_D_INX, "D,S", MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, +{"fcvt.s.d", 0, INSN_CLASS_D_INX, "D,Sm", MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_RV32_EVEN_S }, +{"fclass.d", 0, INSN_CLASS_D_INX, "d,S", MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_RV32_EVEN_S }, +{"feq.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_RV32_EVEN_ST }, +{"flt.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_RV32_EVEN_ST }, +{"fle.d", 0, INSN_CLASS_D_INX, "d,S,T", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_RV32_EVEN_ST }, +{"fgt.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_ALIAS|INSN_RV32_EVEN_ST }, +{"fge.d", 0, INSN_CLASS_D_INX, "d,T,S", MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS|INSN_RV32_EVEN_ST }, {"fmv.x.d", 64, INSN_CLASS_D, "d,S", MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 }, {"fmv.d.x", 64, INSN_CLASS_D, "D,s", MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 }, {"fcvt.l.d", 64, INSN_CLASS_D_INX, "d,Sm", MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 }, From patchwork Fri Jun 19 11:51:10 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 137420 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49245a69f81sm14525175e9.1.2026.06.19.04.51.10 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:51:10 -0700 (PDT) Message-ID: <1aecd2c8-d5f5-4f36-a8ae-36ae4ea83978@suse.com> Date: Fri, 19 Jun 2026 13:51:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 08/13] RISC-V: check operands for Zqinx From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org By analogy to Zdinx on RV32, register pair operands are presumably (there not being any formal spec afaict) required to be encoded with the low bit clear in RV64; in RV32 the low two bits need to be clear. Since match functions don't have XLEN available, introduce respective flags, to be used explicitly in assembler and disassembler. --- Does Zqinx actually make much sense in RV32? Function argument passing, for example, ends up odd: a0..a3 aren't suitable to hold an argument. Hence only a single argument can be passed in registers (a2..a5). No similar checking is easily possible for scalar vector insns, as element width there isn't encoded in the insn. (Plus V and Zqinx can't be enabled together right now anyway.) --- v3: Fix typo in comment. v2: New. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2934,6 +2934,12 @@ riscv_ip (char *str, struct riscv_cl_ins || (rclass) != RCLASS_GPR \ || !((regno) & 1)) +#define RV64_EVEN_CHECK(form, rclass, regno) \ + (!(ip->insn_mo->pinfo & INSN_RV64_EVEN_##form) \ + || xlen > 64 \ + || (rclass) != RCLASS_GPR \ + || !((regno) & (xlen == 32 ? 3 : 1))) + for (oparg = insn->args;; ++oparg) { opargStart = oparg; @@ -3593,12 +3599,14 @@ riscv_ip (char *str, struct riscv_cl_ins switch (c) { case 'D': - if (!RV32_EVEN_CHECK (D, rclass, regno)) + if (!RV32_EVEN_CHECK (D, rclass, regno) + || !RV64_EVEN_CHECK (D, rclass, regno)) break; INSERT_OPERAND (RD, *ip, regno); continue; case 'S': - if (!RV32_EVEN_CHECK (S, rclass, regno)) + if (!RV32_EVEN_CHECK (S, rclass, regno) + || !RV64_EVEN_CHECK (S, rclass, regno)) break; INSERT_OPERAND (RS1, *ip, regno); continue; @@ -3606,12 +3614,14 @@ riscv_ip (char *str, struct riscv_cl_ins INSERT_OPERAND (RS1, *ip, regno); /* Fall through. */ case 'T': - if (!RV32_EVEN_CHECK (T, rclass, regno)) + if (!RV32_EVEN_CHECK (T, rclass, regno) + || !RV64_EVEN_CHECK (T, rclass, regno)) break; INSERT_OPERAND (RS2, *ip, regno); continue; case 'R': - if (!RV32_EVEN_CHECK (R, rclass, regno)) + if (!RV32_EVEN_CHECK (R, rclass, regno) + || !RV64_EVEN_CHECK (R, rclass, regno)) break; INSERT_OPERAND (RS3, *ip, regno); continue; @@ -4312,6 +4322,7 @@ riscv_ip (char *str, struct riscv_cl_ins } #undef RV32_EVEN_CHECK +#undef RV64_EVEN_CHECK out: /* Restore the character we might have clobbered above. */ --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32.d @@ -0,0 +1,52 @@ +#as: -march=rv32i_zqinx +#objdump: -dwr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+078a7453[ ]+fadd\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+078a0453[ ]+fadd\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+0f8a7453[ ]+fsub\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+0f8a0453[ ]+fsub\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+178a7453[ ]+fmul\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+178a0453[ ]+fmul\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+1f8a7453[ ]+fdiv\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+1f8a0453[ ]+fdiv\.q[ ]+s0,s4,s8,rne +[ ]+[0-9a-f]+:[ ]+5e0a7453[ ]+fsqrt\.q[ ]+s0,s4 +[ ]+[0-9a-f]+:[ ]+5e0a0453[ ]+fsqrt\.q[ ]+s0,s4,rne +[ ]+[0-9a-f]+:[ ]+2f8a0453[ ]+fmin\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+2f8a1453[ ]+fmax\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+678a7443[ ]+fmadd\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a0443[ ]+fmadd\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+678a744f[ ]+fnmadd\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a044f[ ]+fnmadd\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+678a7447[ ]+fmsub\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a0447[ ]+fmsub\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+678a744b[ ]+fnmsub\.q[ ]+s0,s4,s8,a2 +[ ]+[0-9a-f]+:[ ]+678a044b[ ]+fnmsub\.q[ ]+s0,s4,s8,a2,rne +[ ]+[0-9a-f]+:[ ]+c60a75d3[ ]+fcvt\.w\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+c60a05d3[ ]+fcvt\.w\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+c61a75d3[ ]+fcvt\.wu\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+c61a05d3[ ]+fcvt\.wu\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+d6058453[ ]+fcvt\.q\.w[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+d6158453[ ]+fcvt\.q\.wu[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+46058453[ ]+fcvt\.q\.s[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+403a75d3[ ]+fcvt\.s\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+403a05d3[ ]+fcvt\.s\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+46150453[ ]+fcvt\.q\.d[ ]+s0,a0 +[ ]+[0-9a-f]+:[ ]+423a7553[ ]+fcvt\.d\.q[ ]+a0,s4 +[ ]+[0-9a-f]+:[ ]+423a0553[ ]+fcvt\.d\.q[ ]+a0,s4,rne +[ ]+[0-9a-f]+:[ ]+46258453[ ]+fcvt\.q\.h[ ]+s0,a1 +[ ]+[0-9a-f]+:[ ]+443a75d3[ ]+fcvt\.h\.q[ ]+a1,s4 +[ ]+[0-9a-f]+:[ ]+443a05d3[ ]+fcvt\.h\.q[ ]+a1,s4,rne +[ ]+[0-9a-f]+:[ ]+278a0453[ ]+fsgnj\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+278a1453[ ]+fsgnjn\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+278a2453[ ]+fsgnjx\.q[ ]+s0,s4,s8 +[ ]+[0-9a-f]+:[ ]+a78a25d3[ ]+feq\.q[ ]+a1,s4,s8 +[ ]+[0-9a-f]+:[ ]+a78a15d3[ ]+flt\.q[ ]+a1,s4,s8 +[ ]+[0-9a-f]+:[ ]+a78a05d3[ ]+fle\.q[ ]+a1,s4,s8 +[ ]+[0-9a-f]+:[ ]+a74c15d3[ ]+flt\.q[ ]+a1,s8,s4 +[ ]+[0-9a-f]+:[ ]+a74c05d3[ ]+fle\.q[ ]+a1,s8,s4 +[ ]+[0-9a-f]+:[ ]+274a0453[ ]+fmv\.q[ ]+s0,s4 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32.s @@ -0,0 +1,54 @@ +target: + fadd.q s0, s4, s8 + fadd.q s0, s4, s8, rne + fsub.q s0, s4, s8 + fsub.q s0, s4, s8, rne + fmul.q s0, s4, s8 + fmul.q s0, s4, s8, rne + fdiv.q s0, s4, s8 + fdiv.q s0, s4, s8, rne + fsqrt.q s0, s4 + fsqrt.q s0, s4, rne + fmin.q s0, s4, s8 + fmax.q s0, s4, s8 + fmadd.q s0, s4, s8, a2 + fmadd.q s0, s4, s8, a2, rne + fnmadd.q s0, s4, s8, a2 + fnmadd.q s0, s4, s8, a2, rne + fmsub.q s0, s4, s8, a2 + fmsub.q s0, s4, s8, a2, rne + fnmsub.q s0, s4, s8, a2 + fnmsub.q s0, s4, s8, a2, rne + + fcvt.w.q a1, s4 + fcvt.w.q a1, s4, rne + fcvt.wu.q a1, s4 + fcvt.wu.q a1, s4, rne + fcvt.q.w s0, a1 + fcvt.q.wu s0, a1 + + fcvt.q.s s0, a1 + fcvt.s.q a1, s4 + fcvt.s.q a1, s4, rne + + fcvt.q.d s0, a0 + fcvt.d.q a0, s4 + fcvt.d.q a0, s4, rne + + .option push + .option arch, +zhinxmin + fcvt.q.h s0, a1 + fcvt.h.q a1, s4 + fcvt.h.q a1, s4, rne + .option pop + + fsgnj.q s0, s4, s8 + fsgnjn.q s0, s4, s8 + fsgnjx.q s0, s4, s8 + feq.q a1, s4, s8 + flt.q a1, s4, s8 + fle.q a1, s4, s8 + fgt.q a1, s4, s8 + fge.q a1, s4, s8 + + fmv.q s0, s4 --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv32i_zqinx +#source: zqinx.s +#error_output: zqinx-rv32-fail.l --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.l @@ -0,0 +1,42 @@ +.*: Assembler messages: +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: unrecognized opcode `fcvt\.l\.q .*' +.*: Error: unrecognized opcode `fcvt\.l\.q .*' +.*: Error: unrecognized opcode `fcvt\.lu\.q .*' +.*: Error: unrecognized opcode `fcvt\.lu\.q .*' +.*: Error: illegal operands `fcvt\.q\.w .*' +.*: Error: illegal operands `fcvt\.q\.wu .*' +.*: Error: unrecognized opcode `fcvt\.q\.l .*' +.*: Error: unrecognized opcode `fcvt\.q\.lu .*' +.*: Error: illegal operands `fcvt\.q\.s .*' +.*: Error: illegal operands `fcvt\.q\.d .*' +.*: Error: illegal operands `fsgnj\.q .*' +.*: Error: illegal operands `fsgnjn\.q .*' +.*: Error: illegal operands `fsgnjx\.q .*' +.*: Error: illegal operands `feq\.q .*' +.*: Error: illegal operands `flt\.q .*' +.*: Error: illegal operands `fle\.q .*' +.*: Error: illegal operands `fgt\.q .*' +.*: Error: illegal operands `fge\.q .*' +.*: Error: illegal operands `fmv\.q .*' +.*: Error: illegal operands `fneg\.q .*' +.*: Error: illegal operands `fabs\.q .*' --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.d @@ -0,0 +1,2 @@ +#as: -march=rv64i_zqinx +#error_output: zqinx-rv64-fail.l --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.l @@ -0,0 +1,62 @@ +.*: Assembler messages: +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fadd\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fsub\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fmul\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fdiv\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fsqrt\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmin\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmax\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fnmadd\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fnmsub\.q .*' +.*: Error: illegal operands `fcvt\.w\.q .*' +.*: Error: illegal operands `fcvt\.wu\.q .*' +.*: Error: illegal operands `fcvt\.q\.w .*' +.*: Error: illegal operands `fcvt\.q\.wu .*' +.*: Error: illegal operands `fcvt\.q\.s .*' +.*: Error: illegal operands `fcvt\.s\.q .*' +.*: Error: illegal operands `fcvt\.q\.d .*' +.*: Error: illegal operands `fcvt\.d\.q .*' +.*: Error: illegal operands `fcvt\.q\.h .*' +.*: Error: illegal operands `fcvt\.h\.q .*' +.*: Error: illegal operands `fsgnj\.q .*' +.*: Error: illegal operands `fsgnjn\.q .*' +.*: Error: illegal operands `fsgnjx\.q .*' +.*: Error: illegal operands `feq\.q .*' +.*: Error: illegal operands `flt\.q .*' +.*: Error: illegal operands `fle\.q .*' +.*: Error: illegal operands `fgt\.q .*' +.*: Error: illegal operands `fge\.q .*' +.*: Error: illegal operands `fmv\.q .*' +.*: Error: illegal operands `fmv\.q .*' +.*: Error: illegal operands `fneg\.q .*' +.*: Error: illegal operands `fneg\.q .*' +.*: Error: illegal operands `fabs\.q .*' +.*: Error: illegal operands `fabs\.q .*' +.*: Error: illegal operands `fclass\.q .*' --- /dev/null +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.s @@ -0,0 +1,70 @@ +target: + fadd.q s1, s4, s8 + fadd.q s0, s5, s8 + fadd.q s0, s4, s9 + fsub.q s1, s4, s8 + fsub.q s0, s5, s8 + fsub.q s0, s4, s9 + fmul.q s1, s4, s8 + fmul.q s0, s5, s8 + fmul.q s0, s4, s9 + fdiv.q s1, s4, s8 + fdiv.q s0, s5, s8 + fdiv.q s0, s4, s9 + fsqrt.q s1, s4 + fsqrt.q s0, s5 + fmin.q s1, s4, s8 + fmin.q s0, s5, s8 + fmin.q s0, s4, s9 + fmax.q s1, s4, s8 + fmax.q s0, s5, s8 + fmax.q s0, s4, s9 + fmadd.q s1, s4, s8, a2 + fmadd.q s0, s5, s8, a2 + fmadd.q s0, s4, s9, a2 + fmadd.q s0, s4, s8, a3 + fnmadd.q s1, s4, s8, a2 + fnmadd.q s0, s5, s8, a2 + fnmadd.q s0, s4, s9, a2 + fnmadd.q s0, s4, s8, a3 + fmsub.q s1, s4, s8, a2 + fmsub.q s0, s5, s8, a2 + fmsub.q s0, s4, s9, a2 + fmsub.q s0, s4, s8, a3 + fnmsub.q s1, s4, s8, a2 + fnmsub.q s0, s5, s8, a2 + fnmsub.q s0, s4, s9, a2 + fnmsub.q s0, s4, s8, a3 + + fcvt.w.q a0, s5 + fcvt.wu.q a0, s5 + fcvt.q.w s1, a0 + fcvt.q.wu s1, a0 + + fcvt.q.s s1, a0 + fcvt.s.q a0, s5 + + fcvt.q.d s1, a0 + fcvt.d.q a0, s5 + + .option push + .option arch, +zhinxmin + fcvt.q.h s1, a0 + fcvt.h.q a0, s5 + .option pop + + fsgnj.q s1, s4, s8 + fsgnjn.q s0, s5, s8 + fsgnjx.q s0, s4, s9 + feq.q a0, s5, s8 + flt.q a0, s4, s9 + fle.q a0, s5, s8 + fgt.q a0, s4, s9 + fge.q a0, s5, s8 + fmv.q s1, s4 + fmv.q s0, s5 + fneg.q s1, s4 + fneg.q s0, s5 + fabs.q s1, s4 + fabs.q s0, s5 + fclass.q a0, s5 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -691,6 +691,19 @@ struct riscv_opcode #define INSN_RV32_EVEN_DU (INSN_RV32_EVEN_D | INSN_RV32_EVEN_T) #define INSN_RV32_EVEN_ST (INSN_RV32_EVEN_S | INSN_RV32_EVEN_T) +/* Operands required to be an even-numbered register (pair) in RV64, and one + divisible by 4 on RV32. */ +#define INSN_RV64_EVEN_D 0x00001000 +#define INSN_RV64_EVEN_S 0x00002000 +#define INSN_RV64_EVEN_T 0x00004000 /* Also covering U. */ +#define INSN_RV64_EVEN_R 0x00008000 +/* Shorthands for combinations of the above. */ +#define INSN_RV64_EVEN_DS (INSN_RV64_EVEN_D | INSN_RV64_EVEN_S) +#define INSN_RV64_EVEN_DST (INSN_RV64_EVEN_DS | INSN_RV64_EVEN_T) +#define INSN_RV64_EVEN_DSTR (INSN_RV64_EVEN_DST | INSN_RV64_EVEN_R) +#define INSN_RV64_EVEN_DU (INSN_RV64_EVEN_D | INSN_RV64_EVEN_T) +#define INSN_RV64_EVEN_ST (INSN_RV64_EVEN_S | INSN_RV64_EVEN_T) + /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ #define INSN_MACRO 0xffffffff --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -1049,6 +1049,25 @@ riscv_disassemble_insn (bfd_vma memaddr, && (word & (1u << OP_SH_RS3))) continue; } + + if (pd->xlen <= 64 + && riscv_subset_supports (&pd->riscv_rps_dis, "zqinx")) + { + unsigned int mask = pd->xlen == 32 ? 3 : 1; + + if ((op->pinfo & INSN_RV64_EVEN_D) + && (word & (mask << OP_SH_RD))) + continue; + if ((op->pinfo & INSN_RV64_EVEN_S) + && (word & (mask << OP_SH_RS1))) + continue; + if ((op->pinfo & INSN_RV64_EVEN_T) + && (word & (mask << OP_SH_RS2))) + continue; + if ((op->pinfo & INSN_RV64_EVEN_R) + && (word & (mask << OP_SH_RS3))) + continue; + } } /* It's a match. */ --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -932,10 +932,10 @@ const struct riscv_opcode riscv_opcodes[ {"fcvt.h.wu", 0, INSN_CLASS_ZFH_INX, "D,sm", MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 }, {"fcvt.s.h", 0, INSN_CLASS_ZFHMIN_INX, "D,S", MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 }, {"fcvt.d.h", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D }, -{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 }, +{"fcvt.q.h", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, {"fcvt.h.s", 0, INSN_CLASS_ZFHMIN_INX, "D,Sm", MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 }, {"fcvt.h.d", 0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S }, -{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 }, +{"fcvt.h.q", 0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, INSN_RV64_EVEN_S }, {"fclass.h", 0, INSN_CLASS_ZFH_INX, "d,S", MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 }, {"feq.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 }, {"flt.h", 0, INSN_CLASS_ZFH_INX, "d,S,T", MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 }, @@ -1062,41 +1062,41 @@ const struct riscv_opcode riscv_opcodes[ {"flq", 0, INSN_CLASS_Q, "D,A,s", 0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO }, {"fsq", 0, INSN_CLASS_Q, "T,q(s)", MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE }, {"fsq", 0, INSN_CLASS_Q, "T,A,s", 0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO }, -{"fmv.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fneg.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fabs.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS }, -{"fsgnj.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 }, -{"fsgnjn.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 }, -{"fsgnjx.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 }, -{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 }, -{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 }, -{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 }, -{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 }, -{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 }, -{"fmin.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 }, -{"fmax.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 }, -{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 }, -{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 }, -{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 }, -{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 }, -{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 }, -{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 }, -{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 }, -{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 }, -{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 }, -{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 }, -{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 }, -{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 }, -{"fclass.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 }, -{"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 }, -{"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 }, -{"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 }, -{"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS }, -{"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS }, -{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 }, -{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 }, -{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 }, -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 }, +{"fmv.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU }, +{"fneg.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU }, +{"fabs.q", 0, INSN_CLASS_Q_INX, "D,U", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU }, +{"fsgnj.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsgnjn.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsgnjx.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fadd.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsub.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fmul.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fdiv.q", 0, INSN_CLASS_Q_INX, "D,S,Tm", MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fsqrt.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_RV64_EVEN_DS }, +{"fmin.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fmax.q", 0, INSN_CLASS_Q_INX, "D,S,T", MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_RV64_EVEN_DST }, +{"fmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fnmadd.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fnmsub.q", 0, INSN_CLASS_Q_INX, "D,S,T,Rm", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR }, +{"fcvt.w.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.wu.q", 0, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.q.w", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.wu", 0, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.s", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.d", 0, INSN_CLASS_Q_INX, "D,S", MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_RV64_EVEN_D|INSN_RV32_EVEN_S }, +{"fcvt.s.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.d.q", 0, INSN_CLASS_Q_INX, "D,Sm", MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_RV32_EVEN_D|INSN_RV64_EVEN_S }, +{"fclass.q", 0, INSN_CLASS_Q_INX, "d,S", MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_RV64_EVEN_S }, +{"feq.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_RV64_EVEN_ST }, +{"flt.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_RV64_EVEN_ST }, +{"fle.q", 0, INSN_CLASS_Q_INX, "d,S,T", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_RV64_EVEN_ST }, +{"fgt.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST }, +{"fge.q", 0, INSN_CLASS_Q_INX, "d,T,S", MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST }, +{"fcvt.l.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.lu.q", 64, INSN_CLASS_Q_INX, "d,Sm", MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_RV64_EVEN_S }, +{"fcvt.q.l", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, +{"fcvt.q.lu", 64, INSN_CLASS_Q_INX, "D,s", MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_RV64_EVEN_D }, /* Compressed instructions. */ {"c.unimp", 0, INSN_CLASS_ZCA, "", 0, 0xffffU, match_opcode, 0 }, From patchwork Fri Jun 19 11:51:36 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-46508a053cesm7232571f8f.4.2026.06.19.04.51.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:51:37 -0700 (PDT) Message-ID: Date: Fri, 19 Jun 2026 13:51:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 09/13] RISC-V/gas: .attribute vs .insn From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org "... before any instruction", as the diagnostic from s_riscv_attribute() says, presumably ought to include also insns resulting from .insn. Make a small helper function. Reviewed-by: Jiawei --- RFC: I can't quite figure why this constraint exists, so there may also be the option of relaxing things (up to fully dropping start_assemble). --- v2: Style correction. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -4415,6 +4415,18 @@ riscv_ip_hardcode (char *str, return NULL; } +/* The architecture and privileged elf attributes should be set before + assembling. */ +static bool +start_assembly (void) +{ + start_assemble = true; + + riscv_set_abi_by_arch (); + + return riscv_set_default_priv_spec (NULL); +} + void md_assemble (char *str) { @@ -4422,16 +4434,8 @@ md_assemble (char *str) expressionS imm_expr; bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; - /* The architecture and privileged elf attributes should be set - before assembling. */ - if (!start_assemble) - { - start_assemble = true; - - riscv_set_abi_by_arch (); - if (!riscv_set_default_priv_spec (NULL)) - return; - } + if (!start_assemble && !start_assembly()) + return; riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); @@ -5640,6 +5644,9 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED) bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; char save_c; + if (!start_assemble && !start_assembly()) + return; + while (!is_end_of_stmt (*input_line_pointer)) ++input_line_pointer; From patchwork Fri Jun 19 11:51:59 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 137424 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1EE934BA2E1E for ; Fri, 19 Jun 2026 11:55:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1EE934BA2E1E Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=suse.com header.i=@suse.com header.a=rsa-sha256 header.s=google header.b=P8wuMa7v X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by sourceware.org (Postfix) with ESMTPS id BAF9B4BAE7C6 for ; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4923fce9590sm64582155e9.4.2026.06.19.04.52.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:52:00 -0700 (PDT) Message-ID: Date: Fri, 19 Jun 2026 13:51:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 10/13] RISC-V/gas: warn about non-boolean unaligned-access attribute From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org The attribute being a boolean one, values should be solely 0 or 1. Reviewed-by: Jiawei --- Shouldn't settings accumulate, much like what riscv_merge_attributes() does? --- v2: New. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -5870,14 +5870,13 @@ s_riscv_attribute (int ignored ATTRIBUTE { obj_attr_tag_t tag = obj_attr_process_attribute (OBJ_ATTR_PROC); unsigned old_xlen; - obj_attribute *attr; + const obj_attribute *attr = elf_known_obj_attributes_proc (stdoutput); explicit_attr = true; switch (tag) { case Tag_RISCV_arch: old_xlen = xlen; - attr = elf_known_obj_attributes_proc (stdoutput); if (!start_assemble) riscv_set_arch (attr[Tag_RISCV_arch].s); else @@ -5903,6 +5902,11 @@ s_riscv_attribute (int ignored ATTRIBUTE "any instructions")); break; + case Tag_RISCV_unaligned_access: + if (attr[Tag_RISCV_unaligned_access].i > 1) + as_warn (_("`unaligned_access' attribute with non-boolean value")); + break; + default: break; } --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-warn.d @@ -0,0 +1,7 @@ +#as: -march-attr +#readelf: -A +#warning_output: attribute-warn.l + +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].* --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-warn.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*:2: Warning: `unaligned_access' attribute with non-boolean value --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-warn.s @@ -0,0 +1,3 @@ + .attribute unaligned_access, 1 + .attribute unaligned_access, 0x1234 + .attribute unaligned_access, 0 From patchwork Fri Jun 19 11:52:18 2026 Content-Type: text/plain; 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Reviewed-by: Jiawei --- Should we reject changing an already set non-zero value, like riscv_merge_attributes() does? Should we permit 0 as an explicit indication of "attribute not set"? --- v2: New. --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -5902,6 +5902,13 @@ s_riscv_attribute (int ignored ATTRIBUTE "any instructions")); break; + case Tag_RISCV_stack_align: + if (!attr[Tag_RISCV_stack_align].i + || (attr[Tag_RISCV_stack_align].i & + (attr[Tag_RISCV_stack_align].i - 1))) + as_warn (_("`stack_align' attribute with non-power-of-2 value")); + break; + case Tag_RISCV_unaligned_access: if (attr[Tag_RISCV_unaligned_access].i > 1) as_warn (_("`unaligned_access' attribute with non-boolean value")); --- a/gas/testsuite/gas/riscv/attribute-warn.d +++ b/gas/testsuite/gas/riscv/attribute-warn.d @@ -4,4 +4,5 @@ Attribute Section: riscv File Attributes + Tag_RISCV_stack_align: 65536-bytes Tag_RISCV_arch: [a-zA-Z0-9_\"].* --- a/gas/testsuite/gas/riscv/attribute-warn.l +++ b/gas/testsuite/gas/riscv/attribute-warn.l @@ -1,2 +1,4 @@ .*: Assembler messages: .*:2: Warning: `unaligned_access' attribute with non-boolean value +.*:5: Warning: `stack_align' attribute with non-power-of-2 value +.*:6: Warning: `stack_align' attribute with non-power-of-2 value --- a/gas/testsuite/gas/riscv/attribute-warn.s +++ b/gas/testsuite/gas/riscv/attribute-warn.s @@ -1,3 +1,7 @@ .attribute unaligned_access, 1 .attribute unaligned_access, 0x1234 .attribute unaligned_access, 0 + + .attribute stack_align, 0 + .attribute stack_align, 0x4444 + .attribute stack_align, 0x10000 From patchwork Fri Jun 19 11:52:40 2026 Content-Type: text/plain; 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Convert other non-zero values to 1. Reviewed-by: Jiawei jiawei@iscas.ac.cn --- v3: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -3777,6 +3777,23 @@ riscv_merge_attributes (bfd *ibfd, struc initialized. */ out_attr[0].i = 1; + for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++) + { + switch (i) + { + case Tag_RISCV_unaligned_access: + if (out_attr[i].i <= 1) + break; + + _bfd_error_handler + (_("warning: %pB uses non-boolean `unaligned access' attribute; " + "converting to boolean"), + ibfd); + out_attr[i].i = 1; + break; + } + } + return true; } @@ -3865,7 +3882,12 @@ riscv_merge_attributes (bfd *ibfd, struc break; case Tag_RISCV_unaligned_access: - out_attr[i].i |= in_attr[i].i; + if (in_attr[i].i > 1) + _bfd_error_handler + (_("warning: %pB uses non-boolean `unaligned access' attribute; " + "converting to boolean"), + ibfd); + out_attr[i].i |= !!in_attr[i].i; break; case Tag_RISCV_stack_align: From patchwork Fri Jun 19 11:53:18 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 137428 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5A3344BAE7E0 for ; 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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4650c114e22sm6673151f8f.34.2026.06.19.04.53.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 19 Jun 2026 04:53:18 -0700 (PDT) Message-ID: <2fcf62ca-0e51-48fc-a9cf-7a48a40dc82e@suse.com> Date: Fri, 19 Jun 2026 13:53:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH v3 13/13] RISC-V/bfd: warn about non-power-of-2 stack-align attribute From: Jan Beulich To: Binutils Cc: Palmer Dabbelt , Andrew Waterman , Jim Wilson , Nelson Chu , jiawei References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> Content-Language: en-US Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com> X-Spam-Status: No, score=-3016.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Only power-of-2 values are sensible for alignment. Reject other values. While there also drop a redundant part of a related conditional. Reviewed-by: Jiawei jiawei@iscas.ac.cn --- v3: New. --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -3791,6 +3791,17 @@ riscv_merge_attributes (bfd *ibfd, struc ibfd); out_attr[i].i = 1; break; + + case Tag_RISCV_stack_align: + if (!(out_attr[i].i & (out_attr[i].i - 1))) + break; + + _bfd_error_handler + (_("warning: %pB uses non-power-of-2 `stack align' attribute; " + "ignoring"), + ibfd); + out_attr[i].i = 0; + break; } } @@ -3891,10 +3902,14 @@ riscv_merge_attributes (bfd *ibfd, struc break; case Tag_RISCV_stack_align: - if (out_attr[i].i == 0) + if ((in_attr[i].i & (in_attr[i].i - 1)) != 0) + _bfd_error_handler + (_("warning: %pB uses non-power-of-2 `stack align' attribute; " + "ignoring"), + ibfd); + else if (out_attr[i].i == 0) out_attr[i].i = in_attr[i].i; else if (in_attr[i].i != 0 - && out_attr[i].i != 0 && out_attr[i].i != in_attr[i].i) { _bfd_error_handler