From patchwork Mon Jun 1 06:24:46 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 136146 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C5DC04BA2E0E for ; Mon, 1 Jun 2026 06:25:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C5DC04BA2E0E Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=n6GlTKGr X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) by sourceware.org (Postfix) with ESMTPS id 9A48B4BA2E15 for ; Mon, 1 Jun 2026 06:24:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9A48B4BA2E15 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9A48B4BA2E15 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1780295089; cv=none; b=JTYbiMzmdrYff7+Xp+njeE0tU31bYrfnrG8nANcJhdM/uB6hrM8sZj/AdY/USkKP8oiOa60CqhHyxWeN//kFInMXVRJWWEZ8JS3cyj16RkpIv05XnpX0IBMyAeIXyKdwXEPgvANOKQ3CjoGgKDxPQW47HI93ly3AcQBR8JMNi9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1780295089; c=relaxed/simple; bh=2yc7DNv1O3j5fmJuCUJSTxBEtr9eccBY1bGRODhYMSE=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=qSWF+f7DIxXP4AaMET2OZlO3aAWJM0BuOOmDzY+8OK8GYIPSkYyaqUQyg/FpzZS6ichpEgQXuZUR9Y3p3XRDK+5EryLDnTK0EccrCTmP6tLrVEw/LVeonmcIeO6MvTx6gE2x9C7SNZ5eGct1nI6dXgrXowTQLiOcwowxYgH5hTM= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=n6GlTKGr DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9A48B4BA2E15 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780295088; x=1811831088; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=2yc7DNv1O3j5fmJuCUJSTxBEtr9eccBY1bGRODhYMSE=; b=n6GlTKGrhtwWDKXXwms5PwEqMoLhac0PC6d8YAKy36g/omqdeLAiKuXL FkLCH9O9IwCbku9dLsVfchnsWlrzO6RNzVVPgXEiJUpXbrxHjM/CekX1t LMyyJMLcyVEPRUQ08BgsaxvAf84aXjAZqT7B5pyYi46/1WZFi8H+uQqeF DftjtlcCFp5m/UKPW838dqQp60XXwlj4dtqXpHVAdfJvZf22a6VOi7HSm XHTr8LCG4hqQMeZS8ktBi3cpvtIPzhJ4HyWfgSj2NDHLeKi2osm5A448m HFAfa9cI0B6a55sp0uei04crXP8u8wJGVumKK4fNWNsfo2MkmU3fjhpOq Q==; X-CSE-ConnectionGUID: 63qfCmeQSu6FAcIXs8DIqA== X-CSE-MsgGUID: Doq/1jlKR/quHMgqqf/U/A== X-IronPort-AV: E=McAfee;i="6800,10657,11803"; a="80184702" X-IronPort-AV: E=Sophos;i="6.24,180,1774335600"; d="scan'208";a="80184702" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2026 23:24:47 -0700 X-CSE-ConnectionGUID: mDjgUIjTStuI9QuHUAJlcg== X-CSE-MsgGUID: iPtt+3ZOSwirvo96RnSK/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,180,1774335600"; d="scan'208";a="248569935" Received: from shliclel4217.sh.intel.com ([10.239.240.127]) by fmviesa005.fm.intel.com with ESMTP; 31 May 2026 23:24:47 -0700 From: Haochen Jiang To: binutils@sourceware.org Cc: hjl.tools@gmail.com, jbeulich@suse.com Subject: [PATCH] x86: Support BHI_CTRL instruction Date: Mon, 1 Jun 2026 14:24:46 +0800 Message-Id: <20260601062446.2367458-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Hi all, The following patch aimed to add BHI_CTRL. The ISA has been published in a separate tech paper last year and still missing its assembler/disassembler support. One tricky thing is that it utilized part of the nops encoding and we need to keep the same behavior for the not touched one, i.e., repz nop. That is why I added a Fixup for now since I did not have a better idea for that. Discussions are welcomed on this. Ok for trunk? Thx, Haochen --- BHI_CTRL is an ISA with only one instruction ibhf. The following tech paper is published in May, 2025: https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html#ibhf As shown in the paper, The encoding is F3 48 0F 1E F8. I added a Fixup for disassembler since we need to keep the same behavior for "repz nop" encodings. gas/ChangeLog: * NEWS: Mention BHI_CTRL. * config/tc-i386.c: Add .bhi_ctrl. * testsuite/gas/i386/x86-64.exp: Add BHI_CTRL tests. * testsuite/gas/i386/x86-64-bhi-ctrl-intel.d: New test. * testsuite/gas/i386/x86-64-bhi-ctrl.d: Ditto. * testsuite/gas/i386/x86-64-bhi-ctrl.s: Ditto. opcodes/ChangeLog: * i386-dis.c: (RM_0F1E_P_1_MOD_3_REG_7): Adjust for ibhf. (IBHF_Fixup): New. Revert mnemonic back to repz nop for ~REX_W. * i386-gen.c: (isa_dependencies): Add BHI_CTRL. (cpu_flags): Ditto. * i386-opc.h (enum i386_cpu): Ditto. (i386_cpu_flags): Ditto. * i386-opc.tbl: Add BHI_CTRL instruction. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-tbl.h: Ditto. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + .../gas/i386/x86-64-bhi-ctrl-intel.d | 12 + gas/testsuite/gas/i386/x86-64-bhi-ctrl.d | 10 + gas/testsuite/gas/i386/x86-64-bhi-ctrl.s | 9 + gas/testsuite/gas/i386/x86-64.exp | 2 + opcodes/i386-dis.c | 21 +- opcodes/i386-gen.c | 3 + opcodes/i386-init.h | 995 ++++--- opcodes/i386-mnem.h | 2639 +++++++++-------- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 6 + opcodes/i386-tbl.h | 1241 ++++---- 13 files changed, 2516 insertions(+), 2428 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-bhi-ctrl.d create mode 100644 gas/testsuite/gas/i386/x86-64-bhi-ctrl.s diff --git a/gas/NEWS b/gas/NEWS index e384d1135c0..0687fd4adfc 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the x86 BHI_CTRL instruction. + Changes in 2.46: * Add support for AMD Zen6 processor. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 365c2ee95f5..b67606d13ad 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1260,6 +1260,7 @@ static const arch_entry cpu_arch[] = SUBARCH (padlockphe2, PADLOCKPHE2, PADLOCKPHE2, false), SUBARCH (padlockxmodx, PADLOCKXMODX, PADLOCKXMODX, false), SUBARCH (movrs, MOVRS, MOVRS, false), + SUBARCH (bhi_ctrl, BHI_CTRL, BHI_CTRL, false), }; #undef SUBARCH diff --git a/gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d b/gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d new file mode 100644 index 00000000000..adc9f87a62a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d @@ -0,0 +1,12 @@ +#objdump: -dw +#name: x86_64 BHI_CTRL insns (Intel disassembly) +#source: x86-64-bhi-ctrl.s + +.*: +file format .* + +Disassembly of section \.text: + +#... +[a-f0-9]+ <_intel>: +\s*[a-f0-9]+:\s*f3 48 0f 1e f8\s+ibhf +#pass diff --git a/gas/testsuite/gas/i386/x86-64-bhi-ctrl.d b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.d new file mode 100644 index 00000000000..164ae5e8839 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.d @@ -0,0 +1,10 @@ +#objdump: -dw +#name: x86_64 BHI_CTRL insns + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f3 48 0f 1e f8\s+ibhf +#pass diff --git a/gas/testsuite/gas/i386/x86-64-bhi-ctrl.s b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.s new file mode 100644 index 00000000000..41beb4210d6 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.s @@ -0,0 +1,9 @@ +# Check 64bit BHI_CTRL instructions + + .text +_start: + ibhf + +_intel: + .intel_syntax noprefix + ibhf diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 8ddf05481a5..cb2334fbe75 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -550,6 +550,8 @@ run_dump_test "x86-64-movrs-avx10_2-512" run_dump_test "x86-64-movrs-avx10_2-512-intel" run_dump_test "x86-64-movrs-avx10_2-256" run_dump_test "x86-64-movrs-avx10_2-256-intel" +run_dump_test "x86-64-bhi-ctrl" +run_dump_test "x86-64-bhi-ctrl-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index db1e4f7a7d5..ecf74840eee 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -109,6 +109,7 @@ static bool PREFETCHI_Fixup (instr_info *, int, int); static bool PUSH2_POP2_Fixup (instr_info *, int, int); static bool JMPABS_Fixup (instr_info *, int, int); static bool CFCMOV_Fixup (instr_info *, int, int); +static bool IBHF_Fixup (instr_info *, int, int); static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, enum disassembler_style, @@ -8750,7 +8751,7 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_0F1E_P_1_MOD_3_REG_7 */ - { "nopQ", { Ev }, PREFIX_IGNORED }, + { "ibhf", { IBHF_Fixup }, 0 }, { "nopQ", { Ev }, PREFIX_IGNORED }, { "endbr64", { Skip_MODRM }, 0 }, { "endbr32", { Skip_MODRM }, 0 }, @@ -14671,3 +14672,21 @@ CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag) return OP_G (ins, v_mode, sizeflag); return OP_E (ins, v_mode, sizeflag); } + +static bool +IBHF_Fixup (instr_info *ins, int bytemode, int sizeflag) +{ + if (!(ins->rex & REX_W)) + { + ins->mnemonicendp = stpcpy (ins->obuf, "repz nop"); + return OP_E (ins, v_mode, sizeflag); + } + else + { + USED_REX (REX_W); + MODRM_CHECK; + ins->codep++; + ins->has_skipped_modrm = true; + return true; + } +} diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index be580d48a18..7033517e777 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -319,6 +319,8 @@ static const dependency isa_dependencies[] = "PadLock" }, { "PadLockXMODX", "PadLock" }, + { "BHI_CTRL", + "64" }, }; /* This array is populated as process_i386_initializers() walks cpu_flags[]. */ @@ -451,6 +453,7 @@ static bitfield cpu_flags[] = BITFIELD (APX_F), BITFIELD (AVX10_2), BITFIELD (MOVRS), + BITFIELD (BHI_CTRL), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 54038f90761..97eaf085dbd 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -241,6 +241,8 @@ enum i386_cpu CpuMSR_IMM, /* Intel MOVRS Instructions support required. */ CpuMOVRS, + /* Intel BHI_CTRL instruction support required. */ + CpuBHI_CTRL, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -523,6 +525,7 @@ typedef union i386_cpu_flags unsigned int cpuuser_msr:1; unsigned int cpumsr_imm:1; unsigned int cpumovrs:1; + unsigned int cpubhi_ctrl:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 5797a634de3..827d4b54906 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3630,3 +3630,9 @@ vmovrs, 0xf26f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5||Disp8ShiftVL vmovrs, 0xf36f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5||Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } // MOVRS instructions end. + +// BHI_CTRL insructions. + +ibhf, 0xf30f1ef8, BHI_CTRL, NoSuf|Size64, {} + +// BHI_CTRL insructions end.