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Date: Thu, 28 May 2026 18:06:02 +0800 Message-ID: <20260528100602.475331-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-CM-TRANSID: rQCowAA3G+KiExhq8n+yEg--.4021S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtF4rtrW7Cw17try5GF17Jrb_yoW3Gr15pF 4kC3WqyrZ3Jan7KrnakF4j9F47Za92grWa9rWFkw13Aa1xXrWDtFyktw15AF4kXF4j93ZF 9a15Gry5Z34UAFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkG14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc7CjxVAaw2AFwI0_ JF0_Jw1l42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67 AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIY rxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14 v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8 JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUBVbkUUU UU= X-Originating-IP: [157.0.80.98] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBg0BAGoXzaP1gwABsu X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_BLOCKED, SPF_HELO_PASS, SPF_PASS, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org This patch adds support for the Zvabd extension instructions: https://github.com/riscv/integer-vector-absolute-difference The Zvabd extension provides RISC-V vector integer absolute difference operations. The widening accumulate mnemonics follow the current frozen specification are vwabda.vv and vwabdau.vv. bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add Zvabd implication of zve32x. (riscv_multi_subset_supports_ext): Add Zvabd. gas/ChangeLog: * NEWS: * testsuite/gas/riscv/march-help.l: Add Zvabd. * testsuite/gas/riscv/zvabd.d: New test. * testsuite/gas/riscv/zvabd.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VABS_V): New macro. (MASK_VABS_V): Ditto. (MATCH_VABD_VV): Ditto. (MASK_VABD_VV): Ditto. (MATCH_VABDU_VV): Ditto. (MASK_VABDU_VV): Ditto. (MATCH_VWABDA_VV): Ditto. (MASK_VWABDA_VV): Ditto. (MATCH_VWABDAU_VV): Ditto. (MASK_VWABDAU_VV): Ditto. * opcode/riscv.h (enum riscv_insn_class): New extension. opcodes/ChangeLog: * riscv-opc.c: New instructions. --- bfd/elfxx-riscv.c | 6 ++++++ gas/NEWS | 3 +++ gas/testsuite/gas/riscv/march-help.l | 1 + gas/testsuite/gas/riscv/zvabd.d | 13 +++++++++++++ gas/testsuite/gas/riscv/zvabd.s | 6 ++++++ include/opcode/riscv-opc.h | 11 +++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 7 +++++++ 8 files changed, 48 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvabd.d create mode 100644 gas/testsuite/gas/riscv/zvabd.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 4b3b878d6c7..058a6e23439 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1230,6 +1230,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] = {"xtheadzvamo", "+zaamo", check_implicit_always}, {"v", "+zve64d,+zvl128b", check_implicit_always}, + {"zvabd", "+zve32x", check_implicit_always}, {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always}, {"zvfhmin", "+zve32f", check_implicit_always}, {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always}, @@ -1511,6 +1512,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvabd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2947,6 +2949,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve64d") || riscv_subset_supports (rps, "zve64f") || riscv_subset_supports (rps, "zve32f")); + case INSN_CLASS_ZVABD: + return riscv_subset_supports (rps, "zvabd"); case INSN_CLASS_ZVBB: return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: @@ -3263,6 +3267,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64x' or `zve32x"); case INSN_CLASS_ZVEF: return _("v' or `zve64d' or `zve64f' or `zve32f"); + case INSN_CLASS_ZVABD: + return _("zvabd"); case INSN_CLASS_ZVBB: return _("zvbb"); case INSN_CLASS_ZVBC: diff --git a/gas/NEWS b/gas/NEWS index e384d1135c0..46ef5a9f21e 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,8 @@ -*- text -*- +* Add support for RISC-V standard extension: + zvabd v1.0. + Changes in 2.46: * Add support for AMD Zen6 processor. diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index 0ce2f896735..6c6ddd8d9c8 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -68,6 +68,7 @@ All available -march extensions for RISC-V: zve64x 1.0 zve64f 1.0 zve64d 1.0 + zvabd 1.0 zvbb 1.0 zvbc 1.0 zvfbfmin 1.0 diff --git a/gas/testsuite/gas/riscv/zvabd.d b/gas/testsuite/gas/riscv/zvabd.d new file mode 100644 index 00000000000..8e5f1197a78 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvabd.d @@ -0,0 +1,13 @@ +#as: -march=rv64gc_zvabd +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+4a282257[ ]+vabs.v[ ]+v4,v2 +[ ]+[0-9a-f]+:[ ]+4620a257[ ]+vabd.vv[ ]+v4,v2,v1 +[ ]+[0-9a-f]+:[ ]+4e20a257[ ]+vabdu.vv[ ]+v4,v2,v1 +[ ]+[0-9a-f]+:[ ]+5620a257[ ]+vwabda.vv[ ]+v4,v2,v1 +[ ]+[0-9a-f]+:[ ]+5a20a257[ ]+vwabdau.vv[ ]+v4,v2,v1 diff --git a/gas/testsuite/gas/riscv/zvabd.s b/gas/testsuite/gas/riscv/zvabd.s new file mode 100644 index 00000000000..4a930702e23 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvabd.s @@ -0,0 +1,6 @@ +target: + vabs.v v4, v2 + vabd.vv v4, v2, v1 + vabdu.vv v4, v2, v1 + vwabda.vv v4, v2, v1 + vwabdau.vv v4, v2, v1 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 6f2775c6152..5364d22ea90 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2275,6 +2275,17 @@ #define MASK_VSM3C_VI 0xfe00707f #define MATCH_VSM3ME_VV 0x82002077 #define MASK_VSM3ME_VV 0xfe00707f +/* Zvabd instructions. */ +#define MATCH_VABS_V 0x48082057 +#define MASK_VABS_V 0xfc0ff07f +#define MATCH_VABD_VV 0x44002057 +#define MASK_VABD_VV 0xfc00707f +#define MATCH_VABDU_VV 0x4c002057 +#define MASK_VABDU_VV 0xfc00707f +#define MATCH_VWABDA_VV 0x54002057 +#define MASK_VWABDA_VV 0xfc00707f +#define MATCH_VWABDAU_VV 0x58002057 +#define MASK_VWABDAU_VV 0xfc00707f /* Zcb instructions. */ #define MATCH_C_LBU 0x8000 #define MASK_C_LBU 0xfc03 diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index de105f5df8b..394a672eb8e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -552,6 +552,7 @@ enum riscv_insn_class INSN_CLASS_ZVKNHA_OR_ZVKNHB, INSN_CLASS_ZVKSED, INSN_CLASS_ZVKSH, + INSN_CLASS_ZVABD, INSN_CLASS_ZICFISS, INSN_CLASS_ZICFISS_AND_ZCMOP, INSN_CLASS_ZICFILP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 54887c97880..a7f8e08dee4 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2277,6 +2277,13 @@ const struct riscv_opcode riscv_opcodes[] = {"vsm3c.vi", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM3C_VI, match_opcode, 0}, {"vsm3me.vv", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0}, +/* Zvabd instructions. */ +{"vabs.v", 0, INSN_CLASS_ZVABD, "Vd,VtVm", MATCH_VABS_V, MASK_VABS_V, match_opcode, 0}, +{"vabd.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABD_VV, MASK_VABD_VV, match_opcode, 0}, +{"vabdu.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABDU_VV, MASK_VABDU_VV, match_opcode, 0}, +{"vwabda.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDA_VV, MASK_VWABDA_VV, match_opcode, 0}, +{"vwabdau.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDAU_VV, MASK_VWABDAU_VV, match_opcode, 0}, + /* ZCB instructions. */ {"c.lbu", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_DREF|INSN_1_BYTE }, {"c.lhu", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_DREF|INSN_2_BYTE },