From patchwork Wed May 20 12:08:50 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alice Carlotti X-Patchwork-Id: 135334 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C97B4BB3B89 for ; Wed, 20 May 2026 12:11:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C97B4BB3B89 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BW6Ju20I; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BW6Ju20I X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from MRWPR03CU001.outbound.protection.outlook.com (mail-francesouthazlp170110003.outbound.protection.outlook.com [IPv6:2a01:111:f403:c207::3]) by sourceware.org (Postfix) with ESMTPS id 7201F4BB3BF8 for ; Wed, 20 May 2026 12:10:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7201F4BB3BF8 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7201F4BB3BF8 Authentication-Results: sourceware.org; arc=fail smtp.remote-ip=2a01:111:f403:c207::3 DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7201F4BB3BF8 ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=fail; b=QhtUJR/uCY+oNLTdWv8eZrJAT/ECpaEvNay9t+Q8S+pidECUZ5kccMp9kZ2tvUrMx/oXoijhQSsoU8IiHvpzSqbaXGsaMpUc64gPcsPA6qFuMkzZVvXco1XgmG0VEGwC4un785eVhNaOVP9kInr0VE9ei0+7y9QsLX2VZtbl5FgcA5vN0y/ZpQ40yRsaISMVf8/sbzQ6rn940tCVu9o8/9g2MWWa/KmPie0IpQO44QPYwAsUYpW2Z+czMMT/PTuvyYC8aJwoBN2RcJWVywwQ2ilBXsjanEug4y3XMdsSTT/8qw3/RzlrKtU4sFZtpBG9QkrwutumFbu/Wekr2plBQA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/y5TSugjNgJshCtFXc68qydQm9i6dAYgyIuWrycoZ0g=; b=kBBz6cEPauiPyHJP8CeQhHmKxXgJrDtHHAr0YCaIAiJvFe2QL+N0l1xF6sGxynMqt2Yxa5CIFWNiVjC7654sZ7aCVtI0PfTK+ZlZwBFdqXFChLQHfYn7CMkigdVRo/nrkNy2p/Jt0ykbIGYlPQ6ZkSnOFbG0KwOBqu9E/60O0XOTGxAT2E/wwZBITqYYyGsLNnHBB6FSCHpr5ePMloZgL6aATeYcEAkMzb4b5sc4x0o6yKHmJLSTrNp/f0Qy+Fp8QyJoQdRWnY9rgHLZZiir7FREkW7ob9rozBDIqXqX0psmgX1bs2DvkNfxZDKlGqf7NQ47s7z9A1J139DQ62FJ+w== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=fail (48) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/y5TSugjNgJshCtFXc68qydQm9i6dAYgyIuWrycoZ0g=; b=BW6Ju20IwAVpnXxS47+96vLVMYHw8QYy+UG/uQclHCegJ553Pgir0mbky5zoC3qyOtb/GIPCcxoUBHwE9oFsgxPw3p+e4te7A7yowtyGSlbQPOnJab6uzGqP3prukpfzxBFlHR+2vwLvR064xzFGCo87UQhkD891j2xnAc278h8= Received: from DUZPR01CA0076.eurprd01.prod.exchangelabs.com (2603:10a6:10:46a::7) by DB9PR08MB9537.eurprd08.prod.outlook.com (2603:10a6:10:459::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:09:55 +0000 Received: from DB1PEPF000509EA.eurprd03.prod.outlook.com (2603:10a6:10:46a:cafe::bf) by DUZPR01CA0076.outlook.office365.com (2603:10a6:10:46a::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.16 via Frontend Transport; Wed, 20 May 2026 12:09:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by DB1PEPF000509EA.mail.protection.outlook.com (10.167.242.68) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Wed, 20 May 2026 12:09:55 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Bz6Yr7hdNYBV03Cq7nNFOgg2li3XtGSdbKSV53y2hRrbREeL0IbI7V8oVxPe8r7cVix+RIhP7X2FnUjcZ2tYIlUs+xXKgGHyzZhIp/l+/BlgYw7r75QDYjpEYCMMY/H/iqEXknon1o8ShyCaW4bajFskjFwzUjAxLXtxGl5t+3DH+44eWO6y3dBr6k66pj+clJWmlcay0p3atqNAHAPSL9gLamdwvV+5wB6HIdxRYuDTXM8WWpvNg37S3znLW9qKkmDSw1HpCvhqqt/loTZehdfSOa1rE7uSyYybx7RBv6Y5HuopB9VJXxCEJxH7kCcurNMO+IK1azDuEgU8YL3SwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/y5TSugjNgJshCtFXc68qydQm9i6dAYgyIuWrycoZ0g=; b=AJHPw1cX+0oIL/zhZ7tIYKlQ66reUcRNkdLgaODGRxQFyHk1GnUDiI4rPcA5QQtbCs38vsDSmhbbMLhG5bTLP8mC9jjUids/w2edJQ8Q4LhdamgR1R6KEbHFrB+Lpd/9niz2jJL9Kp9IRPcFDSughW6yoiOK0Fo/+aC+nFzDm0mDPiU6EuAmvnlG9Y9P/Bdr0q0SHcoxhJ/iK3w/Km1pObR3nj7MWEPHZ+STcS/w9P+lIDaOR/9qiIjZI/TySjG3GTAkFJevVsvsK9mVqzKwjijfDq2UnqXARs+VI6RwsWPFVbKIuTPekXQ8FRdLz4Zc8EfjH9nWhJnKLw6UK/tIUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/y5TSugjNgJshCtFXc68qydQm9i6dAYgyIuWrycoZ0g=; b=BW6Ju20IwAVpnXxS47+96vLVMYHw8QYy+UG/uQclHCegJ553Pgir0mbky5zoC3qyOtb/GIPCcxoUBHwE9oFsgxPw3p+e4te7A7yowtyGSlbQPOnJab6uzGqP3prukpfzxBFlHR+2vwLvR064xzFGCo87UQhkD891j2xnAc278h8= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) by PAWPR08MB11454.eurprd08.prod.outlook.com (2603:10a6:102:50b::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:08:52 +0000 Received: from DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24]) by DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24%5]) with mapi id 15.21.0048.013; Wed, 20 May 2026 12:08:52 +0000 Date: Wed, 20 May 2026 13:08:50 +0100 From: Alice Carlotti To: binutils@sourceware.org Cc: Richard Earnshaw Subject: [PATCH 1/5] aarch64: Remove aarch64_field_kind indirection Message-ID: <01196ecb-956b-eb96-2ab2-e5de6fa143c5@e124511.cambridge.arm.com> References: Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: LO4P123CA0305.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:196::22) To DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DU0PR08MB8255:EE_|PAWPR08MB11454:EE_|DB1PEPF000509EA:EE_|DB9PR08MB9537:EE_ X-MS-Office365-Filtering-Correlation-Id: 680330bc-b6f8-4a02-d0d2-08deb668b489 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|366016|1800799024|376014|56012099003|22082099003|18002099003|11063799006|3023799007; X-Microsoft-Antispam-Message-Info-Original: 7S8eiIkjmHyzp/M629sphoAE4MNquv6jLya8ArC82XL4UI7u33sD7xhxu0wnBNqlYKfI3K81NLL1KrGLTXT4UX6k3EA7zvLhbJpi14LkwEPo98xT12Yj/GRf3HIWpupfgP1vq/iv8acydKmUy6z+Qwf5/rYqI+oqkoGWRKvsdJMoDAK/sSwwYfRiK/iFhT7l6pJn9lpKd0hYHtqs5ELJAmQzNnyiHf3MNFBfckwJE2/a+UhTCjCfkSrdISMz/aeiUi+B2famFJt+BRgphRaHO265vDUf3c3Sbf40GpyCX20Jy5Cg07Qom3BXPKG7wQAl1tkXosbIdydsmmqz3zUBRSy8hfNXU20MMd2zvuJc0eM3abglcXyHYK3/Nr/bO3yYRDxkSfJyAQxrpfz9/KsMeNzR/k0XE+dw2FboJTqFxthBtLvf7DQ4TvKsI3OdC3lG7CP/w0EZoHtuiB9EQ6l/oMoqUCLOHDp6l3U+Tr5RYc3UHUVXDvNAiWX2MbAT+kfPt/cNxzKdg9NIuDIobh+AF+0LR3Hg5lhAu1u2KsywnEuWGbl39PYit0nLer3JxJtANMKbiJypKknQFMQnsd9PfX802prmUupdertxbHC/7yxjx1hwNY5jqH5mueBRGACOtpeEEYo17RKFPZidcIX9KxHxQa4kuhEzDxuQoGp+M5dGAf8dARo8ACBD+LNisJQl X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DU0PR08MB8255.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(1800799024)(376014)(56012099003)(22082099003)(18002099003)(11063799006)(3023799007); DIR:OUT; SFP:1101; X-Exchange-RoutingPolicyChecked: PWCSq0H4Jn7hGsbazVPcNCzuOfoPM2pyDWnRcSJtlU1e/0SyOeM9DvCfhiUeBS0JLDnqEBbVH+3xarzSpAy21f3I1gvVJTnxKg0XPt6pXXETCiSVuDQw/ymIBP1Q3AMv7iwdRt8f8qvivTT+XB2a/b2tk/8Q6CUohcjrcLCL06O7WQ6LRtLaoMHtFd+ccF3PF8eFdKWRlliNo/hV5ChSboQmf5tyhvth9AJ/PVB79IOZ1Z9n+vrQS8D9mnnbs8ZyraFShdhPjt3SkT0tOcj1FZqlxE0xFPe4M3CXkTm+skOnaWGMK/Di+LPSVAbtN6xKujSAbCrgpg08F09ERRF6Bg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB11454 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB1PEPF000509EA.eurprd03.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 580243d0-f816-44db-3a5c-08deb6688ec2 X-Microsoft-Antispam: BCL:0; ARA:13230040|35042699022|36860700016|376014|14060799003|82310400026|1800799024|3023799007|11063799006|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: IicEgb9uWQKV7iXaWq+F6X5Tk2OkJ8J3mGfVkLaDgaEEuCpJZ4phKt0R0WudmpRTOOAv80+Dyi8HlgvG5ETedvTdEZOFlDacRg3GITDeEuFyhiWS/yYwA4lbbsvSUquXJakWSSIM4Xqs6rg1s+dDQYq86usDCT4adcE1MDbb3CRWlN1Oy0mrVJXXmABDgO0ZlA16bFhmzkSYHYHewkvTXxut5G9ztxCauzmgMtjiom0WkPXAgv+Fk0OMls/1tZiXiSg7Vk6SaIovZiZBFmPmcYqwymP/mgHz/k4hh3lkw3Ub3UKhjOv7Nq6nk/U0JR4oQolA8eBGW2Z7Hlmvgp8kfEjZK6gaB0DOjbvtRQ8O6GDM4atC1zbh0XdC3ayCWwyVJG9mow39+et2IdsPfELu9yLEOyDs3d8qL0P4uWW7WzSY97DvlIe2MmnANNi2Jto1/bZTf5JtK2iwtWFby+Jjr8rietMyS4+oPngVG59RJyJdrK/W2jS/28itlz4Afx99JrgECY1UOs3SC0FxOW6y96ziUqRbOPO+DK+W/xQRFENH0BjJ5fpV4uCJb2bqgDGwPegDPA2n/n9PDKJhHh/mObahBCrsf6QgzDjDIOjqQmilRCYCRyoflijF+8gDA2CVS0UavRF31MLcXGBo0ej8XpZmmV/NLqkIE8Pq+wLfGz/2oFlN6jsxT6PKJHLfLE/OIn+q/pBF70+UYTCFVxuWfG4Vjq6iELxL2ZcfgCChrb8= X-Forefront-Antispam-Report: CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(35042699022)(36860700016)(376014)(14060799003)(82310400026)(1800799024)(3023799007)(11063799006)(22082099003)(18002099003)(56012099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: LmmKbbjkbffSS+vGUWyp1W8+5cD6V6ZsenSVdsdBTUrsPMqf2pxEr8tJmI0XgtJ/dPa5TMRoKfSLccvb534SgaX8SK6h9Zo8Lfe0xIWIycycCZ7ut2ioRVJPy+69GdkgQ8kTwAc3jwTyRsF6hzA9Xtw3VGnX4KH6N545hqQTLW48vqpKhlu6DSjXpth5nAzGyzEmM6b9SoWhPGFzSoZxbiP34VmtSH6PO2hW8DiH998Tge6nZLXXzJGmgpNDeD2QejlN4EK4KUUYANUMOV5h55NKDZOVPtn5frF/STTn/jc8GujzmKe6nmPgFz7eyRAFRTlVkZHmDJTOiV4YKUdpKg2Aqtfe3w7Qtg+9JGrfGlIO6cVEKVILDIA6AAVstlilWVIRHckLiPkfAp/FkAsIwRzVmJJJBdupDW4rZ/fuVKPREfOVOuMioEr33c8hKPp7 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 12:09:55.4506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 680330bc-b6f8-4a02-d0d2-08deb668b489 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509EA.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB9537 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, LOCAL_AUTHENTICATION_FAIL_ARC, SPF_HELO_PASS, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Replace all uses of the aarch64_field_kind enum with direct uses of an aarch64_field struct instead. Add macro defines mapping the old enum names to their corresponding aarch64_field values, to reduce the initial diff. These can be substituted directly into their uses in subsequent patches. Once the macro defines are replaced, this should make it simpler to read the code, because it will no longer be necessary to look in a separate table to find out which opcode bits a field actually uses. This has been a growing problem over the years - originally there was a simpler correspondence between field names and positions, but as the architecture has grown it has become harder to guess a field's position from it's name alone. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index d44bc6dc6a4cdaaaed48e2cf286afccba91019c0..305ac2981ce421f703d46aabc5852622017ab5d9 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -40,7 +40,6 @@ static inline void insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...) { uint32_t num; - enum aarch64_field_kind kind; va_list va; va_start (va, mask); @@ -48,9 +47,9 @@ insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...) assert (num <= 5); while (num--) { - kind = va_arg (va, enum aarch64_field_kind); - insert_field (kind, code, value, mask); - value >>= aarch64_fields[kind].width; + aarch64_field field = va_arg (va, aarch64_field); + insert_field (field, code, value, mask); + value >>= field.width; } va_end (va); } @@ -63,14 +62,13 @@ insert_all_fields_after (const aarch64_operand *self, unsigned int start, aarch64_insn *code, aarch64_insn value) { unsigned int i; - enum aarch64_field_kind kind; for (i = ARRAY_SIZE (self->fields); i-- > start; ) - if (self->fields[i] != FLD_NIL) + if (self->fields[i].width != 0) { - kind = self->fields[i]; - insert_field (kind, code, value, 0); - value >>= aarch64_fields[kind].width; + aarch64_field field = self->fields[i]; + insert_field (field, code, value, 0); + value >>= field.width; } } @@ -349,7 +347,7 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, } insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q); gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); - insert_field_2 (&field, code, opcodeh2, 0); + insert_field (field, code, opcodeh2, 0); return true; } @@ -500,7 +498,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, amount >>= 4; gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ } - insert_field_2 (&field, code, amount, 0); + insert_field (field, code, amount, 0); return true; } @@ -753,7 +751,7 @@ aarch64_ins_addr_simm (const aarch64_operand *self, insert_field (FLD_Rn, code, info->addr.base_regno, 0); /* simm (imm9 or imm7) */ imm = info->addr.offset.imm; - if (self->fields[0] == FLD_imm7 + if (self->fields[0].width == 7 || info->qualifier == AARCH64_OPND_QLF_imm_tag) /* scaled immediate in ld/st pair instructions.. */ imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier)); @@ -1868,7 +1866,7 @@ encode_asimd_fcvt (aarch64_inst *inst) || qualifier == AARCH64_OPND_QLF_V_2D); value = (qualifier == AARCH64_OPND_QLF_V_4S) ? 0 : 1; gen_sub_field (FLD_size, 0, 1, &field); - insert_field_2 (&field, &inst->value, value, 0); + insert_field (field, &inst->value, value, 0); } /* Encode size[0], i.e. bit 22, for @@ -1881,7 +1879,7 @@ encode_asisd_fcvtxn (aarch64_inst *inst) aarch64_field field = AARCH64_FIELD_NIL; assert (inst->operands[0].qualifier == AARCH64_OPND_QLF_S_S); gen_sub_field (FLD_size, 0, 1, &field); - insert_field_2 (&field, &inst->value, val, 0); + insert_field (field, &inst->value, val, 0); } /* Encode the 'opc' field for e.g. FCVT
, . */ @@ -1899,7 +1897,7 @@ encode_fcvt (aarch64_inst *inst) case AARCH64_OPND_QLF_S_H: val = 3; break; default: abort (); } - insert_field_2 (&field, &inst->value, val, 0); + insert_field (field, &inst->value, val, 0); return; } @@ -1998,7 +1996,7 @@ static void encode_sizeq (aarch64_inst *inst) { aarch64_insn sizeq; - enum aarch64_field_kind kind; + aarch64_field field; int idx; /* Get the index of the operand whose information we are going to use @@ -2015,10 +2013,10 @@ encode_sizeq (aarch64_inst *inst) || inst->opcode->iclass == asisdlsep || inst->opcode->iclass == asisdlso || inst->opcode->iclass == asisdlsop) - kind = FLD_vldst_size; + field = FLD_vldst_size; else - kind = FLD_size; - insert_field (kind, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask); + field = FLD_size; + insert_field (field, &inst->value, (sizeq >> 1) & 0x3, inst->opcode->mask); } /* Opcodes that have fields shared by multiple operands are usually flagged @@ -2131,7 +2129,7 @@ do_special_encoding (struct aarch64_inst *inst) num = (int) value >> 1; assert (num >= 0 && num <= 3); gen_sub_field (FLD_imm5, 0, num + 1, &field); - insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask); + insert_field (field, &inst->value, 1 << num, inst->opcode->mask); } if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs) @@ -2173,7 +2171,7 @@ do_special_encoding (struct aarch64_inst *inst) == AARCH64_OPND_CLASS_INT_REG); gen_sub_field (FLD_opc, 0, 1, &field); qualifier = inst->operands[0].qualifier; - insert_field_2 (&field, &inst->value, + insert_field (field, &inst->value, 1 - aarch64_get_qualifier_standard_value (qualifier), 0); } /* Miscellaneous encoding as the last step. */ diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index c3a809ef576184969d42d44986e3ead416f50688..f86c5026cf7ccf2935be67cbedb274366e6c04e0 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -162,7 +162,6 @@ aarch64_insn extract_fields (aarch64_insn code, aarch64_insn mask, ...) { uint32_t num; - enum aarch64_field_kind kind; va_list va; va_start (va, mask); @@ -171,9 +170,9 @@ extract_fields (aarch64_insn code, aarch64_insn mask, ...) aarch64_insn value = 0x0; while (num--) { - kind = va_arg (va, enum aarch64_field_kind); - value <<= aarch64_fields[kind].width; - value |= extract_field (kind, code, mask); + aarch64_field field = va_arg (va, aarch64_field); + value <<= field.width; + value |= extract_field (field, code, mask); } va_end (va); return value; @@ -188,15 +187,14 @@ extract_all_fields_after (const aarch64_operand *self, unsigned int start, { aarch64_insn value; unsigned int i; - enum aarch64_field_kind kind; value = 0; for (i = start; - i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i) + i < ARRAY_SIZE (self->fields) && self->fields[i].width != 0; ++i) { - kind = self->fields[i]; - value <<= aarch64_fields[kind].width; - value |= extract_field (kind, code, 0); + aarch64_field field = self->fields[i]; + value <<= field.width; + value |= extract_field (field, code, 0); } return value; } @@ -607,7 +605,7 @@ aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, /* Decode the index, opcode<2:1> and size. */ gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); - opcodeh2 = extract_field_2 (&field, code, 0); + opcodeh2 = extract_field (field, code, 0); QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size); switch (opcodeh2) { @@ -855,13 +853,13 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, default: return false; } /* 00: 0; 01: 8; 10:16; 11:24. */ - info->shifter.amount = extract_field_2 (&field, code, 0) << 3; + info->shifter.amount = extract_field (field, code, 0) << 3; break; case AARCH64_OPND_QLF_MSL: /* shift ones */ info->shifter.kind = AARCH64_MOD_MSL; gen_sub_field (FLD_cmode, 0, 1, &field); /* per word */ - info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8; + info->shifter.amount = extract_field (field, code, 0) ? 16 : 8; break; default: return false; @@ -1250,8 +1248,8 @@ aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, /* simm (imm9 or imm7) */ imm = extract_field (self->fields[0], code, 0); info->addr.offset.imm - = sign_extend (imm, aarch64_fields[self->fields[0]].width - 1); - if (self->fields[0] == FLD_imm7 + = sign_extend (imm, self->fields[0].width - 1); + if (self->fields[0].width == 7 || info->qualifier == AARCH64_OPND_QLF_imm_tag) /* scaled immediate in ld/st pair instructions. */ info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier); @@ -2564,7 +2562,7 @@ decode_sizeq (aarch64_inst *inst) int idx; aarch64_insn code; aarch64_insn value, mask; - enum aarch64_field_kind fld_sz; + aarch64_field fld_sz; enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM]; if (inst->opcode->iclass == asisdlse @@ -2633,7 +2631,7 @@ decode_asimd_fcvt (aarch64_inst *inst) enum aarch64_opnd_qualifier qualifier; gen_sub_field (FLD_size, 0, 1, &field); - value = extract_field_2 (&field, inst->value, 0); + value = extract_field (field, inst->value, 0); qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S : AARCH64_OPND_QLF_V_2D; switch (inst->opcode->op) @@ -2663,7 +2661,7 @@ decode_asisd_fcvtxn (aarch64_inst *inst) { aarch64_field field = AARCH64_FIELD_NIL; gen_sub_field (FLD_size, 0, 1, &field); - if (!extract_field_2 (&field, inst->value, 0)) + if (!extract_field (field, inst->value, 0)) return 0; inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S; return 1; @@ -2678,7 +2676,7 @@ decode_fcvt (aarch64_inst *inst) const aarch64_field field = AARCH64_FIELD (15, 2); /* opc dstsize */ - value = extract_field_2 (&field, inst->value, 0); + value = extract_field (field, inst->value, 0); switch (value) { case 0: qualifier = AARCH64_OPND_QLF_S_S; break; @@ -2958,7 +2956,7 @@ do_special_decoding (aarch64_inst *inst) assert (aarch64_get_operand_class (inst->opcode->operands[0]) == AARCH64_OPND_CLASS_INT_REG); gen_sub_field (FLD_opc, 0, 1, &field); - value = extract_field_2 (&field, inst->value, 0); + value = extract_field (field, inst->value, 0); inst->operands[0].qualifier = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X; } diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c index d989c55752390939ae0ddcdecdf0fd7dc9628909..c10b84d323e7bb7d518d311a3187a875032de2db 100644 --- a/opcodes/aarch64-gen.c +++ b/opcodes/aarch64-gen.c @@ -998,14 +998,14 @@ typedef struct operand operand; static operand operands[] = { - {"NIL", "0", "0", "", "0", "{0}", "", 0, 0, 0}, + {"NIL", "0", "0", "", "0", "{}", "", 0, 0, 0}, #define F(...) #__VA_ARGS__ #define X(a,b,c,d,e,f,g) \ {#a, #b, #c, d, #e, "{"f"}", g, 0, 0, 0}, #define Y(a,b,d,e,f,g) \ {#a, "ins_"#b, "ext_"#b, d, #e, "{"f"}", g, 0, 0, 0}, AARCH64_OPERANDS - {"NIL", "0", "0", "", "0", "{0}", "DUMMY", 0, 0, 0}, + {"NIL", "0", "0", "", "0", "{}", "DUMMY", 0, 0, 0}, }; #undef F diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 8a2c560e53f45592b13daf6d18a9631a3e08a2be..c3e26925194d5ad7d29875ddcac21fa807b4c964 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -25,7 +25,7 @@ const struct aarch64_operand aarch64_operands[] = { - {AARCH64_OPND_CLASS_NIL, "", 0, {0}, ""}, + {AARCH64_OPND_CLASS_NIL, "", 0, {}, ""}, {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"}, @@ -378,7 +378,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SYSTEM, "GIC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, {AARCH64_OPND_CLASS_SYSTEM, "GICR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, {AARCH64_OPND_CLASS_SYSTEM, "GSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller Synchronization Barrier"}, - {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, + {AARCH64_OPND_CLASS_NIL, "", 0, {}, "DUMMY"}, }; /* Indexed by an enum aarch64_op enumerator, the value is the diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 62bb11868fd956b28db468deba9cf1913f716360..3a2694627b35422c21dd72e963c77f7204f26353 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -217,231 +217,6 @@ aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode) significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])]; } -/* Instruction bit-fields. -+ Keep synced with 'enum aarch64_field_kind'. */ -const aarch64_field aarch64_fields[] = -{ - AARCH64_FIELD_NIL, /* NIL. */ - AARCH64_FIELD_CONST (0, 1), /* CONST_0. */ - AARCH64_FIELD_CONST (0, 2), /* CONST_00. */ - AARCH64_FIELD_CONST (1, 2), /* CONST_01. */ - AARCH64_FIELD_CONST (1, 1), /* CONST_1. */ - AARCH64_FIELD ( 8, 4), /* CRm: in the system instructions. */ - AARCH64_FIELD (10, 2), /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */ - AARCH64_FIELD (12, 4), /* CRn: in the system instructions. */ - AARCH64_FIELD (10, 8), /* CSSC_imm8. */ - AARCH64_FIELD (11, 1), /* H: in advsimd scalar x indexed element instructions. */ - AARCH64_FIELD (21, 1), /* L: in advsimd scalar x indexed element instructions. */ - AARCH64_FIELD ( 0, 5), /* LSE128_Rt: Shared input+output operand register. */ - AARCH64_FIELD (16, 5), /* LSE128_Rt2: Shared input+output operand register 2. */ - AARCH64_FIELD (20, 1), /* M: in advsimd scalar x indexed element instructions. */ - AARCH64_FIELD (22, 1), /* N: in logical (immediate) instructions. */ - AARCH64_FIELD (30, 1), /* Q: in most AdvSIMD instructions. */ - AARCH64_FIELD (10, 5), /* Ra: in fp instructions. */ - AARCH64_FIELD ( 0, 5), /* Rd: in many integer instructions. */ - AARCH64_FIELD (16, 5), /* Rm: in ld/st reg offset and some integer inst. */ - AARCH64_FIELD ( 5, 5), /* Rn: in many integer instructions. */ - AARCH64_FIELD (16, 5), /* Rs: in load/store exclusive instructions. */ - AARCH64_FIELD ( 0, 5), /* Rt: in load/store instructions. */ - AARCH64_FIELD (10, 5), /* Rt2: in load/store pair instructions. */ - AARCH64_FIELD (12, 1), /* S: in load/store reg offset instructions. */ - AARCH64_FIELD (12, 2), /* SM3_imm2: Indexed element SM3 2 bits index immediate. */ - AARCH64_FIELD ( 1, 3), /* SME_Pdx2: predicate register, multiple of 2, [3:1]. */ - AARCH64_FIELD (13, 3), /* SME_Pm: second source scalable predicate register P0-P7. */ - AARCH64_FIELD ( 0, 3), /* SME_PNd3: PN0-PN7, bits [2:0]. */ - AARCH64_FIELD ( 5, 3), /* SME_PNn3: PN0-PN7, bits [7:5]. */ - AARCH64_FIELD (16, 1), /* SME_Q: Q class bit, bit 16. */ - AARCH64_FIELD (16, 2), /* SME_Rm: index base register W12-W15 [17:16]. */ - AARCH64_FIELD (13, 2), /* SME_Rv: vector select register W12-W15, bits [14:13]. */ - AARCH64_FIELD (15, 1), /* SME_V: (horizontal / vertical tiles), bit 15. */ - AARCH64_FIELD (10, 1), /* SME_VL_10: VLx2 or VLx4, bit [10]. */ - AARCH64_FIELD (13, 1), /* SME_VL_13: VLx2 or VLx4, bit [13]. */ - AARCH64_FIELD ( 0, 1), /* SME_ZAda_1b: tile ZA0-ZA1. */ - AARCH64_FIELD ( 0, 2), /* SME_ZAda_2b: tile ZA0-ZA3. */ - AARCH64_FIELD ( 0, 3), /* SME_ZAda_3b: tile ZA0-ZA7. */ - AARCH64_FIELD ( 1, 4), /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */ - AARCH64_FIELD ( 2, 3), /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */ - AARCH64_FIELD (16, 4), /* SME_Zm: Z0-Z15, bits [19:16]. */ - AARCH64_FIELD (17, 3), /* SME_Zm17_3: Z0-Z15/Z16-Z31, multiple of 2, bits [19:17]. */ - AARCH64_FIELD (17, 4), /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */ - AARCH64_FIELD (18, 3), /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */ - AARCH64_FIELD ( 6, 4), /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */ - AARCH64_FIELD ( 7, 3), /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */ - AARCH64_FIELD ( 6, 3), /* SME_Zn6_3: Z0-Z15/Z16-Z31, multiple of 2, bits [8:6]. */ - AARCH64_FIELD ( 4, 1), /* SME_ZtT: upper bit of Zt, bit [4]. */ - AARCH64_FIELD ( 0, 3), /* SME_Zt3: lower 3 bits of Zt, bits [2:0]. */ - AARCH64_FIELD ( 0, 2), /* SME_Zt2: lower 2 bits of Zt, bits [1:0]. */ - AARCH64_FIELD (23, 1), /* SME_i1: immediate field, bit 23. */ - AARCH64_FIELD (12, 2), /* SME_size_12: bits [13:12]. */ - AARCH64_FIELD (22, 2), /* SME_size_22: size<1>, size<0> class field, [23:22]. */ - AARCH64_FIELD (23, 1), /* SME_sz_23: bit [23]. */ - AARCH64_FIELD (22, 1), /* SME_tszh: immediate and qualifier field, bit 22. */ - AARCH64_FIELD (18, 3), /* SME_tszl: immediate and qualifier field, bits [20:18]. */ - AARCH64_FIELD (0, 8), /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */ - AARCH64_FIELD ( 4, 1), /* SVE_M_4: Merge/zero select, bit 4. */ - AARCH64_FIELD (14, 1), /* SVE_M_14: Merge/zero select, bit 14. */ - AARCH64_FIELD (16, 1), /* SVE_M_16: Merge/zero select, bit 16. */ - AARCH64_FIELD (17, 1), /* SVE_N: SVE equivalent of N. */ - AARCH64_FIELD ( 0, 4), /* SVE_Pd: p0-p15, bits [3,0]. */ - AARCH64_FIELD (10, 3), /* SVE_Pg3: p0-p7, bits [12,10]. */ - AARCH64_FIELD ( 5, 4), /* SVE_Pg4_5: p0-p15, bits [8,5]. */ - AARCH64_FIELD (10, 4), /* SVE_Pg4_10: p0-p15, bits [13,10]. */ - AARCH64_FIELD (16, 4), /* SVE_Pg4_16: p0-p15, bits [19,16]. */ - AARCH64_FIELD (16, 4), /* SVE_Pm: p0-p15, bits [19,16]. */ - AARCH64_FIELD ( 5, 4), /* SVE_Pn: p0-p15, bits [8,5]. */ - AARCH64_FIELD ( 0, 4), /* SVE_Pt: p0-p15, bits [3,0]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Rm: SVE alternative position for Rm. */ - AARCH64_FIELD (16, 5), /* SVE_Rn: SVE alternative position for Rn. */ - AARCH64_FIELD ( 0, 5), /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Za_5: SVE vector register, bits [9,5]. */ - AARCH64_FIELD (16, 5), /* SVE_Za_16: SVE vector register, bits [20,16]. */ - AARCH64_FIELD ( 0, 5), /* SVE_Zd: SVE vector register. bits [4,0]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Zm_5: SVE vector register, bits [9,5]. */ - AARCH64_FIELD (16, 5), /* SVE_Zm_16: SVE vector register, bits [20,16]. */ - AARCH64_FIELD ( 5, 5), /* SVE_Zn: SVE vector register, bits [9,5]. */ - AARCH64_FIELD ( 0, 5), /* SVE_Zt: SVE vector register, bits [4,0]. */ - AARCH64_FIELD ( 5, 1), /* SVE_i1: single-bit immediate. */ - AARCH64_FIELD (23, 1), /* SVE_i1_23: single-bit immediate. */ - AARCH64_FIELD (22, 2), /* SVE_i2: 2-bit index, bits [23,22]. */ - AARCH64_FIELD (20, 1), /* SVE_i2h: high bit of 2bit immediate, bits. */ - AARCH64_FIELD (22, 1), /* SVE_i3h: high bit of 3-bit immediate. */ - AARCH64_FIELD (19, 2), /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */ - AARCH64_FIELD (22, 2), /* SVE_i3h3: two high bits of 3bit immediate, bits [22,23]. */ - AARCH64_FIELD (11, 1), /* SVE_i3l: low bit of 3-bit immediate. */ - AARCH64_FIELD (12, 1), /* SVE_i3l2: low bit of 3-bit immediate, bit 12. */ - AARCH64_FIELD (10, 2), /* SVE_i4l2: two low bits of 4bit immediate, bits [11,10]. */ - AARCH64_FIELD (16, 3), /* SVE_imm3: 3-bit immediate field. */ - AARCH64_FIELD (16, 4), /* SVE_imm4: 4-bit immediate field. */ - AARCH64_FIELD ( 5, 5), /* SVE_imm5: 5-bit immediate field. */ - AARCH64_FIELD (16, 5), /* SVE_imm5b: secondary 5-bit immediate field. */ - AARCH64_FIELD (16, 6), /* SVE_imm6: 6-bit immediate field. */ - AARCH64_FIELD (14, 7), /* SVE_imm7: 7-bit immediate field. */ - AARCH64_FIELD ( 5, 8), /* SVE_imm8: 8-bit immediate field. */ - AARCH64_FIELD ( 5, 9), /* SVE_imm9: 9-bit immediate field. */ - AARCH64_FIELD (11, 6), /* SVE_immr: SVE equivalent of immr. */ - AARCH64_FIELD ( 5, 6), /* SVE_imms: SVE equivalent of imms. */ - AARCH64_FIELD (10, 2), /* SVE_msz: 2-bit shift amount for ADR. */ - AARCH64_FIELD ( 5, 5), /* SVE_pattern: vector pattern enumeration. */ - AARCH64_FIELD ( 0, 4), /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */ - AARCH64_FIELD (16, 1), /* SVE_rot1: 1-bit rotation amount. */ - AARCH64_FIELD (10, 2), /* SVE_rot2: 2-bit rotation amount. */ - AARCH64_FIELD (10, 1), /* SVE_rot3: 1-bit rotation amount at bit 10. */ - AARCH64_FIELD (17, 2), /* SVE_size: 2-bit element size, bits [18,17]. */ - AARCH64_FIELD (22, 1), /* SVE_sz: 1-bit element size select. */ - AARCH64_FIELD (30, 1), /* SVE_sz2: 1-bit element size select. */ - AARCH64_FIELD (17, 1), /* SVE_sz3: 1-bit element size select. */ - AARCH64_FIELD (14, 1), /* SVE_sz4: 1-bit element size select. */ - AARCH64_FIELD (16, 4), /* SVE_tsz: triangular size select. */ - AARCH64_FIELD (22, 2), /* SVE_tszh: triangular size select high, bits [23,22]. */ - AARCH64_FIELD ( 8, 2), /* SVE_tszl_8: triangular size select low, bits [9,8]. */ - AARCH64_FIELD (19, 2), /* SVE_tszl_19: triangular size select low, bits [20,19]. */ - AARCH64_FIELD (14, 1), /* SVE_xs_14: UXTW/SXTW select (bit 14). */ - AARCH64_FIELD (22, 1), /* SVE_xs_22: UXTW/SXTW select (bit 22). */ - AARCH64_FIELD (22, 1), /* S_imm10: in LDRAA and LDRAB instructions. */ - AARCH64_FIELD (16, 3), /* abc: a:b:c bits in AdvSIMD modified immediate. */ - AARCH64_FIELD (13, 3), /* asisdlso_opcode: opcode in advsimd ld/st single element. */ - AARCH64_FIELD (19, 5), /* b40: in the test bit and branch instructions. */ - AARCH64_FIELD (31, 1), /* b5: in the test bit and branch instructions. */ - AARCH64_FIELD (12, 4), /* cmode: in advsimd modified immediate instructions. */ - AARCH64_FIELD (12, 4), /* cond: condition flags as a source operand. */ - AARCH64_FIELD ( 0, 4), /* cond2: condition in truly conditional-executed inst. */ - AARCH64_FIELD ( 5, 5), /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ - AARCH64_FIELD (21, 2), /* hw: in move wide constant instructions. */ - AARCH64_FIELD ( 0, 1), /* imm1_0: general immediate in bits [0]. */ - AARCH64_FIELD ( 2, 1), /* imm1_2: general immediate in bits [2]. */ - AARCH64_FIELD ( 3, 1), /* imm1_3: general immediate in bits [3]. */ - AARCH64_FIELD ( 8, 1), /* imm1_8: general immediate in bits [8]. */ - AARCH64_FIELD (10, 1), /* imm1_10: general immediate in bits [10]. */ - AARCH64_FIELD (14, 1), /* imm1_14: general immediate in bits [14]. */ - AARCH64_FIELD (15, 1), /* imm1_15: general immediate in bits [15]. */ - AARCH64_FIELD (16, 1), /* imm1_16: general immediate in bits [16]. */ - AARCH64_FIELD (22, 1), /* imm1_22: general immediate in bits [22]. */ - AARCH64_FIELD ( 0, 2), /* imm2_0: general immediate in bits [1:0]. */ - AARCH64_FIELD ( 1, 2), /* imm2_1: general immediate in bits [2:1]. */ - AARCH64_FIELD ( 2, 2), /* imm2_2: general immediate in bits [3:2]. */ - AARCH64_FIELD ( 4, 2), /* imm2_4: general immediate in bits [5:4]. */ - AARCH64_FIELD ( 8, 2), /* imm2_8: general immediate in bits [9:8]. */ - AARCH64_FIELD (10, 2), /* imm2_10: 2-bit immediate, bits [11:10] */ - AARCH64_FIELD (12, 2), /* imm2_12: 2-bit immediate, bits [13:12] */ - AARCH64_FIELD (13, 2), /* imm2_13: 2-bit immediate, bits [14:13] */ - AARCH64_FIELD (15, 2), /* imm2_15: 2-bit immediate, bits [16:15] */ - AARCH64_FIELD (16, 2), /* imm2_16: 2-bit immediate, bits [17:16] */ - AARCH64_FIELD (19, 2), /* imm2_19: 2-bit immediate, bits [20:19] */ - AARCH64_FIELD ( 0, 3), /* imm3_0: general immediate in bits [2:0]. */ - AARCH64_FIELD ( 5, 3), /* imm3_5: general immediate in bits [7:5]. */ - AARCH64_FIELD (10, 3), /* imm3_10: in add/sub extended reg instructions. */ - AARCH64_FIELD (12, 3), /* imm3_12: general immediate in bits [14:12]. */ - AARCH64_FIELD (14, 3), /* imm3_14: general immediate in bits [16:14]. */ - AARCH64_FIELD (15, 3), /* imm3_15: general immediate in bits [17:15]. */ - AARCH64_FIELD (19, 3), /* imm3_19: general immediate in bits [21:19]. */ - AARCH64_FIELD ( 0, 4), /* imm4_0: in rmif instructions. */ - AARCH64_FIELD ( 5, 4), /* imm4_5: in SME instructions. */ - AARCH64_FIELD (10, 4), /* imm4_10: in adddg/subg instructions. */ - AARCH64_FIELD (11, 4), /* imm4_11: in advsimd ext and advsimd ins instructions. */ - AARCH64_FIELD (14, 4), /* imm4_14: general immediate in bits [17:14]. */ - AARCH64_FIELD (16, 5), /* imm5: in conditional compare (immediate) instructions. */ - AARCH64_FIELD (10, 6), /* imm6_10: in add/sub reg shifted instructions. */ - AARCH64_FIELD (15, 6), /* imm6_15: in rmif instructions. */ - AARCH64_FIELD (15, 7), /* imm7: in load/store pair pre/post index instructions. */ - AARCH64_FIELD (13, 8), /* imm8: in floating-point scalar move immediate inst. */ - AARCH64_FIELD (12, 9), /* imm9: in load/store pre/post index instructions. */ - AARCH64_FIELD ( 5, 9), /* imm9_5: in CB (immediate). */ - AARCH64_FIELD (10,12), /* imm12: in ld/st unsigned imm or add/sub shifted inst. */ - AARCH64_FIELD ( 5,14), /* imm14: in test bit and branch instructions. */ - AARCH64_FIELD ( 0,16), /* imm16_0: in udf instruction. */ - AARCH64_FIELD ( 5,16), /* imm16_5: in exception instructions. */ - AARCH64_FIELD (17, 1), /* imm17_1: in 1 bit element index. */ - AARCH64_FIELD (17, 2), /* imm17_2: in 2 bits element index. */ - AARCH64_FIELD ( 5,19), /* imm19: e.g. in CBZ. */ - AARCH64_FIELD ( 0,26), /* imm26: in unconditional branch instructions. */ - AARCH64_FIELD (16, 3), /* immb: in advsimd shift by immediate instructions. */ - AARCH64_FIELD (19, 4), /* immh: in advsimd shift by immediate instructions. */ - AARCH64_FIELD ( 5,19), /* immhi: e.g. in ADRP. */ - AARCH64_FIELD (29, 2), /* immlo: e.g. in ADRP. */ - AARCH64_FIELD (16, 6), /* immr: in bitfield and logical immediate instructions. */ - AARCH64_FIELD (10, 6), /* imms: in bitfield and logical immediate instructions. */ - AARCH64_FIELD (11, 1), /* index: in ld/st inst deciding the pre/post-index. */ - AARCH64_FIELD (24, 1), /* index2: in ld/st pair inst deciding the pre/post-index. */ - AARCH64_FIELD (30, 2), /* ldst_size: size field in ld/st reg offset inst. */ - AARCH64_FIELD (13, 2), /* len: in advsimd tbl/tbx instructions. */ - AARCH64_FIELD (30, 1), /* lse_sz: in LSE extension atomic instructions. */ - AARCH64_FIELD ( 0, 4), /* nzcv: flag bit specifier, encoded in the "nzcv" field. */ - AARCH64_FIELD (29, 1), /* op: in AdvSIMD modified immediate instructions. */ - AARCH64_FIELD (19, 2), /* op0: in the system instructions. */ - AARCH64_FIELD (16, 3), /* op1: in the system instructions. */ - AARCH64_FIELD ( 5, 3), /* op2: in the system instructions. */ - AARCH64_FIELD (22, 2), /* opc: in load/store reg offset instructions. */ - AARCH64_FIELD (23, 1), /* opc1: in load/store reg offset instructions. */ - AARCH64_FIELD (12, 4), /* opcode: in advsimd load/store instructions. */ - AARCH64_FIELD (13, 3), /* option: in ld/st reg offset + add/sub extended reg inst. */ - AARCH64_FIELD (11, 2), /* rotate1: FCMLA immediate rotate. */ - AARCH64_FIELD (13, 2), /* rotate2: Indexed element FCMLA immediate rotate. */ - AARCH64_FIELD (12, 1), /* rotate3: FCADD immediate rotate. */ - AARCH64_FIELD (10, 6), /* scale: in the fixed-point scalar to fp converting inst. */ - AARCH64_FIELD (31, 1), /* sf: in integer data processing instructions. */ - AARCH64_FIELD (22, 2), /* shift: in add/sub reg/imm shifted instructions. */ - AARCH64_FIELD (22, 2), /* size: in most AdvSIMD and floating-point instructions. */ - AARCH64_FIELD (22, 1), /* sz: 1-bit element size select. */ - AARCH64_FIELD (22, 2), /* type: floating point type field in fp data inst. */ - AARCH64_FIELD (10, 2), /* vldst_size: size field in the AdvSIMD load/store inst. */ - AARCH64_FIELD ( 5, 3), /* off3: immediate offset used to calculate slice number in a ZA tile. */ - AARCH64_FIELD ( 5, 2), /* off2: immediate offset used to calculate slice number in a ZA tile. */ - AARCH64_FIELD ( 7, 1), /* ZAn_1: name of the 1bit encoded ZA tile. */ - AARCH64_FIELD ( 5, 1), /* ol: immediate offset used to calculate slice number in a ZA tile. */ - AARCH64_FIELD ( 6, 2), /* ZAn_2: name of the 2bit encoded ZA tile. */ - AARCH64_FIELD ( 5, 3), /* ZAn_3: name of the 3bit encoded ZA tile. */ - AARCH64_FIELD ( 6, 1), /* ZAn: name of the bit encoded ZA tile. */ - AARCH64_FIELD (12, 4), /* opc2: in rcpc3 ld/st inst deciding the pre/post-index. */ - AARCH64_FIELD (30, 2), /* rcpc3_size: in rcpc3 ld/st, field controls Rt/Rt2 width. */ - AARCH64_FIELD ( 5, 1), /* FLD_brbop: used in BRB to mean IALL or INJ. */ - AARCH64_FIELD ( 8, 1), /* ZA8_1: name of the 1 bit encoded ZA tile ZA0-ZA1. */ - AARCH64_FIELD ( 7, 2), /* ZA7_2: name of the 2 bits encoded ZA tile ZA0-ZA3. */ - AARCH64_FIELD ( 6, 3), /* ZA6_3: name of the 3 bits encoded ZA tile ZA0-ZA7. */ - AARCH64_FIELD ( 5, 4), /* ZA5_4: name of the 4 bits encoded ZA tile ZA0-ZA15. */ -}; - enum aarch64_operand_class aarch64_get_operand_class (enum aarch64_opnd type) { diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 9be0275391cd53d2c76b0b5a3533fffcba1fa413..3a7085a3def104ea88817391147b6eef831825b5 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -24,232 +24,6 @@ #include #include "opcode/aarch64.h" -/* Instruction fields. - Keep this sorted alphanumerically and synced with the fields array - in aarch64-opc.c. */ -enum aarch64_field_kind -{ - FLD_NIL, - FLD_CONST_0, - FLD_CONST_00, - FLD_CONST_01, - FLD_CONST_1, - FLD_CRm, - FLD_CRm_dsb_nxs, - FLD_CRn, - FLD_CSSC_imm8, - FLD_H, - FLD_L, - FLD_LSE128_Rt, - FLD_LSE128_Rt2, - FLD_M, - FLD_N, - FLD_Q, - FLD_Ra, - FLD_Rd, - FLD_Rm, - FLD_Rn, - FLD_Rs, - FLD_Rt, - FLD_Rt2, - FLD_S, - FLD_SM3_imm2, - FLD_SME_Pdx2, - FLD_SME_Pm, - FLD_SME_PNd3, - FLD_SME_PNn3, - FLD_SME_Q, - FLD_SME_Rm, - FLD_SME_Rv, - FLD_SME_V, - FLD_SME_VL_10, - FLD_SME_VL_13, - FLD_SME_ZAda_1b, - FLD_SME_ZAda_2b, - FLD_SME_ZAda_3b, - FLD_SME_Zdn2, - FLD_SME_Zdn4, - FLD_SME_Zm, - FLD_SME_Zm17_3, - FLD_SME_Zm2, - FLD_SME_Zm4, - FLD_SME_Zn2, - FLD_SME_Zn4, - FLD_SME_Zn6_3, - FLD_SME_ZtT, - FLD_SME_Zt3, - FLD_SME_Zt2, - FLD_SME_i1, - FLD_SME_size_12, - FLD_SME_size_22, - FLD_SME_sz_23, - FLD_SME_tszh, - FLD_SME_tszl, - FLD_SME_zero_mask, - FLD_SVE_M_4, - FLD_SVE_M_14, - FLD_SVE_M_16, - FLD_SVE_N, - FLD_SVE_Pd, - FLD_SVE_Pg3, - FLD_SVE_Pg4_5, - FLD_SVE_Pg4_10, - FLD_SVE_Pg4_16, - FLD_SVE_Pm, - FLD_SVE_Pn, - FLD_SVE_Pt, - FLD_SVE_Rm, - FLD_SVE_Rn, - FLD_SVE_Vd, - FLD_SVE_Vm, - FLD_SVE_Vn, - FLD_SVE_Za_5, - FLD_SVE_Za_16, - FLD_SVE_Zd, - FLD_SVE_Zm_5, - FLD_SVE_Zm_16, - FLD_SVE_Zn, - FLD_SVE_Zt, - FLD_SVE_i1, - FLD_SVE_i1_23, - FLD_SVE_i2, - FLD_SVE_i2h, - FLD_SVE_i3h, - FLD_SVE_i3h2, - FLD_SVE_i3h3, - FLD_SVE_i3l, - FLD_SVE_i3l2, - FLD_SVE_i4l2, - FLD_SVE_imm3, - FLD_SVE_imm4, - FLD_SVE_imm5, - FLD_SVE_imm5b, - FLD_SVE_imm6, - FLD_SVE_imm7, - FLD_SVE_imm8, - FLD_SVE_imm9, - FLD_SVE_immr, - FLD_SVE_imms, - FLD_SVE_msz, - FLD_SVE_pattern, - FLD_SVE_prfop, - FLD_SVE_rot1, - FLD_SVE_rot2, - FLD_SVE_rot3, - FLD_SVE_size, - FLD_SVE_sz, - FLD_SVE_sz2, - FLD_SVE_sz3, - FLD_SVE_sz4, - FLD_SVE_tsz, - FLD_SVE_tszh, - FLD_SVE_tszl_8, - FLD_SVE_tszl_19, - FLD_SVE_xs_14, - FLD_SVE_xs_22, - FLD_S_imm10, - FLD_abc, - FLD_asisdlso_opcode, - FLD_b40, - FLD_b5, - FLD_cmode, - FLD_cond, - FLD_cond2, - FLD_defgh, - FLD_hw, - FLD_imm1_0, - FLD_imm1_2, - FLD_imm1_3, - FLD_imm1_8, - FLD_imm1_10, - FLD_imm1_14, - FLD_imm1_15, - FLD_imm1_16, - FLD_imm1_22, - FLD_imm2_0, - FLD_imm2_1, - FLD_imm2_2, - FLD_imm2_4, - FLD_imm2_8, - FLD_imm2_10, - FLD_imm2_12, - FLD_imm2_13, - FLD_imm2_15, - FLD_imm2_16, - FLD_imm2_19, - FLD_imm3_0, - FLD_imm3_5, - FLD_imm3_10, - FLD_imm3_12, - FLD_imm3_14, - FLD_imm3_15, - FLD_imm3_19, - FLD_imm4_0, - FLD_imm4_5, - FLD_imm4_10, - FLD_imm4_11, - FLD_imm4_14, - FLD_imm5, - FLD_imm6_10, - FLD_imm6_15, - FLD_imm7, - FLD_imm8, - FLD_imm9, - FLD_imm9_5, - FLD_imm12, - FLD_imm14, - FLD_imm16_0, - FLD_imm16_5, - FLD_imm17_1, - FLD_imm17_2, - FLD_imm19, - FLD_imm26, - FLD_immb, - FLD_immh, - FLD_immhi, - FLD_immlo, - FLD_immr, - FLD_imms, - FLD_index, - FLD_index2, - FLD_ldst_size, - FLD_len, - FLD_lse_sz, - FLD_nzcv, - FLD_op, - FLD_op0, - FLD_op1, - FLD_op2, - FLD_opc, - FLD_opc1, - FLD_opcode, - FLD_option, - FLD_rotate1, - FLD_rotate2, - FLD_rotate3, - FLD_scale, - FLD_sf, - FLD_shift, - FLD_size, - FLD_sz, - FLD_type, - FLD_vldst_size, - FLD_off3, - FLD_off2, - FLD_ZAn_1, - FLD_ol, - FLD_ZAn_2, - FLD_ZAn_3, - FLD_ZAn, - FLD_opc2, - FLD_rcpc3_size, - FLD_brbop, - FLD_ZA8_1, - FLD_ZA7_2, - FLD_ZA6_3, - FLD_ZA5_4, -}; - /* Field description. If is_const is false, this identifies a bitfield in an instruction encoding @@ -281,11 +55,233 @@ struct aarch64_field typedef struct aarch64_field aarch64_field; -#define AARCH64_FIELD(lsb, width) {width, lsb, false} -#define AARCH64_FIELD_CONST(val, width) {width, val, true} -#define AARCH64_FIELD_NIL {0, 0, false} +#define AARCH64_FIELD(lsb, width) ((aarch64_field) {width, lsb, false}) +#define AARCH64_FIELD_CONST(val, width) ((aarch64_field) {width, val, true}) +#define AARCH64_FIELD_NIL ((aarch64_field) {0, 0, false}) + +#define FLD_CONST_0 AARCH64_FIELD_CONST (0, 1) +#define FLD_CONST_00 AARCH64_FIELD_CONST (0, 2) +#define FLD_CONST_01 AARCH64_FIELD_CONST (1, 2) +#define FLD_CONST_1 AARCH64_FIELD_CONST (1, 1) + +/* Instruction fields. These defines are included to reduce the initial diff + size, but the indirection should eventually be eliminated. */ +#define FLD_NIL AARCH64_FIELD( 0, 0) +#define FLD_CRm AARCH64_FIELD( 8, 4) +#define FLD_CRm_dsb_nxs AARCH64_FIELD(10, 2) +#define FLD_CRn AARCH64_FIELD(12, 4) +#define FLD_CSSC_imm8 AARCH64_FIELD(10, 8) +#define FLD_H AARCH64_FIELD(11, 1) +#define FLD_L AARCH64_FIELD(21, 1) +#define FLD_LSE128_Rt AARCH64_FIELD( 0, 5) +#define FLD_LSE128_Rt2 AARCH64_FIELD(16, 5) +#define FLD_M AARCH64_FIELD(20, 1) +#define FLD_N AARCH64_FIELD(22, 1) +#define FLD_Q AARCH64_FIELD(30, 1) +#define FLD_Ra AARCH64_FIELD(10, 5) +#define FLD_Rd AARCH64_FIELD( 0, 5) +#define FLD_Rm AARCH64_FIELD(16, 5) +#define FLD_Rn AARCH64_FIELD( 5, 5) +#define FLD_Rs AARCH64_FIELD(16, 5) +#define FLD_Rt AARCH64_FIELD( 0, 5) +#define FLD_Rt2 AARCH64_FIELD(10, 5) +#define FLD_S AARCH64_FIELD(12, 1) +#define FLD_SM3_imm2 AARCH64_FIELD(12, 2) +#define FLD_SME_Pdx2 AARCH64_FIELD( 1, 3) +#define FLD_SME_Pm AARCH64_FIELD(13, 3) +#define FLD_SME_PNd3 AARCH64_FIELD( 0, 3) +#define FLD_SME_PNn3 AARCH64_FIELD( 5, 3) +#define FLD_SME_Q AARCH64_FIELD(16, 1) +#define FLD_SME_Rm AARCH64_FIELD(16, 2) +#define FLD_SME_Rv AARCH64_FIELD(13, 2) +#define FLD_SME_V AARCH64_FIELD(15, 1) +#define FLD_SME_VL_10 AARCH64_FIELD(10, 1) +#define FLD_SME_VL_13 AARCH64_FIELD(13, 1) +#define FLD_SME_ZAda_1b AARCH64_FIELD( 0, 1) +#define FLD_SME_ZAda_2b AARCH64_FIELD( 0, 2) +#define FLD_SME_ZAda_3b AARCH64_FIELD( 0, 3) +#define FLD_SME_Zdn2 AARCH64_FIELD( 1, 4) +#define FLD_SME_Zdn4 AARCH64_FIELD( 2, 3) +#define FLD_SME_Zm AARCH64_FIELD(16, 4) +#define FLD_SME_Zm17_3 AARCH64_FIELD(17, 3) +#define FLD_SME_Zm2 AARCH64_FIELD(17, 4) +#define FLD_SME_Zm4 AARCH64_FIELD(18, 3) +#define FLD_SME_Zn2 AARCH64_FIELD( 6, 4) +#define FLD_SME_Zn4 AARCH64_FIELD( 7, 3) +#define FLD_SME_Zn6_3 AARCH64_FIELD( 6, 3) +#define FLD_SME_ZtT AARCH64_FIELD( 4, 1) +#define FLD_SME_Zt3 AARCH64_FIELD( 0, 3) +#define FLD_SME_Zt2 AARCH64_FIELD( 0, 2) +#define FLD_SME_i1 AARCH64_FIELD(23, 1) +#define FLD_SME_size_12 AARCH64_FIELD(12, 2) +#define FLD_SME_size_22 AARCH64_FIELD(22, 2) +#define FLD_SME_sz_23 AARCH64_FIELD(23, 1) +#define FLD_SME_tszh AARCH64_FIELD(22, 1) +#define FLD_SME_tszl AARCH64_FIELD(18, 3) +#define FLD_SME_zero_mask AARCH64_FIELD(0, 8) +#define FLD_SVE_M_4 AARCH64_FIELD( 4, 1) +#define FLD_SVE_M_14 AARCH64_FIELD(14, 1) +#define FLD_SVE_M_16 AARCH64_FIELD(16, 1) +#define FLD_SVE_N AARCH64_FIELD(17, 1) +#define FLD_SVE_Pd AARCH64_FIELD( 0, 4) +#define FLD_SVE_Pg3 AARCH64_FIELD(10, 3) +#define FLD_SVE_Pg4_5 AARCH64_FIELD( 5, 4) +#define FLD_SVE_Pg4_10 AARCH64_FIELD(10, 4) +#define FLD_SVE_Pg4_16 AARCH64_FIELD(16, 4) +#define FLD_SVE_Pm AARCH64_FIELD(16, 4) +#define FLD_SVE_Pn AARCH64_FIELD( 5, 4) +#define FLD_SVE_Pt AARCH64_FIELD( 0, 4) +#define FLD_SVE_Rm AARCH64_FIELD( 5, 5) +#define FLD_SVE_Rn AARCH64_FIELD(16, 5) +#define FLD_SVE_Vd AARCH64_FIELD( 0, 5) +#define FLD_SVE_Vm AARCH64_FIELD( 5, 5) +#define FLD_SVE_Vn AARCH64_FIELD( 5, 5) +#define FLD_SVE_Za_5 AARCH64_FIELD( 5, 5) +#define FLD_SVE_Za_16 AARCH64_FIELD(16, 5) +#define FLD_SVE_Zd AARCH64_FIELD( 0, 5) +#define FLD_SVE_Zm_5 AARCH64_FIELD( 5, 5) +#define FLD_SVE_Zm_16 AARCH64_FIELD(16, 5) +#define FLD_SVE_Zn AARCH64_FIELD( 5, 5) +#define FLD_SVE_Zt AARCH64_FIELD( 0, 5) +#define FLD_SVE_i1 AARCH64_FIELD( 5, 1) +#define FLD_SVE_i1_23 AARCH64_FIELD(23, 1) +#define FLD_SVE_i2 AARCH64_FIELD(22, 2) +#define FLD_SVE_i2h AARCH64_FIELD(20, 1) +#define FLD_SVE_i3h AARCH64_FIELD(22, 1) +#define FLD_SVE_i3h2 AARCH64_FIELD(19, 2) +#define FLD_SVE_i3h3 AARCH64_FIELD(22, 2) +#define FLD_SVE_i3l AARCH64_FIELD(11, 1) +#define FLD_SVE_i3l2 AARCH64_FIELD(12, 1) +#define FLD_SVE_i4l2 AARCH64_FIELD(10, 2) +#define FLD_SVE_imm3 AARCH64_FIELD(16, 3) +#define FLD_SVE_imm4 AARCH64_FIELD(16, 4) +#define FLD_SVE_imm5 AARCH64_FIELD( 5, 5) +#define FLD_SVE_imm5b AARCH64_FIELD(16, 5) +#define FLD_SVE_imm6 AARCH64_FIELD(16, 6) +#define FLD_SVE_imm7 AARCH64_FIELD(14, 7) +#define FLD_SVE_imm8 AARCH64_FIELD( 5, 8) +#define FLD_SVE_imm9 AARCH64_FIELD( 5, 9) +#define FLD_SVE_immr AARCH64_FIELD(11, 6) +#define FLD_SVE_imms AARCH64_FIELD( 5, 6) +#define FLD_SVE_msz AARCH64_FIELD(10, 2) +#define FLD_SVE_pattern AARCH64_FIELD( 5, 5) +#define FLD_SVE_prfop AARCH64_FIELD( 0, 4) +#define FLD_SVE_rot1 AARCH64_FIELD(16, 1) +#define FLD_SVE_rot2 AARCH64_FIELD(10, 2) +#define FLD_SVE_rot3 AARCH64_FIELD(10, 1) +#define FLD_SVE_size AARCH64_FIELD(17, 2) +#define FLD_SVE_sz AARCH64_FIELD(22, 1) +#define FLD_SVE_sz2 AARCH64_FIELD(30, 1) +#define FLD_SVE_sz3 AARCH64_FIELD(17, 1) +#define FLD_SVE_sz4 AARCH64_FIELD(14, 1) +#define FLD_SVE_tsz AARCH64_FIELD(16, 4) +#define FLD_SVE_tszh AARCH64_FIELD(22, 2) +#define FLD_SVE_tszl_8 AARCH64_FIELD( 8, 2) +#define FLD_SVE_tszl_19 AARCH64_FIELD(19, 2) +#define FLD_SVE_xs_14 AARCH64_FIELD(14, 1) +#define FLD_SVE_xs_22 AARCH64_FIELD(22, 1) +#define FLD_S_imm10 AARCH64_FIELD(22, 1) +#define FLD_abc AARCH64_FIELD(16, 3) +#define FLD_asisdlso_opcode AARCH64_FIELD(13, 3) +#define FLD_b40 AARCH64_FIELD(19, 5) +#define FLD_b5 AARCH64_FIELD(31, 1) +#define FLD_cmode AARCH64_FIELD(12, 4) +#define FLD_cond AARCH64_FIELD(12, 4) +#define FLD_cond2 AARCH64_FIELD( 0, 4) +#define FLD_defgh AARCH64_FIELD( 5, 5) +#define FLD_hw AARCH64_FIELD(21, 2) +#define FLD_imm1_0 AARCH64_FIELD( 0, 1) +#define FLD_imm1_2 AARCH64_FIELD( 2, 1) +#define FLD_imm1_3 AARCH64_FIELD( 3, 1) +#define FLD_imm1_8 AARCH64_FIELD( 8, 1) +#define FLD_imm1_10 AARCH64_FIELD(10, 1) +#define FLD_imm1_14 AARCH64_FIELD(14, 1) +#define FLD_imm1_15 AARCH64_FIELD(15, 1) +#define FLD_imm1_16 AARCH64_FIELD(16, 1) +#define FLD_imm1_22 AARCH64_FIELD(22, 1) +#define FLD_imm2_0 AARCH64_FIELD( 0, 2) +#define FLD_imm2_1 AARCH64_FIELD( 1, 2) +#define FLD_imm2_2 AARCH64_FIELD( 2, 2) +#define FLD_imm2_4 AARCH64_FIELD( 4, 2) +#define FLD_imm2_8 AARCH64_FIELD( 8, 2) +#define FLD_imm2_10 AARCH64_FIELD(10, 2) +#define FLD_imm2_12 AARCH64_FIELD(12, 2) +#define FLD_imm2_13 AARCH64_FIELD(13, 2) +#define FLD_imm2_15 AARCH64_FIELD(15, 2) +#define FLD_imm2_16 AARCH64_FIELD(16, 2) +#define FLD_imm2_19 AARCH64_FIELD(19, 2) +#define FLD_imm3_0 AARCH64_FIELD( 0, 3) +#define FLD_imm3_5 AARCH64_FIELD( 5, 3) +#define FLD_imm3_10 AARCH64_FIELD(10, 3) +#define FLD_imm3_12 AARCH64_FIELD(12, 3) +#define FLD_imm3_14 AARCH64_FIELD(14, 3) +#define FLD_imm3_15 AARCH64_FIELD(15, 3) +#define FLD_imm3_19 AARCH64_FIELD(19, 3) +#define FLD_imm4_0 AARCH64_FIELD( 0, 4) +#define FLD_imm4_5 AARCH64_FIELD( 5, 4) +#define FLD_imm4_10 AARCH64_FIELD(10, 4) +#define FLD_imm4_11 AARCH64_FIELD(11, 4) +#define FLD_imm4_14 AARCH64_FIELD(14, 4) +#define FLD_imm5 AARCH64_FIELD(16, 5) +#define FLD_imm6_10 AARCH64_FIELD(10, 6) +#define FLD_imm6_15 AARCH64_FIELD(15, 6) +#define FLD_imm7 AARCH64_FIELD(15, 7) +#define FLD_imm8 AARCH64_FIELD(13, 8) +#define FLD_imm9 AARCH64_FIELD(12, 9) +#define FLD_imm9_5 AARCH64_FIELD( 5, 9) +#define FLD_imm12 AARCH64_FIELD(10, 12) +#define FLD_imm14 AARCH64_FIELD( 5, 14) +#define FLD_imm16_0 AARCH64_FIELD( 0, 16) +#define FLD_imm16_5 AARCH64_FIELD( 5, 16) +#define FLD_imm17_1 AARCH64_FIELD(17, 1) +#define FLD_imm17_2 AARCH64_FIELD(17, 2) +#define FLD_imm19 AARCH64_FIELD( 5, 19) +#define FLD_imm26 AARCH64_FIELD( 0, 26) +#define FLD_immb AARCH64_FIELD(16, 3) +#define FLD_immh AARCH64_FIELD(19, 4) +#define FLD_immhi AARCH64_FIELD( 5, 19) +#define FLD_immlo AARCH64_FIELD(29, 2) +#define FLD_immr AARCH64_FIELD(16, 6) +#define FLD_imms AARCH64_FIELD(10, 6) +#define FLD_index AARCH64_FIELD(11, 1) +#define FLD_index2 AARCH64_FIELD(24, 1) +#define FLD_ldst_size AARCH64_FIELD(30, 2) +#define FLD_len AARCH64_FIELD(13, 2) +#define FLD_lse_sz AARCH64_FIELD(30, 1) +#define FLD_nzcv AARCH64_FIELD( 0, 4) +#define FLD_op AARCH64_FIELD(29, 1) +#define FLD_op0 AARCH64_FIELD(19, 2) +#define FLD_op1 AARCH64_FIELD(16, 3) +#define FLD_op2 AARCH64_FIELD( 5, 3) +#define FLD_opc AARCH64_FIELD(22, 2) +#define FLD_opc1 AARCH64_FIELD(23, 1) +#define FLD_opcode AARCH64_FIELD(12, 4) +#define FLD_option AARCH64_FIELD(13, 3) +#define FLD_rotate1 AARCH64_FIELD(11, 2) +#define FLD_rotate2 AARCH64_FIELD(13, 2) +#define FLD_rotate3 AARCH64_FIELD(12, 1) +#define FLD_scale AARCH64_FIELD(10, 6) +#define FLD_sf AARCH64_FIELD(31, 1) +#define FLD_shift AARCH64_FIELD(22, 2) +#define FLD_size AARCH64_FIELD(22, 2) +#define FLD_sz AARCH64_FIELD(22, 1) +#define FLD_type AARCH64_FIELD(22, 2) +#define FLD_vldst_size AARCH64_FIELD(10, 2) +#define FLD_off3 AARCH64_FIELD( 5, 3) +#define FLD_off2 AARCH64_FIELD( 5, 2) +#define FLD_ZAn_1 AARCH64_FIELD( 7, 1) +#define FLD_ol AARCH64_FIELD( 5, 1) +#define FLD_ZAn_2 AARCH64_FIELD( 6, 2) +#define FLD_ZAn_3 AARCH64_FIELD( 5, 3) +#define FLD_ZAn AARCH64_FIELD( 6, 1) +#define FLD_opc2 AARCH64_FIELD(12, 4) +#define FLD_rcpc3_size AARCH64_FIELD(30, 2) +#define FLD_brbop AARCH64_FIELD( 5, 1) +#define FLD_ZA8_1 AARCH64_FIELD( 8, 1) +#define FLD_ZA7_2 AARCH64_FIELD( 7, 2) +#define FLD_ZA6_3 AARCH64_FIELD( 6, 3) +#define FLD_ZA5_4 AARCH64_FIELD( 5, 4) -extern const aarch64_field aarch64_fields[]; /* Operand description. */ @@ -301,7 +297,7 @@ struct aarch64_operand /* The associated instruction bit-fields; no operand has more than 5 bit-fields */ - enum aarch64_field_kind fields[6]; + aarch64_field fields[6]; /* Brief description */ const char *desc; @@ -454,8 +450,8 @@ get_operand_specific_data (const aarch64_operand *operand) static inline unsigned get_operand_field_width (const aarch64_operand *operand, unsigned n) { - assert (operand->fields[n] != FLD_NIL); - return aarch64_fields[operand->fields[n]].width; + assert (operand->fields[n].width != 0); + return operand->fields[n].width; } /* Return the total width of the operand *OPERAND. */ @@ -464,8 +460,8 @@ get_operand_fields_width (const aarch64_operand *operand) { int i = 0; unsigned width = 0; - while (operand->fields[i] != FLD_NIL) - width += aarch64_fields[operand->fields[i++]].width; + while (operand->fields[i].width != 0) + width += operand->fields[i++].width; assert (width > 0 && width < 32); return width; } @@ -508,12 +504,11 @@ gen_mask (int width) /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */ static inline int -gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret) +gen_sub_field (aarch64_field field, int lsb_rel, int width, aarch64_field *ret) { - const aarch64_field *field = &aarch64_fields[kind]; - if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width) + if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field.width) return 0; - ret->num = field->num + lsb_rel; + ret->num = field.num + lsb_rel; ret->width = width; return 1; } @@ -522,19 +517,19 @@ gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_fie of the opcode. */ static inline void -insert_field_2 (const aarch64_field *field, aarch64_insn *code, - aarch64_insn value, aarch64_insn mask) +insert_field (aarch64_field field, aarch64_insn *code, + aarch64_insn value, aarch64_insn mask) { - assert (field->width < 32 && field->width >= 1 - && (field->is_const ? (field->num < 1 << field->width) - : (field->num + field->width <= 32))); - value &= gen_mask (field->width); - if (field->is_const) + assert (field.width < 32 && field.width >= 1 + && (field.is_const ? (field.num < 1 << field.width) + : (field.num + field.width <= 32))); + value &= gen_mask (field.width); + if (field.is_const) { - assert (value == field->num); + assert (value == field.num); return; } - value <<= field->num; + value <<= field.num; /* In some opcodes, field can be part of the base opcode, e.g. the size field in FADD. The following helps avoid corrupt the base opcode. */ value &= ~mask; @@ -545,40 +540,20 @@ insert_field_2 (const aarch64_field *field, aarch64_insn *code, mask of the opcode. */ static inline aarch64_insn -extract_field_2 (const aarch64_field *field, aarch64_insn code, - aarch64_insn mask) +extract_field (aarch64_field field, aarch64_insn code, + aarch64_insn mask) { aarch64_insn value; /* Check for constant field. */ - if (field->is_const) - return field->num; + if (field.is_const) + return field.num; /* Clear any bit that is a part of the base opcode. */ code &= ~mask; - value = (code >> field->num) & gen_mask (field->width); + value = (code >> field.num) & gen_mask (field.width); return value; } -/* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask - of the opcode. */ - -static inline void -insert_field (enum aarch64_field_kind kind, aarch64_insn *code, - aarch64_insn value, aarch64_insn mask) -{ - insert_field_2 (&aarch64_fields[kind], code, value, mask); -} - -/* Extract field KIND of CODE and return the value. MASK can be zero or the - base mask of the opcode. */ - -static inline aarch64_insn -extract_field (enum aarch64_field_kind kind, aarch64_insn code, - aarch64_insn mask) -{ - return extract_field_2 (&aarch64_fields[kind], code, mask); -} - extern aarch64_insn extract_fields (aarch64_insn code, aarch64_insn mask, ...); From patchwork Wed May 20 12:09:07 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alice Carlotti X-Patchwork-Id: 135333 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5703E4BB5881 for ; Wed, 20 May 2026 12:11:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5703E4BB5881 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BbuMwTBp; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=BbuMwTBp X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from GVXPR05CU001.outbound.protection.outlook.com (mail-swedencentralazlp170130007.outbound.protection.outlook.com [IPv6:2a01:111:f403:c202::7]) by sourceware.org (Postfix) with ESMTPS id 9CB5F4BB3BD4 for ; Wed, 20 May 2026 12:10:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9CB5F4BB3BD4 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 9CB5F4BB3BD4 Authentication-Results: sourceware.org; arc=fail smtp.remote-ip=2a01:111:f403:c202::7 DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9CB5F4BB3BD4 ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=fail; b=Nfopa8By3Wmyot/0SM4wpCGG1w2KSH0OCcmgR4+lcMpXdgv2At+IJg0hfuB7IML4w7ZKhm27IgcJpDPfV9BeN/ZyvCHuwHJ6Mx4U3n+0PdQJaeH169lijh/mXPsyxopZMuBjTWlf5Jf5OxMSyFC9n4zFF0/1UgNK2hOQv9K6p0PLsdoXz+OERtu8+Or+vqvJ6UbnGJxHOPz7NFxTGZ5m6jhNt1vW11liuk5t47PenKnCbvyCbSh+CdgvuGCHwnkOB/kwzT7escal9XXtC/Qbb6pJDVm/uNWI/68z6ju+4P+PdGIIPo9/9MzDRi2lqqT5rze78yerV2uyXENTfE5+Pw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MNjxRVX6QdqRLJB/+uFQEJXme/QcV7e2/1D4vf/ip9g=; b=N15LGjFEcstmdZe66ezE2ZOM6PTfP1d8l3Igz4Ilir9xKwl6MFQWsxez0xwweb4eDxKyatHW9mefE14B/+SeU7+HZG3vn95pcNdOUvVL5W7sI/b9n12uVP/hy34BPH8/++9SkbNuBAjH/ocCZDR+74h/JN/w2CqqnHtKUlup2qNrx8yXMpCD45mOTvANrCiFKbyS0jMTwBtjU622OjF2d0HA4U9HhZwlnvbVbhpvPLFb0ZkYq1GvtkhOmeD3P0nGFOkn7xiEM2KqT2BEGN7L2k8o7KMmZqxDl51Azg2mxKbJLjcxbjDyD+CwG8hMobUDpqRpHkUSbJwKDLqsVILC3A== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=fail (48) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MNjxRVX6QdqRLJB/+uFQEJXme/QcV7e2/1D4vf/ip9g=; b=BbuMwTBp/bD6TZ3m23x0GhBXuSztiwNyxkTwbBInU6c75+WurhVIkreD8/XZiuIIxKVUbquOjIe1E0udPs4VcfsOLzwJW9IrHfSHMuTo0jQf/Vhk7OS9mG4NbVcfj9jirWTLGJNlJF9uwS25wFCai628GacY40gkjlae0XvRRWw= Received: from CWLP265CA0460.GBRP265.PROD.OUTLOOK.COM (2603:10a6:400:1d4::20) by AS8PR08MB8924.eurprd08.prod.outlook.com (2603:10a6:20b:5b2::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:10:14 +0000 Received: from AM4PEPF00027A61.eurprd04.prod.outlook.com (2603:10a6:400:1d4:cafe::41) by CWLP265CA0460.outlook.office365.com (2603:10a6:400:1d4::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.16 via Frontend Transport; Wed, 20 May 2026 12:10:13 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AM4PEPF00027A61.mail.protection.outlook.com (10.167.16.70) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Wed, 20 May 2026 12:10:13 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=kgtzxzDWgpUr3Ei2ZXp6ZQcfLvr/S3G9kbBIYkfaIHwr//9vM9d2LnLnT8ypNcuM2SeiYmkisA/X2GJyU92mHwqCD5Uqx8iGhQH21aDdkDiWG2Y6grD9wKVxaUZtuYUqBTn3v026rfm4YkRdw6RtRZQ/TOukxkgUMRJtqmiJW5hs2li/w03d6BM3NrmJwcpiErqHly8Goqai2x+MM8NWw+6GHyV2eKehSSdF4mTT+UI6ACNyVCAL6x4/fmzG778i23iITUOVjXA1KWT8crUoJjd8E3OXD6C8Gt6wIrgrpJ3A6NMOBIhXp/rBuiqQBjfCxoNKSx8nPUoeRVW4iSzntA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MNjxRVX6QdqRLJB/+uFQEJXme/QcV7e2/1D4vf/ip9g=; b=jZwYpQBElNiMoQ/lH4wTjN99QFHqxscCGVZo78JyxdEGMp9eeonZmR1vH7kQx/gTU0oNBzdRRtTg/l3rqtGESxQlRcrIt+UR40vYsapIWzMFSJt/HSNqgNEYDQrUmNZ5I1nkKhbt/SfiVc/m/muYLLMt19xg+fWImilNya8iQlzc0r3vxEmM7QdAydWzumWzd2FymLmODXtbXoQKDrhuV1+Lwy2bgxAWKu1HLp2D18UIkjhPC344oUCNBnGGQG9fkepzLfeeU1/fcZ5lvPVKbnfwhSi+Wb7BHI7fa0lnc8aktA621KGNglNq5O+GXtwiOAleoNdvmwX7dbSrea0LyQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MNjxRVX6QdqRLJB/+uFQEJXme/QcV7e2/1D4vf/ip9g=; b=BbuMwTBp/bD6TZ3m23x0GhBXuSztiwNyxkTwbBInU6c75+WurhVIkreD8/XZiuIIxKVUbquOjIe1E0udPs4VcfsOLzwJW9IrHfSHMuTo0jQf/Vhk7OS9mG4NbVcfj9jirWTLGJNlJF9uwS25wFCai628GacY40gkjlae0XvRRWw= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) by DBBPR08MB6300.eurprd08.prod.outlook.com (2603:10a6:10:209::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:09:09 +0000 Received: from DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24]) by DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24%5]) with mapi id 15.21.0048.013; Wed, 20 May 2026 12:09:09 +0000 Date: Wed, 20 May 2026 13:09:07 +0100 From: Alice Carlotti To: binutils@sourceware.org Cc: Richard Earnshaw Subject: [PATCH 2/5] aarch64: Write AARCH64_FIELD calls to aarch64-opc-2.c Message-ID: References: Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: PA7P264CA0249.FRAP264.PROD.OUTLOOK.COM (2603:10a6:102:371::16) To DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DU0PR08MB8255:EE_|DBBPR08MB6300:EE_|AM4PEPF00027A61:EE_|AS8PR08MB8924:EE_ X-MS-Office365-Filtering-Correlation-Id: d0749af5-fecb-4216-7bd7-08deb668bf02 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|366016|376014|22082099003|18002099003|56012099003|11063799006; X-Microsoft-Antispam-Message-Info-Original: I49sxd4/izQtnteX/fnrqKtMFEXhHBB6d2yxvxVl0AJOTZqv8ERybRZjb9pBJSQI2V4QqguYdyv2f5AidXM5PD5YLIzQ7omxEOZdGpP3GDyrdmLdUtJvZ0SMZ+8+prDWKRyzMVkJPk9M0GVoh/ruSnHIhkTaewsRRgpR8bZOwxI/dif9Q+61U706fm2jSkRNYEeWG/s6YVcSchmCQupcKVmc+obsvKys9PvEfbtmHPJl40LVxAIx6NwXc4xb1ZtojVJwf3pipZWiuq3OGyrGEb4VWNNxCyHw+Hd7i7CEBkQviZGzQPy5ijKZvJPFkJLkgm0BvdXgO54A8fYFO6pHeV8H9Mm1oIeQskk9oqjCNP1YbiXQFXJp3JFKZJmH3W5v0z/VB81Y3F3I+ZEM1o9mj0eAS+UAtCH261ZwYc9u/sUiJk25yO5ZedsJ5DUJyBD0KmI/VWL05kzpYX2hfVoZtBQGnF5+rAC5DRtn0Lex3F91HRv4Ost55dA+sOkcaUkSoi0lXAffjbbeH7RFKq7ttj4KKXdsWSCTfFqeeHoAr8IoLVMTFdQsBB6r4R6EVX2YN62qsbCml2iT6KAVb4q/1FPuX6Bito5+77tdLuZgOD+LzBri718Bv2fNY+6mdNn2fsLmp99Et5/5fRVrCtc5liSWR9yxsRwGfUSjNTYnXJmSuCe5aD5fiIIQC+/St+Gq X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DU0PR08MB8255.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(366016)(376014)(22082099003)(18002099003)(56012099003)(11063799006); DIR:OUT; SFP:1101; X-Exchange-RoutingPolicyChecked: qC8Auj1QszpObyJXznsBJ7alnRHm7JVo8qcJr+SMn2g7ZnzukrV+hLW2waiScKkn4InVNfyM9OW9jeMW2gzoBafdMWmNqy7Noc656bEIFjcxgY1C1kn1mtYwNyBrdXFImkDtcEqNcLKymQf/7q6KuurvAg2Xd9SsBg7n91idH/fRT+NrUujt/q73pjbowrGEOeLlQQSdiJTA3VmnTTX9AlP5AXeMSfg4+OGw36cEe7O3uHQHT+lZ0Ae4H2rL0+8iQhD70tntG1/s6C4CA1cM/1YuV/Bu5rm9Mp+NtdTy8NQhLai6JXRnaX3vDmTjG/qcn4GXUxgtbbSAL0Ec1Yf+zA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6300 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM4PEPF00027A61.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 23d569f4-9769-4c3a-9ad1-08deb66898f7 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|14060799003|1800799024|82310400026|36860700016|35042699022|11063799006|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: GEzWuSjxZCETngWPAEXsZt9YlxN+HfwLowma1cR5zx7nFdToBI3h0XNiGE/9Px9X2012Qp2O8EdpeBC7Y1oosLPfBBgq0SUkLjjggK4PkEeKIh1EzGJ6vs9JDwwrMDvP1+y/fX+yP+WXX1QlFGqwJGFp16LLdo/8TgEBmUe6RH9Q3eG+dO+bIm56R90x/2fbhFUi0K/pHV7B3acAF425ldsoB+f3X0/mAmgl/zHVs+5lv+bPJ+eK+oHQPOMZimqYRkyiy9/B7GnALtlM2LjuvLs0o0bC+aNFN+VJtw7SFJTIigz8Nklsz/XXJ3KSdqIbqv2xgvbVLA9IIFNPVicVvwSFP6Y0b8qf0gZeoeuqMtZbXNhGxfXN4k0KgPySYemXVG8T3gT5humChbM4A3VKB/+nNOxXve2zFq5ZyREVNpqGg2HBZLMJXqJsq/ej6ZhNjWDDu134AZUb20Kg01GjPzisqv3+T0s2e124Kzg7g1PdOzfFOz+LuJDsYPpsGprnGmOffvV6Mtv5SKfunyrOtrmeXita0I4j7VOX85oVfoGopvxv3iC6yHkKned6sKMGecWPPaTe5cvTSuN5WdF2Gyhbw/hxbZrtxNYGhtTW6eDV4pfa2YE+HEbkxgZs8eB3nrEZFfB34nGM3CqmQDvkUuvZE4K4WnMUBGPs8aWQLexZjxhG34Z/Vl6jiDMIypoCQikhUMI1bYGEO4aN8HkcW3FKETvP9UaYUtArM7E12NA= X-Forefront-Antispam-Report: CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(14060799003)(1800799024)(82310400026)(36860700016)(35042699022)(11063799006)(22082099003)(18002099003)(56012099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: lo39SJsYIwRsDHbSwpMXk425jrDPoMRcwahkkfQ7HrBk1PPoCnjYv4K0gUCVLH6bvnNXTUIRqGDRHrNYoaD44+htZpbZAND32HLl4XtNa14GHDo/Wh+nsmQXs+FOC4CPSWJzQ+Yrtqdpm73C6kAXK8LVIUostlkZiFAPo8S9l+clpQXUS+KcnQkzyQJerxb5aUKdTQ15/yQMUDhncAR/oDQxQlshw6cUBUkIgP5za5V+r3ym1aGDXcjXlufc2DwvcBjwMM2GV/URqj5pOhs9nK3QjxB3bQlTyRv1At0xkH8RtL+zx3SB4NpbE/YSq5uVVaaHn4Bp6jn20mvjo/APLKZ3cUO6KpjFvikdv8k84won7+o2pIx+XqinNqWl215FsKBrtByjHsuBjfmrI+vzezEHTHE8EZGxIQUdm8C5u4ze/5hWxVbAj1qzE2kRpAFT X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 12:10:13.0188 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0749af5-fecb-4216-7bd7-08deb668bf02 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A61.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8924 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, LOCAL_AUTHENTICATION_FAIL_ARC, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, UPPERCASE_50_75 shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Parse the operand field lists in aarch64-gen.c, and rewrite the content to aarch64-opc-2.c using AARCH64_FIELD calls. This allows aarch64-tbl.h to use shorthand macros without exporting them elsewhere. diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c index c10b84d323e7bb7d518d311a3187a875032de2db..4bbd71fffff8ec5a86a5785dc051f94717635131 100644 --- a/opcodes/aarch64-gen.c +++ b/opcodes/aarch64-gen.c @@ -973,7 +973,7 @@ struct operand const char *extractor; const char *str; const char *flags; - const char *fields; + aarch64_field fields[6]; const char *desc; unsigned processed : 1; unsigned has_inserter : 1; @@ -994,18 +994,21 @@ typedef struct operand operand; #undef F #endif +/* The parentheses used when calling this macro ensure that the list of fields + appears as a single argument to the X and Y macros. */ +#define F(...) {__VA_ARGS__} + /* Get the operand information in strings. */ static operand operands[] = { - {"NIL", "0", "0", "", "0", "{}", "", 0, 0, 0}, -#define F(...) #__VA_ARGS__ + {"NIL", "0", "0", "", "0", {}, "", 0, 0, 0}, #define X(a,b,c,d,e,f,g) \ - {#a, #b, #c, d, #e, "{"f"}", g, 0, 0, 0}, + {#a, #b, #c, d, #e, f, g, 0, 0, 0}, #define Y(a,b,d,e,f,g) \ - {#a, "ins_"#b, "ext_"#b, d, #e, "{"f"}", g, 0, 0, 0}, + {#a, "ins_"#b, "ext_"#b, d, #e, f, g, 0, 0, 0}, AARCH64_OPERANDS - {"NIL", "0", "0", "", "0", "{}", "DUMMY", 0, 0, 0}, + {"NIL", "0", "0", "", "0", {}, "DUMMY", 0, 0, 0}, }; #undef F @@ -1064,8 +1067,21 @@ print_operand_table (void) flags[0] = '0'; flags[1] = '\0'; } - printf (" {AARCH64_OPND_CLASS_%s, \"%s\", %s, %s, \"%s\"},\n", - opnd->class, opnd->str, flags, opnd->fields, opnd->desc); + char fields[256] = ""; + char *str = fields; + for (int j = 0; j < 6; j++) + { + aarch64_field field = opnd->fields[j]; + if (field.width == 0) + continue; + if (j != 0) + str += sprintf (str, ", "); + str += sprintf (str, "AARCH64_FIELD%s (%d, %d)", + field.is_const ? "_CONST" : "", + field.num, field.width); + } + printf (" {AARCH64_OPND_CLASS_%s, \"%s\", %s, {%s}, \"%s\"},\n", + opnd->class, opnd->str, flags, fields, opnd->desc); } printf ("};\n"); } diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index c3e26925194d5ad7d29875ddcac21fa807b4c964..b9a632300df5eacbb1c608f4757100aa425fe114 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -26,57 +26,57 @@ const struct aarch64_operand aarch64_operands[] = { {AARCH64_OPND_CLASS_NIL, "", 0, {}, ""}, - {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "an integer register"}, {AARCH64_OPND_CLASS_INT_REG, "X16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "X16"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer or stack pointer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "an integer or stack pointer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"}, - {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer or stack pointer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer or stack pointer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rd_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer or stack pointer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer or stack pointer register"}, + {AARCH64_OPND_CLASS_INT_REG, "Rm_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer or stack pointer register"}, {AARCH64_OPND_CLASS_INT_REG, "PAIRREG", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"}, {AARCH64_OPND_CLASS_INT_REG, "PAIRREG_OR_XZR", OPD_F_HAS_EXTRACTOR, {}, "the second reg of a pair"}, {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_EXT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional extension"}, {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_SFT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional shift"}, {AARCH64_OPND_CLASS_MODIFIED_REG, "Rm_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an integer register with optional LSL shift"}, - {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "a floating-point register"}, - {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "a floating-point register"}, - {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD scalar register"}, - {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"}, - {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD scalar register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector register"}, - {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "the top half of a 128-bit FP/SIMD register"}, - {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V7"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_14, FLD_Rm}, "a SIMD vector without a type qualifier encoding a bit index"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_13, FLD_Rm}, "a SIMD vector without a type qualifier encoding a bit index"}, - {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12, FLD_Rm}, "a SIMD vector without a type qualifier encoding a bit index"}, - {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"}, + {AARCH64_OPND_CLASS_FP_REG, "Fd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a floating-point register"}, + {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a floating-point register"}, + {AARCH64_OPND_CLASS_FP_REG, "Fm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a floating-point register"}, + {AARCH64_OPND_CLASS_FP_REG, "Fa", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "a floating-point register"}, + {AARCH64_OPND_CLASS_FP_REG, "Ft", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a floating-point register"}, + {AARCH64_OPND_CLASS_FP_REG, "Ft2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "a floating-point register"}, + {AARCH64_OPND_CLASS_SISD_REG, "Sd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD scalar register"}, + {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD scalar register"}, + {AARCH64_OPND_CLASS_SISD_REG, "Sm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD scalar register"}, + {AARCH64_OPND_CLASS_SIMD_REG, "Va", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 5)}, "a SIMD vector register"}, + {AARCH64_OPND_CLASS_SIMD_REG, "Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD vector register"}, + {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector register"}, + {AARCH64_OPND_CLASS_SIMD_REG, "Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector register"}, + {AARCH64_OPND_CLASS_FP_REG, "VdD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "the top half of a 128-bit FP/SIMD register"}, + {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "the top half of a 128-bit FP/SIMD register"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD vector element"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector element"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector element"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector element limited to V0-V15"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a SIMD vector element limited to V0-V7"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX1_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 1), AARCH64_FIELD (16, 5)}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX2_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (16, 5)}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em_INDEX3_12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 3), AARCH64_FIELD (16, 5)}, "a SIMD vector without a type qualifier encoding a bit index"}, + {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"}, - {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn_LUT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"}, + {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn_LUT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD vector register list"}, {AARCH64_OPND_CLASS_SIMD_REGLIST, "LEt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector element list"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRn}, "a 4-bit opcode field named for historical reasons C0 - C15"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit opcode field named for historical reasons C0 - C15"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_11}, "an immediate as the index of the least significant byte"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_0}, "an immediate as the index of the least significant byte"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "CRn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 4)}, "a 4-bit opcode field named for historical reasons C0 - C15"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "CRm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4)}, "a 4-bit opcode field named for historical reasons C0 - C15"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IDX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (11, 4)}, "an immediate as the index of the least significant byte"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "MASK", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an immediate as the index of the least significant byte"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a left shift amount for an AdvSIMD register"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_VLSR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a right shift amount for an AdvSIMD register"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMD_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an immediate"}, @@ -85,54 +85,54 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "SHLL_IMM", OPD_F_HAS_EXTRACTOR, {}, "an immediate shift amount of 8, 16 or 32"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM0", 0, {}, "0"}, {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM0", 0, {}, "0.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm8}, "an 8-bit floating-point constant"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "the right rotate amount"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "the leftmost bit number to be moved from the source"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "the width of the bit-field"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_10}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMMP1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate plus 1"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm6_15}, "an immediate minus 1"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_10}, "a 4-bit unsigned Logical Address Tag modifier"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_0}, "a 16-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10}, "an optional not balanced indicator (NB)"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_1}, "an optional not balanced indicator (NB)"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit immediate with optional left shift"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "FPIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 8)}, "an 8-bit floating-point constant"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 6)}, "the right rotate amount"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "the leftmost bit number to be moved from the source"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "WIDTH", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "the width of the bit-field"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "an immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 6)}, "an immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMP1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 6)}, "an immediate plus 1"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMMS1_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 6)}, "an immediate minus 1"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 3)}, "a 3-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 3)}, "a 3-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4)}, "a 4-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 4)}, "a 4-bit unsigned Logical Address Tag modifier"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4), AARCH64_FIELD (5, 3)}, "a 7-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 6)}, "a 10-bit unsigned multiple of 16"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (31, 1), AARCH64_FIELD (19, 5)}, "the bit number to be tested"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 16)}, "a 16-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 16)}, "a 16-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a 5-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a 5-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1)}, "an optional not balanced indicator (NB)"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1)}, "an optional not balanced indicator (NB)"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "a flag bit specifier giving an alternative value for each flag"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (16, 6), AARCH64_FIELD (10, 6)}, "Logical immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (10, 12)}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 16)}, "a 16-bit immediate with optional left shift"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 6)}, "the number of bits after the binary point in the fixed-point value"}, {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate1}, "a 2-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate2}, "a 2-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_rotate3}, "a 1-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (11, 2)}, "a 2-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2)}, "a 2-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 1)}, "a 1-bit rotation specifier for complex arithmetic operations"}, {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"}, {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL9", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9_5}, "9-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immhi,FLD_immlo}, "21-bit PC-relative address"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm26}, "26-bit PC-relative address"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 19), AARCH64_FIELD (29, 2)}, "21-bit PC-relative address of a 4KB page"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL9", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 9)}, "9-bit PC-relative address"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 14)}, "14-bit PC-relative address"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 19)}, "19-bit PC-relative address"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL21", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 19), AARCH64_FIELD (29, 2)}, "21-bit PC-relative address"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 26)}, "26-bit PC-relative address"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"}, {AARCH64_OPND_CLASS_ADDRESS, "ADDR_REGOFF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with an optional 10-bit scaled, signed immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 11-bit signed immediate (multiple of 16) offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 13-bit signed immediate (multiple of 16) offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 7), AARCH64_FIELD (24, 1)}, "an address with 7-bit signed immediate offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with 9-bit signed immediate offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (22, 1), AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with an optional 10-bit scaled, signed immediate offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 7), AARCH64_FIELD (24, 1)}, "an address with 11-bit signed immediate (multiple of 16) offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (10, 12)}, "an address with scaled, unsigned immediate offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with 13-bit signed immediate (multiple of 16) offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"}, - {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (12, 9), AARCH64_FIELD (11, 1)}, "an address with an optional 8-bit signed immediate offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"}, {AARCH64_OPND_CLASS_SYSTEM, "SYSREG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a system register"}, {AARCH64_OPND_CLASS_SYSTEM, "SYSREG128", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a 128-bit system register"}, @@ -149,232 +149,232 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_DSB_NXS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"}, {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"}, - {AARCH64_OPND_CLASS_SYSTEM, "RPRFMOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm2_12, FLD_imm3_0}, "a range prefetch operation specifier"}, + {AARCH64_OPND_CLASS_SYSTEM, "RPRFMOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (12, 2), AARCH64_FIELD (0, 3)}, "a range prefetch operation specifier"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_GCSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the GCSB option name DSYNC"}, {AARCH64_OPND_CLASS_SYSTEM, "BTI_TARGET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets r/j/c/jc"}, {AARCH64_OPND_CLASS_SYSTEM, "STSHH_POLICY", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an STSHH policy (keep/strm)"}, {AARCH64_OPND_CLASS_SYSTEM, "SHUH_PHINT", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an optional priority hint (ph)"}, - {AARCH64_OPND_CLASS_SYSTEM, "BRBOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_brbop}, "Branch Record Buffer operation operand"}, - {AARCH64_OPND_CLASS_INT_REG, "Rt_IN_SYS_ALIASES", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "Rt register with defaults for SYS aliases"}, - {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_LSE128_Rt}, "an integer register"}, - {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_LSE128_Rt2}, "an integer register"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 32"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 4*VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit signed offset, multiplied by VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 9-bit signed offset, multiplied by VL"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL4", (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_Rm}, "vector of address with a scalar register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 2"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 4"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an address with a 5-bit unsigned offset, multiplied by 8"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_SVE_Zm_16}, "an address with a vector register offset"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit unsigned arithmetic operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm9}, "a 9-bit signed arithmetic operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit floating-point immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 1.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.5 or 2.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot3}, "a 1-bit rotation specifier for complex arithmetic operations"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_pattern}, "an enumeration value such as POW2"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_prfop}, "an enumeration value such as PLDL1KEEP"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "an SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_5}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_10}, "an SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg4_16}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pm}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pt}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rm}, "an integer register or zero"}, - {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-left immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a 3-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm7}, "a 7-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm8}, "an 8-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5,FLD_imm3_10}, "an 8-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a 4-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vd}, "a SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vm}, "a SIMD register"}, - {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Vn}, "a SIMD register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off3}, "ZA0 tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_1,FLD_off2}, "1 bit ZA tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_2,FLD_ol}, "2 ZA tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3}, "3 ZA tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off2}, "ZA0 tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn,FLD_ol}, "1 bit ZA tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_off2}, "2 bit ZA tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3}, "3 bit ZA tile"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_ARRAY4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv}, "ZA tile to vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_5}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Za_16}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_5}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1_23, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h3, FLD_SVE_i3l2, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_imm3}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm5}, "a 5 bit indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2, FLD_CONST_0}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4, FLD_CONST_00}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_6_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_0, FLD_SME_Zn6_3, FLD_CONST_0}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0}, "an SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_6_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_0, FLD_SME_Zn6_3, FLD_CONST_0}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_17_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_INDEX_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_imm1_22}, "a list of SVE vector registers with index"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2, FLD_CONST_0}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4, FLD_CONST_00}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4, FLD_CONST_00}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zn7xN_UNTYPED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of untyped SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_1b}, "an SME ZA tile ZA0-ZA1"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_2b}, "an SME ZA tile ZA0-ZA3"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_3b}, "an SME ZA tile ZA0-ZA7"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pdx2, FLD_CONST_0}, "a list of SVE predicate registers"}, - {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "a list of SVE predicate registers"}, - {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_PNd3}, "an SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SVE_Pg3}, "an SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_8, FLD_CONST_01, FLD_SME_PNn3}, "an indexed SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_8, FLD_CONST_01, FLD_SME_PNn3}, "an indexed SVE predicate-as-counter register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off1x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm1_0}, "ZA array"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm2_0}, "ZA array"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm2_0}, "ZA array"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_5}, "ZA array"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"}, - {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm4_0}, "ZA array"}, - {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, - {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zk_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_4, FLD_CONST_1, FLD_SVE_i3l2, FLD_CONST_1, FLD_imm2_10}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm1_2, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_10, FLD_imm2_2, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm3_10, FLD_CONST_0, FLD_SME_Zm}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_16, FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_15, FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_16, FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_19", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_19, FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_14, FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_15, FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_14, FLD_SVE_Zn}, "an indexed SVE vector register"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register with option zero index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_1, FLD_SVE_Zn}, "an SVE vector register with optional one bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_2, FLD_SVE_Zn}, "an SVE vector register with optional two bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zn}, "an SVE vector register with optional three bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zd}, "an SVE vector register with option zero index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_1, FLD_SVE_Zd}, "an SVE vector register with optional one bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_2, FLD_SVE_Zd}, "an SVE vector register with optional two bit index"}, - {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zd}, "an SVE vector register with optional three bit index"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"}, + {AARCH64_OPND_CLASS_SYSTEM, "BRBOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "Branch Record Buffer operation operand"}, + {AARCH64_OPND_CLASS_INT_REG, "Rt_IN_SYS_ALIASES", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "Rt register with defaults for SYS aliases"}, + {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_INT_REG, "LSE128_Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 16"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 32"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by VL"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 2*VL"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 3*VL"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x4xVL", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 4-bit signed offset, multiplied by 4*VL"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S6xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit signed offset, multiplied by VL"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S9xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 9-bit signed offset, multiplied by VL"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset, multiplied by 2"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset, multiplied by 4"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 6-bit unsigned offset, multiplied by 8"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RM_LSL4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX", (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL4", (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "vector of address with a scalar register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_14", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW1_22", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_14", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW2_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_14", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (14, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_XTW3_22", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset, multiplied by 2"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset, multiplied by 4"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an address with a 5-bit unsigned offset, multiplied by 8"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_LSL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_SXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZZ_UXTW", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "an address with a vector register offset"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 9)}, "a 9-bit unsigned arithmetic operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_ASIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 9)}, "a 9-bit signed arithmetic operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_FPIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 8)}, "an 8-bit floating-point immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "either 0.5 or 1.0"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_HALF_TWO", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "either 0.5 or 2.0"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 1)}, "either 0.0 or 1.0"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 1)}, "a 1-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2)}, "a 2-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1)}, "a 1-bit rotation specifier for complex arithmetic operations"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (11, 6), AARCH64_FIELD (5, 6)}, "an inverted 13-bit logical immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (11, 6), AARCH64_FIELD (5, 6)}, "a 13-bit logical immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (11, 6), AARCH64_FIELD (5, 6)}, "a 13-bit logical move immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an enumeration value such as POW2"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PATTERN_SCALED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an enumeration value such as POW2"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an enumeration value such as PLDL1KEEP"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 3)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNg4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 4)}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pg4_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_Pt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SVE_PNt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_INT_REG, "SVE_Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer register or zero"}, + {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an integer register or SP"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (5, 5)}, "a shift-left immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "a shift-left immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (19, 2), AARCH64_FIELD (16, 3)}, "a shift-left immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (5, 5)}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (19, 2), AARCH64_FIELD (16, 3)}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a 5-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a 5-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 6)}, "a 6-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 8)}, "an 8-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 3)}, "a 3-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 7)}, "a 7-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 8)}, "an 8-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM8_53", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5), AARCH64_FIELD (10, 3)}, "an 8-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "a 4-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_VZn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD register"}, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a SIMD register"}, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD register"}, + {AARCH64_OPND_CLASS_SIMD_REG, "SVE_Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a SIMD register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "ZA0 tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (7, 1), AARCH64_FIELD (5, 2)}, "1 bit ZA tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (6, 2), AARCH64_FIELD (5, 1)}, "2 ZA tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "3 ZA tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsb_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 2)}, "ZA0 tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsh_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (6, 1), AARCH64_FIELD (5, 1)}, "1 bit ZA tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrss_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 2)}, "2 bit ZA tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_vrsd_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "3 bit ZA tile"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_ARRAY4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2)}, "ZA tile to vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Za_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm1_23_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (23, 1), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm2_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (11, 1), AARCH64_FIELD (16, 3)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_12_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (12, 1), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_19_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (16, 3)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_10_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (10, 2), AARCH64_FIELD (16, 3)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (20, 1), AARCH64_FIELD (11, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_5_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (16, 5)}, "a 5 bit indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (1, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (2, 3), AARCH64_FIELD_CONST (0, 2)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 4)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_6_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (6, 3), AARCH64_FIELD_CONST (0, 1)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (17, 3), AARCH64_FIELD_CONST (0, 1)}, "an SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_6_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (6, 3), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_17_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (17, 3), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_INDEX_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 1)}, "a list of SVE vector registers with index"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (18, 3), AARCH64_FIELD_CONST (0, 2)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (6, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (6, 4), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (7, 3), AARCH64_FIELD_CONST (0, 2)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zn7xN_UNTYPED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (7, 3)}, "a list of untyped SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (4, 1), AARCH64_FIELD (0, 3)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (4, 1), AARCH64_FIELD (0, 2)}, "a list of SVE vector registers"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 1)}, "an SME ZA tile ZA0-ZA1"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_2b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 2)}, "an SME ZA tile ZA0-ZA3"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_3b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 3)}, "an SME ZA tile ZA0-ZA7"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 1), AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 4)}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 1), AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 4)}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 3)}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (1, 3), AARCH64_FIELD_CONST (0, 1)}, "a list of SVE predicate registers"}, + {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 4)}, "a list of SVE predicate registers"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 3)}, "an SVE predicate register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (0, 3)}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (10, 3)}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 4)}, "an SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 1), AARCH64_FIELD_CONST (1, 2), AARCH64_FIELD (5, 3)}, "an indexed SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 2), AARCH64_FIELD_CONST (1, 2), AARCH64_FIELD (5, 3)}, "an indexed SVE predicate-as-counter register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 8)}, "a list of 64-bit ZA element tiles"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (24, 1), AARCH64_FIELD (15, 1), AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 4)}, "an SME horizontal or vertical vector access register"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off1x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 1)}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 2)}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off2x4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 2)}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 3)}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_5", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (5, 3)}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3x2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 3)}, "ZA array"}, + {AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 2), AARCH64_FIELD (0, 4)}, "ZA array"}, + {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (0, 4)}, "memory offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (8, 4)}, "streaming mode"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 2), AARCH64_FIELD (5, 4), AARCH64_FIELD (23, 1), AARCH64_FIELD (22, 1), AARCH64_FIELD (18, 3)}, "Source scalable predicate register with index "}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 3)}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 4)}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 2), AARCH64_FIELD (16, 5)}, "a shift-right immediate operand"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zk_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (4, 2), AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (12, 1), AARCH64_FIELD_CONST (1, 1), AARCH64_FIELD (10, 2)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX2_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1), AARCH64_FIELD (3, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1), AARCH64_FIELD (1, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (2, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (3, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX3_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (10, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (1, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 2), AARCH64_FIELD (2, 2), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (10, 2), AARCH64_FIELD (3, 1), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_INDEX4_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 1), AARCH64_FIELD (10, 3), AARCH64_FIELD_CONST (0, 1), AARCH64_FIELD (16, 4)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 1), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 2), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 2), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_19", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (19, 2), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 3), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (15, 3), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (14, 4), AARCH64_FIELD (5, 5)}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an SVE vector register with option zero index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (5, 5)}, "an SVE vector register with optional one bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 2), AARCH64_FIELD (5, 5)}, "an SVE vector register with optional two bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (17, 2), AARCH64_FIELD (5, 5)}, "an SVE vector register with optional three bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd0_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "an SVE vector register with option zero index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd1_17_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 1), AARCH64_FIELD (0, 5)}, "an SVE vector register with optional one bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd2_18_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (17, 2), AARCH64_FIELD (0, 5)}, "an SVE vector register with optional two bit index"}, + {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zd3_22_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (22, 1), AARCH64_FIELD (17, 2), AARCH64_FIELD (0, 5)}, "an SVE vector register with optional three bit index"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 1)}, "VLx2 or VLx4"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (13, 1)}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 3)}, "a ZT0 index"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 3)}, "a ZT0 index"}, {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"}, - {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, - {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"}, - {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"}, - {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"}, - {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with post-incrementing by ammount of loaded bytes"}, - {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_opc2}, "an address with pre-incrementing with write-back by ammount of stored bytes"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 16)}, "a 16-bit unsigned immediate for TME tcancel"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (0, 5)}, "a register destination address with writeback"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (16, 5)}, "a register source address with writeback"}, + {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5)}, "an integer register with writeback"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 8)}, "an 8-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (10, 8)}, "an 8-bit unsigned immediate"}, + {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 4)}, "an address with post-incrementing by ammount of loaded bytes"}, + {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OPT_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (12, 4)}, "an address with pre-incrementing with write-back by ammount of stored bytes"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"}, {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with pre-incrementing with write-back by ammount of stored bytes"}, - {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9}, "an address with an optional 8-bit signed immediate offset"}, + {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {AARCH64_FIELD (5, 5), AARCH64_FIELD (12, 9)}, "an address with an optional 8-bit signed immediate offset"}, {AARCH64_OPND_CLASS_SYSTEM, "GIC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, {AARCH64_OPND_CLASS_SYSTEM, "GICR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"}, {AARCH64_OPND_CLASS_SYSTEM, "GSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller Synchronization Barrier"}, From patchwork Wed May 20 12:09:22 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alice Carlotti X-Patchwork-Id: 135332 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 215E04BB3BDA for ; Wed, 20 May 2026 12:11:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 215E04BB3BDA Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=OmFvtdAm; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=OmFvtdAm X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from PA4PR04CU001.outbound.protection.outlook.com (mail-francecentralazlp170130007.outbound.protection.outlook.com [IPv6:2a01:111:f403:c20a::7]) by sourceware.org (Postfix) with ESMTPS id 7F4584BB58F1 for ; Wed, 20 May 2026 12:10:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7F4584BB58F1 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7F4584BB58F1 Authentication-Results: sourceware.org; arc=fail smtp.remote-ip=2a01:111:f403:c20a::7 DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7F4584BB58F1 ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=fail; b=foqsq/j4IEgviKadbbJBFq2vo/+GwMBmUOmsnbsX3VOyfkwfyTeL6+TlYEgjrFQ/1ex5sXxOPRfCGILa9bv4gHbBecakeS5mpv0i3khCXeqEGUN+RTocF3Bb9HYo9XjPNzs3H1wbx47WXKbDSqxUaEqkIvbpulEFLqiBFj4K9XGmDNM9gr4+0Wzqhyi4RloqrRsTdcHBi7jYVt2POdh2ioyZgY29jKvFiRcWFrkRn4W+ia40ko78OJ2JtGQcx7SkL84cYBT3RMT0m3q1JhLAecL9i5yim+21Qb1rDeP3NEzhpl1LHGgxT3YD8JnLL2WztsgkFLEGAzHY52Bsol0rAA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YkhKBPsNiOB4t8Wnsx/+CvlgT5ovBxZzvOQlRGIFQbU=; b=MUnHefQ5dD0Xxdsv/Wf55rYAWvqK7r39UZlULIGnHYfPS97hYDYoUBXhCtzrxB9DxWgCWN+S125VBORFks+3nzrfEXyXhEpuT9RWXelwtgB1p3eAMSJh10fJker/WxTvHm860JVjhfTDl6Vdq79GsvD0etOPuAFLtSnVCVBWsXjyHEgOIWysJEF+7VllTdQAwC7TyeriA76aADK4byx/lFcGyFC0umh7FfvYO9Tji4zbh+PJ4Wvypx4Wo3NGgLLcutcgM5u7HlcVa/wkPAVk0/fwqqpL7q2ae8FKfLgcyJ3eTArzRJu5yGy9KCZuyY25G+MBc8m2LaBHRoxj3+r+kg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=fail (48) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YkhKBPsNiOB4t8Wnsx/+CvlgT5ovBxZzvOQlRGIFQbU=; b=OmFvtdAm3yq/p8+ZVW1LzuSmuY9Sw3UM9X5lz/3Wy6tNO1FpLXwkP2ZAQAAszcRMJDNzhteqOKnwZDpJ7wrGe48HnlBu+05x/xRGmfIa/glVgqsx5/FC07sXzhjXOxaT1pbz2RtmTduh5RelX+PuDrdhMibC1Bo6m3WCAH7n0Yc= Received: from DU2P250CA0017.EURP250.PROD.OUTLOOK.COM (2603:10a6:10:231::22) by GVXPR08MB7726.eurprd08.prod.outlook.com (2603:10a6:150:6c::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:10:27 +0000 Received: from DB5PEPF00014B89.eurprd02.prod.outlook.com (2603:10a6:10:231:cafe::bc) by DU2P250CA0017.outlook.office365.com (2603:10a6:10:231::22) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Wed, 20 May 2026 12:10:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by DB5PEPF00014B89.mail.protection.outlook.com (10.167.8.197) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Wed, 20 May 2026 12:10:27 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Hfr/evgWEuTGqIxraOSMkweUv7HSkcQ6Nzww2WZsn0nCozbBDxklxePGqkOhMmEmhWQXjuXqR300/rQpv4Qihnlpn1UwSBc948qz6JtYMJYkYHHwhF0K83Zi0tUvuXP5nVyjahdh8zjlOxqFscchVSBQMKeIsN25UPCGCSCcXIuCIs13DWRzoRZc89MwEJ/Vx3Plvz8RIN7SoogMBSMBrnj+p3U3VdAuvN4lW2TeYYB31pJXSdPV963ulY/HVEgNk7/pQrAqjp9d4C4etbld2XcC7qZxQJfO2gfkCfjMqzFp4FBPkE7568YRThVICeQkhbsXMZ2xC7Enjbtv7WKWoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=YkhKBPsNiOB4t8Wnsx/+CvlgT5ovBxZzvOQlRGIFQbU=; b=Xm76UFvNY0uMUTgDlYfvNgaOHpAY+izM66K2VOiCct9kAnedTvcEUXOpMBkY4t1q86WLiuQw+EOf/Qffj0Ws321XSuuUpgzDhbiAXFVW7XCAdJBR2MxWE4W+JN3Yparqr0+nWVTVGnLOB5cQrMKemX4mS9zCaowSD6pmIrV7OU0dQLZFCwj2d74aJ1fiLZIJY9pwrh8f2oHVRJDQ+lU+skjXcGOzkU7SSmqeS9XpehEhimcfjRV2RcU/kiZzIikbVbqpHQyw7gok3tWuz+Fb3JD0gUxasXUV7oAF+CvE1N/ESplwkWN2WmBeJgLWEMU49GLYBN2zRF9tFxwueXNnSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YkhKBPsNiOB4t8Wnsx/+CvlgT5ovBxZzvOQlRGIFQbU=; b=OmFvtdAm3yq/p8+ZVW1LzuSmuY9Sw3UM9X5lz/3Wy6tNO1FpLXwkP2ZAQAAszcRMJDNzhteqOKnwZDpJ7wrGe48HnlBu+05x/xRGmfIa/glVgqsx5/FC07sXzhjXOxaT1pbz2RtmTduh5RelX+PuDrdhMibC1Bo6m3WCAH7n0Yc= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) by DBBPR08MB6300.eurprd08.prod.outlook.com (2603:10a6:10:209::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:09:24 +0000 Received: from DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24]) by DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24%5]) with mapi id 15.21.0048.013; Wed, 20 May 2026 12:09:24 +0000 Date: Wed, 20 May 2026 13:09:22 +0100 From: Alice Carlotti To: binutils@sourceware.org Cc: Richard Earnshaw Subject: [PATCH 3/5] aarch64: Inline all FLD_* uses in aarch64-tbl.h Message-ID: <8a88091d-e001-e910-3960-4e65cabbb8eb@e124511.cambridge.arm.com> References: Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: LO4P123CA0435.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1a9::8) To DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DU0PR08MB8255:EE_|DBBPR08MB6300:EE_|DB5PEPF00014B89:EE_|GVXPR08MB7726:EE_ X-MS-Office365-Filtering-Correlation-Id: ca1ccee7-5399-49cd-134b-08deb668c79e x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|366016|376014|22082099003|18002099003|56012099003|3023799007|11063799006; X-Microsoft-Antispam-Message-Info-Original: bzUvKrMpjvBlZfqIMwV12MiUOUSZmo6KCIlPWuIFuIFCX5kUi8KUe4raQo3nRRQ1bhCv3svuHE+I/kwElN9pNCQ6852yIgKLJiE5wLUlTVvZcR3M/h3mgpqRCE/bdfWgQOlAc57kKJe/iYXJfL7oRvShMlKVTMUjXKrZC/T+LcMw3SuHGKT+blxdO2CnDuVSUufjMdf3UemgwiaPatF6JdhVEhPiElGZiz/mvjUFtuHdPQPIGxJATGUJrWX5pFnUGob0n8/LbUkWQLVg5O9fic8sWUO5kpekq7AP9OsBjscWlMR0xm1mp2EXKYmxmCaM+mb4N2AEtu+qiQw5Xb7+H6bXxiffTwWCLFqi6FstE7ASBcGI3/lI4Vf7OByUA3wEfbm6rVcxW8i/XQVWybzKMcg4MB7+JH6JQms6/X5wBAOw+9q3QxTT2Rh8jnDPomv42kNJ4BnikNnbTrhMG5h0uzWBrGzFyFFTarGW7104na/JGxJKAZmQQt0ziSm6EMCpCsP3eSCo8NdcDJynyhEUNt94S/02uU548pmbbGm1TRDH1IqRqQcmaUJqg1EcDlSYWcs7dAzXm20RWNASGxqj0kmwZiatXFnwD/49MnWFJ0mcqTuO8zPLXmzJE7rrLjQIsQ18ev+Lpdqx9eETQUFvpzuCuuAvfHA4w3sidQfmIIjb6psM88IF90SQpOYeEBQr X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DU0PR08MB8255.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(366016)(376014)(22082099003)(18002099003)(56012099003)(3023799007)(11063799006); DIR:OUT; SFP:1101; X-Exchange-RoutingPolicyChecked: NK/fOenE8j3wcri0Mm0XeU3yrcjy9o9orPt7OX//WREgv1WbdVBOG5Q0bqL6Rk3BBKocZARkwaGUOiHYDUT015BpYvLSaRDrBsiNYhCWa/cTEtHbqEloXFWBzp2ouBP/sckp3O68OY9QoA34XvbH0H1dE0iO7jurjQ8qL0xpSAXMpsFPPnV9tuwDfLum43JJhbSAtuiubl4+nUHxC7g7WFQ8zdmTOoy7gAYXODZ+pHQUgkby9dHKlzbkEuwyeZwkWjIKudSO3wZVCLVC4i47QqPPJdXPYYFY8xTVFIm0lYkQQTeS+bUTKWeFzZnFpmMwdwQflOKtBGyXER8ElLGK6w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6300 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DB5PEPF00014B89.eurprd02.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 06c6a8fb-ade8-4a4b-b55f-08deb668a204 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|14060799003|376014|36860700016|35042699022|11063799006|18002099003|56012099003|22082099003|3023799007; X-Microsoft-Antispam-Message-Info: TAf6nUc0fMNTrACWSeXctti4l4hzVQRDgd0ZXtjW3HlPshNy/dWFar0LD/DuO8VJyN70S7YpZ/PxTXC7+DPeaZ+mlN0ik0WI/MZumg4U3ldZgDJL5LVnWRgkGpNgm8WrsGd/AsoMb+iATBiZN0Xrzc+RKYSwllPAzkk5IrZU0E0l5BrpTj9XN7iN1jFFIdw6VgTnYasT6bMbVEAixBdWb3sXLQSLqJ0RLbwKyrWb6AVeL5jtsKcjRdsGPUi6gQzAs4dmFjuQMbg6qwwg87p+13CosBd2f6EiaOVWP2dVUOenv1cl5r7Z1MEdiTlQbqQxzmbNX9UU2DLtTYTo9EW1UZNQC6XAmlDrVCQVMde61s9TJrQnjagrtn3HCHIS0gnbwIhSRUd/rZEnCocG95rSTnxXhyYp/lRHLnGekbwrE7jc9S/1POusv7WXpe6AwbXRgYyUKB25/Z0NY3hCL+a9VH6gC9KHOaOwO2DkP+ylQzp9r/PXiH79bSnarNUv5D0Cx3yNbxRUhIaMK01R8qlVEWo9yfiZlqty0K0NMejV74Be7/M0BK78ii+Y61elOsPE23nO5x4xn1X4HocUOu+CbewIX7/pZ96/cUtHjq1lO38vf/TAC1npuKMWCsbXQF5CWZubJnj79Bdc+c+lZ7V8op7zOwYHsE9XEGE/fUA2BfdqD7F4Fr6eef6MXQQK6L33c6inA8AGAotyUi/uHPhzY7RoKCTOT/YNxgBvcZcwJso= X-Forefront-Antispam-Report: CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(14060799003)(376014)(36860700016)(35042699022)(11063799006)(18002099003)(56012099003)(22082099003)(3023799007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MFoPEeUKEtPc9wmeYK3XbTWopm4dL8HexNz39QE+6FjyCm6/MroPpLG4lLAgc+oYtq7WjeReYbOS8IK0Ebyuj5hH/kE5f4vAZ3icYe/cgCyE+9iwGqSzaUCymYd5tZ7E+APviYFFtZQWLYqBaBYhUvf49YfIA7f9H79gjw3cy1QRW92qt8Nmf1wnKRh6ETEh6vmlV4CqfnX1y7e8vVuAFOLGO3P2t8nTY1nKFX0OWjgR81X2GlswTBOkTJjewkXODwGxObfDsykOYUIaUpO3mSYVzGw4ve7byCNLbJiV+Y7B+7upiIUwKab5V0WyIHPhpP9951QHK5KhTPoJn7L1fIbDiOg1bm/BlXR1HvhcAExUuPK9sSpWfo0TMKhdBhDgBb73cJYbBNQtVzQi9WAvkSIZ/DdsX9SShpcP1BWr2pRh0tMq2zKKYMUoy/tItDc0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 12:10:27.4565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ca1ccee7-5399-49cd-134b-08deb668c79e X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B89.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVXPR08MB7726 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, LOCAL_AUTHENTICATION_FAIL_ARC, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Inline all non-constant field definitions into operand field lists, and remove the resulting unused FLD_* macros. For brevity, define FLD as an alias for AARCH64_FLD in aarch64-gen.c. diff --git a/opcodes/aarch64-gen.c b/opcodes/aarch64-gen.c index 4bbd71fffff8ec5a86a5785dc051f94717635131..3dd3e86f86007451e0a6fffa8f202034ef468ffe 100644 --- a/opcodes/aarch64-gen.c +++ b/opcodes/aarch64-gen.c @@ -994,6 +994,8 @@ typedef struct operand operand; #undef F #endif +#define FLD AARCH64_FIELD + /* The parentheses used when calling this macro ensure that the list of fields appears as a single argument to the X and Y macros. */ #define F(...) {__VA_ARGS__} diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index 3a7085a3def104ea88817391147b6eef831825b5..a0553f8fd940c1a0e994bc4a0c8dd945fdb96494 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -66,190 +66,67 @@ typedef struct aarch64_field aarch64_field; /* Instruction fields. These defines are included to reduce the initial diff size, but the indirection should eventually be eliminated. */ -#define FLD_NIL AARCH64_FIELD( 0, 0) #define FLD_CRm AARCH64_FIELD( 8, 4) #define FLD_CRm_dsb_nxs AARCH64_FIELD(10, 2) #define FLD_CRn AARCH64_FIELD(12, 4) -#define FLD_CSSC_imm8 AARCH64_FIELD(10, 8) #define FLD_H AARCH64_FIELD(11, 1) #define FLD_L AARCH64_FIELD(21, 1) -#define FLD_LSE128_Rt AARCH64_FIELD( 0, 5) -#define FLD_LSE128_Rt2 AARCH64_FIELD(16, 5) #define FLD_M AARCH64_FIELD(20, 1) #define FLD_N AARCH64_FIELD(22, 1) #define FLD_Q AARCH64_FIELD(30, 1) -#define FLD_Ra AARCH64_FIELD(10, 5) -#define FLD_Rd AARCH64_FIELD( 0, 5) #define FLD_Rm AARCH64_FIELD(16, 5) #define FLD_Rn AARCH64_FIELD( 5, 5) -#define FLD_Rs AARCH64_FIELD(16, 5) #define FLD_Rt AARCH64_FIELD( 0, 5) -#define FLD_Rt2 AARCH64_FIELD(10, 5) #define FLD_S AARCH64_FIELD(12, 1) #define FLD_SM3_imm2 AARCH64_FIELD(12, 2) -#define FLD_SME_Pdx2 AARCH64_FIELD( 1, 3) -#define FLD_SME_Pm AARCH64_FIELD(13, 3) -#define FLD_SME_PNd3 AARCH64_FIELD( 0, 3) -#define FLD_SME_PNn3 AARCH64_FIELD( 5, 3) #define FLD_SME_Q AARCH64_FIELD(16, 1) -#define FLD_SME_Rm AARCH64_FIELD(16, 2) -#define FLD_SME_Rv AARCH64_FIELD(13, 2) -#define FLD_SME_V AARCH64_FIELD(15, 1) -#define FLD_SME_VL_10 AARCH64_FIELD(10, 1) -#define FLD_SME_VL_13 AARCH64_FIELD(13, 1) -#define FLD_SME_ZAda_1b AARCH64_FIELD( 0, 1) -#define FLD_SME_ZAda_2b AARCH64_FIELD( 0, 2) -#define FLD_SME_ZAda_3b AARCH64_FIELD( 0, 3) -#define FLD_SME_Zdn2 AARCH64_FIELD( 1, 4) -#define FLD_SME_Zdn4 AARCH64_FIELD( 2, 3) -#define FLD_SME_Zm AARCH64_FIELD(16, 4) -#define FLD_SME_Zm17_3 AARCH64_FIELD(17, 3) -#define FLD_SME_Zm2 AARCH64_FIELD(17, 4) -#define FLD_SME_Zm4 AARCH64_FIELD(18, 3) -#define FLD_SME_Zn2 AARCH64_FIELD( 6, 4) -#define FLD_SME_Zn4 AARCH64_FIELD( 7, 3) -#define FLD_SME_Zn6_3 AARCH64_FIELD( 6, 3) -#define FLD_SME_ZtT AARCH64_FIELD( 4, 1) -#define FLD_SME_Zt3 AARCH64_FIELD( 0, 3) -#define FLD_SME_Zt2 AARCH64_FIELD( 0, 2) -#define FLD_SME_i1 AARCH64_FIELD(23, 1) #define FLD_SME_size_12 AARCH64_FIELD(12, 2) #define FLD_SME_size_22 AARCH64_FIELD(22, 2) #define FLD_SME_sz_23 AARCH64_FIELD(23, 1) #define FLD_SME_tszh AARCH64_FIELD(22, 1) #define FLD_SME_tszl AARCH64_FIELD(18, 3) -#define FLD_SME_zero_mask AARCH64_FIELD(0, 8) #define FLD_SVE_M_4 AARCH64_FIELD( 4, 1) #define FLD_SVE_M_14 AARCH64_FIELD(14, 1) #define FLD_SVE_M_16 AARCH64_FIELD(16, 1) -#define FLD_SVE_N AARCH64_FIELD(17, 1) #define FLD_SVE_Pd AARCH64_FIELD( 0, 4) -#define FLD_SVE_Pg3 AARCH64_FIELD(10, 3) -#define FLD_SVE_Pg4_5 AARCH64_FIELD( 5, 4) #define FLD_SVE_Pg4_10 AARCH64_FIELD(10, 4) -#define FLD_SVE_Pg4_16 AARCH64_FIELD(16, 4) #define FLD_SVE_Pm AARCH64_FIELD(16, 4) #define FLD_SVE_Pn AARCH64_FIELD( 5, 4) -#define FLD_SVE_Pt AARCH64_FIELD( 0, 4) -#define FLD_SVE_Rm AARCH64_FIELD( 5, 5) -#define FLD_SVE_Rn AARCH64_FIELD(16, 5) -#define FLD_SVE_Vd AARCH64_FIELD( 0, 5) -#define FLD_SVE_Vm AARCH64_FIELD( 5, 5) -#define FLD_SVE_Vn AARCH64_FIELD( 5, 5) -#define FLD_SVE_Za_5 AARCH64_FIELD( 5, 5) -#define FLD_SVE_Za_16 AARCH64_FIELD(16, 5) #define FLD_SVE_Zd AARCH64_FIELD( 0, 5) -#define FLD_SVE_Zm_5 AARCH64_FIELD( 5, 5) #define FLD_SVE_Zm_16 AARCH64_FIELD(16, 5) #define FLD_SVE_Zn AARCH64_FIELD( 5, 5) -#define FLD_SVE_Zt AARCH64_FIELD( 0, 5) -#define FLD_SVE_i1 AARCH64_FIELD( 5, 1) -#define FLD_SVE_i1_23 AARCH64_FIELD(23, 1) -#define FLD_SVE_i2 AARCH64_FIELD(22, 2) -#define FLD_SVE_i2h AARCH64_FIELD(20, 1) -#define FLD_SVE_i3h AARCH64_FIELD(22, 1) -#define FLD_SVE_i3h2 AARCH64_FIELD(19, 2) -#define FLD_SVE_i3h3 AARCH64_FIELD(22, 2) -#define FLD_SVE_i3l AARCH64_FIELD(11, 1) -#define FLD_SVE_i3l2 AARCH64_FIELD(12, 1) -#define FLD_SVE_i4l2 AARCH64_FIELD(10, 2) -#define FLD_SVE_imm3 AARCH64_FIELD(16, 3) #define FLD_SVE_imm4 AARCH64_FIELD(16, 4) -#define FLD_SVE_imm5 AARCH64_FIELD( 5, 5) -#define FLD_SVE_imm5b AARCH64_FIELD(16, 5) #define FLD_SVE_imm6 AARCH64_FIELD(16, 6) -#define FLD_SVE_imm7 AARCH64_FIELD(14, 7) -#define FLD_SVE_imm8 AARCH64_FIELD( 5, 8) -#define FLD_SVE_imm9 AARCH64_FIELD( 5, 9) -#define FLD_SVE_immr AARCH64_FIELD(11, 6) -#define FLD_SVE_imms AARCH64_FIELD( 5, 6) #define FLD_SVE_msz AARCH64_FIELD(10, 2) -#define FLD_SVE_pattern AARCH64_FIELD( 5, 5) -#define FLD_SVE_prfop AARCH64_FIELD( 0, 4) -#define FLD_SVE_rot1 AARCH64_FIELD(16, 1) -#define FLD_SVE_rot2 AARCH64_FIELD(10, 2) -#define FLD_SVE_rot3 AARCH64_FIELD(10, 1) #define FLD_SVE_size AARCH64_FIELD(17, 2) #define FLD_SVE_sz AARCH64_FIELD(22, 1) #define FLD_SVE_sz2 AARCH64_FIELD(30, 1) #define FLD_SVE_sz3 AARCH64_FIELD(17, 1) #define FLD_SVE_sz4 AARCH64_FIELD(14, 1) -#define FLD_SVE_tsz AARCH64_FIELD(16, 4) #define FLD_SVE_tszh AARCH64_FIELD(22, 2) #define FLD_SVE_tszl_8 AARCH64_FIELD( 8, 2) #define FLD_SVE_tszl_19 AARCH64_FIELD(19, 2) -#define FLD_SVE_xs_14 AARCH64_FIELD(14, 1) -#define FLD_SVE_xs_22 AARCH64_FIELD(22, 1) -#define FLD_S_imm10 AARCH64_FIELD(22, 1) #define FLD_abc AARCH64_FIELD(16, 3) #define FLD_asisdlso_opcode AARCH64_FIELD(13, 3) -#define FLD_b40 AARCH64_FIELD(19, 5) -#define FLD_b5 AARCH64_FIELD(31, 1) #define FLD_cmode AARCH64_FIELD(12, 4) #define FLD_cond AARCH64_FIELD(12, 4) #define FLD_cond2 AARCH64_FIELD( 0, 4) #define FLD_defgh AARCH64_FIELD( 5, 5) #define FLD_hw AARCH64_FIELD(21, 2) -#define FLD_imm1_0 AARCH64_FIELD( 0, 1) -#define FLD_imm1_2 AARCH64_FIELD( 2, 1) -#define FLD_imm1_3 AARCH64_FIELD( 3, 1) -#define FLD_imm1_8 AARCH64_FIELD( 8, 1) -#define FLD_imm1_10 AARCH64_FIELD(10, 1) -#define FLD_imm1_14 AARCH64_FIELD(14, 1) -#define FLD_imm1_15 AARCH64_FIELD(15, 1) -#define FLD_imm1_16 AARCH64_FIELD(16, 1) #define FLD_imm1_22 AARCH64_FIELD(22, 1) -#define FLD_imm2_0 AARCH64_FIELD( 0, 2) -#define FLD_imm2_1 AARCH64_FIELD( 1, 2) -#define FLD_imm2_2 AARCH64_FIELD( 2, 2) -#define FLD_imm2_4 AARCH64_FIELD( 4, 2) -#define FLD_imm2_8 AARCH64_FIELD( 8, 2) -#define FLD_imm2_10 AARCH64_FIELD(10, 2) -#define FLD_imm2_12 AARCH64_FIELD(12, 2) -#define FLD_imm2_13 AARCH64_FIELD(13, 2) -#define FLD_imm2_15 AARCH64_FIELD(15, 2) -#define FLD_imm2_16 AARCH64_FIELD(16, 2) -#define FLD_imm2_19 AARCH64_FIELD(19, 2) -#define FLD_imm3_0 AARCH64_FIELD( 0, 3) #define FLD_imm3_5 AARCH64_FIELD( 5, 3) #define FLD_imm3_10 AARCH64_FIELD(10, 3) -#define FLD_imm3_12 AARCH64_FIELD(12, 3) -#define FLD_imm3_14 AARCH64_FIELD(14, 3) -#define FLD_imm3_15 AARCH64_FIELD(15, 3) #define FLD_imm3_19 AARCH64_FIELD(19, 3) -#define FLD_imm4_0 AARCH64_FIELD( 0, 4) #define FLD_imm4_5 AARCH64_FIELD( 5, 4) -#define FLD_imm4_10 AARCH64_FIELD(10, 4) #define FLD_imm4_11 AARCH64_FIELD(11, 4) -#define FLD_imm4_14 AARCH64_FIELD(14, 4) #define FLD_imm5 AARCH64_FIELD(16, 5) #define FLD_imm6_10 AARCH64_FIELD(10, 6) -#define FLD_imm6_15 AARCH64_FIELD(15, 6) -#define FLD_imm7 AARCH64_FIELD(15, 7) -#define FLD_imm8 AARCH64_FIELD(13, 8) -#define FLD_imm9 AARCH64_FIELD(12, 9) -#define FLD_imm9_5 AARCH64_FIELD( 5, 9) #define FLD_imm12 AARCH64_FIELD(10, 12) -#define FLD_imm14 AARCH64_FIELD( 5, 14) -#define FLD_imm16_0 AARCH64_FIELD( 0, 16) -#define FLD_imm16_5 AARCH64_FIELD( 5, 16) -#define FLD_imm17_1 AARCH64_FIELD(17, 1) -#define FLD_imm17_2 AARCH64_FIELD(17, 2) -#define FLD_imm19 AARCH64_FIELD( 5, 19) -#define FLD_imm26 AARCH64_FIELD( 0, 26) #define FLD_immb AARCH64_FIELD(16, 3) #define FLD_immh AARCH64_FIELD(19, 4) -#define FLD_immhi AARCH64_FIELD( 5, 19) -#define FLD_immlo AARCH64_FIELD(29, 2) -#define FLD_immr AARCH64_FIELD(16, 6) -#define FLD_imms AARCH64_FIELD(10, 6) -#define FLD_index AARCH64_FIELD(11, 1) -#define FLD_index2 AARCH64_FIELD(24, 1) #define FLD_ldst_size AARCH64_FIELD(30, 2) #define FLD_len AARCH64_FIELD(13, 2) #define FLD_lse_sz AARCH64_FIELD(30, 1) -#define FLD_nzcv AARCH64_FIELD( 0, 4) -#define FLD_op AARCH64_FIELD(29, 1) #define FLD_op0 AARCH64_FIELD(19, 2) #define FLD_op1 AARCH64_FIELD(16, 3) #define FLD_op2 AARCH64_FIELD( 5, 3) @@ -257,9 +134,6 @@ typedef struct aarch64_field aarch64_field; #define FLD_opc1 AARCH64_FIELD(23, 1) #define FLD_opcode AARCH64_FIELD(12, 4) #define FLD_option AARCH64_FIELD(13, 3) -#define FLD_rotate1 AARCH64_FIELD(11, 2) -#define FLD_rotate2 AARCH64_FIELD(13, 2) -#define FLD_rotate3 AARCH64_FIELD(12, 1) #define FLD_scale AARCH64_FIELD(10, 6) #define FLD_sf AARCH64_FIELD(31, 1) #define FLD_shift AARCH64_FIELD(22, 2) @@ -267,16 +141,10 @@ typedef struct aarch64_field aarch64_field; #define FLD_sz AARCH64_FIELD(22, 1) #define FLD_type AARCH64_FIELD(22, 2) #define FLD_vldst_size AARCH64_FIELD(10, 2) -#define FLD_off3 AARCH64_FIELD( 5, 3) #define FLD_off2 AARCH64_FIELD( 5, 2) -#define FLD_ZAn_1 AARCH64_FIELD( 7, 1) #define FLD_ol AARCH64_FIELD( 5, 1) -#define FLD_ZAn_2 AARCH64_FIELD( 6, 2) -#define FLD_ZAn_3 AARCH64_FIELD( 5, 3) -#define FLD_ZAn AARCH64_FIELD( 6, 1) #define FLD_opc2 AARCH64_FIELD(12, 4) #define FLD_rcpc3_size AARCH64_FIELD(30, 2) -#define FLD_brbop AARCH64_FIELD( 5, 1) #define FLD_ZA8_1 AARCH64_FIELD( 8, 1) #define FLD_ZA7_2 AARCH64_FIELD( 7, 2) #define FLD_ZA6_3 AARCH64_FIELD( 6, 3) diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 518109ecfd6013fb3dd6e153a9e91a1ee777b476..0a30e720d9dee56fd090c35cc70a09db7f1e7b4b 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -8005,24 +8005,24 @@ const struct aarch64_opcode aarch64_opcode_table[] = listed separately. */ #define AARCH64_OPERANDS \ - Y(INT_REG, regno, "Rd", 0, F(FLD_Rd), "an integer register") \ - Y(INT_REG, regno, "Rn", 0, F(FLD_Rn), "an integer register") \ - Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \ - Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \ - Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \ + Y(INT_REG, regno, "Rd", 0, F(FLD(0, 5)), "an integer register") \ + Y(INT_REG, regno, "Rn", 0, F(FLD(5, 5)), "an integer register") \ + Y(INT_REG, regno, "Rm", 0, F(FLD(16, 5)), "an integer register") \ + Y(INT_REG, regno, "Rt", 0, F(FLD(0, 5)), "an integer register") \ + Y(INT_REG, regno, "Rt2", 0, F(FLD(10, 5)), "an integer register") \ Y(INT_REG, none, "X16", 0, F(), "X16") \ - Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register") \ - Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \ + Y(INT_REG, regno, "Rt_LS64", 0, F(FLD(0, 5)), "an integer register") \ + Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD(0, 5)), \ "an integer or stack pointer register") \ - Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \ - Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \ - X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \ + Y(INT_REG, regno, "Rs", 0, F(FLD(16, 5)), "an integer register") \ + Y(INT_REG, regno, "Ra", 0, F(FLD(10, 5)), "an integer register") \ + X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD(0, 5)), \ "an integer register") \ - Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD_Rd), \ + Y(INT_REG, regno, "Rd_SP", OPD_F_MAYBE_SP, F(FLD(0, 5)), \ "an integer or stack pointer register") \ - Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD_Rn), \ + Y(INT_REG, regno, "Rn_SP", OPD_F_MAYBE_SP, F(FLD(5, 5)), \ "an integer or stack pointer register") \ - Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD_Rm), \ + Y(INT_REG, regno, "Rm_SP", OPD_F_MAYBE_SP, F(FLD(16, 5)), \ "an integer or stack pointer register") \ X(INT_REG, 0, ext_regno_pair, "PAIRREG", 0, F(), \ "the second reg of a pair") \ @@ -8034,59 +8034,59 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an integer register with optional shift") \ Y(MODIFIED_REG, reg_lsl_shifted, "Rm_LSL", 0, F(), \ "an integer register with optional LSL shift") \ - Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \ - Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \ - Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \ - Y(FP_REG, regno, "Fa", 0, F(FLD_Ra), "a floating-point register") \ - Y(FP_REG, ft, "Ft", 0, F(FLD_Rt), "a floating-point register") \ - Y(FP_REG, regno, "Ft2", 0, F(FLD_Rt2), "a floating-point register") \ - Y(SISD_REG, regno, "Sd", 0, F(FLD_Rd), "a SIMD scalar register") \ - Y(SISD_REG, regno, "Sn", 0, F(FLD_Rn), "a SIMD scalar register") \ - Y(SISD_REG, regno, "Sm", 0, F(FLD_Rm), "a SIMD scalar register") \ - Y(SIMD_REG, regno, "Va", 0, F(FLD_Ra), "a SIMD vector register") \ - Y(SIMD_REG, regno, "Vd", 0, F(FLD_Rd), "a SIMD vector register") \ - Y(SIMD_REG, regno, "Vn", 0, F(FLD_Rn), "a SIMD vector register") \ - Y(SIMD_REG, regno, "Vm", 0, F(FLD_Rm), "a SIMD vector register") \ - Y(FP_REG, regno, "VdD1", 0, F(FLD_Rd), \ + Y(FP_REG, regno, "Fd", 0, F(FLD(0, 5)), "a floating-point register") \ + Y(FP_REG, regno, "Fn", 0, F(FLD(5, 5)), "a floating-point register") \ + Y(FP_REG, regno, "Fm", 0, F(FLD(16, 5)), "a floating-point register") \ + Y(FP_REG, regno, "Fa", 0, F(FLD(10, 5)), "a floating-point register") \ + Y(FP_REG, ft, "Ft", 0, F(FLD(0, 5)), "a floating-point register") \ + Y(FP_REG, regno, "Ft2", 0, F(FLD(10, 5)), "a floating-point register") \ + Y(SISD_REG, regno, "Sd", 0, F(FLD(0, 5)), "a SIMD scalar register") \ + Y(SISD_REG, regno, "Sn", 0, F(FLD(5, 5)), "a SIMD scalar register") \ + Y(SISD_REG, regno, "Sm", 0, F(FLD(16, 5)), "a SIMD scalar register") \ + Y(SIMD_REG, regno, "Va", 0, F(FLD(10, 5)), "a SIMD vector register") \ + Y(SIMD_REG, regno, "Vd", 0, F(FLD(0, 5)), "a SIMD vector register") \ + Y(SIMD_REG, regno, "Vn", 0, F(FLD(5, 5)), "a SIMD vector register") \ + Y(SIMD_REG, regno, "Vm", 0, F(FLD(16, 5)), "a SIMD vector register") \ + Y(FP_REG, regno, "VdD1", 0, F(FLD(0, 5)), \ "the top half of a 128-bit FP/SIMD register") \ - Y(FP_REG, regno, "VnD1", 0, F(FLD_Rn), \ + Y(FP_REG, regno, "VnD1", 0, F(FLD(5, 5)), \ "the top half of a 128-bit FP/SIMD register") \ - Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD_Rd), \ + Y(SIMD_ELEMENT, reglane, "Ed", 0, F(FLD(0, 5)), \ "a SIMD vector element") \ - Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD_Rn), \ + Y(SIMD_ELEMENT, reglane, "En", 0, F(FLD(5, 5)), \ "a SIMD vector element") \ - Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \ + Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD(16, 5)), \ "a SIMD vector element") \ - Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \ + Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD(16, 5)), \ "a SIMD vector element limited to V0-V15") \ - Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD_Rm), \ + Y(SIMD_ELEMENT, reglane, "Em8", 0, F(FLD(16, 5)), \ "a SIMD vector element limited to V0-V7") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX1_14", 0, \ - F(FLD_imm1_14, FLD_Rm), \ + F(FLD(14, 1), FLD(16, 5)), \ "a SIMD vector without a type qualifier encoding a bit index") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX2_13", 0, \ - F(FLD_imm2_13, FLD_Rm), \ + F(FLD(13, 2), FLD(16, 5)), \ "a SIMD vector without a type qualifier encoding a bit index") \ Y(SIMD_ELEMENT, simple_index, "Em_INDEX3_12", 0, \ - F(FLD_imm3_12, FLD_Rm), \ + F(FLD(12, 3), FLD(16, 5)), \ "a SIMD vector without a type qualifier encoding a bit index") \ - Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \ + Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD(5, 5)), \ "a SIMD vector register list") \ Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \ "a SIMD vector register list") \ Y(SIMD_REGLIST, ldst_reglist_r, "LVt_AL", 0, F(), \ "a SIMD vector register list") \ - Y(SIMD_REGLIST, lut_reglist, "LVn_LUT", 0, F(FLD_Rn), \ + Y(SIMD_REGLIST, lut_reglist, "LVn_LUT", 0, F(FLD(5, 5)), \ "a SIMD vector register list") \ Y(SIMD_REGLIST, ldst_elemlist, "LEt", 0, F(), \ "a SIMD vector element list") \ - Y(IMMEDIATE, imm, "CRn", 0, F(FLD_CRn), \ + Y(IMMEDIATE, imm, "CRn", 0, F(FLD(12, 4)), \ "a 4-bit opcode field named for historical reasons C0 - C15") \ - Y(IMMEDIATE, imm, "CRm", 0, F(FLD_CRm), \ + Y(IMMEDIATE, imm, "CRm", 0, F(FLD(8, 4)), \ "a 4-bit opcode field named for historical reasons C0 - C15") \ - Y(IMMEDIATE, imm, "IDX", 0, F(FLD_imm4_11), \ + Y(IMMEDIATE, imm, "IDX", 0, F(FLD(11, 4)), \ "an immediate as the index of the least significant byte") \ - Y(IMMEDIATE, imm, "MASK", 0, F(FLD_imm4_0), \ + Y(IMMEDIATE, imm, "MASK", 0, F(FLD(0, 4)), \ "an immediate as the index of the least significant byte") \ Y(IMMEDIATE, advsimd_imm_shift, "IMM_VLSL", 0, F(), \ "a left shift amount for an AdvSIMD register") \ @@ -8102,95 +8102,95 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an immediate shift amount of 8, 16 or 32") \ X(IMMEDIATE, 0, 0, "IMM0", 0, F(), "0") \ X(IMMEDIATE, 0, 0, "FPIMM0", 0, F(), "0.0") \ - Y(IMMEDIATE, fpimm, "FPIMM", 0, F(FLD_imm8), \ + Y(IMMEDIATE, fpimm, "FPIMM", 0, F(FLD(13, 8)), \ "an 8-bit floating-point constant") \ - Y(IMMEDIATE, imm, "IMMR", 0, F(FLD_immr), \ + Y(IMMEDIATE, imm, "IMMR", 0, F(FLD(16, 6)), \ "the right rotate amount") \ - Y(IMMEDIATE, imm, "IMMS", 0, F(FLD_imm6_10), \ + Y(IMMEDIATE, imm, "IMMS", 0, F(FLD(10, 6)), \ "the leftmost bit number to be moved from the source") \ - Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD_imm6_10), \ + Y(IMMEDIATE, imm, "WIDTH", 0, F(FLD(10, 6)), \ "the width of the bit-field") \ - Y(IMMEDIATE, imm, "IMM", 0, F(FLD_imm6_10), "an immediate") \ - Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD_imm6_15), "an immediate") \ - Y(IMMEDIATE, imm, "IMMP1_2", 0, F(FLD_imm6_15), "an immediate plus 1") \ - Y(IMMEDIATE, imm, "IMMS1_2", 0, F(FLD_imm6_15), "an immediate minus 1") \ - Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD_op1), \ + Y(IMMEDIATE, imm, "IMM", 0, F(FLD(10, 6)), "an immediate") \ + Y(IMMEDIATE, imm, "IMM_2", 0, F(FLD(15, 6)), "an immediate") \ + Y(IMMEDIATE, imm, "IMMP1_2", 0, F(FLD(15, 6)), "an immediate plus 1") \ + Y(IMMEDIATE, imm, "IMMS1_2", 0, F(FLD(15, 6)), "an immediate minus 1") \ + Y(IMMEDIATE, imm, "UIMM3_OP1", 0, F(FLD(16, 3)), \ "a 3-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD_op2), \ + Y(IMMEDIATE, imm, "UIMM3_OP2", 0, F(FLD(5, 3)), \ "a 3-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \ + Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD(8, 4)), \ "a 4-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_10), \ + Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD(10, 4)), \ "a 4-bit unsigned Logical Address Tag modifier") \ - Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \ + Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD(8, 4), FLD(5, 3)), \ "a 7-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "UIMM10", OPD_F_SHIFT_BY_4, F(FLD_immr), \ + Y(IMMEDIATE, imm, "UIMM10", OPD_F_SHIFT_BY_4, F(FLD(16, 6)), \ "a 10-bit unsigned multiple of 16") \ - Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \ + Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD(31, 1), FLD(19, 5)), \ "the bit number to be tested") \ - Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16_5), \ + Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD(5, 16)), \ "a 16-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_0), \ + Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD(0, 16)), \ "a 16-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ + Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD(16, 5)), \ "a 5-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ + Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD(16, 5)), \ "a 5-bit signed immediate") \ - Y(IMMEDIATE, imm, "NOT_BALANCED_10", 0, F(FLD_imm1_10), \ + Y(IMMEDIATE, imm, "NOT_BALANCED_10", 0, F(FLD(10, 1)), \ "an optional not balanced indicator (NB)") \ - Y(IMMEDIATE, imm, "NOT_BALANCED_17", 0, F(FLD_imm17_1), \ + Y(IMMEDIATE, imm, "NOT_BALANCED_17", 0, F(FLD(17, 1)), \ "an optional not balanced indicator (NB)") \ - Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ + Y(IMMEDIATE, imm, "NZCV", 0, F(FLD(0, 4)), \ "a flag bit specifier giving an alternative value for each flag") \ - Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \ + Y(IMMEDIATE, limm, "LIMM", 0, F(FLD(22, 1), FLD(16, 6), FLD(10, 6)), \ "Logical immediate") \ - Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD_shift,FLD_imm12), \ + Y(IMMEDIATE, aimm, "AIMM", 0, F(FLD(22, 2), FLD(10, 12)), \ "a 12-bit unsigned immediate with optional left shift of 12 bits")\ - Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD_imm16_5), \ + Y(IMMEDIATE, imm_half, "HALF", 0, F(FLD(5, 16)), \ "a 16-bit immediate with optional left shift") \ - Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale), \ + Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD(10, 6)), \ "the number of bits after the binary point in the fixed-point value")\ X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate") \ - Y(IMMEDIATE, imm_rotate2, "IMM_ROT1", 0, F(FLD_rotate1), \ + Y(IMMEDIATE, imm_rotate2, "IMM_ROT1", 0, F(FLD(11, 2)), \ "a 2-bit rotation specifier for complex arithmetic operations") \ - Y(IMMEDIATE, imm_rotate2, "IMM_ROT2", 0, F(FLD_rotate2), \ + Y(IMMEDIATE, imm_rotate2, "IMM_ROT2", 0, F(FLD(13, 2)), \ "a 2-bit rotation specifier for complex arithmetic operations") \ - Y(IMMEDIATE, imm_rotate1, "IMM_ROT3", 0, F(FLD_rotate3), \ + Y(IMMEDIATE, imm_rotate1, "IMM_ROT3", 0, F(FLD(12, 1)), \ "a 1-bit rotation specifier for complex arithmetic operations") \ Y(COND, cond, "COND", 0, F(), "a condition") \ Y(COND, cond, "COND1", 0, F(), \ "one of the standard conditions, excluding AL and NV.") \ - X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\ + X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD(5, 19), FLD(29, 2)),\ "21-bit PC-relative address of a 4KB page") \ Y(ADDRESS, imm, "ADDR_PCREL9", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ - F(FLD_imm9_5), "9-bit PC-relative address") \ + F(FLD(5, 9)), "9-bit PC-relative address") \ Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ - F(FLD_imm14), "14-bit PC-relative address") \ + F(FLD(5, 14)), "14-bit PC-relative address") \ Y(ADDRESS, imm, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ - F(FLD_imm19), "19-bit PC-relative address") \ - Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD_immhi,FLD_immlo), \ + F(FLD(5, 19)), "19-bit PC-relative address") \ + Y(ADDRESS, imm, "ADDR_PCREL21", OPD_F_SEXT, F(FLD(5, 19), FLD(29, 2)), \ "21-bit PC-relative address") \ Y(ADDRESS, imm, "ADDR_PCREL26", OPD_F_SEXT | OPD_F_SHIFT_BY_2, \ - F(FLD_imm26), "26-bit PC-relative address") \ + F(FLD(0, 26)), "26-bit PC-relative address") \ Y(ADDRESS, addr_simple, "ADDR_SIMPLE", 0, F(), \ "an address with base register (no offset)") \ Y(ADDRESS, addr_regoff, "ADDR_REGOFF", 0, F(), \ "an address with register offset") \ - Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD_imm7,FLD_index2), \ + Y(ADDRESS, addr_simm, "ADDR_SIMM7", 0, F(FLD(15, 7), FLD(24, 1)), \ "an address with 7-bit signed immediate offset") \ - Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD_imm9,FLD_index), \ + Y(ADDRESS, addr_simm, "ADDR_SIMM9", 0, F(FLD(12, 9), FLD(11, 1)), \ "an address with 9-bit signed immediate offset") \ - Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\ + Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD(5, 5), FLD(22, 1), FLD(12, 9), FLD(11, 1)),\ "an address with an optional 10-bit scaled, signed immediate offset") \ - Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\ + Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD(15, 7), FLD(24, 1)),\ "an address with 11-bit signed immediate (multiple of 16) offset")\ - Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \ + Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD(5, 5), FLD(10, 12)), \ "an address with scaled, unsigned immediate offset") \ - Y(ADDRESS, addr_simm, "ADDR_SIMM13", 0, F(FLD_imm9,FLD_index),\ + Y(ADDRESS, addr_simm, "ADDR_SIMM13", 0, F(FLD(12, 9), FLD(11, 1)),\ "an address with 13-bit signed immediate (multiple of 16) offset")\ Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \ "an address with base register (no offset)") \ - Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\ + Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD(5, 5), FLD(12, 9), FLD(11, 1)),\ "an address with an optional 8-bit signed immediate offset") \ Y(ADDRESS, simd_addr_post, "SIMD_ADDR_POST", 0, F(), \ "a post-indexed address with immediate or register increment") \ @@ -8223,532 +8223,532 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SYSTEM, prfop, "PRFOP", 0, F(), \ "a prefetch operation specifier") \ Y(SYSTEM, imm, "RPRFMOP", 0, \ - F(FLD_imm1_15, FLD_imm2_12, FLD_imm3_0), \ + F(FLD(15, 1), FLD(12, 2), FLD(0, 3)), \ "a range prefetch operation specifier") \ - Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \ + Y(SYSTEM, none, "BARRIER_PSB", 0, F(), \ "the PSB/TSB option name CSYNC") \ - Y(SYSTEM, none, "BARRIER_GCSB", 0, F (), \ + Y(SYSTEM, none, "BARRIER_GCSB", 0, F(), \ "the GCSB option name DSYNC") \ - Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \ + Y(SYSTEM, hint, "BTI_TARGET", 0, F(), \ "BTI targets r/j/c/jc") \ Y(SYSTEM, hint, "STSHH_POLICY", 0, F(), \ "an STSHH policy (keep/strm)") \ Y(SYSTEM, hint, "SHUH_PHINT", 0, F(), \ "an optional priority hint (ph)") \ - Y(SYSTEM, imm, "BRBOP", 0, F(FLD_brbop), \ + Y(SYSTEM, imm, "BRBOP", 0, F(FLD(5, 1)), \ "Branch Record Buffer operation operand") \ - Y(INT_REG, regno, "Rt_IN_SYS_ALIASES", 0, F(FLD_Rt), \ + Y(INT_REG, regno, "Rt_IN_SYS_ALIASES", 0, F(FLD(0, 5)), \ "Rt register with defaults for SYS aliases") \ - Y(INT_REG, regno, "LSE128_Rt", 0, F(FLD_LSE128_Rt), "an integer register") \ - Y(INT_REG, regno, "LSE128_Rt2", 0, F(FLD_LSE128_Rt2), "an integer register") \ + Y(INT_REG, regno, "LSE128_Rt", 0, F(FLD(0, 5)), "an integer register") \ + Y(INT_REG, regno, "LSE128_Rt2", 0, F(FLD(16, 5)), "an integer register") \ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ - 4 << OPD_F_OD_LSB, F(FLD_Rn), \ + 4 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 4-bit signed offset, multiplied by 16") \ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x32", \ - 5 << OPD_F_OD_LSB, F(FLD_Rn), \ + 5 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 4-bit signed offset, multiplied by 32") \ Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \ - 0 << OPD_F_OD_LSB, F(FLD_Rn), \ + 0 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 4-bit signed offset, multiplied by VL") \ Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x2xVL", \ - 1 << OPD_F_OD_LSB, F(FLD_Rn), \ + 1 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 4-bit signed offset, multiplied by 2*VL") \ Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x3xVL", \ - 2 << OPD_F_OD_LSB, F(FLD_Rn), \ + 2 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 4-bit signed offset, multiplied by 3*VL") \ Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4x4xVL", \ - 3 << OPD_F_OD_LSB, F(FLD_Rn), \ + 3 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 4-bit signed offset, multiplied by 4*VL") \ Y(ADDRESS, sve_addr_ri_s6xvl, "SVE_ADDR_RI_S6xVL", \ - 0 << OPD_F_OD_LSB, F(FLD_Rn), \ + 0 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 6-bit signed offset, multiplied by VL") \ Y(ADDRESS, sve_addr_ri_s9xvl, "SVE_ADDR_RI_S9xVL", \ - 0 << OPD_F_OD_LSB, F(FLD_Rn), \ + 0 << OPD_F_OD_LSB, F(FLD(5, 5)), \ "an address with a 9-bit signed offset, multiplied by VL") \ Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6", 0 << OPD_F_OD_LSB, \ - F(FLD_Rn), "an address with a 6-bit unsigned offset") \ + F(FLD(5, 5)), "an address with a 6-bit unsigned offset") \ Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB, \ - F(FLD_Rn), \ + F(FLD(5, 5)), \ "an address with a 6-bit unsigned offset, multiplied by 2") \ Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB, \ - F(FLD_Rn), \ + F(FLD(5, 5)), \ "an address with a 6-bit unsigned offset, multiplied by 4") \ Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB, \ - F(FLD_Rn), \ + F(FLD(5, 5)), \ "an address with a 6-bit unsigned offset, multiplied by 8") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR", 0 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL3", 3 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL4", 4 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RM", 0 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RM_LSL1", 1 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RM_LSL2", 2 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RM_LSL3", 3 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RM_LSL4", 4 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \ + F(FLD(5, 5), FLD(16, 5)), "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX", \ - (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + (0 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD(5, 5), FLD(16, 5)), \ "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL1", \ - (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD(5, 5), FLD(16, 5)), \ "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL2", \ - (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD(5, 5), FLD(16, 5)), \ "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \ - (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD(5, 5), FLD(16, 5)), \ "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL4", \ - (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ + (4 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD(5, 5), FLD(16, 5)), \ "an address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_ZX", \ - 0 << OPD_F_OD_LSB , F(FLD_SVE_Zn,FLD_Rm), \ + 0 << OPD_F_OD_LSB , F(FLD(5, 5), FLD(16, 5)), \ "vector of address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ", 0 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_SVE_Zm_16), \ + F(FLD(5, 5), FLD(16, 5)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_SVE_Zm_16), \ + F(FLD(5, 5), FLD(16, 5)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_SVE_Zm_16), \ + F(FLD(5, 5), FLD(16, 5)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ_LSL3", 3 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_SVE_Zm_16), \ + F(FLD(5, 5), FLD(16, 5)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_14", \ - 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ + 0 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(14, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW_22", \ - 0 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ + 0 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(22, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_14", \ - 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ + 1 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(14, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW1_22", \ - 1 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ + 1 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(22, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_14", \ - 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ + 2 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(14, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW2_22", \ - 2 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ + 2 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(22, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_14", \ - 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_14), \ + 3 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(14, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_rz_xtw, "SVE_ADDR_RZ_XTW3_22", \ - 3 << OPD_F_OD_LSB, F(FLD_Rn,FLD_SVE_Zm_16,FLD_SVE_xs_22), \ + 3 << OPD_F_OD_LSB, F(FLD(5, 5), FLD(16, 5), FLD(22, 1)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5", 0 << OPD_F_OD_LSB, \ - F(FLD_SVE_Zn), "an address with a 5-bit unsigned offset") \ + F(FLD(5, 5)), "an address with a 5-bit unsigned offset") \ Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x2", 1 << OPD_F_OD_LSB, \ - F(FLD_SVE_Zn), \ + F(FLD(5, 5)), \ "an address with a 5-bit unsigned offset, multiplied by 2") \ Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x4", 2 << OPD_F_OD_LSB, \ - F(FLD_SVE_Zn), \ + F(FLD(5, 5)), \ "an address with a 5-bit unsigned offset, multiplied by 4") \ Y(ADDRESS, sve_addr_zi_u5, "SVE_ADDR_ZI_U5x8", 3 << OPD_F_OD_LSB, \ - F(FLD_SVE_Zn), \ + F(FLD(5, 5)), \ "an address with a 5-bit unsigned offset, multiplied by 8") \ Y(ADDRESS, sve_addr_zz_lsl, "SVE_ADDR_ZZ_LSL", 0, \ - F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ + F(FLD(5, 5), FLD(16, 5)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_zz_sxtw, "SVE_ADDR_ZZ_SXTW", 0, \ - F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ + F(FLD(5, 5), FLD(16, 5)), \ "an address with a vector register offset") \ Y(ADDRESS, sve_addr_zz_uxtw, "SVE_ADDR_ZZ_UXTW", 0, \ - F(FLD_SVE_Zn,FLD_SVE_Zm_16), \ + F(FLD(5, 5), FLD(16, 5)), \ "an address with a vector register offset") \ - Y(IMMEDIATE, sve_aimm, "SVE_AIMM", 0, F(FLD_SVE_imm9), \ + Y(IMMEDIATE, sve_aimm, "SVE_AIMM", 0, F(FLD(5, 9)), \ "a 9-bit unsigned arithmetic operand") \ - Y(IMMEDIATE, sve_asimm, "SVE_ASIMM", 0, F(FLD_SVE_imm9), \ + Y(IMMEDIATE, sve_asimm, "SVE_ASIMM", 0, F(FLD(5, 9)), \ "a 9-bit signed arithmetic operand") \ - Y(IMMEDIATE, fpimm, "SVE_FPIMM8", 0, F(FLD_SVE_imm8), \ + Y(IMMEDIATE, fpimm, "SVE_FPIMM8", 0, F(FLD(5, 8)), \ "an 8-bit floating-point immediate") \ Y(IMMEDIATE, sve_float_half_one, "SVE_I1_HALF_ONE", 0, \ - F(FLD_SVE_i1), "either 0.5 or 1.0") \ + F(FLD(5, 1)), "either 0.5 or 1.0") \ Y(IMMEDIATE, sve_float_half_two, "SVE_I1_HALF_TWO", 0, \ - F(FLD_SVE_i1), "either 0.5 or 2.0") \ + F(FLD(5, 1)), "either 0.5 or 2.0") \ Y(IMMEDIATE, sve_float_zero_one, "SVE_I1_ZERO_ONE", 0, \ - F(FLD_SVE_i1), "either 0.0 or 1.0") \ - Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT1", 0, F(FLD_SVE_rot1), \ + F(FLD(5, 1)), "either 0.0 or 1.0") \ + Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT1", 0, F(FLD(16, 1)), \ "a 1-bit rotation specifier for complex arithmetic operations") \ - Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \ + Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD(10, 2)), \ "a 2-bit rotation specifier for complex arithmetic operations") \ - Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT3", 0, F(FLD_SVE_rot3), \ + Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT3", 0, F(FLD(10, 1)), \ "a 1-bit rotation specifier for complex arithmetic operations") \ Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \ - F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ + F(FLD(17, 1), FLD(11, 6), FLD(5, 6)), \ "an inverted 13-bit logical immediate") \ Y(IMMEDIATE, limm, "SVE_LIMM", 0, \ - F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ + F(FLD(17, 1), FLD(11, 6), FLD(5, 6)), \ "a 13-bit logical immediate") \ Y(IMMEDIATE, sve_limm_mov, "SVE_LIMM_MOV", 0, \ - F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \ + F(FLD(17, 1), FLD(11, 6), FLD(5, 6)), \ "a 13-bit logical move immediate") \ - Y(IMMEDIATE, imm, "SVE_PATTERN", 0, F(FLD_SVE_pattern), \ + Y(IMMEDIATE, imm, "SVE_PATTERN", 0, F(FLD(5, 5)), \ "an enumeration value such as POW2") \ Y(IMMEDIATE, sve_scale, "SVE_PATTERN_SCALED", 0, \ - F(FLD_SVE_pattern), "an enumeration value such as POW2") \ - Y(IMMEDIATE, imm, "SVE_PRFOP", 0, F(FLD_SVE_prfop), \ + F(FLD(5, 5)), "an enumeration value such as POW2") \ + Y(IMMEDIATE, imm, "SVE_PRFOP", 0, F(FLD(0, 4)), \ "an enumeration value such as PLDL1KEEP") \ - Y(PRED_REG, regno, "SVE_Pd", 0, F(FLD_SVE_Pd), \ + Y(PRED_REG, regno, "SVE_Pd", 0, F(FLD(0, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_PNd", 0, F(FLD_SVE_Pd), \ + Y(PRED_REG, regno, "SVE_PNd", 0, F(FLD(0, 4)), \ "an SVE predicate-as-counter register") \ - Y(PRED_REG, regno, "SVE_Pg3", 0, F(FLD_SVE_Pg3), \ + Y(PRED_REG, regno, "SVE_Pg3", 0, F(FLD(10, 3)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_Pg4_5", 0, F(FLD_SVE_Pg4_5), \ + Y(PRED_REG, regno, "SVE_Pg4_5", 0, F(FLD(5, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_Pg4_10", 0, F(FLD_SVE_Pg4_10), \ + Y(PRED_REG, regno, "SVE_Pg4_10", 0, F(FLD(10, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_PNg4_10", 0, F(FLD_SVE_Pg4_10), \ + Y(PRED_REG, regno, "SVE_PNg4_10", 0, F(FLD(10, 4)), \ "an SVE predicate-as-counter register") \ - Y(PRED_REG, regno, "SVE_Pg4_16", 0, F(FLD_SVE_Pg4_16), \ + Y(PRED_REG, regno, "SVE_Pg4_16", 0, F(FLD(16, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_Pm", 0, F(FLD_SVE_Pm), \ + Y(PRED_REG, regno, "SVE_Pm", 0, F(FLD(16, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_Pn", 0, F(FLD_SVE_Pn), \ + Y(PRED_REG, regno, "SVE_Pn", 0, F(FLD(5, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_PNn", 0, F(FLD_SVE_Pn), \ + Y(PRED_REG, regno, "SVE_PNn", 0, F(FLD(5, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD_SVE_Pt), \ + Y(PRED_REG, regno, "SVE_Pt", 0, F(FLD(0, 4)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SVE_PNt", 0, F(FLD_SVE_Pt), \ + Y(PRED_REG, regno, "SVE_PNt", 0, F(FLD(0, 4)), \ "an SVE predicate register") \ - Y(INT_REG, regno, "SVE_Rm", 0, F(FLD_SVE_Rm), \ + Y(INT_REG, regno, "SVE_Rm", 0, F(FLD(5, 5)), \ "an integer register or zero") \ - Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD_SVE_Rn), \ + Y(INT_REG, regno, "SVE_Rn_SP", OPD_F_MAYBE_SP, F(FLD(16, 5)), \ "an integer register or SP") \ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_PRED", 0, \ - F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \ + F(FLD(22, 2), FLD(5, 5)), "a shift-left immediate operand") \ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \ - F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \ + F(FLD(22, 2), FLD(16, 5)), "a shift-left immediate operand") \ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED_22", 0, \ - F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \ + F(FLD(22, 1), FLD(19, 2), FLD(16, 3)), \ "a shift-left immediate operand") \ Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB, \ - F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \ + F(FLD(22, 2), FLD(5, 5)), "a shift-right immediate operand") \ Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB, \ - F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \ + F(FLD(22, 2), FLD(16, 5)), "a shift-right immediate operand") \ Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB, \ - F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \ + F(FLD(22, 1), FLD(19, 2), FLD(16, 3)), \ "a shift-right immediate operand") \ - Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \ + Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD(5, 5)), \ "a 5-bit signed immediate") \ - Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \ + Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD(16, 5)), \ "a 5-bit signed immediate") \ - Y(IMMEDIATE, imm, "SVE_SIMM6", OPD_F_SEXT, F(FLD_SVE_imms), \ + Y(IMMEDIATE, imm, "SVE_SIMM6", OPD_F_SEXT, F(FLD(5, 6)), \ "a 6-bit signed immediate") \ - Y(IMMEDIATE, imm, "SVE_SIMM8", OPD_F_SEXT, F(FLD_SVE_imm8), \ + Y(IMMEDIATE, imm, "SVE_SIMM8", OPD_F_SEXT, F(FLD(5, 8)), \ "an 8-bit signed immediate") \ - Y(IMMEDIATE, imm, "SVE_UIMM3", 0, F(FLD_SVE_imm3), \ + Y(IMMEDIATE, imm, "SVE_UIMM3", 0, F(FLD(16, 3)), \ "a 3-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "SVE_UIMM7", 0, F(FLD_SVE_imm7), \ + Y(IMMEDIATE, imm, "SVE_UIMM7", 0, F(FLD(14, 7)), \ "a 7-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD_SVE_imm8), \ + Y(IMMEDIATE, imm, "SVE_UIMM8", 0, F(FLD(5, 8)), \ "an 8-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD_imm5,FLD_imm3_10), \ + Y(IMMEDIATE, imm, "SVE_UIMM8_53", 0, F(FLD(16, 5), FLD(10, 3)), \ "an 8-bit unsigned immediate") \ - Y(IMMEDIATE, imm, "SVE_UIMM4", 0, F(FLD_SVE_imm4), \ + Y(IMMEDIATE, imm, "SVE_UIMM4", 0, F(FLD(16, 4)), \ "a 4-bit unsigned immediate") \ - Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD_SVE_Zn), "a SIMD register") \ - Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD_SVE_Vd), "a SIMD register") \ - Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD_SVE_Vm), "a SIMD register") \ - Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD_SVE_Vn), "a SIMD register") \ + Y(SIMD_REG, regno, "SVE_VZn", 0, F(FLD(5, 5)), "a SIMD register") \ + Y(SIMD_REG, regno, "SVE_Vd", 0, F(FLD(0, 5)), "a SIMD register") \ + Y(SIMD_REG, regno, "SVE_Vm", 0, F(FLD(5, 5)), "a SIMD register") \ + Y(SIMD_REG, regno, "SVE_Vn", 0, F(FLD(5, 5)), "a SIMD register") \ Y(ZA_ACCESS, sme_za_vrs1, "SME_ZA_array_vrsb_1", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_off3), "ZA0 tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(5, 3)), "ZA0 tile") \ Y(ZA_ACCESS, sme_za_vrs1, "SME_ZA_array_vrsh_1", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_ZAn_1,FLD_off2), "1 bit ZA tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(7, 1), FLD(5, 2)), "1 bit ZA tile") \ Y(ZA_ACCESS, sme_za_vrs1, "SME_ZA_array_vrss_1", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_ZAn_2,FLD_ol), "2 ZA tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(6, 2), FLD(5, 1)), "2 ZA tile") \ Y(ZA_ACCESS, sme_za_vrs1, "SME_ZA_array_vrsd_1", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3), "3 ZA tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(5, 3)), "3 ZA tile") \ Y(ZA_ACCESS, sme_za_vrs2, "SME_ZA_array_vrsb_2", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_off2), "ZA0 tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(5, 2)), "ZA0 tile") \ Y(ZA_ACCESS, sme_za_vrs2, "SME_ZA_array_vrsh_2", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_ZAn,FLD_ol), "1 bit ZA tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(6, 1), FLD(5, 1)), "1 bit ZA tile") \ Y(ZA_ACCESS, sme_za_vrs2, "SME_ZA_array_vrss_2", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_off2), "2 bit ZA tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(5, 2)), "2 bit ZA tile") \ Y(ZA_ACCESS, sme_za_vrs2, "SME_ZA_array_vrsd_2", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_ZAn_3), "3 bit ZA tile") \ + F(FLD(15, 1), FLD(13, 2), FLD(5, 3)), "3 bit ZA tile") \ Y(ZA_ACCESS, sme_za_tile_to_vec, "SME_ZA_ARRAY4", 0, \ - F(FLD_SME_V,FLD_SME_Rv), "ZA tile to vector register") \ - Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD_SVE_Za_5), \ + F(FLD(15, 1), FLD(13, 2)), "ZA tile to vector register") \ + Y(SVE_REG, regno, "SVE_Za_5", 0, F(FLD(5, 5)), \ "an SVE vector register") \ - Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD_SVE_Za_16), \ + Y(SVE_REG, regno, "SVE_Za_16", 0, F(FLD(16, 5)), \ "an SVE vector register") \ - Y(SVE_REG, regno, "SVE_Zd", 0, F(FLD_SVE_Zd), \ + Y(SVE_REG, regno, "SVE_Zd", 0, F(FLD(0, 5)), \ "an SVE vector register") \ - Y(SVE_REG, regno, "SVE_Zm_5", 0, F(FLD_SVE_Zm_5), \ + Y(SVE_REG, regno, "SVE_Zm_5", 0, F(FLD(5, 5)), \ "an SVE vector register") \ - Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD_SVE_Zm_16), \ + Y(SVE_REG, regno, "SVE_Zm_16", 0, F(FLD(16, 5)), \ "an SVE vector register") \ Y(SVE_REG, simple_index, "SVE_Zm1_23_INDEX", \ - 0, F(FLD_SVE_i1_23, FLD_SVE_Zm_16), \ + 0, F(FLD(23, 1), FLD(16, 5)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SVE_Zm2_22_INDEX", \ - 0, F(FLD_SVE_i2, FLD_SVE_Zm_16), \ + 0, F(FLD(22, 2), FLD(16, 5)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_INDEX", \ - 3 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ + 3 << OPD_F_OD_LSB, F(FLD(16, 5)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \ - 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \ + 3 << OPD_F_OD_LSB, F(FLD(19, 2), FLD(11, 1), FLD(16, 3)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SVE_Zm3_12_INDEX", \ - 0, F(FLD_SVE_i3h3, FLD_SVE_i3l2, FLD_SVE_Zm_16), \ + 0, F(FLD(22, 2), FLD(12, 1), FLD(16, 5)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_19_INDEX", \ - 3 << OPD_F_OD_LSB, F(FLD_imm2_19, FLD_SVE_imm3), \ + 3 << OPD_F_OD_LSB, F(FLD(19, 2), FLD(16, 3)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \ - 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \ + 3 << OPD_F_OD_LSB, F(FLD(22, 1), FLD(16, 5)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm3_10_INDEX", \ - 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i4l2, FLD_SVE_imm3), \ + 3 << OPD_F_OD_LSB, F(FLD(19, 2), FLD(10, 2), FLD(16, 3)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ - 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ + 4 << OPD_F_OD_LSB, F(FLD(20, 1), FLD(11, 1), FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \ - 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ + 4 << OPD_F_OD_LSB, F(FLD(16, 5)), \ "an indexed SVE vector register") \ - Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ + Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD(5, 5)), \ "an SVE vector register") \ Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, \ - F(FLD_SVE_Zn, FLD_SVE_tszh, FLD_imm5), \ + F(FLD(5, 5), FLD(22, 2), FLD(16, 5)), \ "an indexed SVE vector register") \ Y(SVE_REG, sve_index, "SVE_Zn_5_INDEX", 0, \ - F(FLD_SVE_Zn, FLD_imm5), \ + F(FLD(5, 5), FLD(16, 5)), \ "a 5 bit indexed SVE vector register") \ - Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ + Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD(5, 5)), \ "a list of SVE vector registers") \ - Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD_SVE_Zt), \ + Y(SVE_REG, regno, "SVE_Zt", 0, F(FLD(0, 5)), \ "an SVE vector register") \ - Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \ + Y(SVE_REGLIST, sve_reglist, "SVE_ZtxN", 0, F(FLD(0, 5)), \ "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx2", 2 << OPD_F_OD_LSB, \ - F(FLD_SME_Zdn2, FLD_CONST_0), "a list of SVE vector registers") \ + F(FLD(1, 4), FLD_CONST_0), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \ - F(FLD_SME_Zdn4, FLD_CONST_00), "a list of SVE vector registers") \ - Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm), \ + F(FLD(2, 3), FLD_CONST_00), "a list of SVE vector registers") \ + Y(SVE_REG, regno, "SME_Zm", 0, F(FLD(16, 4)), \ "an SVE vector register") \ - Y(SVE_REG, regno, "SME_Zm_17", 0, F(FLD_SME_Zm2), \ + Y(SVE_REG, regno, "SME_Zm_17", 0, F(FLD(17, 4)), \ "an SVE vector register") \ Y(SVE_REG, regno, "SME_Zn_6_3", 0, \ - F(FLD_CONST_0, FLD_SME_Zn6_3, FLD_CONST_0), \ + F(FLD_CONST_0, FLD(6, 3), FLD_CONST_0), \ "an SVE vector register") \ Y(SVE_REG, regno, "SME_Zm_17_3", 0, \ - F(FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0), \ + F(FLD_CONST_1, FLD(17, 3), FLD_CONST_0), \ "an SVE vector register") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2_6_3", \ - 2 << OPD_F_OD_LSB, F(FLD_CONST_0, FLD_SME_Zn6_3, FLD_CONST_0), \ + 2 << OPD_F_OD_LSB, F(FLD_CONST_0, FLD(6, 3), FLD_CONST_0), \ "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2_17_3", \ - 2 << OPD_F_OD_LSB, F(FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0), \ + 2 << OPD_F_OD_LSB, F(FLD_CONST_1, FLD(17, 3), FLD_CONST_0), \ "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_reglist_index, "SME_Zmx2_INDEX_22", 2 << OPD_F_OD_LSB, \ - F(FLD_SVE_Zm_16, FLD_imm1_22), "a list of SVE vector registers with index") \ + F(FLD(16, 5), FLD(22, 1)), "a list of SVE vector registers with index") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \ - F(FLD_SME_Zm2, FLD_CONST_0), "a list of SVE vector registers") \ + F(FLD(17, 4), FLD_CONST_0), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \ - F(FLD_SME_Zm4, FLD_CONST_00), "a list of SVE vector registers") \ + F(FLD(18, 3), FLD_CONST_00), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \ - F(FLD_SME_Zn2, FLD_CONST_0), "a list of SVE vector registers") \ + F(FLD(6, 4), FLD_CONST_0), "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2_BIT_INDEX", \ - 2 << OPD_F_OD_LSB, F(FLD_SME_Zn2, FLD_CONST_0), \ + 2 << OPD_F_OD_LSB, F(FLD(6, 4), FLD_CONST_0), \ "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \ - F(FLD_SME_Zn4, FLD_CONST_00), "a list of SVE vector registers") \ - Y(SVE_REGLIST, sve_reglist, "SME_Zn7xN_UNTYPED", 0, F(FLD_SME_Zn4), \ + F(FLD(7, 3), FLD_CONST_00), "a list of SVE vector registers") \ + Y(SVE_REGLIST, sve_reglist, "SME_Zn7xN_UNTYPED", 0, F(FLD(7, 3)), \ "a list of untyped SVE vector registers") \ Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \ - 2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3), \ + 2 << OPD_F_OD_LSB, F(FLD(4, 1), FLD(0, 3)), \ "a list of SVE vector registers") \ Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx4_STRIDED", \ - 4 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt2), \ + 4 << OPD_F_OD_LSB, F(FLD(4, 1), FLD(0, 2)), \ "a list of SVE vector registers") \ - Y(SVE_REG, regno, "SME_ZAda_1b", 0, F(FLD_SME_ZAda_1b), \ + Y(SVE_REG, regno, "SME_ZAda_1b", 0, F(FLD(0, 1)), \ "an SME ZA tile ZA0-ZA1") \ - Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD_SME_ZAda_2b), \ + Y(SVE_REG, regno, "SME_ZAda_2b", 0, F(FLD(0, 2)), \ "an SME ZA tile ZA0-ZA3") \ - Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD_SME_ZAda_3b), \ + Y(SVE_REG, regno, "SME_ZAda_3b", 0, F(FLD(0, 3)), \ "an SME ZA tile ZA0-ZA7") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_src", 0, \ - F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5), \ + F(FLD(22, 2), FLD(16, 1), FLD(15, 1), FLD(13, 2), FLD(5, 4)), \ "an SME horizontal or vertical vector access register") \ Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_srcxN", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_5), \ + F(FLD(15, 1), FLD(13, 2), FLD(5, 3)), \ "an SME horizontal or vertical vector access register") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_dest", 0, \ - F(FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ + F(FLD(22, 2), FLD(16, 1), FLD(15, 1), FLD(13, 2), FLD(0, 4)), \ "an SME horizontal or vertical vector access register") \ Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \ - F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \ + F(FLD(15, 1), FLD(13, 2), FLD(0, 3)), \ "an SME horizontal or vertical vector access register") \ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Pdx2", 2 << OPD_F_OD_LSB, \ - F(FLD_SME_Pdx2, FLD_CONST_0), "a list of SVE predicate registers")\ - Y(SVE_REGLIST, sve_reglist, "SME_PdxN", 0, F(FLD_SVE_Pd), \ + F(FLD(1, 3), FLD_CONST_0), "a list of SVE predicate registers")\ + Y(SVE_REGLIST, sve_reglist, "SME_PdxN", 0, F(FLD(0, 4)), \ "a list of SVE predicate registers") \ - Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ + Y(PRED_REG, regno, "SME_Pm", 0, F(FLD(13, 3)), \ "an SVE predicate register") \ - Y(PRED_REG, regno, "SME_PNd3", 0, F(FLD_CONST_1, FLD_SME_PNd3), \ + Y(PRED_REG, regno, "SME_PNd3", 0, F(FLD_CONST_1, FLD(0, 3)), \ "an SVE predicate-as-counter register") \ - Y(PRED_REG, regno, "SME_PNg3", 0, F(FLD_CONST_1, FLD_SVE_Pg3), \ + Y(PRED_REG, regno, "SME_PNg3", 0, F(FLD_CONST_1, FLD(10, 3)), \ "an SVE predicate-as-counter register") \ - Y(PRED_REG, regno, "SME_PNn", 0, F(FLD_SVE_Pn), \ + Y(PRED_REG, regno, "SME_PNn", 0, F(FLD(5, 4)), \ "an SVE predicate-as-counter register") \ Y(SVE_REG, simple_index, "SME_PNn3_INDEX1", 0, \ - F(FLD_imm1_8, FLD_CONST_01, FLD_SME_PNn3), \ + F(FLD(8, 1), FLD_CONST_01, FLD(5, 3)), \ "an indexed SVE predicate-as-counter register") \ Y(SVE_REG, simple_index, "SME_PNn3_INDEX2", 0, \ - F(FLD_imm2_8, FLD_CONST_01, FLD_SME_PNn3), \ + F(FLD(8, 2), FLD_CONST_01, FLD(5, 3)), \ "an indexed SVE predicate-as-counter register") \ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ - F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \ + F(FLD(0, 8)), "a list of 64-bit ZA element tiles") \ Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \ - F(FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0), \ + F(FLD(22, 2), FLD(24, 1), FLD(15, 1), FLD(13, 2), FLD(0, 4)), \ "an SME horizontal or vertical vector access register") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off1x4", \ - 4 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm1_0), "ZA array") \ + 4 << OPD_F_OD_LSB, F(FLD(13, 2), FLD(0, 1)), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off2x2", \ - 2 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm2_0), "ZA array") \ + 2 << OPD_F_OD_LSB, F(FLD(13, 2), FLD(0, 2)), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off2x4", \ - 4 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm2_0), "ZA array") \ + 4 << OPD_F_OD_LSB, F(FLD(13, 2), FLD(0, 2)), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_0", 0, \ - F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \ + F(FLD(13, 2), FLD(0, 3)), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3_5", 0, \ - F(FLD_SME_Rv,FLD_imm3_5), "ZA array") \ + F(FLD(13, 2), FLD(5, 3)), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off3x2", \ - 2 << OPD_F_OD_LSB, F(FLD_SME_Rv,FLD_imm3_0), "ZA array") \ + 2 << OPD_F_OD_LSB, F(FLD(13, 2), FLD(0, 3)), "ZA array") \ Y(ZA_ACCESS, sme_za_array, "SME_ZA_array_off4", 0, \ - F(FLD_SME_Rv,FLD_imm4_0), "ZA array") \ + F(FLD(13, 2), FLD(0, 4)), "ZA array") \ Y(ADDRESS, sme_addr_ri_u4xvl, "SME_ADDR_RI_U4xVL", 0 << OPD_F_OD_LSB, \ - F(FLD_Rn,FLD_imm4_0), "memory offset") \ + F(FLD(5, 5), FLD(0, 4)), "memory offset") \ Y(ADDRESS, sme_sm_za, "SME_SM_ZA", 0, \ - F(FLD_CRm), "streaming mode") \ + F(FLD(8, 4)), "streaming mode") \ Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ - F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ + F(FLD(16, 2), FLD(5, 4), FLD(23, 1), FLD(22, 1), FLD(18, 3)), \ "Source scalable predicate register with index ") \ - Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM3", 0, F(FLD_SVE_imm3), \ + Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM3", 0, F(FLD(16, 3)), \ "a shift-right immediate operand") \ - Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD_SVE_imm4), \ + Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD(16, 4)), \ "a shift-right immediate operand") \ Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \ - F(FLD_SVE_tszh,FLD_SVE_imm5b), "a shift-right immediate operand") \ + F(FLD(22, 2), FLD(16, 5)), "a shift-right immediate operand") \ Y(SVE_REG, simple_index, "SME_Zk_INDEX", 0, \ - F(FLD_imm2_4, FLD_CONST_1, FLD_SVE_i3l2, FLD_CONST_1, FLD_imm2_10),\ + F(FLD(4, 2), FLD_CONST_1, FLD(12, 1), FLD_CONST_1, FLD(10, 2)),\ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX1", 0, \ - F(FLD_imm1_10, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 1), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX2", 0, \ - F(FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 2), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX2_3", 0, \ - F(FLD_imm1_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 1), FLD(3, 1), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_1", 0, \ - F(FLD_imm1_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 1), FLD(1, 2), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_2", 0, \ - F(FLD_imm2_10, FLD_imm1_2, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 2), FLD(2, 1), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_3", 0, \ - F(FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 2), FLD(3, 1), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX3_10", 0, \ - F(FLD_imm1_15, FLD_imm2_10, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(15, 1), FLD(10, 2), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_1", 0, \ - F(FLD_imm2_10, FLD_imm2_1, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 2), FLD(1, 2), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_2", 0, \ - F(FLD_imm2_10, FLD_imm2_2, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(10, 2), FLD(2, 2), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_3", 0, \ - F(FLD_imm1_15, FLD_imm2_10, FLD_imm1_3, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(15, 1), FLD(10, 2), FLD(3, 1), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zm_INDEX4_10", 0, \ - F(FLD_imm1_15, FLD_imm3_10, FLD_CONST_0, FLD_SME_Zm), \ + F(FLD(15, 1), FLD(10, 3), FLD_CONST_0, FLD(16, 4)), \ "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \ - F(FLD_imm1_16, FLD_SVE_Zn), "an indexed SVE vector register") \ + F(FLD(16, 1), FLD(5, 5)), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \ - F(FLD_imm2_15, FLD_SVE_Zn), "an indexed SVE vector register") \ + F(FLD(15, 2), FLD(5, 5)), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \ - F(FLD_imm2_16, FLD_SVE_Zn), "an indexed SVE vector register") \ + F(FLD(16, 2), FLD(5, 5)), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX2_19", 0, \ - F(FLD_imm2_19, FLD_SVE_Zn), "an indexed SVE vector register") \ + F(FLD(19, 2), FLD(5, 5)), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \ - F(FLD_imm3_14, FLD_SVE_Zn), "an indexed SVE vector register") \ + F(FLD(14, 3), FLD(5, 5)), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \ - F(FLD_imm3_15, FLD_SVE_Zn), "an indexed SVE vector register") \ + F(FLD(15, 3), FLD(5, 5)), "an indexed SVE vector register") \ Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \ - F(FLD_imm4_14, FLD_SVE_Zn), "an indexed SVE vector register") \ - Y(SVE_REG, regno, "SVE_Zn0_INDEX", 0, F(FLD_SVE_Zn), \ + F(FLD(14, 4), FLD(5, 5)), "an indexed SVE vector register") \ + Y(SVE_REG, regno, "SVE_Zn0_INDEX", 0, F(FLD(5, 5)), \ "an SVE vector register with option zero index") \ Y(SVE_REG, simple_index, "SVE_Zn1_17_INDEX", 0, \ - F(FLD_imm17_1, FLD_SVE_Zn), \ + F(FLD(17, 1), FLD(5, 5)), \ "an SVE vector register with optional one bit index") \ Y(SVE_REG, simple_index, "SVE_Zn2_18_INDEX", 0, \ - F(FLD_imm17_2, FLD_SVE_Zn), \ + F(FLD(17, 2), FLD(5, 5)), \ "an SVE vector register with optional two bit index") \ Y(SVE_REG, simple_index, "SVE_Zn3_22_INDEX", 0, \ - F(FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zn), \ + F(FLD(22, 1), FLD(17, 2), FLD(5, 5)), \ "an SVE vector register with optional three bit index") \ - Y(SVE_REG, regno, "SVE_Zd0_INDEX", 0, F(FLD_SVE_Zd), \ + Y(SVE_REG, regno, "SVE_Zd0_INDEX", 0, F(FLD(0, 5)), \ "an SVE vector register with option zero index") \ Y(SVE_REG, simple_index, "SVE_Zd1_17_INDEX", 0, \ - F(FLD_imm17_1, FLD_SVE_Zd), \ + F(FLD(17, 1), FLD(0, 5)), \ "an SVE vector register with optional one bit index") \ Y(SVE_REG, simple_index, "SVE_Zd2_18_INDEX", 0, \ - F(FLD_imm17_2, FLD_SVE_Zd), \ + F(FLD(17, 2), FLD(0, 5)), \ "an SVE vector register with optional two bit index") \ Y(SVE_REG, simple_index, "SVE_Zd3_22_INDEX", 0, \ - F(FLD_SVE_i3h, FLD_imm17_2, FLD_SVE_Zd), \ + F(FLD(22, 1), FLD(17, 2), FLD(0, 5)), \ "an SVE vector register with optional three bit index") \ - Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \ + Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD(10, 1)), \ "VLx2 or VLx4") \ - Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \ + Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD(13, 1)), \ "VLx2 or VLx4") \ - Y(SYSTEM, none, "SME_ZT0", 0, F (), "ZT0") \ + Y(SYSTEM, none, "SME_ZT0", 0, F(), "ZT0") \ Y(IMMEDIATE, imm, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3, \ - F (FLD_imm3_12), "a ZT0 index") \ + F(FLD(12, 3)), "a ZT0 index") \ Y(IMMEDIATE, imm, "SME_ZT0_INDEX_MUL_VL", 0, \ - F (FLD_imm3_12), "a ZT0 index") \ - Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \ - Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \ + F(FLD(12, 3)), "a ZT0 index") \ + Y(SYSTEM, none, "SME_ZT0_LIST", 0, F(), "{ ZT0 }") \ + Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD(5, 16)), \ "a 16-bit unsigned immediate for TME tcancel") \ /* These next two are really register fields; the [...] notation \ is just syntactic sugar. */ \ - Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD_Rd), \ + Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD(0, 5)), \ "a register destination address with writeback") \ - Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs), \ + Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD(16, 5)), \ "a register source address with writeback") \ - Y(INT_REG, x0_to_x30, "MOPS_WB_Rn", 0, F(FLD_Rn), \ + Y(INT_REG, x0_to_x30, "MOPS_WB_Rn", 0, F(FLD(5, 5)), \ "an integer register with writeback") \ - Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8), \ + Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD(10, 8)), \ "an 8-bit signed immediate") \ - Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8), \ + Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD(10, 8)), \ "an 8-bit unsigned immediate") \ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ - "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \ + "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD(12, 4)), \ "an address with post-incrementing by ammount of loaded bytes") \ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ - "RCPC3_ADDR_OPT_PREIND_WB", 0, F(FLD_opc2), \ + "RCPC3_ADDR_OPT_PREIND_WB", 0, F(FLD(12, 4)), \ "an address with pre-incrementing with write-back by ammount of stored bytes") \ X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ "RCPC3_ADDR_POSTIND", 0, F(), \ @@ -8756,7 +8756,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ "RCPC3_ADDR_PREIND_WB", 0, F(), \ "an address with pre-incrementing with write-back by ammount of stored bytes") \ - Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \ + Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD(5, 5), FLD(12, 9)), \ "an address with an optional 8-bit signed immediate offset") \ Y(SYSTEM, sysins_op, "GIC", 0, F(), \ "Generic Interrupt Controller") \ From patchwork Wed May 20 12:09:40 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alice Carlotti X-Patchwork-Id: 135336 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 876054BB58F6 for ; Wed, 20 May 2026 12:13:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 876054BB58F6 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=OZAiw5Pi; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=OZAiw5Pi X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from AS8PR04CU009.outbound.protection.outlook.com (mail-westeuropeazon11011045.outbound.protection.outlook.com [52.101.70.45]) by sourceware.org (Postfix) with ESMTPS id 118D94BB3BBC for ; Wed, 20 May 2026 12:10:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 118D94BB3BBC Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 118D94BB3BBC Authentication-Results: sourceware.org; arc=fail smtp.remote-ip=52.101.70.45 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1779279058; cv=fail; b=bdoCGEgd+KG9U0ZRyWwfadn2uCZXYm6o3kLVsMB72+OSDDYE7BRwfKp6zAm/cMfAUXZ4qpyDID9w7QGKJz9x0c6D2fJZG7m/TNSqd64xbg/GDpqWJyUhPYSfj//MEPmU6OKRwkInmhIbg6C+wWr7axjupekW569SW6PUXKg5gew= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1779279058; c=relaxed/simple; bh=4fzEd6zr/hbRZ4KREQknP+4aWfrdIzaYC236caLe6lo=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=hit/tBgGpWVTFdV9XNPUmpsTB8ww9T98cV1j6BmQW21qP/X1M+A4U1t/Dhp9qrFlds1wIPmjBqkyTu35Ue+fo9/8XP8BFzNEigoJLt3ELYw3tQFqFnfJWbJllWN+2RWxCgxI0ersFjWlm3BwGnvjsKuF1N868jGhZb5SB6fUiNM= ARC-Authentication-Results: i=3; sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=OZAiw5Pi; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=OZAiw5Pi DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 118D94BB3BBC ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=fail; b=egqYc+mm1xYuh0uf9XrQdNmu+N6Grl9uGQPtIGHih7uOytXppzlwvuYOaAobYSbJnR0wteJtZUVQkm+QIbMJgWCgX1OE3fJhUygLqZmYi7C2SWFqY7V9B4/aaP+0Y0QRBICKkqE/NWm/2CLWOd/pqdLe9SqCI8FcshM7H8EsGseJ3FFqKbnRxYhuJXUvi1cBg2iIBOop8XHYf8DIBJOsthJLVaEtAw+tsDsaH7Z2LJ59GrvZTq8rN+Eap05Q35VOsoukQrXZ9ehSvb0coXyT5KiOjPzJmx4+564K2vJf4vVw1D/epa24cdm/3slf+uTCftuVZzusicyWz4C7Tl2qaQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PH7Uo2zy9pra8reCCR8h+Urfk9bmk3/I2+MutpgGxCI=; b=m+v0SDB9KC+0sOg9QSVpERS9YQwMXuPKGoJzqfeflmXNdBB3Gq0GNZ+Pmeg8wSkqVQrLQ7BweS7cRfaJR4N+puaU3/EH64q+obs8uIp6bNy3CCcBXIsrM2onHkagRutl4i0GgJbN6aLJPcY9cyGpczFiZ5AQAgoTpdzdnvUGuz9oVzbvtWHh1tCnFKy3UBXfakJBpWf4SxBt3ydklLymV079shgFOEq7WQwRgXejQpZSVUfsHBHvW2l6DrbK0dYO+YV/x1/GezBspq/1+SrDZADjSe6FEe9kUa6qe9oab/mtc+Nrv0aWNtOLofO/p4Rww4yTbCf+V32q3pXNu869sQ== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=fail (48) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PH7Uo2zy9pra8reCCR8h+Urfk9bmk3/I2+MutpgGxCI=; b=OZAiw5Pi74eQh1j2edJxrO+hDVlbBfxxjRDFL4TuDBa5rbqjjo+kVX8HyB2YCvGn0r1qRw28RhIw+6yb5zzSrYR+TXLaon1O9oRCUr61FNRAzDJZTZz+CwZFAZauRrO88XWk+YmzSHThDWj8kN93XL4aYAU4C/I6/Fu1IOcanyY= Received: from CWLP123CA0185.GBRP123.PROD.OUTLOOK.COM (2603:10a6:400:19b::23) by AS2PR08MB9428.eurprd08.prod.outlook.com (2603:10a6:20b:5e8::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:10:45 +0000 Received: from AM4PEPF00027A6C.eurprd04.prod.outlook.com (2603:10a6:400:19b:cafe::4c) by CWLP123CA0185.outlook.office365.com (2603:10a6:400:19b::23) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Wed, 20 May 2026 12:10:45 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by AM4PEPF00027A6C.mail.protection.outlook.com (10.167.16.90) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.11 via Frontend Transport; Wed, 20 May 2026 12:10:45 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=JBO01B8SuQ5gfBA1Opg6iMnk8lroLAJSEtzpHSH9TOGbDlWg9awQXj5fqQcI+Oh1hZFvnqH5m3wMUGtlTxCr/acmyZEecCM3ZPDdGloT+OU6aNUwfmf7vnmxtmmIKrqTCmmz6lxHUKpWYY6PQuECHt1m+TQsYFSWZz3DXUQ8la2QySfE0thft+ja8nNceOsi4ZelVz7fpYda9jgCpnfp04UWiOWfnHx6hhaZG4K/+8DthvxYZFSv+ROku3TOzluVufw+8ge7fduOji7FgEuee7GLDBkq9NLi3eY7gIg12qPI1veykYNyV2BctOsKL7U7qk301fNcF4PCWxGj5ItwGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=PH7Uo2zy9pra8reCCR8h+Urfk9bmk3/I2+MutpgGxCI=; b=lqM/gcgRufQ8zFiKQwiC9LEGn979CJbnv5bw95JeBEqiUCLg6Ro+qpzz+XRD9WEtZo9z5kKFOUOvB5Y9TVsa0/X8+beoA1GBnKgtuQ1imfwgITBscOq/hM3QhBxBoJvH1wVF5OB3NquyuZG9DTC56a4vZRa0EQkCP6YyMS6NNzGQeepE0Yr5F81k3UbdlabGVarzPsUau6sY59jG4FlD2VWooYCveRA/nHClXJMELRS5VWA5v4L5GICY+0fXID2V2qhGbXbBR9rYqKI9ZwpwXlvdLS3OmjV8gLMxdWN/vzCZMP3gWmsm4c9d6SkcVMRL7juP78IGLXp6k1UXjXNDog== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=PH7Uo2zy9pra8reCCR8h+Urfk9bmk3/I2+MutpgGxCI=; b=OZAiw5Pi74eQh1j2edJxrO+hDVlbBfxxjRDFL4TuDBa5rbqjjo+kVX8HyB2YCvGn0r1qRw28RhIw+6yb5zzSrYR+TXLaon1O9oRCUr61FNRAzDJZTZz+CwZFAZauRrO88XWk+YmzSHThDWj8kN93XL4aYAU4C/I6/Fu1IOcanyY= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) by DBBPR08MB6300.eurprd08.prod.outlook.com (2603:10a6:10:209::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:09:43 +0000 Received: from DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24]) by DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24%5]) with mapi id 15.21.0048.013; Wed, 20 May 2026 12:09:42 +0000 Date: Wed, 20 May 2026 13:09:40 +0100 From: Alice Carlotti To: binutils@sourceware.org Cc: Richard Earnshaw Subject: [PATCH 4/5] aarch64: Remove disassembly restriction on OP_MOV_Z_Zi Message-ID: References: Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: LO4P265CA0180.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:311::11) To DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DU0PR08MB8255:EE_|DBBPR08MB6300:EE_|AM4PEPF00027A6C:EE_|AS2PR08MB9428:EE_ X-MS-Office365-Filtering-Correlation-Id: 21fcd07f-0c89-4392-03df-08deb668d24c x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|366016|376014|22082099003|18002099003|56012099003|11063799006; X-Microsoft-Antispam-Message-Info-Original: GXk8xmvUH3COdrXe/uRJp1goidv/IyHqBZezA62379uwJZ2z1hE2Q7N9ptsShI0XWLO6t+UBzvOKOlYQqvlIHyR+L3OzgmMOgH3ncJ/6TgYEORknBS2SXT/PAJRI0U8Foaaj+c9KBny384J3BIwf1Q+U1rkp2LvItmTpkciyCEHL81HcrN6cdzKk+KrjP3qCZlFb3a1fTkAOWmqrdtzpN6/i3J0CM/LpnB7VdRMQKSPv12FFkuM+jlbtqp1oV7e2fLqWLrSkHZeufXsYK6fyxD8szSuFaX7mQ+wHxqxpPYyX1l7XSnbRhx0dT3jQVLvMuTIxNFEXdHFMIcGjdl5wo6Sx/EbiDV81lPp+YfTJ1XzDOITKunwcrmh3aODkTpKTXZwZNVc0PQgn5VginB3RcgofOERiK6EIEylyOnGcxqdg77ZHQtk6PTViLVE3WFv0Msb5YrALfsjseRyuCy3Vy/GJO2gTei1+w1A765jO9hNQrjD6uqFTFxDInGPputPc744dKbgIyjwiNhWmLN5srP6A4T0sYslpolwYCB8qf5uNHuY65KrpBEdDqfdW8tCmfEzsP2IrkO3hMzjYAcR40mQ3m1cwfBL8jxN/bDfgDHeXJm04Qf/+VGej7/G/z3s4vPQNfyKINxmWZitbsJKXSpu1vp78RCZihy0KkdNSFCVfHCaokRPlioYb5HbLSeB7 X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DU0PR08MB8255.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(366016)(376014)(22082099003)(18002099003)(56012099003)(11063799006); DIR:OUT; SFP:1101; X-Exchange-RoutingPolicyChecked: RZ07i5GuDx6CwNdWdj0eSi1SKh77Kdt6lGmdRP5HMHdYwcPEIMmTqlHDcWDfxD15XfPjZQ0ekZW+QafXG1MjlRP9KdX8kqX+qS6rszdYmla0ULLF5g/aF4C0AwZXdXAgP5LLwLLRBRvgMYlSwTLC6neZsgkJoV7V79mh3QBtr9FFD0ACXJMZ6MznhIBREKu4ujSEbIfOHGB3hDaz1KTUSfQb3jBAl2W3eNjSRmlDTGf4e3oGDPolkFng4t69fkhq2ePlZ4PQRlOX/2cptsM+gq7kmlnWQ5IMrrSn4bH3A7Msn/Y9llrLxNQyZxF05HruKiG3iXU3kXTL0pJrDrrvug== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6300 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM4PEPF00027A6C.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: cd5603b1-2180-4310-aeea-08deb668ace4 X-Microsoft-Antispam: BCL:0; ARA:13230040|14060799003|376014|36860700016|82310400026|35042699022|1800799024|11063799006|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: Mz5T41j//inkM/A7g23rW5+gfkyJhAxUsCun2ObrWeQ0mz5eOSBQVtdmhO4akM/ttnuq6CxaDfP7vWy++2tZjD8mZDLVe8+iYxmdrcxBr7fPJwSa2QO2twdoZ+qMrzKYb1LuDV55zK3InJhGT1qeJ0s4/zhWeeqrNrZhrQfsJsQ0/G4ycX81sCC3YqfgEK7RPa1RnKlyT+vfV8hEcUSCZcWohel0i+tIARZCVaR8Hb9IVZKzW7/YyWb8/h/4MBV/1Hv4JmP4u779Zh8Pt6Uf4EJh+YbI2Nh2IHMCyrYGlkuVrwrehg/EZLdyfT18PFdLc8Z/8VZYtacVENUONb4PR8b1ht2vynqiys+2QRv3txXzzeSftI5rNRqAsodO3XRZJxbNh2evRd1CkQgom2P1gh8bjuuKjunpi0SOAcqcKDQbCB10faa7APcD4pGl397WtEXWqDOI/shF3oAuapzB0hpzHHRSi1g2L492uWkQ8emDJR1Dt2b3CqibWvSSrVW/QEcwJIZ+JqB/tQ62yWfQBgJKpHoObjrHzY3Bu3wxK4ja6EUIeVbyzoIvaxgoXaS1hs1L42cFDq7la4sI2pDpUoWAQVLo7i6+9HBreW4DbYkVF3UrdEV9J/oDUuGKLKpt1D1apKwKu79UoKb7uzqvID/hnhFtoaVjn4lXLaO3NEq5QQIZjbqaizVnIhL3YC89qyS8yDnogu+cLn7j1J0Tfcrlwm2QWZdydJNmVtcEmTU= X-Forefront-Antispam-Report: CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(14060799003)(376014)(36860700016)(82310400026)(35042699022)(1800799024)(11063799006)(56012099003)(22082099003)(18002099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WhQO22AJIWTfC43MSX/SP9rguRX+r/T2HxTIW4gBaApXXFw30g7ZTbdfKCs8neaU1qbK7XcQpLnuQ/H97m43+hIlojGRiAQkXjTK/AWvKqfhGidtQ0FlFJ/dx08DTF4HkcilZVJtfylH+PziSjz/pF67rgoyBiP9vC9lD1pzJSHF5mbUQ8GT5ITYLGqr7Ls7Wy2j6jom90TKA29g3DU0LfSX/blMlA4E+OHmV/VbNX/8D4h/Jhuuhvj7cJ9XYozcylK4gYGe3PmFfTmUzMp3A33ZYyY+1foXFS56zQAIq3e0vjoYfPeby0ldilF3TBqOV0NJngSx+VuFe+O926X3tWjQbliv0lUcnrhqiKws6SEPkN2zduwi0Fr62i9g3ixG48ex4ia4H8AgcShMTJIELKAJguatpro9RWyCqVbOcYF9hAYd9xv7Ps/+0zk6y4BO X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 12:10:45.3833 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21fcd07f-0c89-4392-03df-08deb668d24c X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A6C.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9428 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, LOCAL_AUTHENTICATION_FAIL_ARC, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Disassembly for the OP_MOV_Z_Zi opcode artificially rejected a zero index value, to indicate that the preferred disassembly uses a different alias. This is more naturally indicated by specifying the other alias as a higher priority. Update the alias priority, and remove the zero check and the now-unused OP_MOV_Z_Zi enum value. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 6d1b414444ae65f76cb4362d1d7e861156fc2759..23e9ec66ee2c2d5d5a97012d959bcb052cad706b 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1325,7 +1325,6 @@ enum aarch64_op OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, - OP_MOV_Z_Zi, OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZS_P_P_P, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index d2e302e610022056eb174344b610a7aedebe85da..98c24a8620e7781bf83fda4c6611454c86586313 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -631,8 +631,8 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode) case A64_OPID_05203800_dup_SVE_Zd_Rn_SP: value = A64_OPID_05203800_dup_SVE_Zd_Rn_SP; break; - case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX: case A64_OPID_05202000_mov_SVE_Zd_SVE_VZn: + case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX: case A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX: value = A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX; break; diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 305ac2981ce421f703d46aabc5852622017ab5d9..ef1e093ed94ef3923399e00fbd4495047b5e4969 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1968,8 +1968,6 @@ do_misc_encoding (aarch64_inst *inst) value = extract_field (FLD_SVE_Zn, inst->value, 0); insert_field (FLD_SVE_Zm_16, &inst->value, value, 0); break; - case OP_MOV_Z_Zi: - break; case OP_MOVM_P_P_P: /* Copy Pd to Pm. */ value = extract_field (FLD_SVE_Pd, inst->value, 0); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 3cbf33db77cd2540ef5298364b7deb18b05575b1..1219bf00e0669517f466c4d7cf6ddc110271b12c 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -36944,7 +36944,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode) value = A64_OPID_05203800_mov_SVE_Zd_Rn_SP; break; case A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX: - value = A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX; + value = A64_OPID_05202000_mov_SVE_Zd_SVE_VZn; break; case A64_OPID_2538c000_dup_SVE_Zd_SVE_ASIMM: value = A64_OPID_2538c000_fmov_SVE_Zd_FPIMM0; @@ -37638,10 +37638,10 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode) case A64_OPID_05203800_mov_SVE_Zd_Rn_SP: value = A64_OPID_05203800_dup_SVE_Zd_Rn_SP; break; - case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX: - value = A64_OPID_05202000_mov_SVE_Zd_SVE_VZn; - break; case A64_OPID_05202000_mov_SVE_Zd_SVE_VZn: + value = A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX; + break; + case A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX: value = A64_OPID_05202000_dup_SVE_Zd_SVE_Zn_INDEX; break; case A64_OPID_2538c000_fmov_SVE_Zd_FPIMM0: diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index f86c5026cf7ccf2935be67cbedb274366e6c04e0..3723defe5e019d9188b150e16f645b0551421688 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2729,11 +2729,6 @@ do_misc_decoding (aarch64_inst *inst) return (extract_field (FLD_SVE_Zn, inst->value, 0) == extract_field (FLD_SVE_Zm_16, inst->value, 0)); - case OP_MOV_Z_Zi: - /* Index must be nonzero. */ - value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); - return value > 0 && value != (value & -value); - case OP_MOVM_P_P_P: return (extract_field (FLD_SVE_Pd, inst->value, 0) == extract_field (FLD_SVE_Pm, inst->value, 0)); diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index b9a632300df5eacbb1c608f4757100aa425fe114..a6d43a13f4cfa74447203dc81c1e895e4b4c0440 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -461,7 +461,6 @@ static const enum aarch64_opcode_idx op_enum_table [] = A64_OPID_0520c000_mov_SVE_Zd_SVE_Pg4_10_SVE_Zn, A64_OPID_05202000_mov_SVE_Zd_SVE_VZn, A64_OPID_04603000_mov_SVE_Zd_SVE_Zn, - A64_OPID_05202000_mov_SVE_Zd_SVE_Zn_INDEX, A64_OPID_25004210_mov_SVE_Pd_SVE_Pg4_10_SVE_Pn, A64_OPID_25c04000_movs_SVE_Pd_SVE_Pn, A64_OPID_25404000_movs_SVE_Pd_SVE_Pg4_10_SVE_Pn, diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 0a30e720d9dee56fd090c35cc70a09db7f1e7b4b..c58f4dd7972468dc81af1168f38fabab182069ed 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5268,11 +5268,11 @@ const struct aarch64_opcode aarch64_opcode_table[] = _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0), _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0), _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0), - _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), + _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_P1 | F_MISC, 0), _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0), _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0), _SVE_INSN ("mov", 0x25804000, 0xfff0c210, sve_misc, OP_MOV_PN_PN, OP2 (SVE_PNd, SVE_PNn), OP_SVE_BB, F_ALIAS | F_PSEUDO | F_MISC, 0), - _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0), + _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS, 0), _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0), _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0), _SVE_INSNC ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0), From patchwork Wed May 20 12:10:00 2026 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alice Carlotti X-Patchwork-Id: 135335 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 05DA04BB58A2 for ; Wed, 20 May 2026 12:12:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 05DA04BB58A2 Authentication-Results: sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=KhgtetYg; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=KhgtetYg X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11010009.outbound.protection.outlook.com [52.101.84.9]) by sourceware.org (Postfix) with ESMTPS id 306E04BB58FE for ; Wed, 20 May 2026 12:11:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 306E04BB58FE Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 306E04BB58FE Authentication-Results: sourceware.org; arc=fail smtp.remote-ip=52.101.84.9 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1779279083; cv=fail; b=V7hi3ymE0zBbjREm7ysK6MXpc0TZkJFqFpzwckR39Xfpad2EYOMGute9na5NwONAD4Rnw181gqcL7bxadlziFoUqj+b3AuDspbwRceFV7c/Zq6B+4qQDHd1cbV7a0bBb8aH1OUcV8qYs5zGEwUILvIDAn+GrMJ6j/jLDVlX89q4= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1779279083; c=relaxed/simple; bh=8MMHMkEHj4xbt7qWThKYlgP+EPT33fvgLUyDj/ssYQY=; h=DKIM-Signature:DKIM-Signature:Date:From:To:Subject:Message-ID: MIME-Version; b=v48wgPbUYRfkpmT8/IqRRuHwp0dvuxlVD0ruDgDGNJqMtkYGVWrivEtGqdCtn8Ps7mcoQOjYRYJ/ilN0DoXb9fJBx/Pql83ms90hF1IGxdDEHBK2BfkcHvDaKoOYVOfVgdAqiWUn8M6j+9EVRPt+dapslT5E2d4TDSXtCP4AosI= ARC-Authentication-Results: i=3; sourceware.org; dkim=pass (1024-bit key, unprotected) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=KhgtetYg; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.a=rsa-sha256 header.s=selector1 header.b=KhgtetYg DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 306E04BB58FE ARC-Seal: i=2; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=fail; b=eYaiOGxvk8jxas09gWL8cPTSeNSVt4x5EpIYUQeYwK/NmgwuFOJUEBkGRuq1xwgMhlZsrAjgED8iMvPPQ+cfuuTJwL0GnSaWguJoJtV/bR6Wyk2timNffFUd2kZHstjmBRYn6LNqoOI40Xo7dII+AcPW/zIpYFO9jCMi+WhWl3SSau4urVZ6PUyrKj8Qn+7UfMrDLqVtK/m+otOal9vr2AMIzQDHPrGiZGUjsh1kEs0QU0ze72+hPVxLKDUVfjGRBvBYCRKJAphw5ULRjkNof17sk4MQVhCy8F5z1DZtYdCoer3ITG+oK+KayieY8FaPg+XVBd5oG9BIkClKMBa6Mw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ivh75r0ysR2laqlNd00sVBf2o+QkGTodZrHKlF9DLSc=; b=HYWyUL0vKAUTL5hxwXyvb2UmZi5e9ezz1wmxnSywHNbEQY2qAfNmJDoKrQrzJa7SgDdfkh0GFklRYRW3JUiWXixtTRjP3tvGvDvTCbysG3q8/AWREf8/XN28z0QCDRDeBAutb2FwM7aRJO4mhzgcsYj7YYEVKJdE3M2+ZgNb+r8CbOba1HNawhO/CHHA8DxXgDSreEAKEznEnEJpj4hTj4jMer9plwle9+LoGmVOOilgaLEHJ27Qkw55eT2ZeoaEKY8Lt0p1hJj30TlEdX/v0k10SFMBdqgR6re8Zazqx3d9M8lzK4SiVAMXZfwfRzKCsx4w2+i9wpsrpoULj7XVcg== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 4.158.2.129) smtp.rcpttodomain=sourceware.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=arm.com; arc=fail (48) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ivh75r0ysR2laqlNd00sVBf2o+QkGTodZrHKlF9DLSc=; b=KhgtetYgZrgdeZTqGoZVxLb52AjDj/BJcMm9NoCcE8jYdvXllEHJG7DF4EbelBHw7rbsk66LrG1GvSwDXk+peEUqLhegZDYJvqMXRhvomoCMSlO0Pfty/jTFfGlkfZoihHvNnPT0j0eh7CLwx3qv9forDayTeJMDPV5VOroKxH0= Received: from DU2P251CA0001.EURP251.PROD.OUTLOOK.COM (2603:10a6:10:230::12) by DU0PR08MB7922.eurprd08.prod.outlook.com (2603:10a6:10:3c9::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:11:08 +0000 Received: from DU2PEPF00028D0A.eurprd03.prod.outlook.com (2603:10a6:10:230:cafe::86) by DU2P251CA0001.outlook.office365.com (2603:10a6:10:230::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.48.14 via Frontend Transport; Wed, 20 May 2026 12:11:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 4.158.2.129) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=arm.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 4.158.2.129 as permitted sender) receiver=protection.outlook.com; client-ip=4.158.2.129; helo=outbound-uk1.az.dlp.m.darktrace.com; pr=C Received: from outbound-uk1.az.dlp.m.darktrace.com (4.158.2.129) by DU2PEPF00028D0A.mail.protection.outlook.com (10.167.242.170) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.25.13 via Frontend Transport; Wed, 20 May 2026 12:11:04 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Cd2BBpaladywEWpscnMRK+Ex0c6OR37ua9MgHQ/mxqGVTMslnDngGoUovGxnPcJI0kGMnIz0y94yxK4u2DuuDIHECls+bdKrl0h1E6evxiBMrXEZkTJM2K5tKvCalP2mubAXmxhxfUW4Qlt45mdxOjc4Mc5YtUMsNWFQs1/EwiWJoFoNRwKWMhlM94VGY/HAC+Hxz2dHHAsXcud7suLHDDCZcjHaRLtlzu5poTQ4X05y6a5NB4+0wshKD4AkwYk11+jfg5YjpEy8Bb8n1WSJxP7PObiVQZMpJ5TNJK19AvwgcbIvmDB8DX/KrrH+jNWfMQ82wTH0DDwZdSt0yYx3KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=ivh75r0ysR2laqlNd00sVBf2o+QkGTodZrHKlF9DLSc=; b=bwqwbmPqEDUWhfU01hDCobJOPh1g/Rh1N9z8oAfMTMsMVkQ248LsmRO48uNLaFpO5+TIqL2HR9F9vkZJVNUOw8NZCUVu+6DSpHSqmzN0/IZQsWNXoSYbGS8QAi0xO2TtXKK9zNyf9R89Q0LP2eBexh2AMz1rtl/g2c7a7YjUzm2L2JT6NuUboYfd6FMR7kc5+gLaCTdT9D4xVYmOSLwgrifkiUbs/R3YUfZFQ6NqVFSG3mn5aMalSVZyeN0CIgdz/tejdv19DLCqiMwOsKvPlmh5QFgsGThsyK7lvzNAoxQPrkvnGXW04RO6FdLMbx6XiFHU+1PrNiKi5s+e4xjDBg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arm.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ivh75r0ysR2laqlNd00sVBf2o+QkGTodZrHKlF9DLSc=; b=KhgtetYgZrgdeZTqGoZVxLb52AjDj/BJcMm9NoCcE8jYdvXllEHJG7DF4EbelBHw7rbsk66LrG1GvSwDXk+peEUqLhegZDYJvqMXRhvomoCMSlO0Pfty/jTFfGlkfZoihHvNnPT0j0eh7CLwx3qv9forDayTeJMDPV5VOroKxH0= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) by DBBPR08MB6300.eurprd08.prod.outlook.com (2603:10a6:10:209::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.48.14; Wed, 20 May 2026 12:10:02 +0000 Received: from DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24]) by DU0PR08MB8255.eurprd08.prod.outlook.com ([fe80::281d:22ec:87cd:8a24%5]) with mapi id 15.21.0048.013; Wed, 20 May 2026 12:10:02 +0000 Date: Wed, 20 May 2026 13:10:00 +0100 From: Alice Carlotti To: binutils@sourceware.org Cc: Richard Earnshaw Subject: [PATCH 5/5] aarch64: Replace FLD_* macros in do_misc_{en|de}coding Message-ID: <93a453e3-789a-5792-7e73-c6abc97df283@e124511.cambridge.arm.com> References: Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: LO4P265CA0202.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:318::8) To DU0PR08MB8255.eurprd08.prod.outlook.com (2603:10a6:10:411::9) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DU0PR08MB8255:EE_|DBBPR08MB6300:EE_|DU2PEPF00028D0A:EE_|DU0PR08MB7922:EE_ X-MS-Office365-Filtering-Correlation-Id: 1aae7f3f-2a86-4b0a-b9e5-08deb668ddf6 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; ARA:13230040|1800799024|366016|376014|22082099003|18002099003|56012099003|3023799007|11063799006; X-Microsoft-Antispam-Message-Info-Original: a0tE7YJiZ3/DEQdiu6DxYuacF5P78xEUuqJzQQdB7S0P1+CdFnGivZ0dwV2q5Z3jqwgfA99sM6+wmYM4NoLW7PdLwDZAgt4262UApu2KHPtSd9GwrGAtIP2LUixhT3qvmm23dPO/Ci211o3FuH+nzGCjTxbwzs3AkW2jTlW7pqemT4J0Q3O3ekULFqMJsPSh+1iu56vhsZyzGPJL9fC5PuLPiPRnOfzyYpYjQzz65VtJIC/s0M4i0ksU7958RfXDaWbrBnA761tbrBaN7DAiOv4OKgT/k90yKUneqw5Kk+w3oqiDPre0YhqCloMQybi2ODACslwXdltowkHe1D9zcbSf/uW44yDXQDv47p7+6EXWPQbjfGqTAzaLq8MecGlS44dLA1kJXmwj41ZTA9y4Jj10dcxVJG37tIbbuiqciaVQBq4R/+33g6UPX6lOFoUkiU1zMq3qqlyHoPoVjQHSjjmnEIR6l7Wahg5LdMAWq235D92oDPZ0vv1v+8e4JZpiBKXsfeleQ/Gqc8zDtcl+RiNrMeiwvXrKq+4Ok89L9nGtU+YgXGD/XwqPGngEZq5fYpj9zCLCDOLQvyv718fzOCG9iJ8OD9iQGKFjgbmkvfRwgJfreaC1JJVFC5pcy7Z+mA+z918XJBzpGj4Dh0unDaYUPlFVE4E8EzCOs5vv9xlrBYItDjXnbIKUDJDOhSNB X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DU0PR08MB8255.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(1800799024)(366016)(376014)(22082099003)(18002099003)(56012099003)(3023799007)(11063799006); DIR:OUT; SFP:1101; X-Exchange-RoutingPolicyChecked: d2CjJ/umvLebp8H9ViGH+k+rqq6b9lWwrRODNm23WAzHqYUWfMxPwunN9Uu/ocYEBygB6mQZx4hTZWBhvIHHpd9ivJpLsMNZORP0xX4XjUGK+P35nMlQVRjOG0D0y04ECIb3m8kSjJDux3Ciy609iQxvebmhw6vPCX8vdEWEd3rGKO7ZtFEcL5Hn83BUp6AsZAT1NVrjNd6iEgyRv8WivhZA86JfFEANLDw19K1L12RXxRzis844ebzXZdUtnVlQMwo5PpLNcILapdHcAhpihdLuRZcoxKMpSyhQ/+9FwDh2j6iAkG83fnYSN540bSajtTrmvQZ9OsDZidWnLP+BBQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB6300 X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DU2PEPF00028D0A.eurprd03.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 37c60265-7886-4ec1-577f-08deb668b8c3 X-Microsoft-Antispam: BCL:0; ARA:13230040|14060799003|1800799024|82310400026|36860700016|376014|35042699022|56012099003|22082099003|18002099003|11063799006|3023799007; X-Microsoft-Antispam-Message-Info: +Bsoofu6YXnyW8csQ9I+Zp4p4vv5Pkt+NX8fcevlEaCeiICnxjqGZuP63FfRq84RDe4bWIslOqteGDlfunBX0Fryee/DAjEYbvrY0TtVrwT4S3zRUlftViC37fpbOhhJb4FSag0ZU5AsnH2JVQw2i188cLjvnphiNRcWNmah8OA3zAJ5amdO2IFEz7cd2bS65Bi+0TzwzGjzJGxasyrhaVyJ4+NLzA9gxURGka5mglki9+WN2S1Eex7Y3nBhhE7X+Kl0ddDd5kwE8gxvPKiGHzh1pbDP1Rsarl32iuC4uRmvIPsFxemypQiRRn2VcMQ1jak6aJkx2TuzUCCiirgkGc09kyv5daPCuDnKdCBKjL9YtoZwnXLfjzw6F2pF8etGo+vNU+HKlm9RYn0INcSHklKy3BdAjly0JKhnLrHmHxGaHJQeWAcLhcdNUwzJogyzyrg8ADNVJwUxYxP0NbH5MWqxNquvlgBVqdM6eskRcv1abLlNjTz9+AbP7qsLjFrzE669iIpSUsmeSRfi4p63dCxoQjT/Hwu0rxX94rCrwCl27z7VctQI4E58Zs1S7C2J/N5V+F2Pven1RZaNwcBqnPTcLKPDK3E1UQq3moY5jliRZ4yFB23FYwYWyDDWnNvNqzLlphl72/7/f6KdepJ76eSeJr/ts+wpoS5H7xbaQEelXNh/w/6I8OGYx4lWeCACEsctrej1cUJBPQcur6IifUYJqFfGARQ6PVoL+HtKJvs= X-Forefront-Antispam-Report: CIP:4.158.2.129; CTRY:GB; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:outbound-uk1.az.dlp.m.darktrace.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(14060799003)(1800799024)(82310400026)(36860700016)(376014)(35042699022)(56012099003)(22082099003)(18002099003)(11063799006)(3023799007); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eA3CiZGpR7vSIlAjnr6wVH8qfxPkyTsY1fH9qMxvhpgh3/1aNiMHNtaZDtTEa3iV+iJNYarxi2oGoga0vfF5C+YCbmwKQezWhZIEzMBO66HM5vhGrhY2C3uLLhgg3klcoF6ebcfJ0AnaHQLY8yg8tH480MtsWTgRoejx1JR48SfIqjIign4lD0jftrZrZKRX8gjrEE4Cu2n1hAIcRraEuqPBGys6qO/CyE4W2zjr/PgtdiQ4EhuhIwLfA0QwyhQGAWZaKu3p1VHUQ43YwyIf5+LiBvp6hnTCbwkAWO4KRMqRyCi7rPaQEkeHIon7zdAuxP5CiZjT7oNglyxPTR7fX39vwDYJfxcRuTk7UJp17R6jt/WKDlb385b0Cn1ngKJXvr/gRQQ4weFTOHjsPrB6JkgpWds1V3EkG/ZPAX4jjb1KYC0ani1BMwccvfz/L6jE X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 May 2026 12:11:04.9505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1aae7f3f-2a86-4b0a-b9e5-08deb668ddf6 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[4.158.2.129]; Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D0A.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7922 X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FORGED_SPF_HELO, GIT_PATCH_0, KAM_LOTSOFHASH, LOCAL_AUTHENTICATION_FAIL_ARC, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces~patchwork=sourceware.org@sourceware.org Replace the macros with explicit AARCH64_FIELD calls, and extend the comments to clarify which aliased instructions are involved. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index ef1e093ed94ef3923399e00fbd4495047b5e4969..188cdd8a4770190f6a516aa3acc5a32ca662e207 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1948,42 +1948,42 @@ do_misc_encoding (aarch64_inst *inst) case OP_MOV_P_P: case OP_MOV_PN_PN: case OP_MOVS_P_P: - /* Copy Pn to Pm and Pg. */ - value = extract_field (FLD_SVE_Pn, inst->value, 0); - insert_field (FLD_SVE_Pm, &inst->value, value, 0); - insert_field (FLD_SVE_Pg4_10, &inst->value, value, 0); + /* ORR/ORRS alias. Copy Pn to Pm and Pg. */ + value = extract_field (AARCH64_FIELD (5, 4), inst->value, 0); + insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0); + insert_field (AARCH64_FIELD (10, 4), &inst->value, value, 0); break; case OP_MOV_Z_P_Z: - /* Copy Zd to Zm. */ - value = extract_field (FLD_SVE_Zd, inst->value, 0); - insert_field (FLD_SVE_Zm_16, &inst->value, value, 0); + /* SEL alias. Copy Zd to Zm. */ + value = extract_field (AARCH64_FIELD (0, 5), inst->value, 0); + insert_field (AARCH64_FIELD (16, 5), &inst->value, value, 0); break; case OP_MOV_Z_V: - /* Fill in the zero immediate. */ + /* DUP alias. Fill in the zero index and element size. */ insert_fields (&inst->value, 1 << aarch64_get_variant (inst), 0, - 2, FLD_imm5, FLD_SVE_tszh); + 2, AARCH64_FIELD (16, 5), AARCH64_FIELD (22, 2)); break; case OP_MOV_Z_Z: - /* Copy Zn to Zm. */ - value = extract_field (FLD_SVE_Zn, inst->value, 0); - insert_field (FLD_SVE_Zm_16, &inst->value, value, 0); + /* ORR alias. Copy Zn to Zm. */ + value = extract_field (AARCH64_FIELD (5, 5), inst->value, 0); + insert_field (AARCH64_FIELD (16, 5), &inst->value, value, 0); break; case OP_MOVM_P_P_P: - /* Copy Pd to Pm. */ - value = extract_field (FLD_SVE_Pd, inst->value, 0); - insert_field (FLD_SVE_Pm, &inst->value, value, 0); + /* SEL alias. Copy Pd to Pm. */ + value = extract_field (AARCH64_FIELD (0, 4), inst->value, 0); + insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0); break; case OP_MOVZS_P_P_P: case OP_MOVZ_P_P_P: - /* Copy Pn to Pm. */ - value = extract_field (FLD_SVE_Pn, inst->value, 0); - insert_field (FLD_SVE_Pm, &inst->value, value, 0); + /* AND/ANDS alias. Copy Pn to Pm. */ + value = extract_field (AARCH64_FIELD (5, 4), inst->value, 0); + insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0); break; case OP_NOTS_P_P_P_Z: case OP_NOT_P_P_P_Z: - /* Copy Pg to Pm. */ - value = extract_field (FLD_SVE_Pg4_10, inst->value, 0); - insert_field (FLD_SVE_Pm, &inst->value, value, 0); + /* EOR/EORS alias. Copy Pg to Pm. */ + value = extract_field (AARCH64_FIELD (10, 4), inst->value, 0); + insert_field (AARCH64_FIELD (16, 4), &inst->value, value, 0); break; default: break; } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 3723defe5e019d9188b150e16f645b0551421688..3b3ad7615de9eec3a25aaaa03a7ebb4cbc64aabc 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2712,36 +2712,46 @@ do_misc_decoding (aarch64_inst *inst) case OP_MOV_P_P: case OP_MOVS_P_P: - value = extract_field (FLD_SVE_Pn, inst->value, 0); - return (value == extract_field (FLD_SVE_Pm, inst->value, 0) - && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); + /* ORR/ORRS alias with Pn == Pm == Pg. */ + value = extract_field (AARCH64_FIELD (5, 4), inst->value, 0); + return (value == extract_field (AARCH64_FIELD (16, 4), inst->value, 0) + && value == extract_field (AARCH64_FIELD (10, 4), + inst->value, 0)); case OP_MOV_Z_P_Z: - return (extract_field (FLD_SVE_Zd, inst->value, 0) - == extract_field (FLD_SVE_Zm_16, inst->value, 0)); + /* SEL alias with Zd == Zm. */ + return (extract_field (AARCH64_FIELD (0, 5), inst->value, 0) + == extract_field (AARCH64_FIELD (16, 5), inst->value, 0)); case OP_MOV_Z_V: - /* Index must be zero. */ - value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5); - return value > 0 && value <= 16 && value == (value & -value); + /* DUP alias with zero index. Index and size use a triangle encoding, + and we already know that one of the bottom 5 bits is nonzero, so we + just need to check that the bitcount is at most 1. */ + value = extract_fields (inst->value, 0, 2, AARCH64_FIELD (22, 2), + AARCH64_FIELD (16, 5)); + return value == (value & -value); case OP_MOV_Z_Z: - return (extract_field (FLD_SVE_Zn, inst->value, 0) - == extract_field (FLD_SVE_Zm_16, inst->value, 0)); + /* ORR alias with Zn == Zm. */ + return (extract_field (AARCH64_FIELD (5, 5), inst->value, 0) + == extract_field (AARCH64_FIELD (16, 5), inst->value, 0)); case OP_MOVM_P_P_P: - return (extract_field (FLD_SVE_Pd, inst->value, 0) - == extract_field (FLD_SVE_Pm, inst->value, 0)); + /* SEL alias with Pd == Pm. */ + return (extract_field (AARCH64_FIELD (0, 4), inst->value, 0) + == extract_field (AARCH64_FIELD (16, 4), inst->value, 0)); case OP_MOVZS_P_P_P: case OP_MOVZ_P_P_P: - return (extract_field (FLD_SVE_Pn, inst->value, 0) - == extract_field (FLD_SVE_Pm, inst->value, 0)); + /* AND/ANDS alias with Pn == Pm. */ + return (extract_field (AARCH64_FIELD (5, 4), inst->value, 0) + == extract_field (AARCH64_FIELD (16, 4), inst->value, 0)); case OP_NOTS_P_P_P_Z: case OP_NOT_P_P_P_Z: - return (extract_field (FLD_SVE_Pm, inst->value, 0) - == extract_field (FLD_SVE_Pg4_10, inst->value, 0)); + /* EOR/EORS alias with Pm == Pg. */ + return (extract_field (AARCH64_FIELD (16, 4), inst->value, 0) + == extract_field (AARCH64_FIELD (10, 4), inst->value, 0)); default: return 0; diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index a0553f8fd940c1a0e994bc4a0c8dd945fdb96494..772f485f50ab9bd9d32f53b5f2f87e6034a74682 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -88,13 +88,6 @@ typedef struct aarch64_field aarch64_field; #define FLD_SVE_M_4 AARCH64_FIELD( 4, 1) #define FLD_SVE_M_14 AARCH64_FIELD(14, 1) #define FLD_SVE_M_16 AARCH64_FIELD(16, 1) -#define FLD_SVE_Pd AARCH64_FIELD( 0, 4) -#define FLD_SVE_Pg4_10 AARCH64_FIELD(10, 4) -#define FLD_SVE_Pm AARCH64_FIELD(16, 4) -#define FLD_SVE_Pn AARCH64_FIELD( 5, 4) -#define FLD_SVE_Zd AARCH64_FIELD( 0, 5) -#define FLD_SVE_Zm_16 AARCH64_FIELD(16, 5) -#define FLD_SVE_Zn AARCH64_FIELD( 5, 5) #define FLD_SVE_imm4 AARCH64_FIELD(16, 4) #define FLD_SVE_imm6 AARCH64_FIELD(16, 6) #define FLD_SVE_msz AARCH64_FIELD(10, 2)