From patchwork Mon Jan 3 20:01:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 49488 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C6BC23858429 for ; Mon, 3 Jan 2022 20:02:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C6BC23858429 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1641240169; bh=/9/EWbJZFMg1wRq/d2RlZkz/6Jn6E7h8aYqpyftJaC8=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=xGVm6M7+m7mvmZ+z7kFhFVDeD2TVgta9rC4krSXw/PIIHBcuKc7dYaJ4IRzrvBUQS 4vp/YEhEhv60VtJ29poL8hgphETV87+2AR/ojlmK6kqTxIeWv4vbmLVEMRbX9bRx8T 7WGo44+Dq3Y/ybGmfvJ2vxnKGI5uV1JL8TIJ0dDE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-qt1-x82d.google.com (mail-qt1-x82d.google.com [IPv6:2607:f8b0:4864:20::82d]) by sourceware.org (Postfix) with ESMTPS id D8748385840E for ; Mon, 3 Jan 2022 20:01:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D8748385840E Received: by mail-qt1-x82d.google.com with SMTP id f9so31599140qtk.4 for ; Mon, 03 Jan 2022 12:01:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=/9/EWbJZFMg1wRq/d2RlZkz/6Jn6E7h8aYqpyftJaC8=; b=Orf8+aA+9nJzt7S7aFO47pDUWpotq0KIYhp4QgA1aA4s/i+esj8TBASX4jmTErzhS4 iDt+zOxmPomgTb65jJ972ESxrHAaUfgExGKjDIGUwLONkRreqNaMxXuKUcejCw4mtzco ptoLIfSQiIqxO5DrQYsyqPJKbUZml0ENHE5CG9O0bqlnm8FIKjE93dLRUxT2MlPpjDUx 4KhgGQ/AqDRwInT1AWtgIN2QNEQoPdCHShVYUvHXbLCD4O7tMq1dJ/fKqpYKxQmgisP9 Sdb3d6maV6tqJmby1Zvw0DPVCv/CZWDGhLC56q8y9515qo5zrjeoduK4wvB2K2yVAOGm j0ww== X-Gm-Message-State: AOAM5331XwjmBZLCunlcwxs29v37Anz77AKRY6C61/UKj1J5NG7i2nYI 0oZS+TA417DrL5HaVKyPVXx0shOBFVGpCJG4kClkUI+/w8QxOw== X-Google-Smtp-Source: ABdhPJxSkwiDUjKbBp3UUytB9YyuxPyTddTyfgKmJKRfYAFU0U1ucafRFDmcSJQw3mZlJKpjtknWSyG0YGx39I1ihSs= X-Received: by 2002:a05:622a:24a:: with SMTP id c10mr41305836qtx.209.1641240096873; Mon, 03 Jan 2022 12:01:36 -0800 (PST) MIME-Version: 1.0 Date: Mon, 3 Jan 2022 21:01:25 +0100 Message-ID: Subject: [PATCH] i386: Always enable mov patterns [PR103894] To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Middle end tries to generate V4QImode moves to implement V2QImode inserts and calls emit_move_multi_word when V4QImode moves are unavailable, as is the case with 32-bit vector moves, constrainted with TARGET_SSE2. However, this triggers gcc_assert (mode_size >= UNITS_PER_WORD); in emit_move_multi_word, since mode_size of V4QImode operand is less than UNITS_PER_WORD of 64-bit targets. The patch unconditionally enables 32-bit vector moves to match 16-bit vector moves. This also enables implementation of 32-bit vector logic operations with GPR in a follow-up patch. 2022-01-03 Uroš Bizjak gcc/ChangeLog: PR target/103894 * config/i386/mmx.md (mov): Remove TARGET_SSE2 constraint. (mov_internal): Ditto. (*push_rex64): Ditto. (movmisalign): Ditto. (*push_rex64 splitter): Enable for TARGET_64BIT && TARGET_SSE. (*push2): Remove insn pattern. gcc/testsuite/ChangeLog: PR target/103894 * gcc.target/i386/pr103894.c: New test. Patch was bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 67b02661243..5b33d3cfc1c 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -250,7 +250,7 @@ (define_expand "mov" [(set (match_operand:V_32 0 "nonimmediate_operand") (match_operand:V_32 1 "nonimmediate_operand"))] - "TARGET_SSE2" + "" { ix86_expand_vector_move (mode, operands); DONE; @@ -261,8 +261,7 @@ "=r ,m ,v,v,v,m,r,v") (match_operand:V_32 1 "general_operand" "rmC,rC,C,v,m,v,v,r"))] - "TARGET_SSE2 - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + "!(MEM_P (operands[0]) && MEM_P (operands[1]))" { switch (get_attr_type (insn)) { @@ -321,29 +320,19 @@ (define_insn "*push2_rex64" [(set (match_operand:V_32 0 "push_operand" "=X,X") (match_operand:V_32 1 "nonmemory_no_elim_operand" "rC,*v"))] - "TARGET_SSE2 && TARGET_64BIT" + "TARGET_64BIT" "@ push{q}\t%q1 #" [(set_attr "type" "push,multi") (set_attr "mode" "DI")]) -(define_insn "*push2" - [(set (match_operand:V_32 0 "push_operand" "=<,<") - (match_operand:V_32 1 "general_no_elim_operand" "rC*m,*v"))] - "TARGET_SSE2 && !TARGET_64BIT" - "@ - push{l}\t%1 - #" - [(set_attr "type" "push,multi") - (set_attr "mode" "SI")]) - (define_split [(set (match_operand:V_32 0 "push_operand") (match_operand:V_32 1 "sse_reg_operand"))] - "TARGET_SSE2 && reload_completed" + "TARGET_64BIT && TARGET_SSE && reload_completed" [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) - (set (match_dup 0) (match_dup 1))] + (set (match_dup 0) (match_dup 1))] { operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (mode))); /* Preserve memory attributes. */ @@ -353,7 +342,7 @@ (define_expand "movmisalign" [(set (match_operand:V_32 0 "nonimmediate_operand") (match_operand:V_32 1 "nonimmediate_operand"))] - "TARGET_SSE2" + "" { ix86_expand_vector_move (mode, operands); DONE; diff --git a/gcc/testsuite/gcc.target/i386/pr103894.c b/gcc/testsuite/gcc.target/i386/pr103894.c new file mode 100644 index 00000000000..69c81046930 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103894.c @@ -0,0 +1,13 @@ +/* PR target/103894 */ +/* { dg-do compile } */ +/* { dg-options "-msse -mno-sse2" } */ + +typedef unsigned char __attribute__((__vector_size__ (32))) V; +typedef unsigned char __attribute__((__vector_size__ (2))) W; + +V v; + +W foo (W w) +{ + return __builtin_shufflevector (v, w, 3, 4); +}