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Thu, 23 Dec 2021 02:12:22 +0000 (GMT) Subject: [PATCH] rs6000: Move the hunk affecting VSX/ALTIVEC ahead [PR103627] To: GCC Patches Message-ID: Date: Thu, 23 Dec 2021 10:12:19 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Hj2z3BOXj_KnyCoC7dfFUvwtaq3tKlST X-Proofpoint-GUID: yE1XMYNkYYDEgKkYKdh6WzsVGoZP3Bgx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-22_09,2021-12-22_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 mlxscore=0 priorityscore=1501 adultscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112230008 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Kewen.Lin via Gcc-patches" From: "Kewen.Lin" Reply-To: "Kewen.Lin" Cc: Michael Meissner , Bill Schmidt , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, There is one hunk checking for functions with target attribute/pragma have the same altivec abi as the one of main_target_opt, it can update both VSX and ALTIVEC flags. Meanwhile, we have some codes to check or warn for some isa flags related to VSX and ALTIVEC, that sit where the mentioned hunk is proposed to be moved to in this patch. Since the flags update in the mentioned hunk happen behind those adjustments based on VSX and ALTIVEC flags, it can cause the incompatibility and result in unexpected behaviors, the associated test case is one typical case. Besides, we already have the code which sets TARGET_FLOAT128_TYPE and lays after where the hunk is moved to, and OPTION_MASK_FLOAT128_KEYWORD will rely on TARGET_FLOAT128_TYPE, so this patch just simply removes them. Bootstrapped and regtested on powerpc64le-linux-gnu P9 and powerpc64-linux-gnu P8 and P7. Is it ok for trunk? BR, Kewen ----- gcc/ChangeLog: PR target/103627 * config/rs6000/rs6000.c (rs6000_option_override_internal): Move the hunk affecting VSX and ALTIVEC to the appropriate place. gcc/testsuite/ChangeLog: PR target/103627 * gcc.target/powerpc/pr103627-3.c: New test. --- gcc/config/rs6000/rs6000.c | 21 ++++++++----------- gcc/testsuite/gcc.target/powerpc/pr103627-3.c | 20 ++++++++++++++++++ 2 files changed, 29 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr103627-3.c -- 2.27.0 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ec3b46682a7..0b09713b2f5 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3955,6 +3955,15 @@ rs6000_option_override_internal (bool global_init_p) else if (TARGET_ALTIVEC) rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks); + /* Disable VSX and Altivec silently if the user switched cpus to power7 in a + target attribute or pragma which automatically enables both options, + unless the altivec ABI was set. This is set by default for 64-bit, but + not for 32-bit. Don't move this before the above code using ignore_masks, + since it can reset the cleared VSX/ALTIVEC flag again. */ + if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) + rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC) + & ~rs6000_isa_flags_explicit); + if (TARGET_CRYPTO && !TARGET_ALTIVEC) { if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO) @@ -4373,18 +4382,6 @@ rs6000_option_override_internal (bool global_init_p) } } - /* Disable VSX and Altivec silently if the user switched cpus to power7 in a - target attribute or pragma which automatically enables both options, - unless the altivec ABI was set. This is set by default for 64-bit, but - not for 32-bit. */ - if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi) - { - TARGET_FLOAT128_TYPE = 0; - rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC - | OPTION_MASK_FLOAT128_KEYWORD) - & ~rs6000_isa_flags_explicit); - } - /* Enable Altivec ABI for AIX -maltivec. */ if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX) diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-3.c b/gcc/testsuite/gcc.target/powerpc/pr103627-3.c new file mode 100644 index 00000000000..9df2b73fe85 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-3.c @@ -0,0 +1,20 @@ +/* There are no error messages for either LE or BE 64bit. */ +/* { dg-require-effective-target be }*/ +/* { dg-require-effective-target ilp32 } */ +/* We don't have one powerpc.*_ok for Power6, use altivec_ok conservatively. */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-mdejagnu-cpu=power6" } */ + +/* Verify compiler emits error message instead of ICE. */ + +#pragma GCC target "cpu=power10" +int +main () +{ + float *b; + __vector_quad c; + __builtin_mma_disassemble_acc (b, &c); + /* { dg-error "'__builtin_mma_disassemble_acc' requires the '-mmma' option" "" { target *-*-* } .-1 } */ + return 0; +} +