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Wed, 8 Apr 2026 02:36:24 GMT Received: from smtprelay06.fra02v.mail.ibm.com ([9.218.2.230]) by ppma12.dal12v.mail.ibm.com (PPS) with ESMTPS id 4dcmg7wpwx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 08 Apr 2026 02:36:24 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 6382aLQv23724360 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 8 Apr 2026 02:36:21 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E83EA2004B; Wed, 8 Apr 2026 02:36:20 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5543120043; Wed, 8 Apr 2026 02:36:18 +0000 (GMT) Received: from li-4c4c4544-0036-3810-8050-b5c04f423534.ibm.com.com (unknown [9.39.20.122]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Wed, 8 Apr 2026 02:36:18 +0000 (GMT) From: Avinash Jayakar To: gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org, jskumari@linux.ibm.com, meissner@linux.ibm.com, dje.gcc@gmail.com, linkw@gcc.gnu.org, jeevitha@linux.ibm.com, kishan@linux.ibm.com, mmatti@linux.ibm.com, vijay@linux.ibm.com, Avinash Jayakar Subject: [PATCH] rs6000: Add long long support and fix 32 bit failures for __builtin_ppc_atomic_cas_local [PR124800] Date: Wed, 8 Apr 2026 08:06:15 +0530 Message-ID: <20260408023615.653320-1-avinashd@linux.ibm.com> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA4MDAxOSBTYWx0ZWRfXyhNGsLjX8CxU qfhvt32DFwf3EXRbinhWhnc6nzc2/nZoZzKVsjgBQyFLlE+A0/+fHIBppD4SElyb1invG4wxJA6 5+YpfCmxGmokoQdlyf6xtu2Cz3bgXcpPuqm5DdRnekl1PCPc/j7m5cxayXZ9iHPwE3NJZb4B6hv 0T0a2Sj1sQJqoRVVBaFVlIJhZKijetwVyhkXOCHaVsCk6LMsYAriYoX+jYyRRYIjHGVhOcld8v4 VXHcmfnUazHFE53RDce3uEzx/7mSWgtspvnKSGxz7Xr6dfTV9mzux1g4vE+RZhIZgUuL8p2cN0I GztfUVEiC4bRy8KiP/ftNVcfnmI8ex05nw3e2lx4G2hAIY/7sCww3SgkiVoM4FNRHNXsY2BCRee 34q90ydKXFreMTHcifARPcAAY1HglFnpfamY4Vi1a4V8981zLTrdGf5BhU30JZJNxYFJ75Ty+xN CosV22URBIdTGQVM0wQ== X-Proofpoint-GUID: bh4AnU1-e8JfCMGCZKk_YNazqeYewf0a X-Authority-Analysis: v=2.4 cv=a/wAM0SF c=1 sm=1 tr=0 ts=69d5bf29 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=V8glGbnc2Ofi9Qvn3v5h:22 a=mDV3o1hIAAAA:8 a=wRVZ3OLsB-j7YOAFBSQA:9 X-Proofpoint-ORIG-GUID: Sg53Jqf9xaShCfbcjvYAf0i4iLBYo-ae X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-08_01,2026-04-07_05,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 spamscore=0 impostorscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080019 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, RCVD_IN_VALIDITY_RPBL_BLOCKED, RCVD_IN_VALIDITY_SAFE_BLOCKED, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces~patchwork=sourceware.org@gcc.gnu.org From: Avinash Jayakar A few types were not tested with the patch https://gcc.gnu.org/pipermail/gcc-patches/2026-March/711326.html i.e., (signed/unsigned) long long, and long support in 32 bit system. This patch adds support for long long in 64 bit system and for long in 32 bit. Although the generic builtin __atomic_compare_exchange does support long long even in 32 bit, it does not generate larx instructions in assembly, and instead expands using internal function. Therefore decided not to support the new builtin for this type in 32 bit. Added a few more tests for checking this failure scenario in 32 bit, and separated out 32 bit tests from 64 bit tests. Regtested on powerpc64le-linux-gnu with no regressions, ok for trunk? gcc/ChangeLog: PR target/124800 * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add long long support. Expand using SI mode for long type in 32 bit. * config/rs6000/rs6000-builtins.def: New builtins for long long. * config/rs6000/rs6000-overload.def: New overloads for long long. gcc/testsuite/ChangeLog: PR target/124800 * gcc.target/powerpc/acmp-tst.c: Run only for 64 bit or where __int128 is supported. * gcc.target/powerpc/acmp-tst-32-fail.c: New test. * gcc.target/powerpc/acmp-tst-32.c: New test. --- gcc/config/rs6000/rs6000-builtin.cc | 15 ++++++++-- gcc/config/rs6000/rs6000-builtins.def | 2 ++ gcc/config/rs6000/rs6000-overload.def | 4 +++ .../gcc.target/powerpc/acmp-tst-32-fail.c | 18 ++++++++++++ .../gcc.target/powerpc/acmp-tst-32.c | 29 +++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/acmp-tst.c | 5 +++- 6 files changed, 69 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c create mode 100644 gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index bbf60de3b1b..845dd4c1e50 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -3288,7 +3288,8 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, || fcode == RS6000_BIF_PPC_ATOMIC_CAS_HI || fcode == RS6000_BIF_PPC_ATOMIC_CAS_SI || fcode == RS6000_BIF_PPC_ATOMIC_CAS_DI - || fcode == RS6000_BIF_PPC_ATOMIC_CAS_TI) + || fcode == RS6000_BIF_PPC_ATOMIC_CAS_TI + || fcode == RS6000_BIF_PPC_ATOMIC_CAS_DI_LL) { machine_mode mode; // Get mode based on BIF ID (QImode, SImode, etc.) @@ -3307,13 +3308,21 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, icode = CODE_FOR_atomic_compare_and_swap_localsi; break; case RS6000_BIF_PPC_ATOMIC_CAS_DI: - mode = DImode; - icode = CODE_FOR_atomic_compare_and_swap_localdi; + mode = TARGET_32BIT ? SImode : DImode; + icode = TARGET_32BIT ? CODE_FOR_atomic_compare_and_swap_localsi + : CODE_FOR_atomic_compare_and_swap_localdi; break; case RS6000_BIF_PPC_ATOMIC_CAS_TI: mode = TImode; icode = CODE_FOR_atomic_compare_and_swap_localti; break; + case RS6000_BIF_PPC_ATOMIC_CAS_DI_LL: + if (TARGET_32BIT) + error ("Invalid arguments to %qs", + "__builtin_ppc_atomic_cas_local"); + mode = DImode; + icode = CODE_FOR_atomic_compare_and_swap_localdi; + break; default: gcc_unreachable (); } diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 577c9d6c8f0..a7918b4184d 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -255,6 +255,8 @@ PPC_ATOMIC_CAS_SI nothing {} bool __builtin_ppc_atomic_cas_local_di (long *, long *, long *, const int, const int, const int); PPC_ATOMIC_CAS_DI nothing {} + bool __builtin_ppc_atomic_cas_local_di_ll (long long *, long long *, long long *, const int, const int, const int); + PPC_ATOMIC_CAS_DI_LL nothing {} bool __builtin_ppc_atomic_cas_local_ti (vsq *, vsq *, vsq *, const int, const int, const int); PPC_ATOMIC_CAS_TI nothing {} diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def index 8f2fa978475..6ee90c0f8c7 100644 --- a/gcc/config/rs6000/rs6000-overload.def +++ b/gcc/config/rs6000/rs6000-overload.def @@ -96,6 +96,10 @@ PPC_ATOMIC_CAS_DI PPC_ATOMIC_CAS_SDI bool __builtin_ppc_atomic_cas_local (unsigned long *, unsigned long *, unsigned long *, const int, const int, const int); PPC_ATOMIC_CAS_DI PPC_ATOMIC_CAS_UDI + bool __builtin_ppc_atomic_cas_local (signed long long *, signed long long *, signed long long *, const int, const int, const int); + PPC_ATOMIC_CAS_DI_LL PPC_ATOMIC_CAS_SDI_LL + bool __builtin_ppc_atomic_cas_local (unsigned long long *, unsigned long long *, unsigned long long *, const int, const int, const int); + PPC_ATOMIC_CAS_DI_LL PPC_ATOMIC_CAS_UDI_LL bool __builtin_ppc_atomic_cas_local (vsq *, vsq *, vsq *, const int, const int, const int); PPC_ATOMIC_CAS_TI PPC_ATOMIC_CAS_STI bool __builtin_ppc_atomic_cas_local (vuq *, vuq *, vuq *, const int, const int, const int); diff --git a/gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c new file mode 100644 index 00000000000..c466d7bb18e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32-fail.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -m32" } */ + +#define TESTS \ + X(signed long long, sdi) \ + X(unsigned long long, udi) + +#define X(T, name) \ +bool word_exchange_##name (T *ptr, T *expected, T * desired) \ +{ \ + return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0, \ + __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE); \ +} + +TESTS + +/* { dg-excess-errors "This test is expected to fail on 32-bit" { target ilp32 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c new file mode 100644 index 00000000000..6763cee5ff8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/acmp-tst-32.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -m32" } */ + +#define TESTS \ + X(signed char, qi) \ + X(unsigned char, uqi) \ + X(short, hi) \ + X(signed short, shi) \ + X(unsigned short, uhi) \ + X(int, si) \ + X(signed int, ssi) \ + X(unsigned int, usi) \ + X(long, di) \ + X(signed long, sdi) \ + X(unsigned long, udi) + +#define X(T, name) \ +bool word_exchange_##name (T *ptr, T *expected, T * desired) \ +{ \ + return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0, \ + __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE); \ +} + +TESTS + +/* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */ +/* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */ +/* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/acmp-tst.c b/gcc/testsuite/gcc.target/powerpc/acmp-tst.c index 6ebd2ebbc28..27c98c37acf 100644 --- a/gcc/testsuite/gcc.target/powerpc/acmp-tst.c +++ b/gcc/testsuite/gcc.target/powerpc/acmp-tst.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target int128 } */ /* { dg-options "-O2" } */ #define TESTS \ @@ -13,6 +14,8 @@ X(long, di) \ X(signed long, sdi) \ X(unsigned long, udi) \ + X(signed long long, sdi2) \ + X(unsigned long long, udi2) \ X(vector signed __int128, sti) \ X(vector unsigned __int128, uti) @@ -28,5 +31,5 @@ TESTS /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */ -/* { dg-final { scan-assembler-times {\mldarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */ +/* { dg-final { scan-assembler-times {\mldarx +[0-9]+,[0-9]+,[0-9]+,1} 5 } } */ /* { dg-final { scan-assembler-times {\mlqarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */