From patchwork Thu Dec 16 05:55:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 49004 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 498923858420 for ; Thu, 16 Dec 2021 05:55:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 498923858420 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1639634151; bh=60/A6Plgmdr08IZbyfMlIJdIkx1VmcSqoBomsifH49A=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=jRdvSHdqb+HWaerjanWOWfDejCdp7Apuvs6BorZyIRaoyQv9hYhkp3WLhvIMPwO0r TeKrNa/7vaQ8FGSdf79SDehiSpa82IaI1WvQPhHAJzx08efDAAyPQ2E6pKZ92jGZoG bQTRQ7VjG+KVsGP59NBrtS5TXa0SPagPCOri3spI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 119823858D28 for ; Thu, 16 Dec 2021 05:55:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 119823858D28 X-IronPort-AV: E=McAfee;i="6200,9189,10199"; a="263571671" X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="263571671" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Dec 2021 21:55:18 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,210,1635231600"; d="scan'208";a="615015795" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga004.jf.intel.com with ESMTP; 15 Dec 2021 21:55:18 -0800 Received: from shliclel057.sh.intel.com (shliclel057.sh.intel.com [10.239.236.57]) by scymds01.sc.intel.com with ESMTP id 1BG5tGJo012208; Wed, 15 Dec 2021 21:55:17 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Add option -mvect-compare-costs Date: Thu, 16 Dec 2021 13:55:16 +0800 Message-Id: <20211216055516.3375485-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.2 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Also with corresponding target attribute, option default disabled. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: * config/i386/i386-options.c (ix86_target_string): Handle -mvect-compare-costs. (ix86_valid_target_attribute_inner_p): Support target attribute vect-compare-costs. * config/i386/i386.c (ix86_autovectorize_vector_modes): Return 1 when TARGET_X86_VECT_COMPARE_COSTS. * config/i386/i386.opt: Add option -mvect-compare-costs. * doc/invoke.texi: Document -mvect-compare-costs. --- gcc/config/i386/i386-options.c | 7 ++++++- gcc/config/i386/i386.c | 2 +- gcc/config/i386/i386.opt | 5 +++++ gcc/doc/invoke.texi | 7 ++++++- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 53bd55a12e3..53794b13fc5 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -406,7 +406,8 @@ ix86_target_string (HOST_WIDE_INT isa, HOST_WIDE_INT isa2, /* Additional flag options. */ static struct ix86_target_opts flag2_opts[] = { - { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY } + { "-mgeneral-regs-only", OPTION_MASK_GENERAL_REGS_ONLY }, + { "-mvect-compare-costs", OPTION_MASK_X86_VECT_COMPARE_COSTS } }; const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (isa2_opts) @@ -1111,6 +1112,10 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], OPT_mgeneral_regs_only, OPTION_MASK_GENERAL_REGS_ONLY), + IX86_ATTR_IX86_YES ("vect-compare-costs", + OPT_mvect_compare_costs, + OPTION_MASK_X86_VECT_COMPARE_COSTS), + IX86_ATTR_YES ("relax-cmpxchg-loop", OPT_mrelax_cmpxchg_loop, MASK_RELAX_CMPXCHG_LOOP), diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 9f4ed34ffd5..8d3fc3be1b9 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -22836,7 +22836,7 @@ ix86_autovectorize_vector_modes (vector_modes *modes, bool all) if (TARGET_SSE2) modes->safe_push (V4QImode); - return 0; + return TARGET_X86_VECT_COMPARE_COSTS ? 1 : 0; } /* Implemenation of targetm.vectorize.get_mask_mode. */ diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index e1af3e417b0..80c7a073d07 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1206,3 +1206,8 @@ Support MWAIT and MONITOR built-in functions and code generation. mavx512fp16 Target Mask(ISA2_AVX512FP16) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F and AVX512FP16 built-in functions and code generation. + +mvect-compare-costs +Target Mask(X86_VECT_COMPARE_COSTS) Var(ix86_target_flags) Save +Tells the loop vectorizer to try all the provided vector lengths and pick the +one with the lowest cost. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 80c36b9abe0..fa2f63af65f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1428,7 +1428,7 @@ See RS/6000 and PowerPC Options. -malign-data=@var{type} -mstack-protector-guard=@var{guard} @gol -mstack-protector-guard-reg=@var{reg} @gol -mstack-protector-guard-offset=@var{offset} @gol --mstack-protector-guard-symbol=@var{symbol} @gol +-mstack-protector-guard-symbol=@var{symbol} -mvect-compare-costs@gol -mgeneral-regs-only -mcall-ms2sysv-xlogues -mrelax-cmpxchg-loop @gol -mindirect-branch=@var{choice} -mfunction-return=@var{choice} @gol -mindirect-branch-register -mharden-sls=@var{choice} @gol @@ -32440,6 +32440,11 @@ Generate code that uses only the general-purpose registers. This prevents the compiler from using floating-point, vector, mask and bound registers. +@item -mvect-compare-costs +@opindex mcompare-vect-costs +Tells the loop vectorizer to try all the vector lengths and pick the one +with the lowest cost. + @item -mrelax-cmpxchg-loop @opindex mrelax-cmpxchg-loop Relax cmpxchg loop by emitting an early load and compare before cmpxchg,