From patchwork Tue Dec 14 05:17:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 48886 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B58FE385841A for ; Tue, 14 Dec 2021 05:17:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B58FE385841A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1639459079; bh=Hx8pShKpQVdXjILCVT4nO3Jz+rC1fbqZtIDVyLdLnS4=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=rxpgw0eU6+EWro95+v1GiXRllc7hOR+36gx/KJgZK/W+WAEmKdhhNgL48sWzzbCRs lcbK7qFjHY0bQUa1TYwWT82lRDhGG0aF2ymCOH+/btjOWYeNYFT3xdYUgn3bu9IEZi ENGIfh1ZUTFA2ugodcpphXRMIc2TrONGso82m7ik= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 2F0573858D28 for ; Tue, 14 Dec 2021 05:17:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2F0573858D28 X-IronPort-AV: E=McAfee;i="6200,9189,10197"; a="299679207" X-IronPort-AV: E=Sophos;i="5.88,204,1635231600"; d="scan'208";a="299679207" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2021 21:17:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,204,1635231600"; d="scan'208";a="519004911" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga007.fm.intel.com with ESMTP; 13 Dec 2021 21:17:25 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 1BE5HOaW024835; Mon, 13 Dec 2021 21:17:24 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [Gimple] Fix ICE. [PR103682] Date: Tue, 14 Dec 2021 13:17:23 +0800 Message-Id: <20211214051723.62082-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: References: X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" > This testcase should just go in gcc.c-torture/compile and remove the > dg-options too. > The main reason there is nothing specific to x86 here. > Thanks, here's the updated patch. Check is_gimple_assign before gimple_assign_rhs_code. gcc/ChangeLog: PR target/103682 * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check is_gimple_assign before gimple_assign_rhs_code. gcc/testsuite/ChangeLog: * gcc.c-torture/compile/pr103682.c: New test. --- gcc/testsuite/gcc.c-torture/compile/pr103682.c | 3 +++ gcc/tree-ssa-ccp.c | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr103682.c diff --git a/gcc/testsuite/gcc.c-torture/compile/pr103682.c b/gcc/testsuite/gcc.c-torture/compile/pr103682.c new file mode 100644 index 00000000000..5ee4b21f7e6 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr103682.c @@ -0,0 +1,3 @@ +int bug(unsigned *ready, unsigned u) { + return __atomic_fetch_and (ready, ~u, 0) & u; +} diff --git a/gcc/tree-ssa-ccp.c b/gcc/tree-ssa-ccp.c index 9e12da8f011..a5b1f60f979 100644 --- a/gcc/tree-ssa-ccp.c +++ b/gcc/tree-ssa-ccp.c @@ -3703,8 +3703,8 @@ optimize_atomic_bit_test_and (gimple_stmt_iterator *gsip, g = SSA_NAME_DEF_STMT (mask); } - rhs_code = gimple_assign_rhs_code (g); - if (rhs_code != LSHIFT_EXPR + if (!is_gimple_assign (g) + || gimple_assign_rhs_code (g) != LSHIFT_EXPR || !integer_onep (gimple_assign_rhs1 (g))) return; bit = gimple_assign_rhs2 (g);